1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852a.h"
11 #include "rtw8852a_rfk.h"
12 #include "rtw8852a_table.h"
13 #include "txrx.h"
14 
15 #define RTW8852A_FW_FORMAT_MAX 0
16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
17 #define RTW8852A_MODULE_FIRMWARE \
18 	RTW8852A_FW_BASENAME ".bin"
19 
20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
21 	{128, 1896, grp_0}, /* ACH 0 */
22 	{128, 1896, grp_0}, /* ACH 1 */
23 	{128, 1896, grp_0}, /* ACH 2 */
24 	{128, 1896, grp_0}, /* ACH 3 */
25 	{128, 1896, grp_1}, /* ACH 4 */
26 	{128, 1896, grp_1}, /* ACH 5 */
27 	{128, 1896, grp_1}, /* ACH 6 */
28 	{128, 1896, grp_1}, /* ACH 7 */
29 	{32, 1896, grp_0}, /* B0MGQ */
30 	{128, 1896, grp_0}, /* B0HIQ */
31 	{32, 1896, grp_1}, /* B1MGQ */
32 	{128, 1896, grp_1}, /* B1HIQ */
33 	{40, 0, 0} /* FWCMDQ */
34 };
35 
36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
37 	1896, /* Group 0 */
38 	1896, /* Group 1 */
39 	3792, /* Public Max */
40 	0 /* WP threshold */
41 };
42 
43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
44 	[RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
45 			   &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
46 	[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
47 			    RTW89_HCIFC_POH},
48 	[RTW89_QTA_INVALID] = {NULL},
49 };
50 
51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
52 	[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
53 			   &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
54 			   &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
55 			   &rtw89_mac_size.ple_qt5},
56 	[RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
57 			   &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
58 			   &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
59 			   &rtw89_mac_size.ple_qt_52a_wow},
60 	[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
61 			    &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
62 			    &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
63 			    &rtw89_mac_size.ple_qt13},
64 	[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
65 			       NULL},
66 };
67 
68 static const struct rtw89_reg2_def  rtw8852a_pmac_ht20_mcs7_tbl[] = {
69 	{0x44AC, 0x00000000},
70 	{0x44B0, 0x00000000},
71 	{0x44B4, 0x00000000},
72 	{0x44B8, 0x00000000},
73 	{0x44BC, 0x00000000},
74 	{0x44C0, 0x00000000},
75 	{0x44C4, 0x00000000},
76 	{0x44C8, 0x00000000},
77 	{0x44CC, 0x00000000},
78 	{0x44D0, 0x00000000},
79 	{0x44D4, 0x00000000},
80 	{0x44D8, 0x00000000},
81 	{0x44DC, 0x00000000},
82 	{0x44E0, 0x00000000},
83 	{0x44E4, 0x00000000},
84 	{0x44E8, 0x00000000},
85 	{0x44EC, 0x00000000},
86 	{0x44F0, 0x00000000},
87 	{0x44F4, 0x00000000},
88 	{0x44F8, 0x00000000},
89 	{0x44FC, 0x00000000},
90 	{0x4500, 0x00000000},
91 	{0x4504, 0x00000000},
92 	{0x4508, 0x00000000},
93 	{0x450C, 0x00000000},
94 	{0x4510, 0x00000000},
95 	{0x4514, 0x00000000},
96 	{0x4518, 0x00000000},
97 	{0x451C, 0x00000000},
98 	{0x4520, 0x00000000},
99 	{0x4524, 0x00000000},
100 	{0x4528, 0x00000000},
101 	{0x452C, 0x00000000},
102 	{0x4530, 0x4E1F3E81},
103 	{0x4534, 0x00000000},
104 	{0x4538, 0x0000005A},
105 	{0x453C, 0x00000000},
106 	{0x4540, 0x00000000},
107 	{0x4544, 0x00000000},
108 	{0x4548, 0x00000000},
109 	{0x454C, 0x00000000},
110 	{0x4550, 0x00000000},
111 	{0x4554, 0x00000000},
112 	{0x4558, 0x00000000},
113 	{0x455C, 0x00000000},
114 	{0x4560, 0x4060001A},
115 	{0x4564, 0x40000000},
116 	{0x4568, 0x00000000},
117 	{0x456C, 0x00000000},
118 	{0x4570, 0x04000007},
119 	{0x4574, 0x0000DC87},
120 	{0x4578, 0x00000BAB},
121 	{0x457C, 0x03E00000},
122 	{0x4580, 0x00000048},
123 	{0x4584, 0x00000000},
124 	{0x4588, 0x000003E8},
125 	{0x458C, 0x30000000},
126 	{0x4590, 0x00000000},
127 	{0x4594, 0x10000000},
128 	{0x4598, 0x00000001},
129 	{0x459C, 0x00030000},
130 	{0x45A0, 0x01000000},
131 	{0x45A4, 0x03000200},
132 	{0x45A8, 0xC00001C0},
133 	{0x45AC, 0x78018000},
134 	{0x45B0, 0x80000000},
135 	{0x45B4, 0x01C80600},
136 	{0x45B8, 0x00000002},
137 	{0x4594, 0x10000000}
138 };
139 
140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
141 	{0x4624, GENMASK(20, 14), 0x40},
142 	{0x46f8, GENMASK(20, 14), 0x40},
143 	{0x4674, GENMASK(20, 19), 0x2},
144 	{0x4748, GENMASK(20, 19), 0x2},
145 	{0x4650, GENMASK(14, 10), 0x18},
146 	{0x4724, GENMASK(14, 10), 0x18},
147 	{0x4688, GENMASK(1, 0), 0x3},
148 	{0x475c, GENMASK(1, 0), 0x3},
149 };
150 
151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
152 
153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
154 	{0x4624, GENMASK(20, 14), 0x1a},
155 	{0x46f8, GENMASK(20, 14), 0x1a},
156 	{0x4674, GENMASK(20, 19), 0x1},
157 	{0x4748, GENMASK(20, 19), 0x1},
158 	{0x4650, GENMASK(14, 10), 0x12},
159 	{0x4724, GENMASK(14, 10), 0x12},
160 	{0x4688, GENMASK(1, 0), 0x0},
161 	{0x475c, GENMASK(1, 0), 0x0},
162 };
163 
164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
165 
166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
167 	{0x00C6,
168 	 PWR_CV_MSK_B,
169 	 PWR_INTF_MSK_PCIE,
170 	 PWR_BASE_MAC,
171 	 PWR_CMD_WRITE, BIT(6), BIT(6)},
172 	{0x1086,
173 	 PWR_CV_MSK_ALL,
174 	 PWR_INTF_MSK_SDIO,
175 	 PWR_BASE_MAC,
176 	 PWR_CMD_WRITE, BIT(0), 0},
177 	{0x1086,
178 	 PWR_CV_MSK_ALL,
179 	 PWR_INTF_MSK_SDIO,
180 	 PWR_BASE_MAC,
181 	 PWR_CMD_POLL, BIT(1), BIT(1)},
182 	{0x0005,
183 	 PWR_CV_MSK_ALL,
184 	 PWR_INTF_MSK_ALL,
185 	 PWR_BASE_MAC,
186 	 PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
187 	{0x0005,
188 	 PWR_CV_MSK_ALL,
189 	 PWR_INTF_MSK_ALL,
190 	 PWR_BASE_MAC,
191 	 PWR_CMD_WRITE, BIT(7), 0},
192 	{0x0005,
193 	 PWR_CV_MSK_ALL,
194 	 PWR_INTF_MSK_ALL,
195 	 PWR_BASE_MAC,
196 	 PWR_CMD_WRITE, BIT(2), 0},
197 	{0x0006,
198 	 PWR_CV_MSK_ALL,
199 	 PWR_INTF_MSK_ALL,
200 	 PWR_BASE_MAC,
201 	 PWR_CMD_POLL, BIT(1), BIT(1)},
202 	{0x0006,
203 	 PWR_CV_MSK_ALL,
204 	 PWR_INTF_MSK_ALL,
205 	 PWR_BASE_MAC,
206 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
207 	{0x0005,
208 	 PWR_CV_MSK_ALL,
209 	 PWR_INTF_MSK_ALL,
210 	 PWR_BASE_MAC,
211 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
212 	{0x0005,
213 	 PWR_CV_MSK_ALL,
214 	 PWR_INTF_MSK_ALL,
215 	 PWR_BASE_MAC,
216 	 PWR_CMD_POLL, BIT(0), 0},
217 	{0x106D,
218 	 PWR_CV_MSK_B | PWR_CV_MSK_C,
219 	 PWR_INTF_MSK_USB,
220 	 PWR_BASE_MAC,
221 	 PWR_CMD_WRITE, BIT(6), 0},
222 	{0x0088,
223 	 PWR_CV_MSK_ALL,
224 	 PWR_INTF_MSK_ALL,
225 	 PWR_BASE_MAC,
226 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
227 	{0x0088,
228 	 PWR_CV_MSK_ALL,
229 	 PWR_INTF_MSK_ALL,
230 	 PWR_BASE_MAC,
231 	 PWR_CMD_WRITE, BIT(0), 0},
232 	{0x0088,
233 	 PWR_CV_MSK_ALL,
234 	 PWR_INTF_MSK_ALL,
235 	 PWR_BASE_MAC,
236 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
237 	{0x0088,
238 	 PWR_CV_MSK_ALL,
239 	 PWR_INTF_MSK_ALL,
240 	 PWR_BASE_MAC,
241 	 PWR_CMD_WRITE, BIT(0), 0},
242 	{0x0088,
243 	 PWR_CV_MSK_ALL,
244 	 PWR_INTF_MSK_ALL,
245 	 PWR_BASE_MAC,
246 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
247 	{0x0083,
248 	 PWR_CV_MSK_ALL,
249 	 PWR_INTF_MSK_ALL,
250 	 PWR_BASE_MAC,
251 	 PWR_CMD_WRITE, BIT(6), 0},
252 	{0x0080,
253 	 PWR_CV_MSK_ALL,
254 	 PWR_INTF_MSK_ALL,
255 	 PWR_BASE_MAC,
256 	 PWR_CMD_WRITE, BIT(5), BIT(5)},
257 	{0x0024,
258 	 PWR_CV_MSK_ALL,
259 	 PWR_INTF_MSK_ALL,
260 	 PWR_BASE_MAC,
261 	 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
262 	{0x02A0,
263 	 PWR_CV_MSK_ALL,
264 	 PWR_INTF_MSK_ALL,
265 	 PWR_BASE_MAC,
266 	 PWR_CMD_WRITE, BIT(1), BIT(1)},
267 	{0x02A2,
268 	 PWR_CV_MSK_ALL,
269 	 PWR_INTF_MSK_ALL,
270 	 PWR_BASE_MAC,
271 	 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
272 	{0x0071,
273 	 PWR_CV_MSK_ALL,
274 	 PWR_INTF_MSK_PCIE,
275 	 PWR_BASE_MAC,
276 	 PWR_CMD_WRITE, BIT(4), 0},
277 	{0x0010,
278 	 PWR_CV_MSK_A,
279 	 PWR_INTF_MSK_PCIE,
280 	 PWR_BASE_MAC,
281 	 PWR_CMD_WRITE, BIT(2), BIT(2)},
282 	{0x02A0,
283 	 PWR_CV_MSK_A,
284 	 PWR_INTF_MSK_ALL,
285 	 PWR_BASE_MAC,
286 	 PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
287 	{0xFFFF,
288 	 PWR_CV_MSK_ALL,
289 	 PWR_INTF_MSK_ALL,
290 	 0,
291 	 PWR_CMD_END, 0, 0},
292 };
293 
294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
295 	{0x02F0,
296 	 PWR_CV_MSK_ALL,
297 	 PWR_INTF_MSK_ALL,
298 	 PWR_BASE_MAC,
299 	 PWR_CMD_WRITE, 0xFF, 0},
300 	{0x02F1,
301 	 PWR_CV_MSK_ALL,
302 	 PWR_INTF_MSK_ALL,
303 	 PWR_BASE_MAC,
304 	 PWR_CMD_WRITE, 0xFF, 0},
305 	{0x0006,
306 	 PWR_CV_MSK_ALL,
307 	 PWR_INTF_MSK_ALL,
308 	 PWR_BASE_MAC,
309 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
310 	{0x0002,
311 	 PWR_CV_MSK_ALL,
312 	 PWR_INTF_MSK_ALL,
313 	 PWR_BASE_MAC,
314 	 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
315 	{0x0082,
316 	 PWR_CV_MSK_ALL,
317 	 PWR_INTF_MSK_ALL,
318 	 PWR_BASE_MAC,
319 	 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
320 	{0x106D,
321 	 PWR_CV_MSK_B | PWR_CV_MSK_C,
322 	 PWR_INTF_MSK_USB,
323 	 PWR_BASE_MAC,
324 	 PWR_CMD_WRITE, BIT(6), BIT(6)},
325 	{0x0005,
326 	 PWR_CV_MSK_ALL,
327 	 PWR_INTF_MSK_ALL,
328 	 PWR_BASE_MAC,
329 	 PWR_CMD_WRITE, BIT(1), BIT(1)},
330 	{0x0005,
331 	 PWR_CV_MSK_ALL,
332 	 PWR_INTF_MSK_ALL,
333 	 PWR_BASE_MAC,
334 	 PWR_CMD_POLL, BIT(1), 0},
335 	{0x0091,
336 	 PWR_CV_MSK_ALL,
337 	 PWR_INTF_MSK_PCIE,
338 	 PWR_BASE_MAC,
339 	 PWR_CMD_WRITE, BIT(0), 0},
340 	{0x0005,
341 	 PWR_CV_MSK_ALL,
342 	 PWR_INTF_MSK_PCIE,
343 	 PWR_BASE_MAC,
344 	 PWR_CMD_WRITE, BIT(2), BIT(2)},
345 	{0x0007,
346 	 PWR_CV_MSK_ALL,
347 	 PWR_INTF_MSK_USB,
348 	 PWR_BASE_MAC,
349 	 PWR_CMD_WRITE, BIT(4), 0},
350 	{0x0007,
351 	 PWR_CV_MSK_ALL,
352 	 PWR_INTF_MSK_SDIO,
353 	 PWR_BASE_MAC,
354 	 PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
355 	{0x0005,
356 	 PWR_CV_MSK_ALL,
357 	 PWR_INTF_MSK_SDIO,
358 	 PWR_BASE_MAC,
359 	 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
360 	{0x0005,
361 	 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
362 	 PWR_CV_MSK_G,
363 	 PWR_INTF_MSK_USB,
364 	 PWR_BASE_MAC,
365 	 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
366 	{0x1086,
367 	 PWR_CV_MSK_ALL,
368 	 PWR_INTF_MSK_SDIO,
369 	 PWR_BASE_MAC,
370 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
371 	{0x1086,
372 	 PWR_CV_MSK_ALL,
373 	 PWR_INTF_MSK_SDIO,
374 	 PWR_BASE_MAC,
375 	 PWR_CMD_POLL, BIT(1), 0},
376 	{0xFFFF,
377 	 PWR_CV_MSK_ALL,
378 	 PWR_INTF_MSK_ALL,
379 	 0,
380 	 PWR_CMD_END, 0, 0},
381 };
382 
383 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
384 	rtw8852a_pwron, NULL
385 };
386 
387 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
388 	rtw8852a_pwroff, NULL
389 };
390 
391 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
392 	R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1,  R_AX_H2CREG_DATA2,
393 	R_AX_H2CREG_DATA3
394 };
395 
396 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
397 	R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
398 	R_AX_C2HREG_DATA3
399 };
400 
401 static const struct rtw89_page_regs rtw8852a_page_regs = {
402 	.hci_fc_ctrl	= R_AX_HCI_FC_CTRL,
403 	.ch_page_ctrl	= R_AX_CH_PAGE_CTRL,
404 	.ach_page_ctrl	= R_AX_ACH0_PAGE_CTRL,
405 	.ach_page_info	= R_AX_ACH0_PAGE_INFO,
406 	.pub_page_info3	= R_AX_PUB_PAGE_INFO3,
407 	.pub_page_ctrl1	= R_AX_PUB_PAGE_CTRL1,
408 	.pub_page_ctrl2	= R_AX_PUB_PAGE_CTRL2,
409 	.pub_page_info1	= R_AX_PUB_PAGE_INFO1,
410 	.pub_page_info2 = R_AX_PUB_PAGE_INFO2,
411 	.wp_page_ctrl1	= R_AX_WP_PAGE_CTRL1,
412 	.wp_page_ctrl2	= R_AX_WP_PAGE_CTRL2,
413 	.wp_page_info1	= R_AX_WP_PAGE_INFO1,
414 };
415 
416 static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
417 	R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
418 };
419 
420 static const struct rtw89_imr_info rtw8852a_imr_info = {
421 	.wdrls_imr_set		= B_AX_WDRLS_IMR_SET,
422 	.wsec_imr_reg		= R_AX_SEC_DEBUG,
423 	.wsec_imr_set		= B_AX_IMR_ERROR,
424 	.mpdu_tx_imr_set	= 0,
425 	.mpdu_rx_imr_set	= 0,
426 	.sta_sch_imr_set	= B_AX_STA_SCHEDULER_IMR_SET,
427 	.txpktctl_imr_b0_reg	= R_AX_TXPKTCTL_ERR_IMR_ISR,
428 	.txpktctl_imr_b0_clr	= B_AX_TXPKTCTL_IMR_B0_CLR,
429 	.txpktctl_imr_b0_set	= B_AX_TXPKTCTL_IMR_B0_SET,
430 	.txpktctl_imr_b1_reg	= R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
431 	.txpktctl_imr_b1_clr	= B_AX_TXPKTCTL_IMR_B1_CLR,
432 	.txpktctl_imr_b1_set	= B_AX_TXPKTCTL_IMR_B1_SET,
433 	.wde_imr_clr		= B_AX_WDE_IMR_CLR,
434 	.wde_imr_set		= B_AX_WDE_IMR_SET,
435 	.ple_imr_clr		= B_AX_PLE_IMR_CLR,
436 	.ple_imr_set		= B_AX_PLE_IMR_SET,
437 	.host_disp_imr_clr	= B_AX_HOST_DISP_IMR_CLR,
438 	.host_disp_imr_set	= B_AX_HOST_DISP_IMR_SET,
439 	.cpu_disp_imr_clr	= B_AX_CPU_DISP_IMR_CLR,
440 	.cpu_disp_imr_set	= B_AX_CPU_DISP_IMR_SET,
441 	.other_disp_imr_clr	= B_AX_OTHER_DISP_IMR_CLR,
442 	.other_disp_imr_set	= 0,
443 	.bbrpt_com_err_imr_reg	= R_AX_BBRPT_COM_ERR_IMR_ISR,
444 	.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
445 	.bbrpt_err_imr_set	= 0,
446 	.bbrpt_dfs_err_imr_reg	= R_AX_BBRPT_DFS_ERR_IMR_ISR,
447 	.ptcl_imr_clr		= B_AX_PTCL_IMR_CLR,
448 	.ptcl_imr_set		= B_AX_PTCL_IMR_SET,
449 	.cdma_imr_0_reg		= R_AX_DLE_CTRL,
450 	.cdma_imr_0_clr		= B_AX_DLE_IMR_CLR,
451 	.cdma_imr_0_set		= B_AX_DLE_IMR_SET,
452 	.cdma_imr_1_reg		= 0,
453 	.cdma_imr_1_clr		= 0,
454 	.cdma_imr_1_set		= 0,
455 	.phy_intf_imr_reg	= R_AX_PHYINFO_ERR_IMR,
456 	.phy_intf_imr_clr	= 0,
457 	.phy_intf_imr_set	= 0,
458 	.rmac_imr_reg		= R_AX_RMAC_ERR_ISR,
459 	.rmac_imr_clr		= B_AX_RMAC_IMR_CLR,
460 	.rmac_imr_set		= B_AX_RMAC_IMR_SET,
461 	.tmac_imr_reg		= R_AX_TMAC_ERR_IMR_ISR,
462 	.tmac_imr_clr		= B_AX_TMAC_IMR_CLR,
463 	.tmac_imr_set		= B_AX_TMAC_IMR_SET,
464 };
465 
466 static const struct rtw89_xtal_info rtw8852a_xtal_info = {
467 	.xcap_reg		= R_AX_XTAL_ON_CTRL0,
468 	.sc_xo_mask		= B_AX_XTAL_SC_XO_MASK,
469 	.sc_xi_mask		= B_AX_XTAL_SC_XI_MASK,
470 };
471 
472 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
473 	.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
474 	.rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
475 };
476 
477 static const struct rtw89_dig_regs rtw8852a_dig_regs = {
478 	.seg0_pd_reg = R_SEG0R_PD,
479 	.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
480 	.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
481 	.bmode_pd_reg = R_BMODE_PDTH_EN_V1,
482 	.bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
483 	.bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
484 	.bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
485 	.p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
486 	.p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
487 	.p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
488 	.p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
489 	.p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
490 	.p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
491 	.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
492 			      B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
493 	.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
494 			      B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
495 	.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
496 			      B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
497 	.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
498 			      B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
499 };
500 
rtw8852ae_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8852a_efuse * map)501 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
502 				    struct rtw8852a_efuse *map)
503 {
504 	ether_addr_copy(efuse->addr, map->e.mac_addr);
505 	efuse->rfe_type = map->rfe_type;
506 	efuse->xtal_cap = map->xtal_k;
507 }
508 
rtw8852a_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8852a_efuse * map)509 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
510 					struct rtw8852a_efuse *map)
511 {
512 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
513 	struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
514 	u8 i, j;
515 
516 	tssi->thermal[RF_PATH_A] = map->path_a_therm;
517 	tssi->thermal[RF_PATH_B] = map->path_b_therm;
518 
519 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
520 		memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
521 		       sizeof(ofst[i]->cck_tssi));
522 
523 		for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
524 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
525 				    "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
526 				    i, j, tssi->tssi_cck[i][j]);
527 
528 		memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
529 		       sizeof(ofst[i]->bw40_tssi));
530 		memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
531 		       ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
532 
533 		for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
534 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
535 				    "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
536 				    i, j, tssi->tssi_mcs[i][j]);
537 	}
538 }
539 
rtw8852a_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map)540 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
541 {
542 	struct rtw89_efuse *efuse = &rtwdev->efuse;
543 	struct rtw8852a_efuse *map;
544 
545 	map = (struct rtw8852a_efuse *)log_map;
546 
547 	efuse->country_code[0] = map->country_code[0];
548 	efuse->country_code[1] = map->country_code[1];
549 	rtw8852a_efuse_parsing_tssi(rtwdev, map);
550 
551 	switch (rtwdev->hci.type) {
552 	case RTW89_HCI_TYPE_PCIE:
553 		rtw8852ae_efuse_parsing(efuse, map);
554 		break;
555 	default:
556 		return -ENOTSUPP;
557 	}
558 
559 	rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
560 
561 	return 0;
562 }
563 
rtw8852a_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)564 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
565 {
566 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
567 	static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
568 	u32 addr = rtwdev->chip->phycap_addr;
569 	bool pg = false;
570 	u32 ofst;
571 	u8 i, j;
572 
573 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
574 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
575 			/* addrs are in decreasing order */
576 			ofst = tssi_trim_addr[i] - addr - j;
577 			tssi->tssi_trim[i][j] = phycap_map[ofst];
578 
579 			if (phycap_map[ofst] != 0xff)
580 				pg = true;
581 		}
582 	}
583 
584 	if (!pg) {
585 		memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
586 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
587 			    "[TSSI][TRIM] no PG, set all trim info to 0\n");
588 	}
589 
590 	for (i = 0; i < RF_PATH_NUM_8852A; i++)
591 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
592 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
593 				    "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
594 				    i, j, tssi->tssi_trim[i][j],
595 				    tssi_trim_addr[i] - j);
596 }
597 
rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)598 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
599 						 u8 *phycap_map)
600 {
601 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
602 	static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
603 	u32 addr = rtwdev->chip->phycap_addr;
604 	u8 i;
605 
606 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
607 		info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
608 
609 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
610 			    "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
611 			    i, info->thermal_trim[i]);
612 
613 		if (info->thermal_trim[i] != 0xff)
614 			info->pg_thermal_trim = true;
615 	}
616 }
617 
rtw8852a_thermal_trim(struct rtw89_dev * rtwdev)618 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
619 {
620 #define __thm_setting(raw)				\
621 ({							\
622 	u8 __v = (raw);					\
623 	((__v & 0x1) << 3) | ((__v & 0x1f) >> 1);	\
624 })
625 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
626 	u8 i, val;
627 
628 	if (!info->pg_thermal_trim) {
629 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
630 			    "[THERMAL][TRIM] no PG, do nothing\n");
631 
632 		return;
633 	}
634 
635 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
636 		val = __thm_setting(info->thermal_trim[i]);
637 		rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
638 
639 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
640 			    "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
641 			    i, val);
642 	}
643 #undef __thm_setting
644 }
645 
rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)646 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
647 						 u8 *phycap_map)
648 {
649 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
650 	static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
651 	u32 addr = rtwdev->chip->phycap_addr;
652 	u8 i;
653 
654 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
655 		info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
656 
657 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
658 			    "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
659 			    i, info->pa_bias_trim[i]);
660 
661 		if (info->pa_bias_trim[i] != 0xff)
662 			info->pg_pa_bias_trim = true;
663 	}
664 }
665 
rtw8852a_pa_bias_trim(struct rtw89_dev * rtwdev)666 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
667 {
668 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
669 	u8 pabias_2g, pabias_5g;
670 	u8 i;
671 
672 	if (!info->pg_pa_bias_trim) {
673 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
674 			    "[PA_BIAS][TRIM] no PG, do nothing\n");
675 
676 		return;
677 	}
678 
679 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
680 		pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
681 		pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
682 
683 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
684 			    "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
685 			    i, pabias_2g, pabias_5g);
686 
687 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
688 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
689 	}
690 }
691 
rtw8852a_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)692 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
693 {
694 	rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
695 	rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
696 	rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
697 
698 	return 0;
699 }
700 
rtw8852a_power_trim(struct rtw89_dev * rtwdev)701 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
702 {
703 	rtw8852a_thermal_trim(rtwdev);
704 	rtw8852a_pa_bias_trim(rtwdev);
705 }
706 
rtw8852a_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)707 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
708 				     const struct rtw89_chan *chan,
709 				     u8 mac_idx)
710 {
711 	u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
712 	u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
713 	u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
714 	u8 txsc20 = 0, txsc40 = 0;
715 
716 	switch (chan->band_width) {
717 	case RTW89_CHANNEL_WIDTH_80:
718 		txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
719 					    RTW89_CHANNEL_WIDTH_40);
720 		fallthrough;
721 	case RTW89_CHANNEL_WIDTH_40:
722 		txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
723 					    RTW89_CHANNEL_WIDTH_20);
724 		break;
725 	default:
726 		break;
727 	}
728 
729 	switch (chan->band_width) {
730 	case RTW89_CHANNEL_WIDTH_80:
731 		rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
732 		rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
733 		break;
734 	case RTW89_CHANNEL_WIDTH_40:
735 		rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
736 		rtw89_write32(rtwdev, sub_carr, txsc20);
737 		break;
738 	case RTW89_CHANNEL_WIDTH_20:
739 		rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
740 		rtw89_write32(rtwdev, sub_carr, 0);
741 		break;
742 	default:
743 		break;
744 	}
745 
746 	if (chan->channel > 14)
747 		rtw89_write8_set(rtwdev, chk_rate,
748 				 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
749 	else
750 		rtw89_write8_clr(rtwdev, chk_rate,
751 				 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
752 }
753 
754 static const u32 rtw8852a_sco_barker_threshold[14] = {
755 	0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
756 	0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
757 };
758 
759 static const u32 rtw8852a_sco_cck_threshold[14] = {
760 	0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
761 	0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
762 };
763 
rtw8852a_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 central_ch,u8 primary_ch,enum rtw89_bandwidth bw)764 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
765 				 u8 primary_ch, enum rtw89_bandwidth bw)
766 {
767 	u8 ch_element;
768 
769 	if (bw == RTW89_CHANNEL_WIDTH_20) {
770 		ch_element = central_ch - 1;
771 	} else if (bw == RTW89_CHANNEL_WIDTH_40) {
772 		if (primary_ch == 1)
773 			ch_element = central_ch - 1 + 2;
774 		else
775 			ch_element = central_ch - 1 - 2;
776 	} else {
777 		rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
778 		return -EINVAL;
779 	}
780 	rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
781 			       rtw8852a_sco_barker_threshold[ch_element]);
782 	rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
783 			       rtw8852a_sco_cck_threshold[ch_element]);
784 
785 	return 0;
786 }
787 
rtw8852a_ch_setting(struct rtw89_dev * rtwdev,u8 central_ch,u8 path)788 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
789 				u8 path)
790 {
791 	u32 val;
792 
793 	val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
794 	if (val == INV_RF_DATA) {
795 		rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
796 		return;
797 	}
798 	val &= ~0x303ff;
799 	val |= central_ch;
800 	if (central_ch > 14)
801 		val |= (BIT(16) | BIT(8));
802 	rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
803 }
804 
rtw8852a_sco_mapping(u8 central_ch)805 static u8 rtw8852a_sco_mapping(u8 central_ch)
806 {
807 	if (central_ch == 1)
808 		return 109;
809 	else if (central_ch >= 2 && central_ch <= 6)
810 		return 108;
811 	else if (central_ch >= 7 && central_ch <= 10)
812 		return 107;
813 	else if (central_ch >= 11 && central_ch <= 14)
814 		return 106;
815 	else if (central_ch == 36 || central_ch == 38)
816 		return 51;
817 	else if (central_ch >= 40 && central_ch <= 58)
818 		return 50;
819 	else if (central_ch >= 60 && central_ch <= 64)
820 		return 49;
821 	else if (central_ch == 100 || central_ch == 102)
822 		return 48;
823 	else if (central_ch >= 104 && central_ch <= 126)
824 		return 47;
825 	else if (central_ch >= 128 && central_ch <= 151)
826 		return 46;
827 	else if (central_ch >= 153 && central_ch <= 177)
828 		return 45;
829 	else
830 		return 0;
831 }
832 
rtw8852a_ctrl_ch(struct rtw89_dev * rtwdev,u8 central_ch,enum rtw89_phy_idx phy_idx)833 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
834 			     enum rtw89_phy_idx phy_idx)
835 {
836 	u8 sco_comp;
837 	bool is_2g = central_ch <= 14;
838 
839 	if (phy_idx == RTW89_PHY_0) {
840 		/* Path A */
841 		rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
842 		if (is_2g)
843 			rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
844 					      B_PATH0_TIA_ERR_G1_SEL, 1,
845 					      phy_idx);
846 		else
847 			rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
848 					      B_PATH0_TIA_ERR_G1_SEL, 0,
849 					      phy_idx);
850 
851 		/* Path B */
852 		if (!rtwdev->dbcc_en) {
853 			rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
854 			if (is_2g)
855 				rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
856 						      B_P1_MODE_SEL,
857 						      1, phy_idx);
858 			else
859 				rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
860 						      B_P1_MODE_SEL,
861 						      0, phy_idx);
862 		} else {
863 			if (is_2g)
864 				rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
865 						      B_2P4G_BAND_SEL);
866 			else
867 				rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
868 						      B_2P4G_BAND_SEL);
869 		}
870 		/* SCO compensate FC setting */
871 		sco_comp = rtw8852a_sco_mapping(central_ch);
872 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
873 				      sco_comp, phy_idx);
874 	} else {
875 		/* Path B */
876 		rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
877 		if (is_2g)
878 			rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
879 					      B_P1_MODE_SEL,
880 					      1, phy_idx);
881 		else
882 			rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
883 					      B_P1_MODE_SEL,
884 					      0, phy_idx);
885 		/* SCO compensate FC setting */
886 		sco_comp = rtw8852a_sco_mapping(central_ch);
887 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
888 				      sco_comp, phy_idx);
889 	}
890 
891 	/* Band edge */
892 	if (is_2g)
893 		rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
894 				      phy_idx);
895 	else
896 		rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
897 				      phy_idx);
898 
899 	/* CCK parameters */
900 	if (central_ch == 14) {
901 		rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
902 				       0x3b13ff);
903 		rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
904 				       0x1c42de);
905 		rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
906 				       0xfdb0ad);
907 		rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
908 				       0xf60f6e);
909 		rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
910 				       0xfd8f92);
911 		rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
912 		rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
913 		rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
914 				       0xfff00a);
915 	} else {
916 		rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
917 				       0x3d23ff);
918 		rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
919 				       0x29b354);
920 		rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
921 		rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
922 				       0xfdb053);
923 		rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
924 				       0xf86f9a);
925 		rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
926 				       0xfaef92);
927 		rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
928 				       0xfe5fcc);
929 		rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
930 				       0xffdff5);
931 	}
932 }
933 
rtw8852a_bw_setting(struct rtw89_dev * rtwdev,u8 bw,u8 path)934 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
935 {
936 	u32 val = 0;
937 	u32 adc_sel[2] = {0x12d0, 0x32d0};
938 	u32 wbadc_sel[2] = {0x12ec, 0x32ec};
939 
940 	val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
941 	if (val == INV_RF_DATA) {
942 		rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
943 		return;
944 	}
945 	val &= ~(BIT(11) | BIT(10));
946 	switch (bw) {
947 	case RTW89_CHANNEL_WIDTH_5:
948 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
949 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
950 		val |= (BIT(11) | BIT(10));
951 		break;
952 	case RTW89_CHANNEL_WIDTH_10:
953 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
954 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
955 		val |= (BIT(11) | BIT(10));
956 		break;
957 	case RTW89_CHANNEL_WIDTH_20:
958 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
959 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
960 		val |= (BIT(11) | BIT(10));
961 		break;
962 	case RTW89_CHANNEL_WIDTH_40:
963 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
964 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
965 		val |= BIT(11);
966 		break;
967 	case RTW89_CHANNEL_WIDTH_80:
968 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
969 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
970 		val |= BIT(10);
971 		break;
972 	default:
973 		rtw89_warn(rtwdev, "Fail to set ADC\n");
974 	}
975 
976 	rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
977 }
978 
979 static void
rtw8852a_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)980 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
981 		 enum rtw89_phy_idx phy_idx)
982 {
983 	/* Switch bandwidth */
984 	switch (bw) {
985 	case RTW89_CHANNEL_WIDTH_5:
986 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
987 				      phy_idx);
988 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
989 				      phy_idx);
990 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
991 				      0x0, phy_idx);
992 		break;
993 	case RTW89_CHANNEL_WIDTH_10:
994 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
995 				      phy_idx);
996 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
997 				      phy_idx);
998 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
999 				      0x0, phy_idx);
1000 		break;
1001 	case RTW89_CHANNEL_WIDTH_20:
1002 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1003 				      phy_idx);
1004 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1005 				      phy_idx);
1006 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1007 				      0x0, phy_idx);
1008 		break;
1009 	case RTW89_CHANNEL_WIDTH_40:
1010 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1011 				      phy_idx);
1012 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1013 				      phy_idx);
1014 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1015 				      pri_ch,
1016 				      phy_idx);
1017 		if (pri_ch == RTW89_SC_20_UPPER)
1018 			rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1019 		else
1020 			rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1021 		break;
1022 	case RTW89_CHANNEL_WIDTH_80:
1023 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1024 				      phy_idx);
1025 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1026 				      phy_idx);
1027 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1028 				      pri_ch,
1029 				      phy_idx);
1030 		break;
1031 	default:
1032 		rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1033 			   pri_ch);
1034 	}
1035 
1036 	if (phy_idx == RTW89_PHY_0) {
1037 		rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
1038 		if (!rtwdev->dbcc_en)
1039 			rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1040 	} else {
1041 		rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1042 	}
1043 }
1044 
rtw8852a_spur_elimination(struct rtw89_dev * rtwdev,u8 central_ch)1045 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1046 {
1047 	if (central_ch == 153) {
1048 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1049 				       0x210);
1050 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1051 				       0x210);
1052 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);
1053 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1054 				       B_P0_NBIIDX_NOTCH_EN, 0x1);
1055 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1056 				       B_P1_NBIIDX_NOTCH_EN, 0x1);
1057 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1058 				       0x1);
1059 	} else if (central_ch == 151) {
1060 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1061 				       0x210);
1062 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1063 				       0x210);
1064 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);
1065 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1066 				       B_P0_NBIIDX_NOTCH_EN, 0x1);
1067 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1068 				       B_P1_NBIIDX_NOTCH_EN, 0x1);
1069 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1070 				       0x1);
1071 	} else if (central_ch == 155) {
1072 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1073 				       0x2d0);
1074 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1075 				       0x2d0);
1076 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);
1077 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1078 				       B_P0_NBIIDX_NOTCH_EN, 0x1);
1079 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1080 				       B_P1_NBIIDX_NOTCH_EN, 0x1);
1081 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1082 				       0x1);
1083 	} else {
1084 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1085 				       B_P0_NBIIDX_NOTCH_EN, 0x0);
1086 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1087 				       B_P1_NBIIDX_NOTCH_EN, 0x0);
1088 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1089 				       0x0);
1090 	}
1091 }
1092 
rtw8852a_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1093 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1094 				  enum rtw89_phy_idx phy_idx)
1095 {
1096 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1097 			      phy_idx);
1098 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1099 			      phy_idx);
1100 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1101 			      phy_idx);
1102 }
1103 
rtw8852a_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,bool en)1104 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1105 				 enum rtw89_phy_idx phy_idx, bool en)
1106 {
1107 	if (en)
1108 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1109 				      1,
1110 				      phy_idx);
1111 	else
1112 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1113 				      0,
1114 				      phy_idx);
1115 }
1116 
rtw8852a_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1117 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1118 			      enum rtw89_phy_idx phy_idx)
1119 {
1120 	rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1121 	rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1122 	rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1123 	rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1124 	rtw8852a_bb_reset_all(rtwdev, phy_idx);
1125 	rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1126 	rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1127 	rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1128 	rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1129 }
1130 
rtw8852a_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1131 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1132 					enum rtw89_phy_idx phy_idx)
1133 {
1134 	u32 addr;
1135 
1136 	for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1137 	     addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1138 		rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1139 }
1140 
rtw8852a_bb_sethw(struct rtw89_dev * rtwdev)1141 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1142 {
1143 	rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1144 	rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1145 
1146 	if (rtwdev->hal.cv <= CHIP_CCV) {
1147 		rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1148 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
1149 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);
1150 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
1151 		rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1152 		rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1153 		rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1154 		rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
1155 	}
1156 	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
1157 	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
1158 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1159 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
1160 	rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1161 	rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1162 
1163 	rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1164 }
1165 
rtw8852a_bbrst_for_rfk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1166 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1167 				   enum rtw89_phy_idx phy_idx)
1168 {
1169 	rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1170 	rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1171 	rtw8852a_bb_reset_all(rtwdev, phy_idx);
1172 	rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1173 	rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1174 	udelay(1);
1175 }
1176 
rtw8852a_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1177 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1178 				    const struct rtw89_chan *chan,
1179 				    enum rtw89_phy_idx phy_idx)
1180 {
1181 	bool cck_en = chan->channel <= 14;
1182 	u8 pri_ch_idx = chan->pri_ch_idx;
1183 
1184 	if (cck_en)
1185 		rtw8852a_ctrl_sco_cck(rtwdev, chan->channel,
1186 				      chan->primary_channel,
1187 				      chan->band_width);
1188 
1189 	rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx);
1190 	rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1191 	if (cck_en) {
1192 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1193 	} else {
1194 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1195 		rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1196 	}
1197 	rtw8852a_spur_elimination(rtwdev, chan->channel);
1198 	rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1199 			       chan->primary_channel);
1200 	rtw8852a_bb_reset_all(rtwdev, phy_idx);
1201 }
1202 
rtw8852a_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1203 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1204 				 const struct rtw89_chan *chan,
1205 				 enum rtw89_mac_idx mac_idx,
1206 				 enum rtw89_phy_idx phy_idx)
1207 {
1208 	rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
1209 	rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
1210 }
1211 
rtw8852a_dfs_en(struct rtw89_dev * rtwdev,bool en)1212 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1213 {
1214 	if (en)
1215 		rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1216 	else
1217 		rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1218 }
1219 
rtw8852a_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1220 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1221 				  enum rtw89_rf_path path)
1222 {
1223 	static const u32 tssi_trk[2] = {0x5818, 0x7818};
1224 	static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};
1225 
1226 	if (en) {
1227 		rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
1228 		rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
1229 	} else {
1230 		rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
1231 		rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
1232 	}
1233 }
1234 
rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1235 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1236 					 u8 phy_idx)
1237 {
1238 	if (!rtwdev->dbcc_en) {
1239 		rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1240 		rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1241 	} else {
1242 		if (phy_idx == RTW89_PHY_0)
1243 			rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1244 		else
1245 			rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1246 	}
1247 }
1248 
rtw8852a_adc_en(struct rtw89_dev * rtwdev,bool en)1249 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1250 {
1251 	if (en)
1252 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1253 				       0x0);
1254 	else
1255 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1256 				       0xf);
1257 }
1258 
rtw8852a_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1259 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1260 				      struct rtw89_channel_help_params *p,
1261 				      const struct rtw89_chan *chan,
1262 				      enum rtw89_mac_idx mac_idx,
1263 				      enum rtw89_phy_idx phy_idx)
1264 {
1265 	if (enter) {
1266 		rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1267 				       RTW89_SCH_TX_SEL_ALL);
1268 		rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1269 		rtw8852a_dfs_en(rtwdev, false);
1270 		rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1271 		rtw8852a_adc_en(rtwdev, false);
1272 		fsleep(40);
1273 		rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
1274 	} else {
1275 		rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1276 		rtw8852a_adc_en(rtwdev, true);
1277 		rtw8852a_dfs_en(rtwdev, true);
1278 		rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1279 		rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
1280 		rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1281 	}
1282 }
1283 
rtw8852a_fem_setup(struct rtw89_dev * rtwdev)1284 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1285 {
1286 	struct rtw89_efuse *efuse = &rtwdev->efuse;
1287 
1288 	switch (efuse->rfe_type) {
1289 	case 11:
1290 	case 12:
1291 	case 17:
1292 	case 18:
1293 	case 51:
1294 	case 53:
1295 		rtwdev->fem.epa_2g = true;
1296 		rtwdev->fem.elna_2g = true;
1297 		fallthrough;
1298 	case 9:
1299 	case 10:
1300 	case 15:
1301 	case 16:
1302 		rtwdev->fem.epa_5g = true;
1303 		rtwdev->fem.elna_5g = true;
1304 		break;
1305 	default:
1306 		break;
1307 	}
1308 }
1309 
rtw8852a_rfk_init(struct rtw89_dev * rtwdev)1310 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1311 {
1312 	rtwdev->is_tssi_mode[RF_PATH_A] = false;
1313 	rtwdev->is_tssi_mode[RF_PATH_B] = false;
1314 
1315 	rtw8852a_rck(rtwdev);
1316 	rtw8852a_dack(rtwdev);
1317 	rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true);
1318 }
1319 
rtw8852a_rfk_channel(struct rtw89_dev * rtwdev)1320 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev)
1321 {
1322 	enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1323 
1324 	rtw8852a_rx_dck(rtwdev, phy_idx, true);
1325 	rtw8852a_iqk(rtwdev, phy_idx);
1326 	rtw8852a_tssi(rtwdev, phy_idx);
1327 	rtw8852a_dpk(rtwdev, phy_idx);
1328 }
1329 
rtw8852a_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1330 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
1331 				      enum rtw89_phy_idx phy_idx)
1332 {
1333 	rtw8852a_tssi_scan(rtwdev, phy_idx);
1334 }
1335 
rtw8852a_rfk_scan(struct rtw89_dev * rtwdev,bool start)1336 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1337 {
1338 	rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1339 }
1340 
rtw8852a_rfk_track(struct rtw89_dev * rtwdev)1341 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1342 {
1343 	rtw8852a_dpk_track(rtwdev);
1344 	rtw8852a_tssi_track(rtwdev);
1345 }
1346 
rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1347 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1348 				     enum rtw89_phy_idx phy_idx, s16 ref)
1349 {
1350 	s8 ofst_int = 0;
1351 	u8 base_cw_0db = 0x27;
1352 	u16 tssi_16dbm_cw = 0x12c;
1353 	s16 pwr_s10_3 = 0;
1354 	s16 rf_pwr_cw = 0;
1355 	u16 bb_pwr_cw = 0;
1356 	u32 pwr_cw = 0;
1357 	u32 tssi_ofst_cw = 0;
1358 
1359 	pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1360 	bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1361 	rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1362 	rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1363 	pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1364 
1365 	tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1366 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1367 		    "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1368 		    tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1369 
1370 	return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1371 }
1372 
1373 static
rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1374 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1375 				     s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1376 {
1377 	s8 val_1t = 0;
1378 	s8 val_2t = 0;
1379 	u32 reg;
1380 
1381 	if (pw_ofst < -16 || pw_ofst > 15) {
1382 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
1383 			    pw_ofst);
1384 		return;
1385 	}
1386 	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1387 	rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1388 	val_1t = pw_ofst;
1389 	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1390 	rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
1391 	val_2t = max(val_1t - 3, -16);
1392 	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1393 	rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
1394 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1395 		    val_1t, val_2t);
1396 }
1397 
rtw8852a_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1398 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1399 				   enum rtw89_phy_idx phy_idx)
1400 {
1401 	static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};
1402 	const u32 mask = 0x7FFFFFF;
1403 	const u8 ofst_ofdm = 0x4;
1404 	const u8 ofst_cck = 0x8;
1405 	s16 ref_ofdm = 0;
1406 	s16 ref_cck = 0;
1407 	u32 val;
1408 	u8 i;
1409 
1410 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1411 
1412 	rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1413 				     GENMASK(27, 10), 0x0);
1414 
1415 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1416 	val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1417 
1418 	for (i = 0; i < RF_PATH_NUM_8852A; i++)
1419 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1420 				      phy_idx);
1421 
1422 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1423 	val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1424 
1425 	for (i = 0; i < RF_PATH_NUM_8852A; i++)
1426 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1427 				      phy_idx);
1428 }
1429 
rtw8852a_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1430 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
1431 			       const struct rtw89_chan *chan,
1432 			       enum rtw89_phy_idx phy_idx)
1433 {
1434 	rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1435 	rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1436 	rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1437 	rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1438 }
1439 
rtw8852a_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1440 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1441 				    enum rtw89_phy_idx phy_idx)
1442 {
1443 	rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
1444 }
1445 
1446 static int
rtw8852a_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1447 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1448 {
1449 	int ret;
1450 
1451 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1452 	if (ret)
1453 		return ret;
1454 
1455 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
1456 	if (ret)
1457 		return ret;
1458 
1459 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1460 	if (ret)
1461 		return ret;
1462 
1463 	return 0;
1464 }
1465 
rtw8852a_bb_set_plcp_tx(struct rtw89_dev * rtwdev)1466 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1467 {
1468 	u8 i = 0;
1469 	u32 addr, val;
1470 
1471 	for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {
1472 		addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr;
1473 		val = rtw8852a_pmac_ht20_mcs7_tbl[i].data;
1474 		rtw89_phy_write32(rtwdev, addr, val);
1475 	}
1476 }
1477 
rtw8852a_stop_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1478 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1479 				  struct rtw8852a_bb_pmac_info *tx_info,
1480 				  enum rtw89_phy_idx idx)
1481 {
1482 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1483 	if (tx_info->mode == CONT_TX)
1484 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
1485 				      idx);
1486 	else if (tx_info->mode == PKTS_TX)
1487 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
1488 				      idx);
1489 }
1490 
rtw8852a_start_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1491 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1492 				   struct rtw8852a_bb_pmac_info *tx_info,
1493 				   enum rtw89_phy_idx idx)
1494 {
1495 	enum rtw8852a_pmac_mode mode = tx_info->mode;
1496 	u32 pkt_cnt = tx_info->tx_cnt;
1497 	u16 period = tx_info->period;
1498 
1499 	if (mode == CONT_TX && !tx_info->is_cck) {
1500 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
1501 				      idx);
1502 		rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1503 	} else if (mode == PKTS_TX) {
1504 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
1505 				      idx);
1506 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1507 				      B_PMAC_TX_PRD_MSK, period, idx);
1508 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1509 				      pkt_cnt, idx);
1510 		rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1511 	}
1512 	rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1513 	rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1514 }
1515 
rtw8852a_bb_set_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1516 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1517 			     struct rtw8852a_bb_pmac_info *tx_info,
1518 			     enum rtw89_phy_idx idx)
1519 {
1520 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1521 
1522 	if (!tx_info->en_pmac_tx) {
1523 		rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1524 		rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1525 		if (chan->band_type == RTW89_BAND_2G)
1526 			rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1527 		return;
1528 	}
1529 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1530 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1531 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1532 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
1533 			      idx);
1534 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1535 	rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1536 	rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1537 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1538 	rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1539 }
1540 
rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev * rtwdev,u8 enable,u16 tx_cnt,u16 period,u16 tx_time,enum rtw89_phy_idx idx)1541 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1542 				 u16 tx_cnt, u16 period, u16 tx_time,
1543 				 enum rtw89_phy_idx idx)
1544 {
1545 	struct rtw8852a_bb_pmac_info tx_info = {0};
1546 
1547 	tx_info.en_pmac_tx = enable;
1548 	tx_info.is_cck = 0;
1549 	tx_info.mode = PKTS_TX;
1550 	tx_info.tx_cnt = tx_cnt;
1551 	tx_info.period = period;
1552 	tx_info.tx_time = tx_time;
1553 	rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx);
1554 }
1555 
rtw8852a_bb_set_power(struct rtw89_dev * rtwdev,s16 pwr_dbm,enum rtw89_phy_idx idx)1556 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1557 			   enum rtw89_phy_idx idx)
1558 {
1559 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1560 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1561 	rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1562 }
1563 
rtw8852a_bb_cfg_tx_path(struct rtw89_dev * rtwdev,u8 tx_path)1564 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1565 {
1566 	u32 rst_mask0 = 0;
1567 	u32 rst_mask1 = 0;
1568 
1569 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1570 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
1571 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1572 	if (!rtwdev->dbcc_en) {
1573 		if (tx_path == RF_PATH_A) {
1574 			rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1575 					       B_TXPATH_SEL_MSK, 1);
1576 			rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1577 					       B_TXNSS_MAP_MSK, 0);
1578 		} else if (tx_path == RF_PATH_B) {
1579 			rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1580 					       B_TXPATH_SEL_MSK, 2);
1581 			rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1582 					       B_TXNSS_MAP_MSK, 0);
1583 		} else if (tx_path == RF_PATH_AB) {
1584 			rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1585 					       B_TXPATH_SEL_MSK, 3);
1586 			rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1587 					       B_TXNSS_MAP_MSK, 4);
1588 		} else {
1589 			rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1590 		}
1591 	} else {
1592 		rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1593 				       1);
1594 		rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
1595 				      RTW89_PHY_1);
1596 		rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1597 				       0);
1598 		rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
1599 				      RTW89_PHY_1);
1600 	}
1601 	rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1602 	rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1603 	if (tx_path == RF_PATH_A) {
1604 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1605 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1606 	} else {
1607 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1608 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1609 	}
1610 }
1611 
rtw8852a_bb_tx_mode_switch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,u8 mode)1612 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1613 				enum rtw89_phy_idx idx, u8 mode)
1614 {
1615 	if (mode != 0)
1616 		return;
1617 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1618 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1619 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1620 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1621 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1622 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1623 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1624 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1625 }
1626 
rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)1627 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1628 {
1629 	rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl :
1630 						 &rtw8852a_btc_preagc_dis_defs_tbl);
1631 }
1632 
rtw8852a_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1633 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1634 {
1635 	if (rtwdev->is_tssi_mode[rf_path]) {
1636 		u32 addr = 0x1c10 + (rf_path << 13);
1637 
1638 		return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1639 	}
1640 
1641 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1642 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1643 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1644 
1645 	fsleep(200);
1646 
1647 	return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1648 }
1649 
rtw8852a_btc_set_rfe(struct rtw89_dev * rtwdev)1650 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1651 {
1652 	struct rtw89_btc *btc = &rtwdev->btc;
1653 	struct rtw89_btc_module *module = &btc->mdinfo;
1654 
1655 	module->rfe_type = rtwdev->efuse.rfe_type;
1656 	module->cv = rtwdev->hal.cv;
1657 	module->bt_solo = 0;
1658 	module->switch_type = BTC_SWITCH_INTERNAL;
1659 
1660 	if (module->rfe_type > 0)
1661 		module->ant.num = (module->rfe_type % 2 ? 2 : 3);
1662 	else
1663 		module->ant.num = 2;
1664 
1665 	module->ant.diversity = 0;
1666 	module->ant.isolation = 10;
1667 
1668 	if (module->ant.num == 3) {
1669 		module->ant.type = BTC_ANT_DEDICATED;
1670 		module->bt_pos = BTC_BT_ALONE;
1671 	} else {
1672 		module->ant.type = BTC_ANT_SHARED;
1673 		module->bt_pos = BTC_BT_BTG;
1674 	}
1675 }
1676 
1677 static
rtw8852a_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1678 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1679 {
1680 	rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
1681 	rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
1682 	rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
1683 	rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
1684 }
1685 
rtw8852a_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)1686 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1687 {
1688 	if (btg) {
1689 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
1690 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
1691 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1692 	} else {
1693 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
1694 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
1695 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
1696 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
1697 	}
1698 }
1699 
rtw8852a_btc_init_cfg(struct rtw89_dev * rtwdev)1700 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1701 {
1702 	struct rtw89_btc *btc = &rtwdev->btc;
1703 	struct rtw89_btc_module *module = &btc->mdinfo;
1704 	const struct rtw89_chip_info *chip = rtwdev->chip;
1705 	const struct rtw89_mac_ax_coex coex_params = {
1706 		.pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1707 		.direction = RTW89_MAC_AX_COEX_INNER,
1708 	};
1709 
1710 	/* PTA init  */
1711 	rtw89_mac_coex_init(rtwdev, &coex_params);
1712 
1713 	/* set WL Tx response = Hi-Pri */
1714 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1715 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1716 
1717 	/* set rf gnt debug off */
1718 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
1719 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
1720 
1721 	/* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1722 	if (module->ant.type == BTC_ANT_SHARED) {
1723 		rtw8852a_set_trx_mask(rtwdev,
1724 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
1725 		rtw8852a_set_trx_mask(rtwdev,
1726 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
1727 		/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1728 		rtw8852a_set_trx_mask(rtwdev,
1729 				      RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1730 	} else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1731 		rtw8852a_set_trx_mask(rtwdev,
1732 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
1733 		rtw8852a_set_trx_mask(rtwdev,
1734 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
1735 	}
1736 
1737 	/* set PTA break table */
1738 	rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1739 
1740 	 /* enable BT counter 0xda40[16,2] = 2b'11 */
1741 	rtw89_write32_set(rtwdev,
1742 			  R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1743 	btc->cx.wl.status.map.init_ok = true;
1744 }
1745 
1746 static
rtw8852a_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)1747 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1748 {
1749 	u32 bitmap = 0;
1750 	u32 reg = 0;
1751 
1752 	switch (map) {
1753 	case BTC_PRI_MASK_TX_RESP:
1754 		reg = R_BTC_BT_COEX_MSK_TABLE;
1755 		bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1756 		break;
1757 	case BTC_PRI_MASK_BEACON:
1758 		reg = R_AX_WL_PRI_MSK;
1759 		bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1760 		break;
1761 	default:
1762 		return;
1763 	}
1764 
1765 	if (state)
1766 		rtw89_write32_set(rtwdev, reg, bitmap);
1767 	else
1768 		rtw89_write32_clr(rtwdev, reg, bitmap);
1769 }
1770 
__btc_ctrl_val_all_time(u32 ctrl)1771 static inline u32 __btc_ctrl_val_all_time(u32 ctrl)
1772 {
1773 	return FIELD_GET(GENMASK(15, 0), ctrl);
1774 }
1775 
__btc_ctrl_rst_all_time(u32 cur)1776 static inline u32 __btc_ctrl_rst_all_time(u32 cur)
1777 {
1778 	return cur & ~B_AX_FORCE_PWR_BY_RATE_EN;
1779 }
1780 
__btc_ctrl_gen_all_time(u32 cur,u32 val)1781 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)
1782 {
1783 	u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1784 	u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1785 
1786 	return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN;
1787 }
1788 
__btc_ctrl_val_gnt_bt(u32 ctrl)1789 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)
1790 {
1791 	return FIELD_GET(GENMASK(31, 16), ctrl);
1792 }
1793 
__btc_ctrl_rst_gnt_bt(u32 cur)1794 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)
1795 {
1796 	return cur & ~B_AX_TXAGC_BT_EN;
1797 }
1798 
__btc_ctrl_gen_gnt_bt(u32 cur,u32 val)1799 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)
1800 {
1801 	u32 ov = cur & ~B_AX_TXAGC_BT_MASK;
1802 	u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val);
1803 
1804 	return ov | iv | B_AX_TXAGC_BT_EN;
1805 }
1806 
1807 static void
rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)1808 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1809 {
1810 	const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL;
1811 	const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL;
1812 
1813 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0))
1814 #define __handle(_case)							\
1815 	do {								\
1816 		const u32 _reg = __btc_cr_ ## _case;			\
1817 		u32 _val = __btc_ctrl_val_ ## _case(txpwr_val);		\
1818 		u32 _cur, _wrt;						\
1819 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,			\
1820 			    "btc ctrl %s: 0x%x\n", #_case, _val);	\
1821 		if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
1822 			break;						\
1823 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,			\
1824 			    "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur);	\
1825 		_wrt = __do_clr(_val) ?					\
1826 			__btc_ctrl_rst_ ## _case(_cur) :		\
1827 			__btc_ctrl_gen_ ## _case(_cur, _val);		\
1828 		rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
1829 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,			\
1830 			    "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt);	\
1831 	} while (0)
1832 
1833 	__handle(all_time);
1834 	__handle(gnt_bt);
1835 
1836 #undef __handle
1837 #undef __do_clr
1838 }
1839 
1840 static
rtw8852a_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)1841 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1842 {
1843 	/* +6 for compensate offset */
1844 	return clamp_t(s8, val + 6, -100, 0) + 100;
1845 }
1846 
1847 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = {
1848 	{255, 0, 0, 7}, /* 0 -> original */
1849 	{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
1850 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1851 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1852 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1853 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1854 	{6, 1, 0, 7},
1855 	{13, 1, 0, 7},
1856 	{13, 1, 0, 7}
1857 };
1858 
1859 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = {
1860 	{255, 0, 0, 7}, /* 0 -> original */
1861 	{255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
1862 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1863 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1864 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1865 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1866 	{255, 1, 0, 7},
1867 	{255, 1, 0, 7},
1868 	{255, 1, 0, 7}
1869 };
1870 
1871 static const
1872 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
1873 static const
1874 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
1875 
1876 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
1877 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
1878 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
1879 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
1880 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
1881 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
1882 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
1883 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
1884 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
1885 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
1886 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
1887 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
1888 	RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
1889 };
1890 
1891 static
rtw8852a_btc_update_bt_cnt(struct rtw89_dev * rtwdev)1892 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1893 {
1894 	struct rtw89_btc *btc = &rtwdev->btc;
1895 	const struct rtw89_btc_ver *ver = btc->ver;
1896 	struct rtw89_btc_cx *cx = &btc->cx;
1897 	u32 val;
1898 
1899 	if (ver->fcxbtcrpt != 1)
1900 		return;
1901 
1902 	val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
1903 	cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
1904 	cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
1905 
1906 	val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
1907 	cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
1908 	cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
1909 
1910 	/* clock-gate off before reset counter*/
1911 	rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1912 	rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1913 	rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1914 	rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1915 }
1916 
1917 static
rtw8852a_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)1918 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1919 {
1920 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1921 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1922 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
1923 
1924 	/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
1925 	if (state)
1926 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1927 			       RFREG_MASK, 0xa2d7c);
1928 	else
1929 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1930 			       RFREG_MASK, 0xa2020);
1931 
1932 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1933 }
1934 
rtw8852a_set_wl_lna2(struct rtw89_dev * rtwdev,u8 level)1935 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
1936 {
1937 	/* level=0 Default:    TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
1938 	 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
1939 	 * To improve BT ACI in co-rx
1940 	 */
1941 
1942 	switch (level) {
1943 	case 0: /* default */
1944 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1945 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1946 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1947 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1948 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1949 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1950 		break;
1951 	case 1: /* Fix LNA2=5  */
1952 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1953 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1954 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
1955 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1956 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1957 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1958 		break;
1959 	}
1960 }
1961 
rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)1962 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
1963 {
1964 	struct rtw89_btc *btc = &rtwdev->btc;
1965 
1966 	switch (level) {
1967 	case 0: /* original */
1968 	default:
1969 		rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
1970 		btc->dm.wl_lna2 = 0;
1971 		break;
1972 	case 1: /* for FDD free-run */
1973 		rtw8852a_bb_ctrl_btc_preagc(rtwdev, true);
1974 		btc->dm.wl_lna2 = 0;
1975 		break;
1976 	case 2: /* for BTG Co-Rx*/
1977 		rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
1978 		btc->dm.wl_lna2 = 1;
1979 		break;
1980 	}
1981 
1982 	rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
1983 }
1984 
rtw8852a_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)1985 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
1986 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
1987 					 struct ieee80211_rx_status *status)
1988 {
1989 	u16 chan = phy_ppdu->chan_idx;
1990 	u8 band;
1991 
1992 	if (chan == 0)
1993 		return;
1994 
1995 	band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1996 	status->freq = ieee80211_channel_to_frequency(chan, band);
1997 	status->band = band;
1998 }
1999 
rtw8852a_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2000 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
2001 				struct rtw89_rx_phy_ppdu *phy_ppdu,
2002 				struct ieee80211_rx_status *status)
2003 {
2004 	u8 path;
2005 	u8 *rx_power = phy_ppdu->rssi;
2006 
2007 	status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
2008 	for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2009 		status->chains |= BIT(path);
2010 		status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2011 	}
2012 	if (phy_ppdu->valid)
2013 		rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2014 }
2015 
2016 #ifdef CONFIG_PM
2017 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
2018 	.flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2019 	.n_patterns = RTW89_MAX_PATTERN_NUM,
2020 	.pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2021 	.pattern_min_len = 1,
2022 };
2023 #endif
2024 
2025 static const struct rtw89_chip_ops rtw8852a_chip_ops = {
2026 	.enable_bb_rf		= rtw89_mac_enable_bb_rf,
2027 	.disable_bb_rf		= rtw89_mac_disable_bb_rf,
2028 	.bb_reset		= rtw8852a_bb_reset,
2029 	.bb_sethw		= rtw8852a_bb_sethw,
2030 	.read_rf		= rtw89_phy_read_rf,
2031 	.write_rf		= rtw89_phy_write_rf,
2032 	.set_channel		= rtw8852a_set_channel,
2033 	.set_channel_help	= rtw8852a_set_channel_help,
2034 	.read_efuse		= rtw8852a_read_efuse,
2035 	.read_phycap		= rtw8852a_read_phycap,
2036 	.fem_setup		= rtw8852a_fem_setup,
2037 	.rfe_gpio		= NULL,
2038 	.rfk_init		= rtw8852a_rfk_init,
2039 	.rfk_channel		= rtw8852a_rfk_channel,
2040 	.rfk_band_changed	= rtw8852a_rfk_band_changed,
2041 	.rfk_scan		= rtw8852a_rfk_scan,
2042 	.rfk_track		= rtw8852a_rfk_track,
2043 	.power_trim		= rtw8852a_power_trim,
2044 	.set_txpwr		= rtw8852a_set_txpwr,
2045 	.set_txpwr_ctrl		= rtw8852a_set_txpwr_ctrl,
2046 	.init_txpwr_unit	= rtw8852a_init_txpwr_unit,
2047 	.get_thermal		= rtw8852a_get_thermal,
2048 	.ctrl_btg		= rtw8852a_ctrl_btg,
2049 	.query_ppdu		= rtw8852a_query_ppdu,
2050 	.bb_ctrl_btc_preagc	= rtw8852a_bb_ctrl_btc_preagc,
2051 	.cfg_txrx_path		= NULL,
2052 	.set_txpwr_ul_tb_offset	= rtw8852a_set_txpwr_ul_tb_offset,
2053 	.pwr_on_func		= NULL,
2054 	.pwr_off_func		= NULL,
2055 	.query_rxdesc		= rtw89_core_query_rxdesc,
2056 	.fill_txdesc		= rtw89_core_fill_txdesc,
2057 	.fill_txdesc_fwcmd	= rtw89_core_fill_txdesc,
2058 	.cfg_ctrl_path		= rtw89_mac_cfg_ctrl_path,
2059 	.mac_cfg_gnt		= rtw89_mac_cfg_gnt,
2060 	.stop_sch_tx		= rtw89_mac_stop_sch_tx,
2061 	.resume_sch_tx		= rtw89_mac_resume_sch_tx,
2062 	.h2c_dctl_sec_cam	= NULL,
2063 
2064 	.btc_set_rfe		= rtw8852a_btc_set_rfe,
2065 	.btc_init_cfg		= rtw8852a_btc_init_cfg,
2066 	.btc_set_wl_pri		= rtw8852a_btc_set_wl_pri,
2067 	.btc_set_wl_txpwr_ctrl	= rtw8852a_btc_set_wl_txpwr_ctrl,
2068 	.btc_get_bt_rssi	= rtw8852a_btc_get_bt_rssi,
2069 	.btc_update_bt_cnt	= rtw8852a_btc_update_bt_cnt,
2070 	.btc_wl_s1_standby	= rtw8852a_btc_wl_s1_standby,
2071 	.btc_set_wl_rx_gain	= rtw8852a_btc_set_wl_rx_gain,
2072 	.btc_set_policy		= rtw89_btc_set_policy,
2073 };
2074 
2075 const struct rtw89_chip_info rtw8852a_chip_info = {
2076 	.chip_id		= RTL8852A,
2077 	.chip_gen		= RTW89_CHIP_AX,
2078 	.ops			= &rtw8852a_chip_ops,
2079 	.mac_def		= &rtw89_mac_gen_ax,
2080 	.phy_def		= &rtw89_phy_gen_ax,
2081 	.fw_basename		= RTW8852A_FW_BASENAME,
2082 	.fw_format_max		= RTW8852A_FW_FORMAT_MAX,
2083 	.try_ce_fw		= false,
2084 	.needed_fw_elms		= 0,
2085 	.fifo_size		= 458752,
2086 	.small_fifo_size	= false,
2087 	.dle_scc_rsvd_size	= 0,
2088 	.max_amsdu_limit	= 3500,
2089 	.dis_2g_40m_ul_ofdma	= true,
2090 	.rsvd_ple_ofst		= 0x6f800,
2091 	.hfc_param_ini		= rtw8852a_hfc_param_ini_pcie,
2092 	.dle_mem		= rtw8852a_dle_mem_pcie,
2093 	.wde_qempty_acq_num	= 16,
2094 	.wde_qempty_mgq_sel	= 16,
2095 	.rf_base_addr		= {0xc000, 0xd000},
2096 	.pwr_on_seq		= pwr_on_seq_8852a,
2097 	.pwr_off_seq		= pwr_off_seq_8852a,
2098 	.bb_table		= &rtw89_8852a_phy_bb_table,
2099 	.bb_gain_table		= NULL,
2100 	.rf_table		= {&rtw89_8852a_phy_radioa_table,
2101 				   &rtw89_8852a_phy_radiob_table,},
2102 	.nctl_table		= &rtw89_8852a_phy_nctl_table,
2103 	.nctl_post_table	= NULL,
2104 	.byr_table		= &rtw89_8852a_byr_table,
2105 	.dflt_parms		= &rtw89_8852a_dflt_parms,
2106 	.rfe_parms_conf		= NULL,
2107 	.txpwr_factor_rf	= 2,
2108 	.txpwr_factor_mac	= 1,
2109 	.dig_table		= &rtw89_8852a_phy_dig_table,
2110 	.dig_regs		= &rtw8852a_dig_regs,
2111 	.tssi_dbw_table		= NULL,
2112 	.support_chanctx_num	= 1,
2113 	.support_bands		= BIT(NL80211_BAND_2GHZ) |
2114 				  BIT(NL80211_BAND_5GHZ),
2115 	.support_bw160		= false,
2116 	.support_unii4		= false,
2117 	.support_ul_tb_ctrl     = false,
2118 	.hw_sec_hdr		= false,
2119 	.rf_path_num		= 2,
2120 	.tx_nss			= 2,
2121 	.rx_nss			= 2,
2122 	.acam_num		= 128,
2123 	.bcam_num		= 10,
2124 	.scam_num		= 128,
2125 	.bacam_num		= 2,
2126 	.bacam_dynamic_num	= 4,
2127 	.bacam_ver		= RTW89_BACAM_V0,
2128 	.sec_ctrl_efuse_size	= 4,
2129 	.physical_efuse_size	= 1216,
2130 	.logical_efuse_size	= 1536,
2131 	.limit_efuse_size	= 1152,
2132 	.dav_phy_efuse_size	= 0,
2133 	.dav_log_efuse_size	= 0,
2134 	.phycap_addr		= 0x580,
2135 	.phycap_size		= 128,
2136 	.para_ver		= 0x0,
2137 	.wlcx_desired		= 0x06000000,
2138 	.btcx_desired		= 0x7,
2139 	.scbd			= 0x1,
2140 	.mailbox		= 0x1,
2141 
2142 	.afh_guard_ch		= 6,
2143 	.wl_rssi_thres		= rtw89_btc_8852a_wl_rssi_thres,
2144 	.bt_rssi_thres		= rtw89_btc_8852a_bt_rssi_thres,
2145 	.rssi_tol		= 2,
2146 	.mon_reg_num		= ARRAY_SIZE(rtw89_btc_8852a_mon_reg),
2147 	.mon_reg		= rtw89_btc_8852a_mon_reg,
2148 	.rf_para_ulink_num	= ARRAY_SIZE(rtw89_btc_8852a_rf_ul),
2149 	.rf_para_ulink		= rtw89_btc_8852a_rf_ul,
2150 	.rf_para_dlink_num	= ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
2151 	.rf_para_dlink		= rtw89_btc_8852a_rf_dl,
2152 	.ps_mode_supported	= BIT(RTW89_PS_MODE_RFOFF) |
2153 				  BIT(RTW89_PS_MODE_CLK_GATED) |
2154 				  BIT(RTW89_PS_MODE_PWR_GATED),
2155 	.low_power_hci_modes	= 0,
2156 	.h2c_cctl_func_id	= H2C_FUNC_MAC_CCTLINFO_UD,
2157 	.hci_func_en_addr	= R_AX_HCI_FUNC_EN,
2158 	.h2c_desc_size		= sizeof(struct rtw89_txwd_body),
2159 	.txwd_body_size		= sizeof(struct rtw89_txwd_body),
2160 	.h2c_ctrl_reg		= R_AX_H2CREG_CTRL,
2161 	.h2c_counter_reg	= {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2162 	.h2c_regs		= rtw8852a_h2c_regs,
2163 	.c2h_ctrl_reg		= R_AX_C2HREG_CTRL,
2164 	.c2h_regs		= rtw8852a_c2h_regs,
2165 	.c2h_counter_reg	= {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2166 	.page_regs		= &rtw8852a_page_regs,
2167 	.cfo_src_fd		= false,
2168 	.cfo_hw_comp            = false,
2169 	.dcfo_comp		= &rtw8852a_dcfo_comp,
2170 	.dcfo_comp_sft		= 10,
2171 	.imr_info		= &rtw8852a_imr_info,
2172 	.rrsr_cfgs		= &rtw8852a_rrsr_cfgs,
2173 	.bss_clr_map_reg	= R_BSS_CLR_MAP,
2174 	.dma_ch_mask		= 0,
2175 	.edcca_lvl_reg		= R_SEG0R_EDCCA_LVL,
2176 #ifdef CONFIG_PM
2177 	.wowlan_stub		= &rtw_wowlan_stub_8852a,
2178 #endif
2179 	.xtal_info		= &rtw8852a_xtal_info,
2180 };
2181 EXPORT_SYMBOL(rtw8852a_chip_info);
2182 
2183 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE);
2184 MODULE_AUTHOR("Realtek Corporation");
2185 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver");
2186 MODULE_LICENSE("Dual BSD/GPL");
2187