1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rtw8851b.h"
12 #include "rtw8851b_rfk.h"
13 #include "rtw8851b_rfk_table.h"
14 #include "rtw8851b_table.h"
15 #include "txrx.h"
16 #include "util.h"
17
18 #define RTW8851B_FW_FORMAT_MAX 0
19 #define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
20 #define RTW8851B_MODULE_FIRMWARE \
21 RTW8851B_FW_BASENAME ".bin"
22
23 static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
24 {5, 343, grp_0}, /* ACH 0 */
25 {5, 343, grp_0}, /* ACH 1 */
26 {5, 343, grp_0}, /* ACH 2 */
27 {5, 343, grp_0}, /* ACH 3 */
28 {0, 0, grp_0}, /* ACH 4 */
29 {0, 0, grp_0}, /* ACH 5 */
30 {0, 0, grp_0}, /* ACH 6 */
31 {0, 0, grp_0}, /* ACH 7 */
32 {4, 344, grp_0}, /* B0MGQ */
33 {4, 344, grp_0}, /* B0HIQ */
34 {0, 0, grp_0}, /* B1MGQ */
35 {0, 0, grp_0}, /* B1HIQ */
36 {40, 0, 0} /* FWCMDQ */
37 };
38
39 static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = {
40 448, /* Group 0 */
41 0, /* Group 1 */
42 448, /* Public Max */
43 0 /* WP threshold */
44 };
45
46 static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
47 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie,
48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
50 RTW89_HCIFC_POH},
51 [RTW89_QTA_INVALID] = {NULL},
52 };
53
54 static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
55 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
56 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
57 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
58 &rtw89_mac_size.ple_qt58},
59 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6,
60 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
61 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
62 &rtw89_mac_size.ple_qt_51b_wow},
63 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
64 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
65 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
66 &rtw89_mac_size.ple_qt13},
67 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
68 NULL},
69 };
70
71 static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = {
72 {0x46D0, GENMASK(1, 0), 0x3},
73 {0x4AD4, GENMASK(31, 0), 0xf},
74 {0x4688, GENMASK(23, 16), 0x80},
75 {0x4688, GENMASK(31, 24), 0x80},
76 {0x4694, GENMASK(7, 0), 0x80},
77 {0x4694, GENMASK(15, 8), 0x80},
78 {0x4AE4, GENMASK(11, 6), 0x34},
79 {0x4AE4, GENMASK(17, 12), 0x0},
80 {0x469C, GENMASK(31, 26), 0x34},
81 };
82
83 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs);
84
85 static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = {
86 {0x46D0, GENMASK(1, 0), 0x0},
87 {0x4AD4, GENMASK(31, 0), 0x60},
88 {0x4688, GENMASK(23, 16), 0x10},
89 {0x4690, GENMASK(31, 24), 0x2a},
90 {0x4694, GENMASK(15, 8), 0x2a},
91 {0x4AE4, GENMASK(11, 6), 0x26},
92 {0x4AE4, GENMASK(17, 12), 0x1e},
93 {0x469C, GENMASK(31, 26), 0x26},
94 };
95
96 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs);
97
98 static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = {
99 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
100 R_AX_H2CREG_DATA3
101 };
102
103 static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
104 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
105 R_AX_C2HREG_DATA3
106 };
107
108 static const struct rtw89_page_regs rtw8851b_page_regs = {
109 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
110 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
111 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
112 .ach_page_info = R_AX_ACH0_PAGE_INFO,
113 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
114 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
115 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
116 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
117 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
118 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
119 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
120 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
121 };
122
123 static const struct rtw89_reg_def rtw8851b_dcfo_comp = {
124 R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2
125 };
126
127 static const struct rtw89_imr_info rtw8851b_imr_info = {
128 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
129 .wsec_imr_reg = R_AX_SEC_DEBUG,
130 .wsec_imr_set = B_AX_IMR_ERROR,
131 .mpdu_tx_imr_set = 0,
132 .mpdu_rx_imr_set = 0,
133 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
134 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
135 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
136 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
137 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
138 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
139 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
140 .wde_imr_clr = B_AX_WDE_IMR_CLR,
141 .wde_imr_set = B_AX_WDE_IMR_SET,
142 .ple_imr_clr = B_AX_PLE_IMR_CLR,
143 .ple_imr_set = B_AX_PLE_IMR_SET,
144 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
145 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
146 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
147 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
148 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
149 .other_disp_imr_set = 0,
150 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
151 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
152 .bbrpt_err_imr_set = 0,
153 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
154 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
155 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
156 .cdma_imr_0_reg = R_AX_DLE_CTRL,
157 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
158 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
159 .cdma_imr_1_reg = 0,
160 .cdma_imr_1_clr = 0,
161 .cdma_imr_1_set = 0,
162 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
163 .phy_intf_imr_clr = 0,
164 .phy_intf_imr_set = 0,
165 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
166 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
167 .rmac_imr_set = B_AX_RMAC_IMR_SET,
168 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
169 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
170 .tmac_imr_set = B_AX_TMAC_IMR_SET,
171 };
172
173 static const struct rtw89_xtal_info rtw8851b_xtal_info = {
174 .xcap_reg = R_AX_XTAL_ON_CTRL3,
175 .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK,
176 .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK,
177 };
178
179 static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = {
180 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
181 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
182 };
183
184 static const struct rtw89_dig_regs rtw8851b_dig_regs = {
185 .seg0_pd_reg = R_SEG0R_PD_V1,
186 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
187 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
188 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
189 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
190 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
191 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
192 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
193 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
194 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
195 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
196 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
197 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
198 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
199 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
200 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
201 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
202 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
203 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
204 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
205 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
206 };
207
208 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
209 {255, 0, 0, 7}, /* 0 -> original */
210 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
211 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
212 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
213 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
214 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
215 {6, 1, 0, 7},
216 {13, 1, 0, 7},
217 {13, 1, 0, 7}
218 };
219
220 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = {
221 {255, 0, 0, 7}, /* 0 -> original */
222 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
223 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
224 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
225 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
226 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
227 {255, 1, 0, 7},
228 {255, 1, 0, 7},
229 {255, 1, 0, 7}
230 };
231
232 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = {
233 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
234 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
235 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
236 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
237 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
238 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
239 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
240 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
241 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
242 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
243 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
244 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
245 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
246 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
247 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
248 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
249 };
250
251 static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
252 static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
253
rtw8851b_pwr_on_func(struct rtw89_dev * rtwdev)254 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
255 {
256 u32 val32;
257 u8 val8;
258 u32 ret;
259
260 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
261 B_AX_AFSM_PCIE_SUS_EN);
262 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
263 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
264 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
265 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
266
267 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
268 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
269 if (ret)
270 return ret;
271
272 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
273 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
274
275 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
276 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
277 if (ret)
278 return ret;
279
280 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
281 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
282 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
283 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
284
285 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
286 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
287
288 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
289 XTAL_SI_OFF_WEI);
290 if (ret)
291 return ret;
292 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
293 XTAL_SI_OFF_EI);
294 if (ret)
295 return ret;
296 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
297 if (ret)
298 return ret;
299 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
300 XTAL_SI_PON_WEI);
301 if (ret)
302 return ret;
303 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
304 XTAL_SI_PON_EI);
305 if (ret)
306 return ret;
307 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
308 if (ret)
309 return ret;
310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
311 if (ret)
312 return ret;
313 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
314 if (ret)
315 return ret;
316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
317 if (ret)
318 return ret;
319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
320 if (ret)
321 return ret;
322
323 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
324 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
325 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
326
327 fsleep(1000);
328
329 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
330 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
331 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
332 B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1);
333
334 if (rtwdev->hal.cv == CHIP_CAV) {
335 ret = rtw89_read_efuse_ver(rtwdev, &val8);
336 if (!ret)
337 rtwdev->hal.cv = val8;
338 }
339
340 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
341 B_AX_XTAL_SI_ADDR_NOT_CHK);
342 if (rtwdev->hal.cv != CHIP_CAV) {
343 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
344 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
345 }
346
347 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
348 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
349 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
350 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
351 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
352 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
353 B_AX_DMACREG_GCKEN);
354 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
355 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
356 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
357 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
358 B_AX_RMAC_EN);
359
360 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
361 PINMUX_EESK_FUNC_SEL_BT_LOG);
362
363 return 0;
364 }
365
rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev * rtwdev)366 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
367 {
368 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
369 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
370 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
371 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
372 }
373
rtw8851b_pwr_off_func(struct rtw89_dev * rtwdev)374 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
375 {
376 u32 val32;
377 u32 ret;
378
379 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
380 XTAL_SI_RFC2RF);
381 if (ret)
382 return ret;
383 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
384 if (ret)
385 return ret;
386 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
387 if (ret)
388 return ret;
389 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
390 if (ret)
391 return ret;
392 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
393 XTAL_SI_SRAM2RFC);
394 if (ret)
395 return ret;
396 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
397 if (ret)
398 return ret;
399 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
400 if (ret)
401 return ret;
402
403 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
404 B_AX_XTAL_SI_ADDR_NOT_CHK);
405 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
406 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
407 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
408
409 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
410
411 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
412 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
413 if (ret)
414 return ret;
415
416 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
417
418 if (rtwdev->hal.cv == CHIP_CAV) {
419 rtw8851b_patch_swr_pfm2pwm(rtwdev);
420 } else {
421 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
422 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
423 }
424
425 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
426
427 return 0;
428 }
429
rtw8851b_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8851b_efuse * map)430 static void rtw8851b_efuse_parsing(struct rtw89_efuse *efuse,
431 struct rtw8851b_efuse *map)
432 {
433 ether_addr_copy(efuse->addr, map->e.mac_addr);
434 efuse->rfe_type = map->rfe_type;
435 efuse->xtal_cap = map->xtal_k;
436 }
437
rtw8851b_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)438 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
439 struct rtw8851b_efuse *map)
440 {
441 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
442 struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi};
443 u8 i, j;
444
445 tssi->thermal[RF_PATH_A] = map->path_a_therm;
446
447 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
448 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
449 sizeof(ofst[i]->cck_tssi));
450
451 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
452 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
453 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
454 i, j, tssi->tssi_cck[i][j]);
455
456 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
457 sizeof(ofst[i]->bw40_tssi));
458 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
459 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
460
461 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
462 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
463 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
464 i, j, tssi->tssi_mcs[i][j]);
465 }
466 }
467
_decode_efuse_gain(u8 data,s8 * high,s8 * low)468 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
469 {
470 if (high)
471 *high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3);
472 if (low)
473 *low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3);
474
475 return data != 0xff;
476 }
477
rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)478 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
479 struct rtw8851b_efuse *map)
480 {
481 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
482 bool valid = false;
483
484 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
485 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
486 NULL);
487 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
488 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
489 NULL);
490 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
491 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
492 NULL);
493 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
494 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
495 NULL);
496 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
497 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
498 NULL);
499
500 gain->offset_valid = valid;
501 }
502
rtw8851b_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map)503 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
504 {
505 struct rtw89_efuse *efuse = &rtwdev->efuse;
506 struct rtw8851b_efuse *map;
507
508 map = (struct rtw8851b_efuse *)log_map;
509
510 efuse->country_code[0] = map->country_code[0];
511 efuse->country_code[1] = map->country_code[1];
512 rtw8851b_efuse_parsing_tssi(rtwdev, map);
513 rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
514
515 switch (rtwdev->hci.type) {
516 case RTW89_HCI_TYPE_PCIE:
517 rtw8851b_efuse_parsing(efuse, map);
518 break;
519 default:
520 return -EOPNOTSUPP;
521 }
522
523 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
524
525 return 0;
526 }
527
rtw8851b_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)528 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
529 {
530 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
531 static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6};
532 u32 addr = rtwdev->chip->phycap_addr;
533 bool pg = false;
534 u32 ofst;
535 u8 i, j;
536
537 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
538 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
539 /* addrs are in decreasing order */
540 ofst = tssi_trim_addr[i] - addr - j;
541 tssi->tssi_trim[i][j] = phycap_map[ofst];
542
543 if (phycap_map[ofst] != 0xff)
544 pg = true;
545 }
546 }
547
548 if (!pg) {
549 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
550 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
551 "[TSSI][TRIM] no PG, set all trim info to 0\n");
552 }
553
554 for (i = 0; i < RF_PATH_NUM_8851B; i++)
555 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
556 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
557 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
558 i, j, tssi->tssi_trim[i][j],
559 tssi_trim_addr[i] - j);
560 }
561
rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)562 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
563 u8 *phycap_map)
564 {
565 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
566 static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF};
567 u32 addr = rtwdev->chip->phycap_addr;
568 u8 i;
569
570 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
571 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
572
573 rtw89_debug(rtwdev, RTW89_DBG_RFK,
574 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
575 i, info->thermal_trim[i]);
576
577 if (info->thermal_trim[i] != 0xff)
578 info->pg_thermal_trim = true;
579 }
580 }
581
rtw8851b_thermal_trim(struct rtw89_dev * rtwdev)582 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
583 {
584 #define __thm_setting(raw) \
585 ({ \
586 u8 __v = (raw); \
587 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
588 })
589 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
590 u8 i, val;
591
592 if (!info->pg_thermal_trim) {
593 rtw89_debug(rtwdev, RTW89_DBG_RFK,
594 "[THERMAL][TRIM] no PG, do nothing\n");
595
596 return;
597 }
598
599 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
600 val = __thm_setting(info->thermal_trim[i]);
601 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
602
603 rtw89_debug(rtwdev, RTW89_DBG_RFK,
604 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
605 i, val);
606 }
607 #undef __thm_setting
608 }
609
rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)610 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
611 u8 *phycap_map)
612 {
613 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
614 static const u32 pabias_trim_addr[] = {0x5DE};
615 u32 addr = rtwdev->chip->phycap_addr;
616 u8 i;
617
618 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
619 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
620
621 rtw89_debug(rtwdev, RTW89_DBG_RFK,
622 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
623 i, info->pa_bias_trim[i]);
624
625 if (info->pa_bias_trim[i] != 0xff)
626 info->pg_pa_bias_trim = true;
627 }
628 }
629
rtw8851b_pa_bias_trim(struct rtw89_dev * rtwdev)630 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
631 {
632 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
633 u8 pabias_2g, pabias_5g;
634 u8 i;
635
636 if (!info->pg_pa_bias_trim) {
637 rtw89_debug(rtwdev, RTW89_DBG_RFK,
638 "[PA_BIAS][TRIM] no PG, do nothing\n");
639
640 return;
641 }
642
643 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
644 pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
645 pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
646
647 rtw89_debug(rtwdev, RTW89_DBG_RFK,
648 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
649 i, pabias_2g, pabias_5g);
650
651 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
652 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
653 }
654 }
655
rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev * rtwdev,u8 * phycap_map)656 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
657 {
658 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
659 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
660 };
661 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
662 u32 phycap_addr = rtwdev->chip->phycap_addr;
663 bool valid = false;
664 int path, i;
665 u8 data;
666
667 for (path = 0; path < BB_PATH_NUM_8851B; path++)
668 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
669 if (comp_addrs[path][i] == 0)
670 continue;
671
672 data = phycap_map[comp_addrs[path][i] - phycap_addr];
673 valid |= _decode_efuse_gain(data, NULL,
674 &gain->comp[path][i]);
675 }
676
677 gain->comp_valid = valid;
678 }
679
rtw8851b_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)680 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
681 {
682 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
683 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
684 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
685 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
686
687 return 0;
688 }
689
rtw8851b_set_bb_gpio(struct rtw89_dev * rtwdev,u8 gpio_idx,bool inv,u8 src_sel)690 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
691 u8 src_sel)
692 {
693 u32 addr, mask;
694
695 if (gpio_idx >= 32)
696 return;
697
698 /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */
699 addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32);
700 mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2;
701
702 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
703 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
704
705 /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */
706 addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32);
707 mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4;
708
709 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
710 }
711
rtw8851b_set_mac_gpio(struct rtw89_dev * rtwdev,u8 func)712 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
713 {
714 static const struct rtw89_reg3_def func16 = {
715 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3)
716 };
717 static const struct rtw89_reg3_def func17 = {
718 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4,
719 };
720 const struct rtw89_reg3_def *def;
721
722 switch (func) {
723 case 16:
724 def = &func16;
725 break;
726 case 17:
727 def = &func17;
728 break;
729 default:
730 rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
731 return;
732 }
733
734 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
735 }
736
rtw8851b_rfe_gpio(struct rtw89_dev * rtwdev)737 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
738 {
739 u8 rfe_type = rtwdev->efuse.rfe_type;
740
741 if (rfe_type > 50)
742 return;
743
744 if (rfe_type % 3 == 2) {
745 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
746 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
747
748 rtw8851b_set_mac_gpio(rtwdev, 16);
749 rtw8851b_set_mac_gpio(rtwdev, 17);
750 }
751 }
752
rtw8851b_power_trim(struct rtw89_dev * rtwdev)753 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
754 {
755 rtw8851b_thermal_trim(rtwdev);
756 rtw8851b_pa_bias_trim(rtwdev);
757 }
758
rtw8851b_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)759 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
760 const struct rtw89_chan *chan,
761 u8 mac_idx)
762 {
763 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
764 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
765 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
766 u8 txsc20 = 0, txsc40 = 0;
767
768 switch (chan->band_width) {
769 case RTW89_CHANNEL_WIDTH_80:
770 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
771 fallthrough;
772 case RTW89_CHANNEL_WIDTH_40:
773 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
774 break;
775 default:
776 break;
777 }
778
779 switch (chan->band_width) {
780 case RTW89_CHANNEL_WIDTH_80:
781 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
782 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
783 break;
784 case RTW89_CHANNEL_WIDTH_40:
785 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
786 rtw89_write32(rtwdev, sub_carr, txsc20);
787 break;
788 case RTW89_CHANNEL_WIDTH_20:
789 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
790 rtw89_write32(rtwdev, sub_carr, 0);
791 break;
792 default:
793 break;
794 }
795
796 if (chan->channel > 14) {
797 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
798 rtw89_write8_set(rtwdev, chk_rate,
799 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
800 } else {
801 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
802 rtw89_write8_clr(rtwdev, chk_rate,
803 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
804 }
805 }
806
807 static const u32 rtw8851b_sco_barker_threshold[14] = {
808 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
809 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
810 };
811
812 static const u32 rtw8851b_sco_cck_threshold[14] = {
813 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
814 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
815 };
816
rtw8851b_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch)817 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
818 {
819 u8 ch_element = primary_ch - 1;
820
821 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
822 rtw8851b_sco_barker_threshold[ch_element]);
823 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
824 rtw8851b_sco_cck_threshold[ch_element]);
825 }
826
rtw8851b_sco_mapping(u8 central_ch)827 static u8 rtw8851b_sco_mapping(u8 central_ch)
828 {
829 if (central_ch == 1)
830 return 109;
831 else if (central_ch >= 2 && central_ch <= 6)
832 return 108;
833 else if (central_ch >= 7 && central_ch <= 10)
834 return 107;
835 else if (central_ch >= 11 && central_ch <= 14)
836 return 106;
837 else if (central_ch == 36 || central_ch == 38)
838 return 51;
839 else if (central_ch >= 40 && central_ch <= 58)
840 return 50;
841 else if (central_ch >= 60 && central_ch <= 64)
842 return 49;
843 else if (central_ch == 100 || central_ch == 102)
844 return 48;
845 else if (central_ch >= 104 && central_ch <= 126)
846 return 47;
847 else if (central_ch >= 128 && central_ch <= 151)
848 return 46;
849 else if (central_ch >= 153 && central_ch <= 177)
850 return 45;
851 else
852 return 0;
853 }
854
855 struct rtw8851b_bb_gain {
856 u32 gain_g[BB_PATH_NUM_8851B];
857 u32 gain_a[BB_PATH_NUM_8851B];
858 u32 gain_mask;
859 };
860
861 static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
862 { .gain_g = {0x4678}, .gain_a = {0x45DC},
863 .gain_mask = 0x00ff0000 },
864 { .gain_g = {0x4678}, .gain_a = {0x45DC},
865 .gain_mask = 0xff000000 },
866 { .gain_g = {0x467C}, .gain_a = {0x4660},
867 .gain_mask = 0x000000ff },
868 { .gain_g = {0x467C}, .gain_a = {0x4660},
869 .gain_mask = 0x0000ff00 },
870 { .gain_g = {0x467C}, .gain_a = {0x4660},
871 .gain_mask = 0x00ff0000 },
872 { .gain_g = {0x467C}, .gain_a = {0x4660},
873 .gain_mask = 0xff000000 },
874 { .gain_g = {0x4680}, .gain_a = {0x4664},
875 .gain_mask = 0x000000ff },
876 };
877
878 static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
879 { .gain_g = {0x4680}, .gain_a = {0x4664},
880 .gain_mask = 0x00ff0000 },
881 { .gain_g = {0x4680}, .gain_a = {0x4664},
882 .gain_mask = 0xff000000 },
883 };
884
rtw8851b_set_gain_error(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_rf_path path)885 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
886 enum rtw89_subband subband,
887 enum rtw89_rf_path path)
888 {
889 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
890 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
891 s32 val;
892 u32 reg;
893 u32 mask;
894 int i;
895
896 for (i = 0; i < LNA_GAIN_NUM; i++) {
897 if (subband == RTW89_CH_2G)
898 reg = bb_gain_lna[i].gain_g[path];
899 else
900 reg = bb_gain_lna[i].gain_a[path];
901
902 mask = bb_gain_lna[i].gain_mask;
903 val = gain->lna_gain[gain_band][path][i];
904 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
905 }
906
907 for (i = 0; i < TIA_GAIN_NUM; i++) {
908 if (subband == RTW89_CH_2G)
909 reg = bb_gain_tia[i].gain_g[path];
910 else
911 reg = bb_gain_tia[i].gain_a[path];
912
913 mask = bb_gain_tia[i].gain_mask;
914 val = gain->tia_gain[gain_band][path][i];
915 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
916 }
917 }
918
rtw8851b_set_gain_offset(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_phy_idx phy_idx)919 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
920 enum rtw89_subband subband,
921 enum rtw89_phy_idx phy_idx)
922 {
923 static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1};
924 static const u32 gain_err_addr[] = {R_P0_AGC_RSVD};
925 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
926 enum rtw89_gain_offset gain_ofdm_band;
927 s32 offset_ofdm, offset_cck;
928 s32 offset_a;
929 s32 tmp;
930 u8 path;
931
932 if (!efuse_gain->comp_valid)
933 goto next;
934
935 for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) {
936 tmp = efuse_gain->comp[path][subband];
937 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
938 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
939 }
940
941 next:
942 if (!efuse_gain->offset_valid)
943 return;
944
945 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
946
947 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
948
949 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
950 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
951 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
952
953 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
954 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
955
956 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
957 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
958 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
959
960 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
961 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
962 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
963
964 if (subband == RTW89_CH_2G) {
965 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
966 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
967 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
968 B_RX_RPL_OFST_CCK_MASK, tmp);
969 }
970 }
971
972 static
rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev * rtwdev,enum rtw89_subband subband)973 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
974 {
975 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
976 u8 band = rtw89_subband_to_bb_gain_band(subband);
977 u32 val;
978
979 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
980 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
981 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
982 val >>= B_P0_RPL1_SHIFT;
983 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
984 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
985
986 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
987 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
988 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
989 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
990 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
991 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
992
993 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
994 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
995 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
996 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
997 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
998 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
999 }
1000
rtw8851b_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1001 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
1002 const struct rtw89_chan *chan,
1003 enum rtw89_phy_idx phy_idx)
1004 {
1005 u8 subband = chan->subband_type;
1006 u8 central_ch = chan->channel;
1007 bool is_2g = central_ch <= 14;
1008 u8 sco_comp;
1009
1010 if (is_2g)
1011 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1012 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
1013 else
1014 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1015 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
1016 /* SCO compensate FC setting */
1017 sco_comp = rtw8851b_sco_mapping(central_ch);
1018 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1019
1020 if (chan->band_type == RTW89_BAND_6G)
1021 return;
1022
1023 /* CCK parameters */
1024 if (central_ch == 14) {
1025 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1026 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1027 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1028 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1029 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1030 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1031 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1032 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1033 } else {
1034 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1035 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1036 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1037 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1038 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1039 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1040 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1041 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1042 }
1043
1044 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1045 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1046 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1047 }
1048
rtw8851b_bw_setting(struct rtw89_dev * rtwdev,u8 bw)1049 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1050 {
1051 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1052 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1053 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1054 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1055 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1056 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1057 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1058
1059 switch (bw) {
1060 case RTW89_CHANNEL_WIDTH_5:
1061 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1062 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1063 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1064 break;
1065 case RTW89_CHANNEL_WIDTH_10:
1066 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1067 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1068 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1069 break;
1070 case RTW89_CHANNEL_WIDTH_20:
1071 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1072 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1073 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1074 break;
1075 case RTW89_CHANNEL_WIDTH_40:
1076 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1077 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1078 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1079 break;
1080 case RTW89_CHANNEL_WIDTH_80:
1081 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1082 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1083 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1084 break;
1085 default:
1086 rtw89_warn(rtwdev, "Fail to set ADC\n");
1087 }
1088 }
1089
rtw8851b_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)1090 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1091 enum rtw89_phy_idx phy_idx)
1092 {
1093 switch (bw) {
1094 case RTW89_CHANNEL_WIDTH_5:
1095 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1096 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1097 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1098 break;
1099 case RTW89_CHANNEL_WIDTH_10:
1100 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1101 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1102 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1103 break;
1104 case RTW89_CHANNEL_WIDTH_20:
1105 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1106 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1107 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1108 break;
1109 case RTW89_CHANNEL_WIDTH_40:
1110 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1111 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1112 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1113 pri_ch, phy_idx);
1114 /* CCK primary channel */
1115 if (pri_ch == RTW89_SC_20_UPPER)
1116 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1117 else
1118 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1119
1120 break;
1121 case RTW89_CHANNEL_WIDTH_80:
1122 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1123 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1124 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1125 pri_ch, phy_idx);
1126 break;
1127 default:
1128 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1129 pri_ch);
1130 }
1131
1132 rtw8851b_bw_setting(rtwdev, bw);
1133 }
1134
rtw8851b_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en)1135 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1136 {
1137 if (cck_en) {
1138 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1139 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1140 B_PD_ARBITER_OFF, 0);
1141 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1142 } else {
1143 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1144 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1145 B_PD_ARBITER_OFF, 1);
1146 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1147 }
1148 }
1149
rtw8851b_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1150 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1151 const struct rtw89_chan *chan)
1152 {
1153 u8 center_chan = chan->channel;
1154
1155 switch (chan->band_type) {
1156 case RTW89_BAND_5G:
1157 if (center_chan == 151 || center_chan == 153 ||
1158 center_chan == 155 || center_chan == 163)
1159 return 5760;
1160 else if (center_chan == 54 || center_chan == 58)
1161 return 5280;
1162 break;
1163 default:
1164 break;
1165 }
1166
1167 return 0;
1168 }
1169
1170 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1171 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1172 #define MAX_TONE_NUM 2048
1173
rtw8851b_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1174 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1175 const struct rtw89_chan *chan,
1176 enum rtw89_phy_idx phy_idx)
1177 {
1178 u32 spur_freq;
1179 s32 freq_diff, csi_idx, csi_tone_idx;
1180
1181 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1182 if (spur_freq == 0) {
1183 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1184 0, phy_idx);
1185 return;
1186 }
1187
1188 freq_diff = (spur_freq - chan->freq) * 1000000;
1189 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1190 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1191
1192 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1193 csi_tone_idx, phy_idx);
1194 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1195 }
1196
1197 static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = {
1198 .notch1_idx = {0x46E4, 0xFF},
1199 .notch1_frac_idx = {0x46E4, 0xC00},
1200 .notch1_en = {0x46E4, 0x1000},
1201 .notch2_idx = {0x47A4, 0xFF},
1202 .notch2_frac_idx = {0x47A4, 0xC00},
1203 .notch2_en = {0x47A4, 0x1000},
1204 };
1205
rtw8851b_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1206 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1207 const struct rtw89_chan *chan)
1208 {
1209 const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def;
1210 s32 nbi_frac_idx, nbi_frac_tone_idx;
1211 s32 nbi_idx, nbi_tone_idx;
1212 bool notch2_chk = false;
1213 u32 spur_freq, fc;
1214 s32 freq_diff;
1215
1216 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1217 if (spur_freq == 0) {
1218 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1219 nbi->notch1_en.mask, 0);
1220 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1221 nbi->notch2_en.mask, 0);
1222 return;
1223 }
1224
1225 fc = chan->freq;
1226 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1227 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1228 if ((fc > spur_freq &&
1229 chan->channel < chan->primary_channel) ||
1230 (fc < spur_freq &&
1231 chan->channel > chan->primary_channel))
1232 notch2_chk = true;
1233 }
1234
1235 freq_diff = (spur_freq - fc) * 1000000;
1236 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1237 &nbi_frac_idx);
1238
1239 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1240 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1241 } else {
1242 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1243 128 : 256;
1244
1245 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1246 }
1247 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx,
1248 CARRIER_SPACING_78_125);
1249
1250 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1251 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1252 nbi->notch2_idx.mask, nbi_tone_idx);
1253 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1254 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1255 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1256 nbi->notch2_en.mask, 0);
1257 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1258 nbi->notch2_en.mask, 1);
1259 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1260 nbi->notch1_en.mask, 0);
1261 } else {
1262 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1263 nbi->notch1_idx.mask, nbi_tone_idx);
1264 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1265 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1266 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1267 nbi->notch1_en.mask, 0);
1268 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1269 nbi->notch1_en.mask, 1);
1270 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1271 nbi->notch2_en.mask, 0);
1272 }
1273 }
1274
rtw8851b_set_cfr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1275 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1276 {
1277 if (chan->band_type == RTW89_BAND_2G &&
1278 chan->band_width == RTW89_CHANNEL_WIDTH_20 &&
1279 (chan->channel == 1 || chan->channel == 13)) {
1280 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1281 B_PATH0_TX_CFR_LGC0, 0xf8);
1282 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1283 B_PATH0_TX_CFR_LGC1, 0x120);
1284 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1285 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0);
1286 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1287 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3);
1288 } else {
1289 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1290 B_PATH0_TX_CFR_LGC0, 0x120);
1291 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1292 B_PATH0_TX_CFR_LGC1, 0x3ff);
1293 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1294 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3);
1295 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1296 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7);
1297 }
1298 }
1299
rtw8851b_5m_mask(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1300 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1301 enum rtw89_phy_idx phy_idx)
1302 {
1303 u8 pri_ch = chan->pri_ch_idx;
1304 bool mask_5m_low;
1305 bool mask_5m_en;
1306
1307 switch (chan->band_width) {
1308 case RTW89_CHANNEL_WIDTH_40:
1309 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1310 mask_5m_en = true;
1311 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1312 break;
1313 case RTW89_CHANNEL_WIDTH_80:
1314 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1315 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1316 pri_ch == RTW89_SC_20_LOWEST;
1317 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1318 break;
1319 default:
1320 mask_5m_en = false;
1321 break;
1322 }
1323
1324 if (!mask_5m_en) {
1325 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1326 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1327 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1328 return;
1329 }
1330
1331 if (mask_5m_low) {
1332 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1333 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1334 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1335 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1336 } else {
1337 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1338 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1339 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1340 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1341 }
1342 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1343 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1344 }
1345
rtw8851b_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1346 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1347 {
1348 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1349 fsleep(1);
1350 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1351 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1352 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1353 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1354 }
1355
rtw8851b_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)1356 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1357 enum rtw89_phy_idx phy_idx, bool en)
1358 {
1359 if (en) {
1360 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1361 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1362 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1363 if (band == RTW89_BAND_2G)
1364 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1365 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1366 } else {
1367 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1368 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1369 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1370 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1371 fsleep(1);
1372 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1373 }
1374 }
1375
rtw8851b_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1376 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1377 enum rtw89_phy_idx phy_idx)
1378 {
1379 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1380 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);
1381 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1382 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1383 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1384 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);
1385 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1386 }
1387
1388 static
rtw8851b_bb_gpio_trsw(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 tx_path_en,u8 trsw_tx,u8 trsw_rx,u8 trsw_a,u8 trsw_b)1389 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1390 u8 tx_path_en, u8 trsw_tx,
1391 u8 trsw_rx, u8 trsw_a, u8 trsw_b)
1392 {
1393 u32 mask_ofst = 16;
1394 u32 val;
1395
1396 if (path != RF_PATH_A)
1397 return;
1398
1399 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1400 val = u32_encode_bits(trsw_a, B_P0_TRSW_A) |
1401 u32_encode_bits(trsw_b, B_P0_TRSW_B);
1402
1403 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1404 (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1405 }
1406
rtw8851b_bb_gpio_init(struct rtw89_dev * rtwdev)1407 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1408 {
1409 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1410 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1411 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1412 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1413 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1414
1415 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1416 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1417 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1418 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1419
1420 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1421 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1422 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1423 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1424 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1425 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1426 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1427 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1428 }
1429
rtw8851b_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1430 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1431 enum rtw89_phy_idx phy_idx)
1432 {
1433 u32 addr;
1434
1435 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1436 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1437 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1438 }
1439
rtw8851b_bb_sethw(struct rtw89_dev * rtwdev)1440 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1441 {
1442 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1443
1444 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1445
1446 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1447 rtw8851b_bb_gpio_init(rtwdev);
1448
1449 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1450 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1451
1452 /* read these registers after loading BB parameters */
1453 gain->offset_base[RTW89_PHY_0] =
1454 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1455 gain->rssi_base[RTW89_PHY_0] =
1456 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1457 }
1458
rtw8851b_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1459 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1460 enum rtw89_phy_idx phy_idx)
1461 {
1462 u8 band = chan->band_type, chan_idx;
1463 bool cck_en = chan->channel <= 14;
1464 u8 pri_ch_idx = chan->pri_ch_idx;
1465
1466 if (cck_en)
1467 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1468
1469 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1470 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1471 rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1472 rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1473 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1474
1475 if (chan->band_type == RTW89_BAND_5G) {
1476 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1477 B_PATH0_BT_SHARE_V1, 0x0);
1478 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1479 B_PATH0_BTG_PATH_V1, 0x0);
1480 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1481 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1482 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1483 B_BT_DYN_DC_EST_EN_MSK, 0x0);
1484 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1485 }
1486
1487 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1488 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1489 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1490 rtw8851b_set_cfr(rtwdev, chan);
1491 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1492 }
1493
rtw8851b_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1494 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1495 const struct rtw89_chan *chan,
1496 enum rtw89_mac_idx mac_idx,
1497 enum rtw89_phy_idx phy_idx)
1498 {
1499 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1500 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1501 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1502 }
1503
rtw8851b_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1504 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1505 enum rtw89_rf_path path)
1506 {
1507 if (en) {
1508 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1509 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1510 } else {
1511 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1512 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1513 }
1514 }
1515
rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1516 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1517 u8 phy_idx)
1518 {
1519 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1520 }
1521
rtw8851b_adc_en(struct rtw89_dev * rtwdev,bool en)1522 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1523 {
1524 if (en)
1525 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1526 else
1527 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1528 }
1529
rtw8851b_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1530 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1531 struct rtw89_channel_help_params *p,
1532 const struct rtw89_chan *chan,
1533 enum rtw89_mac_idx mac_idx,
1534 enum rtw89_phy_idx phy_idx)
1535 {
1536 if (enter) {
1537 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1538 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1539 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1540 rtw8851b_adc_en(rtwdev, false);
1541 fsleep(40);
1542 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1543 } else {
1544 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1545 rtw8851b_adc_en(rtwdev, true);
1546 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1547 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1548 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1549 }
1550 }
1551
rtw8851b_rfk_init(struct rtw89_dev * rtwdev)1552 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1553 {
1554 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1555 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1556 rtw8851b_lck_init(rtwdev);
1557
1558 rtw8851b_dpk_init(rtwdev);
1559 rtw8851b_aack(rtwdev);
1560 rtw8851b_rck(rtwdev);
1561 rtw8851b_dack(rtwdev);
1562 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0);
1563 }
1564
rtw8851b_rfk_channel(struct rtw89_dev * rtwdev)1565 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev)
1566 {
1567 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1568
1569 rtw8851b_rx_dck(rtwdev, phy_idx);
1570 rtw8851b_iqk(rtwdev, phy_idx);
1571 rtw8851b_tssi(rtwdev, phy_idx, true);
1572 rtw8851b_dpk(rtwdev, phy_idx);
1573 }
1574
rtw8851b_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1575 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1576 enum rtw89_phy_idx phy_idx)
1577 {
1578 rtw8851b_tssi_scan(rtwdev, phy_idx);
1579 }
1580
rtw8851b_rfk_scan(struct rtw89_dev * rtwdev,bool start)1581 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1582 {
1583 rtw8851b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1584 }
1585
rtw8851b_rfk_track(struct rtw89_dev * rtwdev)1586 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1587 {
1588 rtw8851b_dpk_track(rtwdev);
1589 rtw8851b_lck_track(rtwdev);
1590 }
1591
rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1592 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1593 enum rtw89_phy_idx phy_idx, s16 ref)
1594 {
1595 const u16 tssi_16dbm_cw = 0x12c;
1596 const u8 base_cw_0db = 0x27;
1597 const s8 ofst_int = 0;
1598 s16 pwr_s10_3;
1599 s16 rf_pwr_cw;
1600 u16 bb_pwr_cw;
1601 u32 pwr_cw;
1602 u32 tssi_ofst_cw;
1603
1604 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1605 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
1606 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
1607 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1608 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1609
1610 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1611 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1612 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1613 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1614
1615 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
1616 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
1617 u32_encode_bits(ref, B_DPD_REF);
1618 }
1619
rtw8851b_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1620 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1621 enum rtw89_phy_idx phy_idx)
1622 {
1623 static const u32 addr[RF_PATH_NUM_8851B] = {0x5800};
1624 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1625 const u8 ofst_ofdm = 0x4;
1626 const u8 ofst_cck = 0x8;
1627 const s16 ref_ofdm = 0;
1628 const s16 ref_cck = 0;
1629 u32 val;
1630 u8 i;
1631
1632 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1633
1634 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1635 B_AX_PWR_REF, 0x0);
1636
1637 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1638 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1639
1640 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1641 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1642 phy_idx);
1643
1644 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1645 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1646
1647 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1648 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1649 phy_idx);
1650 }
1651
rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 tx_shape_idx,enum rtw89_phy_idx phy_idx)1652 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1653 const struct rtw89_chan *chan,
1654 u8 tx_shape_idx,
1655 enum rtw89_phy_idx phy_idx)
1656 {
1657 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1658 #define __DFIR_CFG_MASK 0xffffffff
1659 #define __DFIR_CFG_NR 8
1660 #define __DECL_DFIR_PARAM(_name, _val...) \
1661 static const u32 param_ ## _name[] = {_val}; \
1662 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1663
1664 __DECL_DFIR_PARAM(flat,
1665 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1666 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1667 __DECL_DFIR_PARAM(sharp,
1668 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1669 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1670 __DECL_DFIR_PARAM(sharp_14,
1671 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1672 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1673 u8 ch = chan->channel;
1674 const u32 *param;
1675 u32 addr;
1676 int i;
1677
1678 if (ch > 14) {
1679 rtw89_warn(rtwdev,
1680 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1681 return;
1682 }
1683
1684 if (ch == 14)
1685 param = param_sharp_14;
1686 else
1687 param = tx_shape_idx == 0 ? param_flat : param_sharp;
1688
1689 for (i = 0; i < __DFIR_CFG_NR; i++) {
1690 addr = __DFIR_CFG_ADDR(i);
1691 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1692 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1693 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1694 phy_idx);
1695 }
1696
1697 #undef __DECL_DFIR_PARAM
1698 #undef __DFIR_CFG_NR
1699 #undef __DFIR_CFG_MASK
1700 #undef __DECL_CFG_ADDR
1701 }
1702
rtw8851b_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1703 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1704 const struct rtw89_chan *chan,
1705 enum rtw89_phy_idx phy_idx)
1706 {
1707 u8 band = chan->band_type;
1708 u8 regd = rtw89_regd_get(rtwdev, band);
1709 u8 tx_shape_cck = rtw89_8851b_tx_shape[band][RTW89_RS_CCK][regd];
1710 u8 tx_shape_ofdm = rtw89_8851b_tx_shape[band][RTW89_RS_OFDM][regd];
1711
1712 if (band == RTW89_BAND_2G)
1713 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1714
1715 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1716 tx_shape_ofdm);
1717 }
1718
rtw8851b_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1719 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1720 const struct rtw89_chan *chan,
1721 enum rtw89_phy_idx phy_idx)
1722 {
1723 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1724 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1725 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1726 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1727 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1728 }
1729
rtw8851b_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1730 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1731 enum rtw89_phy_idx phy_idx)
1732 {
1733 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1734 }
1735
1736 static
rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1737 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1738 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1739 {
1740 u32 reg;
1741
1742 if (pw_ofst < -16 || pw_ofst > 15) {
1743 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1744 return;
1745 }
1746
1747 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1748 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1749
1750 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1751 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1752
1753 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1754 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1755 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1756 }
1757
1758 static int
rtw8851b_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1759 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1760 {
1761 int ret;
1762
1763 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1764 if (ret)
1765 return ret;
1766
1767 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1768 if (ret)
1769 return ret;
1770
1771 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1772 if (ret)
1773 return ret;
1774
1775 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1776 RTW89_MAC_1 : RTW89_MAC_0);
1777
1778 return 0;
1779 }
1780
rtw8851b_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)1781 static void rtw8851b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1782 {
1783 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1784
1785 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8851b_btc_preagc_en_defs_tbl :
1786 &rtw8851b_btc_preagc_dis_defs_tbl);
1787
1788 if (!bt_en) {
1789 if (chan->band_type == RTW89_BAND_2G) {
1790 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1791 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1792 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1793 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1794 } else {
1795 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1796 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1797 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1798 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1799 }
1800 }
1801 }
1802
rtw8851b_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)1803 static void rtw8851b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1804 {
1805 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1806
1807 if (btg) {
1808 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1809 B_PATH0_BT_SHARE_V1, 0x1);
1810 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1811 B_PATH0_BTG_PATH_V1, 0x1);
1812 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1813 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1814 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1815 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1816 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1817 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1818 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1819 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1820 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1821 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1822 } else {
1823 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1824 B_PATH0_BT_SHARE_V1, 0x0);
1825 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1826 B_PATH0_BTG_PATH_V1, 0x0);
1827 if (chan->band_type == RTW89_BAND_2G) {
1828 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1829 B_PATH0_G_LNA6_OP1DB_V1, 0x80);
1830 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1831 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
1832 } else {
1833 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1834 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1835 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1836 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1837 }
1838 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1839 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1840 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1841 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1842 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1843 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1844 }
1845 }
1846
rtw8851b_bb_ctrl_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path)1847 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1848 enum rtw89_rf_path_bit rx_path)
1849 {
1850 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1851 u32 rst_mask0;
1852
1853 if (rx_path == RF_A) {
1854 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1855 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1856 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1857 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1858 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1859 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1860 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1861 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1862 }
1863
1864 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1865
1866 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1867 if (rx_path == RF_A) {
1868 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1869 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1870 }
1871 }
1872
rtw8851b_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)1873 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1874 {
1875 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1876
1877 if (rtwdev->hal.rx_nss == 1) {
1878 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1879 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1880 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1881 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1882 }
1883
1884 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1885 }
1886
rtw8851b_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1887 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1888 {
1889 if (rtwdev->is_tssi_mode[rf_path]) {
1890 u32 addr = R_TSSI_THER + (rf_path << 13);
1891
1892 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1893 }
1894
1895 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1896 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1897 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1898
1899 fsleep(200);
1900
1901 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1902 }
1903
rtw8851b_btc_set_rfe(struct rtw89_dev * rtwdev)1904 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1905 {
1906 struct rtw89_btc *btc = &rtwdev->btc;
1907 struct rtw89_btc_module *module = &btc->mdinfo;
1908
1909 module->rfe_type = rtwdev->efuse.rfe_type;
1910 module->cv = rtwdev->hal.cv;
1911 module->bt_solo = 0;
1912 module->switch_type = BTC_SWITCH_INTERNAL;
1913 module->ant.isolation = 10;
1914 module->kt_ver_adie = rtwdev->hal.acv;
1915
1916 if (module->rfe_type == 0)
1917 return;
1918
1919 /* rfe_type 3*n+1: 1-Ant(shared),
1920 * 3*n+2: 2-Ant+Div(non-shared),
1921 * 3*n+3: 2-Ant+no-Div(non-shared)
1922 */
1923 module->ant.num = (module->rfe_type % 3 == 1) ? 1 : 2;
1924 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1925 module->ant.single_pos = RF_PATH_A;
1926 module->ant.btg_pos = RF_PATH_A;
1927 module->ant.stream_cnt = 1;
1928
1929 if (module->ant.num == 1) {
1930 module->ant.type = BTC_ANT_SHARED;
1931 module->bt_pos = BTC_BT_BTG;
1932 module->wa_type = 1;
1933 module->ant.diversity = 0;
1934 } else { /* ant.num == 2 */
1935 module->ant.type = BTC_ANT_DEDICATED;
1936 module->bt_pos = BTC_BT_ALONE;
1937 module->switch_type = BTC_SWITCH_EXTERNAL;
1938 module->wa_type = 0;
1939 if (module->rfe_type % 3 == 2)
1940 module->ant.diversity = 1;
1941 }
1942 }
1943
1944 static
rtw8851b_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1945 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1946 {
1947 if (group > BTC_BT_SS_GROUP)
1948 group--; /* Tx-group=1, Rx-group=2 */
1949
1950 if (rtwdev->btc.mdinfo.ant.type == BTC_ANT_SHARED) /* 1-Ant */
1951 group += 3;
1952
1953 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
1954 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
1955 }
1956
rtw8851b_btc_init_cfg(struct rtw89_dev * rtwdev)1957 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
1958 {
1959 static const struct rtw89_mac_ax_coex coex_params = {
1960 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1961 .direction = RTW89_MAC_AX_COEX_INNER,
1962 };
1963 const struct rtw89_chip_info *chip = rtwdev->chip;
1964 struct rtw89_btc *btc = &rtwdev->btc;
1965 struct rtw89_btc_module *module = &btc->mdinfo;
1966 struct rtw89_btc_ant_info *ant = &module->ant;
1967 u8 path, path_min, path_max;
1968
1969 /* PTA init */
1970 rtw89_mac_coex_init(rtwdev, &coex_params);
1971
1972 /* set WL Tx response = Hi-Pri */
1973 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1974 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1975
1976 /* for 1-Ant && 1-ss case: only 1-path */
1977 if (ant->stream_cnt == 1) {
1978 path_min = ant->single_pos;
1979 path_max = path_min;
1980 } else {
1981 path_min = RF_PATH_A;
1982 path_max = RF_PATH_B;
1983 }
1984
1985 for (path = path_min; path <= path_max; path++) {
1986 /* set rf gnt-debug off */
1987 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
1988
1989 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
1990 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
1991
1992 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
1993 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
1994
1995 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
1996 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
1997
1998 /* if GNT_WL = 0 && BT = Tx_group -->
1999 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
2000 */
2001 if (ant->type == BTC_ANT_SHARED && ant->btg_pos == path)
2002 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2003 else
2004 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2005
2006 /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */
2007 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2008 }
2009
2010 /* set PTA break table */
2011 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2012
2013 /* enable BT counter 0xda40[16,2] = 2b'11 */
2014 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2015
2016 btc->cx.wl.status.map.init_ok = true;
2017 }
2018
2019 static
rtw8851b_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)2020 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2021 {
2022 u32 bitmap;
2023 u32 reg;
2024
2025 switch (map) {
2026 case BTC_PRI_MASK_TX_RESP:
2027 reg = R_BTC_BT_COEX_MSK_TABLE;
2028 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
2029 break;
2030 case BTC_PRI_MASK_BEACON:
2031 reg = R_AX_WL_PRI_MSK;
2032 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
2033 break;
2034 case BTC_PRI_MASK_RX_CCK:
2035 reg = R_BTC_BT_COEX_MSK_TABLE;
2036 bitmap = B_BTC_PRI_MASK_RXCCK_V1;
2037 break;
2038 default:
2039 return;
2040 }
2041
2042 if (state)
2043 rtw89_write32_set(rtwdev, reg, bitmap);
2044 else
2045 rtw89_write32_clr(rtwdev, reg, bitmap);
2046 }
2047
2048 union rtw8851b_btc_wl_txpwr_ctrl {
2049 u32 txpwr_val;
2050 struct {
2051 union {
2052 u16 ctrl_all_time;
2053 struct {
2054 s16 data:9;
2055 u16 rsvd:6;
2056 u16 flag:1;
2057 } all_time;
2058 };
2059 union {
2060 u16 ctrl_gnt_bt;
2061 struct {
2062 s16 data:9;
2063 u16 rsvd:7;
2064 } gnt_bt;
2065 };
2066 };
2067 } __packed;
2068
2069 static void
rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)2070 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2071 {
2072 union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2073 s32 val;
2074
2075 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2076 do { \
2077 u32 _wrt = FIELD_PREP(_msk, _val); \
2078 BUILD_BUG_ON(!!(_msk & _en)); \
2079 if (_cond) \
2080 _wrt |= _en; \
2081 else \
2082 _wrt &= ~_en; \
2083 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2084 _msk | _en, _wrt); \
2085 } while (0)
2086
2087 switch (arg.ctrl_all_time) {
2088 case 0xffff:
2089 val = 0;
2090 break;
2091 default:
2092 val = arg.all_time.data;
2093 break;
2094 }
2095
2096 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2097 val, B_AX_FORCE_PWR_BY_RATE_EN,
2098 arg.ctrl_all_time != 0xffff);
2099
2100 switch (arg.ctrl_gnt_bt) {
2101 case 0xffff:
2102 val = 0;
2103 break;
2104 default:
2105 val = arg.gnt_bt.data;
2106 break;
2107 }
2108
2109 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2110 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2111
2112 #undef __write_ctrl
2113 }
2114
2115 static
rtw8851b_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2116 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2117 {
2118 val = clamp_t(s8, val, -100, 0) + 100;
2119 val = min(val + 6, 100); /* compensate offset */
2120
2121 return val;
2122 }
2123
2124 static
rtw8851b_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2125 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2126 {
2127 /* Feature move to firmware */
2128 }
2129
rtw8851b_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2130 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2131 {
2132 struct rtw89_btc *btc = &rtwdev->btc;
2133 struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
2134
2135 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2136 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2137 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2138
2139 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2140 if (state)
2141 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2142 else
2143 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2144
2145 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2146 }
2147
2148 #define LNA2_51B_MA 0x700
2149
2150 static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}};
2151 static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}};
2152
rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)2153 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2154 {
2155 /* To improve BT ACI in co-rx
2156 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2157 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2158 */
2159 struct rtw89_btc *btc = &rtwdev->btc;
2160 struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
2161 const struct rtw89_reg2_def *rf;
2162 u32 n, i, val;
2163
2164 switch (level) {
2165 case 0: /* original */
2166 default:
2167 btc->dm.wl_lna2 = 0;
2168 break;
2169 case 1: /* for FDD free-run */
2170 btc->dm.wl_lna2 = 0;
2171 break;
2172 case 2: /* for BTG Co-Rx*/
2173 btc->dm.wl_lna2 = 1;
2174 break;
2175 }
2176
2177 if (btc->dm.wl_lna2 == 0) {
2178 rf = btc_8851b_rf_0;
2179 n = ARRAY_SIZE(btc_8851b_rf_0);
2180 } else {
2181 rf = btc_8851b_rf_1;
2182 n = ARRAY_SIZE(btc_8851b_rf_1);
2183 }
2184
2185 for (i = 0; i < n; i++, rf++) {
2186 val = rf->data;
2187 /* bit[10] = 1 if non-shared-ant for 8851b */
2188 if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED)
2189 val |= 0x4;
2190
2191 rtw89_write_rf(rtwdev, ant->btg_pos, rf->addr, LNA2_51B_MA, val);
2192 }
2193 }
2194
rtw8851b_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2195 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2196 struct rtw89_rx_phy_ppdu *phy_ppdu,
2197 struct ieee80211_rx_status *status)
2198 {
2199 u16 chan = phy_ppdu->chan_idx;
2200 enum nl80211_band band;
2201 u8 ch;
2202
2203 if (chan == 0)
2204 return;
2205
2206 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2207 status->freq = ieee80211_channel_to_frequency(ch, band);
2208 status->band = band;
2209 }
2210
rtw8851b_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2211 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2212 struct rtw89_rx_phy_ppdu *phy_ppdu,
2213 struct ieee80211_rx_status *status)
2214 {
2215 u8 path;
2216 u8 *rx_power = phy_ppdu->rssi;
2217
2218 status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]);
2219
2220 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2221 status->chains |= BIT(path);
2222 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2223 }
2224 if (phy_ppdu->valid)
2225 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2226 }
2227
rtw8851b_mac_enable_bb_rf(struct rtw89_dev * rtwdev)2228 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2229 {
2230 int ret;
2231
2232 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2233 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2234 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2235 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2236 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2237
2238 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2239 FULL_BIT_MASK);
2240 if (ret)
2241 return ret;
2242
2243 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2244 FULL_BIT_MASK);
2245 if (ret)
2246 return ret;
2247
2248 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2249
2250 return 0;
2251 }
2252
rtw8851b_mac_disable_bb_rf(struct rtw89_dev * rtwdev)2253 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2254 {
2255 u8 wl_rfc_s0;
2256 u8 wl_rfc_s1;
2257 int ret;
2258
2259 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2260 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2261
2262 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2263 if (ret)
2264 return ret;
2265 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2266 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2267 FULL_BIT_MASK);
2268 if (ret)
2269 return ret;
2270
2271 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2272 if (ret)
2273 return ret;
2274 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2275 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2276 FULL_BIT_MASK);
2277 return ret;
2278 }
2279
2280 static const struct rtw89_chip_ops rtw8851b_chip_ops = {
2281 .enable_bb_rf = rtw8851b_mac_enable_bb_rf,
2282 .disable_bb_rf = rtw8851b_mac_disable_bb_rf,
2283 .bb_reset = rtw8851b_bb_reset,
2284 .bb_sethw = rtw8851b_bb_sethw,
2285 .read_rf = rtw89_phy_read_rf_v1,
2286 .write_rf = rtw89_phy_write_rf_v1,
2287 .set_channel = rtw8851b_set_channel,
2288 .set_channel_help = rtw8851b_set_channel_help,
2289 .read_efuse = rtw8851b_read_efuse,
2290 .read_phycap = rtw8851b_read_phycap,
2291 .fem_setup = NULL,
2292 .rfe_gpio = rtw8851b_rfe_gpio,
2293 .rfk_init = rtw8851b_rfk_init,
2294 .rfk_channel = rtw8851b_rfk_channel,
2295 .rfk_band_changed = rtw8851b_rfk_band_changed,
2296 .rfk_scan = rtw8851b_rfk_scan,
2297 .rfk_track = rtw8851b_rfk_track,
2298 .power_trim = rtw8851b_power_trim,
2299 .set_txpwr = rtw8851b_set_txpwr,
2300 .set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl,
2301 .init_txpwr_unit = rtw8851b_init_txpwr_unit,
2302 .get_thermal = rtw8851b_get_thermal,
2303 .ctrl_btg = rtw8851b_ctrl_btg,
2304 .query_ppdu = rtw8851b_query_ppdu,
2305 .bb_ctrl_btc_preagc = rtw8851b_bb_ctrl_btc_preagc,
2306 .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path,
2307 .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset,
2308 .pwr_on_func = rtw8851b_pwr_on_func,
2309 .pwr_off_func = rtw8851b_pwr_off_func,
2310 .query_rxdesc = rtw89_core_query_rxdesc,
2311 .fill_txdesc = rtw89_core_fill_txdesc,
2312 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2313 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2314 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2315 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2316 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2317 .h2c_dctl_sec_cam = NULL,
2318
2319 .btc_set_rfe = rtw8851b_btc_set_rfe,
2320 .btc_init_cfg = rtw8851b_btc_init_cfg,
2321 .btc_set_wl_pri = rtw8851b_btc_set_wl_pri,
2322 .btc_set_wl_txpwr_ctrl = rtw8851b_btc_set_wl_txpwr_ctrl,
2323 .btc_get_bt_rssi = rtw8851b_btc_get_bt_rssi,
2324 .btc_update_bt_cnt = rtw8851b_btc_update_bt_cnt,
2325 .btc_wl_s1_standby = rtw8851b_btc_wl_s1_standby,
2326 .btc_set_wl_rx_gain = rtw8851b_btc_set_wl_rx_gain,
2327 .btc_set_policy = rtw89_btc_set_policy_v1,
2328 };
2329
2330 #ifdef CONFIG_PM
2331 static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = {
2332 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2333 .n_patterns = RTW89_MAX_PATTERN_NUM,
2334 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2335 .pattern_min_len = 1,
2336 };
2337 #endif
2338
2339 const struct rtw89_chip_info rtw8851b_chip_info = {
2340 .chip_id = RTL8851B,
2341 .chip_gen = RTW89_CHIP_AX,
2342 .ops = &rtw8851b_chip_ops,
2343 .mac_def = &rtw89_mac_gen_ax,
2344 .phy_def = &rtw89_phy_gen_ax,
2345 .fw_basename = RTW8851B_FW_BASENAME,
2346 .fw_format_max = RTW8851B_FW_FORMAT_MAX,
2347 .try_ce_fw = true,
2348 .needed_fw_elms = 0,
2349 .fifo_size = 196608,
2350 .small_fifo_size = true,
2351 .dle_scc_rsvd_size = 98304,
2352 .max_amsdu_limit = 3500,
2353 .dis_2g_40m_ul_ofdma = true,
2354 .rsvd_ple_ofst = 0x2f800,
2355 .hfc_param_ini = rtw8851b_hfc_param_ini_pcie,
2356 .dle_mem = rtw8851b_dle_mem_pcie,
2357 .wde_qempty_acq_num = 4,
2358 .wde_qempty_mgq_sel = 4,
2359 .rf_base_addr = {0xe000},
2360 .pwr_on_seq = NULL,
2361 .pwr_off_seq = NULL,
2362 .bb_table = &rtw89_8851b_phy_bb_table,
2363 .bb_gain_table = &rtw89_8851b_phy_bb_gain_table,
2364 .rf_table = {&rtw89_8851b_phy_radioa_table,},
2365 .nctl_table = &rtw89_8851b_phy_nctl_table,
2366 .nctl_post_table = &rtw8851b_nctl_post_defs_tbl,
2367 .byr_table = &rtw89_8851b_byr_table,
2368 .dflt_parms = &rtw89_8851b_dflt_parms,
2369 .rfe_parms_conf = rtw89_8851b_rfe_parms_conf,
2370 .txpwr_factor_rf = 2,
2371 .txpwr_factor_mac = 1,
2372 .dig_table = NULL,
2373 .dig_regs = &rtw8851b_dig_regs,
2374 .tssi_dbw_table = NULL,
2375 .support_chanctx_num = 0,
2376 .support_bands = BIT(NL80211_BAND_2GHZ) |
2377 BIT(NL80211_BAND_5GHZ),
2378 .support_bw160 = false,
2379 .support_unii4 = true,
2380 .support_ul_tb_ctrl = true,
2381 .hw_sec_hdr = false,
2382 .rf_path_num = 1,
2383 .tx_nss = 1,
2384 .rx_nss = 1,
2385 .acam_num = 32,
2386 .bcam_num = 20,
2387 .scam_num = 128,
2388 .bacam_num = 2,
2389 .bacam_dynamic_num = 4,
2390 .bacam_ver = RTW89_BACAM_V0,
2391 .sec_ctrl_efuse_size = 4,
2392 .physical_efuse_size = 1216,
2393 .logical_efuse_size = 2048,
2394 .limit_efuse_size = 1280,
2395 .dav_phy_efuse_size = 0,
2396 .dav_log_efuse_size = 0,
2397 .phycap_addr = 0x580,
2398 .phycap_size = 128,
2399 .para_ver = 0,
2400 .wlcx_desired = 0x06000000,
2401 .btcx_desired = 0x7,
2402 .scbd = 0x1,
2403 .mailbox = 0x1,
2404
2405 .afh_guard_ch = 6,
2406 .wl_rssi_thres = rtw89_btc_8851b_wl_rssi_thres,
2407 .bt_rssi_thres = rtw89_btc_8851b_bt_rssi_thres,
2408 .rssi_tol = 2,
2409 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8851b_mon_reg),
2410 .mon_reg = rtw89_btc_8851b_mon_reg,
2411 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_ul),
2412 .rf_para_ulink = rtw89_btc_8851b_rf_ul,
2413 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
2414 .rf_para_dlink = rtw89_btc_8851b_rf_dl,
2415 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2416 BIT(RTW89_PS_MODE_CLK_GATED),
2417 .low_power_hci_modes = 0,
2418 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2419 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2420 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2421 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2422 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2423 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2424 .h2c_regs = rtw8851b_h2c_regs,
2425 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2426 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2427 .c2h_regs = rtw8851b_c2h_regs,
2428 .page_regs = &rtw8851b_page_regs,
2429 .cfo_src_fd = true,
2430 .cfo_hw_comp = true,
2431 .dcfo_comp = &rtw8851b_dcfo_comp,
2432 .dcfo_comp_sft = 12,
2433 .imr_info = &rtw8851b_imr_info,
2434 .rrsr_cfgs = &rtw8851b_rrsr_cfgs,
2435 .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
2436 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
2437 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
2438 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
2439 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL_V1,
2440 #ifdef CONFIG_PM
2441 .wowlan_stub = &rtw_wowlan_stub_8851b,
2442 #endif
2443 .xtal_info = &rtw8851b_xtal_info,
2444 };
2445 EXPORT_SYMBOL(rtw8851b_chip_info);
2446
2447 MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE);
2448 MODULE_AUTHOR("Realtek Corporation");
2449 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver");
2450 MODULE_LICENSE("Dual BSD/GPL");
2451