1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * Contact Information: wlanfae <wlanfae@realtek.com>
6 */
7 #include <linux/bitops.h>
8 #include "rtl_core.h"
9 #include "r8192E_hw.h"
10 #include "r8192E_phyreg.h"
11 #include "r8190P_rtl8256.h"
12 #include "r8192E_phy.h"
13 #include "rtl_dm.h"
14
15 #include "table.h"
16
17 /*************************Define local function prototype**********************/
18
19 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
20 enum rf90_radio_path eRFPath, u32 Offset);
21 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
22 enum rf90_radio_path eRFPath, u32 Offset,
23 u32 Data);
24
_rtl92e_calculate_bit_shift(u32 dwBitMask)25 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask)
26 {
27 if (!dwBitMask)
28 return 32;
29 return ffs(dwBitMask) - 1;
30 }
31
rtl92e_set_bb_reg(struct net_device * dev,u32 dwRegAddr,u32 dwBitMask,u32 dwData)32 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
33 u32 dwData)
34 {
35 u32 OriginalValue, BitShift, NewValue;
36
37 if (dwBitMask != bMaskDWord) {
38 OriginalValue = rtl92e_readl(dev, dwRegAddr);
39 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
40 NewValue = (OriginalValue & ~dwBitMask) | (dwData << BitShift);
41 rtl92e_writel(dev, dwRegAddr, NewValue);
42 } else {
43 rtl92e_writel(dev, dwRegAddr, dwData);
44 }
45 }
46
rtl92e_get_bb_reg(struct net_device * dev,u32 dwRegAddr,u32 dwBitMask)47 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
48 {
49 u32 OriginalValue, BitShift;
50
51 OriginalValue = rtl92e_readl(dev, dwRegAddr);
52 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
53
54 return (OriginalValue & dwBitMask) >> BitShift;
55 }
56
_rtl92e_phy_rf_read(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset)57 static u32 _rtl92e_phy_rf_read(struct net_device *dev,
58 enum rf90_radio_path eRFPath, u32 Offset)
59 {
60 struct r8192_priv *priv = rtllib_priv(dev);
61 u32 ret = 0;
62 u32 NewOffset = 0;
63 struct bb_reg_definition *pPhyReg = &priv->phy_reg_def[eRFPath];
64
65 Offset &= 0x3f;
66
67 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
68 if (Offset >= 31) {
69 priv->rf_reg_0value[eRFPath] |= 0x140;
70 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
71 bMaskDWord,
72 (priv->rf_reg_0value[eRFPath] << 16));
73 NewOffset = Offset - 30;
74 } else if (Offset >= 16) {
75 priv->rf_reg_0value[eRFPath] |= 0x100;
76 priv->rf_reg_0value[eRFPath] &= (~0x40);
77 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
78 bMaskDWord,
79 (priv->rf_reg_0value[eRFPath] << 16));
80 NewOffset = Offset - 15;
81 } else {
82 NewOffset = Offset;
83 }
84 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
85 NewOffset);
86 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
87 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
88
89 mdelay(1);
90
91 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack,
92 bLSSIReadBackData);
93
94 priv->rf_reg_0value[eRFPath] &= 0xebf;
95
96 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
97 (priv->rf_reg_0value[eRFPath] << 16));
98
99 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
100
101 return ret;
102 }
103
_rtl92e_phy_rf_write(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data)104 static void _rtl92e_phy_rf_write(struct net_device *dev,
105 enum rf90_radio_path eRFPath, u32 Offset,
106 u32 Data)
107 {
108 struct r8192_priv *priv = rtllib_priv(dev);
109 u32 DataAndAddr = 0, NewOffset = 0;
110 struct bb_reg_definition *pPhyReg = &priv->phy_reg_def[eRFPath];
111
112 Offset &= 0x3f;
113
114 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
115
116 if (Offset >= 31) {
117 priv->rf_reg_0value[eRFPath] |= 0x140;
118 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
119 bMaskDWord,
120 (priv->rf_reg_0value[eRFPath] << 16));
121 NewOffset = Offset - 30;
122 } else if (Offset >= 16) {
123 priv->rf_reg_0value[eRFPath] |= 0x100;
124 priv->rf_reg_0value[eRFPath] &= (~0x40);
125 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
126 bMaskDWord,
127 (priv->rf_reg_0value[eRFPath] << 16));
128 NewOffset = Offset - 15;
129 } else {
130 NewOffset = Offset;
131 }
132
133 DataAndAddr = (NewOffset & 0x3f) | (Data << 16);
134
135 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
136
137 if (Offset == 0x0)
138 priv->rf_reg_0value[eRFPath] = Data;
139
140 if (Offset != 0) {
141 priv->rf_reg_0value[eRFPath] &= 0xebf;
142 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
143 bMaskDWord,
144 (priv->rf_reg_0value[eRFPath] << 16));
145 }
146 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
147 }
148
rtl92e_set_rf_reg(struct net_device * dev,enum rf90_radio_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)149 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
150 u32 RegAddr, u32 BitMask, u32 Data)
151 {
152 struct r8192_priv *priv = rtllib_priv(dev);
153 u32 Original_Value, BitShift, New_Value;
154
155 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter)
156 return;
157
158 if (priv->rf_mode == RF_OP_By_FW) {
159 if (BitMask != bMask12Bits) {
160 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath,
161 RegAddr);
162 BitShift = _rtl92e_calculate_bit_shift(BitMask);
163 New_Value = (Original_Value & ~BitMask) | (Data << BitShift);
164
165 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr,
166 New_Value);
167 } else {
168 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data);
169 }
170 udelay(200);
171 } else {
172 if (BitMask != bMask12Bits) {
173 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath,
174 RegAddr);
175 BitShift = _rtl92e_calculate_bit_shift(BitMask);
176 New_Value = (Original_Value & ~BitMask) | (Data << BitShift);
177
178 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value);
179 } else {
180 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data);
181 }
182 }
183 }
184
rtl92e_get_rf_reg(struct net_device * dev,enum rf90_radio_path eRFPath,u32 RegAddr,u32 BitMask)185 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
186 u32 RegAddr, u32 BitMask)
187 {
188 u32 Original_Value, Readback_Value, BitShift;
189 struct r8192_priv *priv = rtllib_priv(dev);
190
191 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter)
192 return 0;
193 mutex_lock(&priv->rf_mutex);
194 if (priv->rf_mode == RF_OP_By_FW) {
195 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr);
196 udelay(200);
197 } else {
198 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr);
199 }
200 BitShift = _rtl92e_calculate_bit_shift(BitMask);
201 Readback_Value = (Original_Value & BitMask) >> BitShift;
202 mutex_unlock(&priv->rf_mutex);
203 return Readback_Value;
204 }
205
_rtl92e_phy_rf_fw_read(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset)206 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
207 enum rf90_radio_path eRFPath, u32 Offset)
208 {
209 u32 Data = 0;
210 u8 time = 0;
211
212 Data |= ((Offset & 0xFF) << 12);
213 Data |= ((eRFPath & 0x3) << 20);
214 Data |= 0x80000000;
215 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
216 if (time++ < 100)
217 udelay(10);
218 else
219 break;
220 }
221 rtl92e_writel(dev, QPNR, Data);
222 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
223 if (time++ < 100)
224 udelay(10);
225 else
226 return 0;
227 }
228 return rtl92e_readl(dev, RF_DATA);
229 }
230
_rtl92e_phy_rf_fw_write(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data)231 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
232 enum rf90_radio_path eRFPath, u32 Offset,
233 u32 Data)
234 {
235 u8 time = 0;
236
237 Data |= ((Offset & 0xFF) << 12);
238 Data |= ((eRFPath & 0x3) << 20);
239 Data |= 0x400000;
240 Data |= 0x80000000;
241
242 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
243 if (time++ < 100)
244 udelay(10);
245 else
246 break;
247 }
248 rtl92e_writel(dev, QPNR, Data);
249 }
250
rtl92e_config_mac(struct net_device * dev)251 void rtl92e_config_mac(struct net_device *dev)
252 {
253 u32 dwArrayLen = 0, i = 0;
254 u32 *pdwArray = NULL;
255 struct r8192_priv *priv = rtllib_priv(dev);
256
257 if (priv->tx_pwr_data_read_from_eeprom) {
258 dwArrayLen = RTL8192E_MACPHY_ARR_PG_LEN;
259 pdwArray = RTL8192E_MACPHY_ARR_PG;
260
261 } else {
262 dwArrayLen = RTL8192E_MACPHY_ARR_LEN;
263 pdwArray = RTL8192E_MACPHY_ARR;
264 }
265 for (i = 0; i < dwArrayLen; i += 3) {
266 if (pdwArray[i] == 0x318)
267 pdwArray[i + 2] = 0x00000800;
268 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i + 1],
269 pdwArray[i + 2]);
270 }
271 }
272
_rtl92e_phy_config_bb(struct net_device * dev,u8 ConfigType)273 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
274 {
275 int i;
276 u32 *Rtl819XPHY_REGArray_Table = NULL;
277 u32 *Rtl819XAGCTAB_Array_Table = NULL;
278 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
279
280 AGCTAB_ArrayLen = RTL8192E_AGCTAB_ARR_LEN;
281 Rtl819XAGCTAB_Array_Table = RTL8192E_AGCTAB_ARR;
282 PHY_REGArrayLen = RTL8192E_PHY_REG_1T2R_ARR_LEN;
283 Rtl819XPHY_REGArray_Table = RTL8192E_PHY_REG_1T2R_ARR;
284
285 if (ConfigType == BB_CONFIG_PHY_REG) {
286 for (i = 0; i < PHY_REGArrayLen; i += 2) {
287 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i],
288 bMaskDWord,
289 Rtl819XPHY_REGArray_Table[i + 1]);
290 }
291 } else if (ConfigType == BB_CONFIG_AGC_TAB) {
292 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
293 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i],
294 bMaskDWord,
295 Rtl819XAGCTAB_Array_Table[i + 1]);
296 }
297 }
298 }
299
_rtl92e_init_bb_rf_reg_def(struct net_device * dev)300 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev)
301 {
302 struct r8192_priv *priv = rtllib_priv(dev);
303
304 priv->phy_reg_def[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
305 priv->phy_reg_def[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
306
307 priv->phy_reg_def[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
308 priv->phy_reg_def[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
309
310 priv->phy_reg_def[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
311 priv->phy_reg_def[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
312
313 priv->phy_reg_def[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
314 priv->phy_reg_def[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
315
316 priv->phy_reg_def[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
317 priv->phy_reg_def[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
318
319 priv->phy_reg_def[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
320 priv->phy_reg_def[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
321 }
322
rtl92e_check_bb_and_rf(struct net_device * dev,enum hw90_block CheckBlock,enum rf90_radio_path eRFPath)323 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock,
324 enum rf90_radio_path eRFPath)
325 {
326 bool ret = true;
327 u32 i, CheckTimes = 4, dwRegRead = 0;
328 u32 WriteAddr[4];
329 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
330
331 WriteAddr[HW90_BLOCK_MAC] = 0x100;
332 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
333 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
334 WriteAddr[HW90_BLOCK_RF] = 0x3;
335
336 if (CheckBlock == HW90_BLOCK_MAC) {
337 netdev_warn(dev, "%s(): No checks available for MAC block.\n",
338 __func__);
339 return ret;
340 }
341
342 for (i = 0; i < CheckTimes; i++) {
343 switch (CheckBlock) {
344 case HW90_BLOCK_PHY0:
345 case HW90_BLOCK_PHY1:
346 rtl92e_writel(dev, WriteAddr[CheckBlock],
347 WriteData[i]);
348 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]);
349 break;
350
351 case HW90_BLOCK_RF:
352 WriteData[i] &= 0xfff;
353 rtl92e_set_rf_reg(dev, eRFPath,
354 WriteAddr[HW90_BLOCK_RF],
355 bMask12Bits, WriteData[i]);
356 mdelay(10);
357 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath,
358 WriteAddr[HW90_BLOCK_RF],
359 bMaskDWord);
360 mdelay(10);
361 break;
362
363 default:
364 ret = false;
365 break;
366 }
367
368 if (dwRegRead != WriteData[i]) {
369 netdev_warn(dev, "%s(): Check failed.\n", __func__);
370 ret = false;
371 break;
372 }
373 }
374
375 return ret;
376 }
377
_rtl92e_bb_config_para_file(struct net_device * dev)378 static bool _rtl92e_bb_config_para_file(struct net_device *dev)
379 {
380 struct r8192_priv *priv = rtllib_priv(dev);
381 bool rtStatus = true;
382 u8 bRegValue = 0, eCheckItem = 0;
383 u32 dwRegValue = 0;
384
385 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET);
386 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue | BB_GLOBAL_RESET_BIT));
387
388 dwRegValue = rtl92e_readl(dev, CPU_GEN);
389 rtl92e_writel(dev, CPU_GEN, (dwRegValue & (~CPU_GEN_BB_RST)));
390
391 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
392 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
393 rtStatus = rtl92e_check_bb_and_rf(dev,
394 (enum hw90_block)eCheckItem,
395 (enum rf90_radio_path)0);
396 if (!rtStatus)
397 return rtStatus;
398 }
399 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn | bOFDMEn, 0x0);
400 _rtl92e_phy_config_bb(dev, BB_CONFIG_PHY_REG);
401
402 dwRegValue = rtl92e_readl(dev, CPU_GEN);
403 rtl92e_writel(dev, CPU_GEN, (dwRegValue | CPU_GEN_BB_RST));
404
405 _rtl92e_phy_config_bb(dev, BB_CONFIG_AGC_TAB);
406
407 if (priv->ic_cut > VERSION_8190_BD) {
408 dwRegValue = 0x0;
409 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
410 (bXBTxAGC | bXCTxAGC | bXDTxAGC), dwRegValue);
411
412 dwRegValue = priv->crystal_cap;
413 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
414 dwRegValue);
415 }
416
417 return rtStatus;
418 }
rtl92e_config_bb(struct net_device * dev)419 bool rtl92e_config_bb(struct net_device *dev)
420 {
421 _rtl92e_init_bb_rf_reg_def(dev);
422 return _rtl92e_bb_config_para_file(dev);
423 }
424
rtl92e_get_tx_power(struct net_device * dev)425 void rtl92e_get_tx_power(struct net_device *dev)
426 {
427 struct r8192_priv *priv = rtllib_priv(dev);
428
429 priv->mcs_tx_pwr_level_org_offset[0] =
430 rtl92e_readl(dev, rTxAGC_Rate18_06);
431 priv->mcs_tx_pwr_level_org_offset[1] =
432 rtl92e_readl(dev, rTxAGC_Rate54_24);
433 priv->mcs_tx_pwr_level_org_offset[2] =
434 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00);
435 priv->mcs_tx_pwr_level_org_offset[3] =
436 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04);
437 priv->mcs_tx_pwr_level_org_offset[4] =
438 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08);
439 priv->mcs_tx_pwr_level_org_offset[5] =
440 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12);
441
442 priv->def_initial_gain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1);
443 priv->def_initial_gain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1);
444 priv->def_initial_gain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1);
445 priv->def_initial_gain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1);
446
447 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3);
448 }
449
rtl92e_set_tx_power(struct net_device * dev,u8 channel)450 void rtl92e_set_tx_power(struct net_device *dev, u8 channel)
451 {
452 struct r8192_priv *priv = rtllib_priv(dev);
453 u8 powerlevel = 0, powerlevelOFDM24G = 0;
454
455 if (priv->epromtype == EEPROM_93C46) {
456 powerlevel = priv->tx_pwr_level_cck[channel - 1];
457 powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1];
458 }
459
460 rtl92e_set_cck_tx_power(dev, powerlevel);
461 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
462 }
463
rtl92e_config_rf_path(struct net_device * dev,enum rf90_radio_path eRFPath)464 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
465 {
466 int i;
467
468 switch (eRFPath) {
469 case RF90_PATH_A:
470 for (i = 0; i < RTL8192E_RADIO_A_ARR_LEN; i += 2) {
471 if (RTL8192E_RADIO_A_ARR[i] == 0xfe) {
472 msleep(100);
473 continue;
474 }
475 rtl92e_set_rf_reg(dev, eRFPath, RTL8192E_RADIO_A_ARR[i],
476 bMask12Bits,
477 RTL8192E_RADIO_A_ARR[i + 1]);
478 }
479 break;
480 case RF90_PATH_B:
481 for (i = 0; i < RTL8192E_RADIO_B_ARR_LEN; i += 2) {
482 if (RTL8192E_RADIO_B_ARR[i] == 0xfe) {
483 msleep(100);
484 continue;
485 }
486 rtl92e_set_rf_reg(dev, eRFPath, RTL8192E_RADIO_B_ARR[i],
487 bMask12Bits,
488 RTL8192E_RADIO_B_ARR[i + 1]);
489 }
490 break;
491 default:
492 break;
493 }
494
495 return 0;
496 }
497
_rtl92e_set_tx_power_level(struct net_device * dev,u8 channel)498 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel)
499 {
500 struct r8192_priv *priv = rtllib_priv(dev);
501 u8 powerlevel = priv->tx_pwr_level_cck[channel - 1];
502 u8 powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1];
503
504 rtl92e_set_cck_tx_power(dev, powerlevel);
505 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
506 }
507
_rtl92e_phy_set_sw_chnl_cmd_array(struct net_device * dev,struct sw_chnl_cmd * CmdTable,u32 CmdTableIdx,u32 CmdTableSz,enum sw_chnl_cmd_id CmdID,u32 Para1,u32 Para2,u32 msDelay)508 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev,
509 struct sw_chnl_cmd *CmdTable,
510 u32 CmdTableIdx, u32 CmdTableSz,
511 enum sw_chnl_cmd_id CmdID,
512 u32 Para1, u32 Para2, u32 msDelay)
513 {
514 struct sw_chnl_cmd *pCmd;
515
516 if (CmdTable == NULL) {
517 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__);
518 return false;
519 }
520 if (CmdTableIdx >= CmdTableSz) {
521 netdev_err(dev, "%s(): Invalid index requested.\n", __func__);
522 return false;
523 }
524
525 pCmd = CmdTable + CmdTableIdx;
526 pCmd->CmdID = CmdID;
527 pCmd->Para1 = Para1;
528 pCmd->Para2 = Para2;
529 pCmd->msDelay = msDelay;
530
531 return true;
532 }
533
_rtl92e_phy_switch_channel_step(struct net_device * dev,u8 channel,u8 * stage,u8 * step,u32 * delay)534 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel,
535 u8 *stage, u8 *step, u32 *delay)
536 {
537 struct r8192_priv *priv = rtllib_priv(dev);
538 struct rtllib_device *ieee = priv->rtllib;
539 u32 PreCommonCmdCnt;
540 u32 PostCommonCmdCnt;
541 u32 RfDependCmdCnt;
542 struct sw_chnl_cmd *CurrentCmd = NULL;
543 u8 eRFPath;
544
545 if (!rtllib_legal_channel(priv->rtllib, channel)) {
546 netdev_err(dev, "Invalid channel requested: %d\n", channel);
547 return true;
548 }
549
550 {
551 PreCommonCmdCnt = 0;
552 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
553 PreCommonCmdCnt++,
554 MAX_PRECMD_CNT,
555 CmdID_SetTxPowerLevel,
556 0, 0, 0);
557 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
558 PreCommonCmdCnt++,
559 MAX_PRECMD_CNT, CmdID_End,
560 0, 0, 0);
561
562 PostCommonCmdCnt = 0;
563
564 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd,
565 PostCommonCmdCnt++,
566 MAX_POSTCMD_CNT, CmdID_End,
567 0, 0, 0);
568
569 RfDependCmdCnt = 0;
570
571 if (!(channel >= 1 && channel <= 14)) {
572 netdev_err(dev,
573 "Invalid channel requested for 8256: %d\n",
574 channel);
575 return false;
576 }
577 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
578 ieee->RfDependCmd,
579 RfDependCmdCnt++,
580 MAX_RFDEPENDCMD_CNT,
581 CmdID_RF_WriteReg,
582 rZebra1_Channel,
583 channel, 10);
584 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
585 ieee->RfDependCmd,
586 RfDependCmdCnt++,
587 MAX_RFDEPENDCMD_CNT,
588 CmdID_End, 0, 0, 0);
589
590 do {
591 switch (*stage) {
592 case 0:
593 CurrentCmd = &ieee->PreCommonCmd[*step];
594 break;
595 case 1:
596 CurrentCmd = &ieee->RfDependCmd[*step];
597 break;
598 case 2:
599 CurrentCmd = &ieee->PostCommonCmd[*step];
600 break;
601 }
602
603 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
604 if ((*stage) == 2)
605 return true;
606 (*stage)++;
607 (*step) = 0;
608 continue;
609 }
610
611 if (!CurrentCmd)
612 continue;
613 switch (CurrentCmd->CmdID) {
614 case CmdID_SetTxPowerLevel:
615 if (priv->ic_cut > VERSION_8190_BD)
616 _rtl92e_set_tx_power_level(dev,
617 channel);
618 break;
619 case CmdID_WritePortUlong:
620 rtl92e_writel(dev, CurrentCmd->Para1,
621 CurrentCmd->Para2);
622 break;
623 case CmdID_WritePortUshort:
624 rtl92e_writew(dev, CurrentCmd->Para1,
625 CurrentCmd->Para2);
626 break;
627 case CmdID_WritePortUchar:
628 rtl92e_writeb(dev, CurrentCmd->Para1,
629 CurrentCmd->Para2);
630 break;
631 case CmdID_RF_WriteReg:
632 for (eRFPath = 0; eRFPath <
633 priv->num_total_rf_path; eRFPath++)
634 rtl92e_set_rf_reg(dev,
635 (enum rf90_radio_path)eRFPath,
636 CurrentCmd->Para1, bMask12Bits,
637 CurrentCmd->Para2 << 7);
638 break;
639 default:
640 break;
641 }
642
643 break;
644 } while (true);
645 } /*for (Number of RF paths)*/
646
647 (*delay) = CurrentCmd->msDelay;
648 (*step)++;
649 return false;
650 }
651
_rtl92e_phy_switch_channel(struct net_device * dev,u8 channel)652 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel)
653 {
654 struct r8192_priv *priv = rtllib_priv(dev);
655 u32 delay = 0;
656
657 while (!_rtl92e_phy_switch_channel_step(dev, channel,
658 &priv->sw_chnl_stage,
659 &priv->sw_chnl_step, &delay)) {
660 if (delay > 0)
661 msleep(delay);
662 if (!priv->up)
663 break;
664 }
665 }
666
_rtl92e_phy_switch_channel_work_item(struct net_device * dev)667 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev)
668 {
669 struct r8192_priv *priv = rtllib_priv(dev);
670
671 _rtl92e_phy_switch_channel(dev, priv->chan);
672 }
673
rtl92e_set_channel(struct net_device * dev,u8 channel)674 u8 rtl92e_set_channel(struct net_device *dev, u8 channel)
675 {
676 struct r8192_priv *priv = rtllib_priv(dev);
677
678 if (!priv->up) {
679 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
680 return false;
681 }
682 if (priv->sw_chnl_in_progress)
683 return false;
684
685 switch (priv->rtllib->mode) {
686 case WIRELESS_MODE_B:
687 if (channel > 14) {
688 netdev_warn(dev,
689 "Channel %d not available in 802.11b.\n",
690 channel);
691 return false;
692 }
693 break;
694 case WIRELESS_MODE_G:
695 case WIRELESS_MODE_N_24G:
696 if (channel > 14) {
697 netdev_warn(dev,
698 "Channel %d not available in 802.11g.\n",
699 channel);
700 return false;
701 }
702 break;
703 }
704
705 priv->sw_chnl_in_progress = true;
706 if (channel == 0)
707 channel = 1;
708
709 priv->chan = channel;
710
711 priv->sw_chnl_stage = 0;
712 priv->sw_chnl_step = 0;
713
714 if (priv->up)
715 _rtl92e_phy_switch_channel_work_item(dev);
716 priv->sw_chnl_in_progress = false;
717 return true;
718 }
719
_rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device * dev)720 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev)
721 {
722 struct r8192_priv *priv = rtllib_priv(dev);
723
724 switch (priv->current_chnl_bw) {
725 case HT_CHANNEL_WIDTH_20:
726 priv->cck_present_attn =
727 priv->cck_present_attn_20m_def +
728 priv->cck_present_attn_diff;
729
730 if (priv->cck_present_attn >
731 (CCK_TX_BB_GAIN_TABLE_LEN - 1))
732 priv->cck_present_attn =
733 CCK_TX_BB_GAIN_TABLE_LEN - 1;
734 if (priv->cck_present_attn < 0)
735 priv->cck_present_attn = 0;
736
737 if (priv->rtllib->current_network.channel == 14 &&
738 !priv->bcck_in_ch14) {
739 priv->bcck_in_ch14 = true;
740 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
741 } else if (priv->rtllib->current_network.channel !=
742 14 && priv->bcck_in_ch14) {
743 priv->bcck_in_ch14 = false;
744 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
745 } else {
746 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
747 }
748 break;
749
750 case HT_CHANNEL_WIDTH_20_40:
751 priv->cck_present_attn =
752 priv->cck_present_attn_40m_def +
753 priv->cck_present_attn_diff;
754
755 if (priv->cck_present_attn >
756 (CCK_TX_BB_GAIN_TABLE_LEN - 1))
757 priv->cck_present_attn =
758 CCK_TX_BB_GAIN_TABLE_LEN - 1;
759 if (priv->cck_present_attn < 0)
760 priv->cck_present_attn = 0;
761
762 if (priv->rtllib->current_network.channel == 14 &&
763 !priv->bcck_in_ch14) {
764 priv->bcck_in_ch14 = true;
765 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
766 } else if (priv->rtllib->current_network.channel != 14
767 && priv->bcck_in_ch14) {
768 priv->bcck_in_ch14 = false;
769 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
770 } else {
771 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
772 }
773 break;
774 }
775 }
776
_rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device * dev)777 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev)
778 {
779 struct r8192_priv *priv = rtllib_priv(dev);
780
781 if (priv->rtllib->current_network.channel == 14 &&
782 !priv->bcck_in_ch14)
783 priv->bcck_in_ch14 = true;
784 else if (priv->rtllib->current_network.channel != 14 &&
785 priv->bcck_in_ch14)
786 priv->bcck_in_ch14 = false;
787
788 switch (priv->current_chnl_bw) {
789 case HT_CHANNEL_WIDTH_20:
790 if (priv->rec_cck_20m_idx == 0)
791 priv->rec_cck_20m_idx = 6;
792 priv->cck_index = priv->rec_cck_20m_idx;
793 break;
794
795 case HT_CHANNEL_WIDTH_20_40:
796 priv->cck_index = priv->rec_cck_40m_idx;
797 break;
798 }
799 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
800 }
801
_rtl92e_cck_tx_power_track_bw_switch(struct net_device * dev)802 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev)
803 {
804 struct r8192_priv *priv = rtllib_priv(dev);
805
806 if (priv->ic_cut >= IC_VersionCut_D)
807 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev);
808 else
809 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev);
810 }
811
_rtl92e_set_bw_mode_work_item(struct net_device * dev)812 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev)
813 {
814 struct r8192_priv *priv = rtllib_priv(dev);
815 u8 regBwOpMode;
816
817 if (!priv->up) {
818 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
819 return;
820 }
821 regBwOpMode = rtl92e_readb(dev, BW_OPMODE);
822
823 switch (priv->current_chnl_bw) {
824 case HT_CHANNEL_WIDTH_20:
825 regBwOpMode |= BW_OPMODE_20MHZ;
826 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
827 break;
828
829 case HT_CHANNEL_WIDTH_20_40:
830 regBwOpMode &= ~BW_OPMODE_20MHZ;
831 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
832 break;
833
834 default:
835 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
836 priv->current_chnl_bw);
837 break;
838 }
839
840 switch (priv->current_chnl_bw) {
841 case HT_CHANNEL_WIDTH_20:
842 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
843 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
844
845 if (!priv->btxpower_tracking) {
846 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000);
847 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317);
848 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204);
849 } else {
850 _rtl92e_cck_tx_power_track_bw_switch(dev);
851 }
852
853 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
854
855 break;
856 case HT_CHANNEL_WIDTH_20_40:
857 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
858 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
859
860 if (!priv->btxpower_tracking) {
861 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000);
862 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e);
863 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409);
864 } else {
865 _rtl92e_cck_tx_power_track_bw_switch(dev);
866 }
867
868 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand,
869 (priv->n_cur_40mhz_prime_sc >> 1));
870 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00,
871 priv->n_cur_40mhz_prime_sc);
872
873 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
874 break;
875 default:
876 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
877 priv->current_chnl_bw);
878 break;
879 }
880
881 rtl92e_set_bandwidth(dev, priv->current_chnl_bw);
882
883 atomic_dec(&(priv->rtllib->atm_swbw));
884 priv->set_bw_mode_in_progress = false;
885 }
886
rtl92e_set_bw_mode(struct net_device * dev,enum ht_channel_width bandwidth,enum ht_extchnl_offset Offset)887 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width bandwidth,
888 enum ht_extchnl_offset Offset)
889 {
890 struct r8192_priv *priv = rtllib_priv(dev);
891
892 if (priv->set_bw_mode_in_progress)
893 return;
894
895 atomic_inc(&(priv->rtllib->atm_swbw));
896 priv->set_bw_mode_in_progress = true;
897
898 priv->current_chnl_bw = bandwidth;
899
900 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
901 priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_UPPER;
902 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
903 priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_LOWER;
904 else
905 priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
906
907 _rtl92e_set_bw_mode_work_item(dev);
908 }
909
rtl92e_init_gain(struct net_device * dev,u8 Operation)910 void rtl92e_init_gain(struct net_device *dev, u8 Operation)
911 {
912 #define SCAN_RX_INITIAL_GAIN 0x17
913 #define POWER_DETECTION_TH 0x08
914 struct r8192_priv *priv = rtllib_priv(dev);
915 u32 BitMask;
916 u8 initial_gain;
917
918 if (priv->up) {
919 switch (Operation) {
920 case IG_Backup:
921 initial_gain = SCAN_RX_INITIAL_GAIN;
922 BitMask = bMaskByte0;
923 if (dm_digtable.dig_algorithm ==
924 DIG_ALGO_BY_FALSE_ALARM)
925 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
926 priv->initgain_backup.xaagccore1 =
927 rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1,
928 BitMask);
929 priv->initgain_backup.xbagccore1 =
930 rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1,
931 BitMask);
932 priv->initgain_backup.xcagccore1 =
933 rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1,
934 BitMask);
935 priv->initgain_backup.xdagccore1 =
936 rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1,
937 BitMask);
938 BitMask = bMaskByte2;
939 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev,
940 rCCK0_CCA, BitMask);
941
942 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain);
943 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain);
944 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain);
945 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain);
946 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH);
947 break;
948 case IG_Restore:
949 BitMask = 0x7f;
950 if (dm_digtable.dig_algorithm ==
951 DIG_ALGO_BY_FALSE_ALARM)
952 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
953
954 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask,
955 (u32)priv->initgain_backup.xaagccore1);
956 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask,
957 (u32)priv->initgain_backup.xbagccore1);
958 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask,
959 (u32)priv->initgain_backup.xcagccore1);
960 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask,
961 (u32)priv->initgain_backup.xdagccore1);
962 BitMask = bMaskByte2;
963 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask,
964 (u32)priv->initgain_backup.cca);
965
966 rtl92e_set_tx_power(dev,
967 priv->rtllib->current_network.channel);
968
969 if (dm_digtable.dig_algorithm ==
970 DIG_ALGO_BY_FALSE_ALARM)
971 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
972 break;
973 }
974 }
975 }
976
rtl92e_set_rf_off(struct net_device * dev)977 void rtl92e_set_rf_off(struct net_device *dev)
978 {
979 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
980 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
981 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
982 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
983 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
984 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
985 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
986 rtl92e_writeb(dev, ANAPAR_FOR_8192PCIE, 0x07);
987 }
988
_rtl92e_set_rf_power_state(struct net_device * dev,enum rt_rf_power_state rf_power_state)989 static bool _rtl92e_set_rf_power_state(struct net_device *dev,
990 enum rt_rf_power_state rf_power_state)
991 {
992 struct r8192_priv *priv = rtllib_priv(dev);
993 struct rt_pwr_save_ctrl *psc = (struct rt_pwr_save_ctrl *)
994 (&priv->rtllib->pwr_save_ctrl);
995 bool bResult = true;
996 u8 i = 0, QueueID = 0;
997 struct rtl8192_tx_ring *ring = NULL;
998
999 if (priv->set_rf_pwr_state_in_progress)
1000 return false;
1001 priv->set_rf_pwr_state_in_progress = true;
1002
1003 switch (rf_power_state) {
1004 case rf_on:
1005 if ((priv->rtllib->rf_power_state == rf_off) &&
1006 RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) {
1007 bool rtstatus;
1008 u32 InitilizeCount = 3;
1009
1010 do {
1011 InitilizeCount--;
1012 rtstatus = rtl92e_enable_nic(dev);
1013 } while (!rtstatus && (InitilizeCount > 0));
1014 if (!rtstatus) {
1015 netdev_err(dev,
1016 "%s(): Failed to initialize Adapter.\n",
1017 __func__);
1018 priv->set_rf_pwr_state_in_progress = false;
1019 return false;
1020 }
1021 RT_CLEAR_PS_LEVEL(psc,
1022 RT_RF_OFF_LEVL_HALT_NIC);
1023 } else {
1024 rtl92e_writeb(dev, ANAPAR, 0x37);
1025 mdelay(1);
1026 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1027 0x4, 0x1);
1028 priv->hw_rf_off_action = 0;
1029 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
1030 BIT4, 0x1);
1031 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
1032 0x300, 0x3);
1033 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1034 0x18, 0x3);
1035 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
1036 0x3, 0x3);
1037 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
1038 0x3, 0x3);
1039 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1040 0x60, 0x3);
1041 }
1042 break;
1043 case rf_sleep:
1044 if (priv->rtllib->rf_power_state == rf_off)
1045 break;
1046 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1047 ring = &priv->tx_ring[QueueID];
1048 if (skb_queue_len(&ring->queue) == 0) {
1049 QueueID++;
1050 continue;
1051 } else {
1052 udelay(10);
1053 i++;
1054 }
1055 if (i >= MAX_DOZE_WAITING_TIMES_9x)
1056 break;
1057 }
1058 rtl92e_set_rf_off(dev);
1059 break;
1060 case rf_off:
1061 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1062 ring = &priv->tx_ring[QueueID];
1063 if (skb_queue_len(&ring->queue) == 0) {
1064 QueueID++;
1065 continue;
1066 } else {
1067 udelay(10);
1068 i++;
1069 }
1070 if (i >= MAX_DOZE_WAITING_TIMES_9x)
1071 break;
1072 }
1073 rtl92e_set_rf_off(dev);
1074 break;
1075 default:
1076 bResult = false;
1077 netdev_warn(dev,
1078 "%s(): Unknown state requested: 0x%X.\n",
1079 __func__, rf_power_state);
1080 break;
1081 }
1082
1083 if (bResult)
1084 priv->rtllib->rf_power_state = rf_power_state;
1085
1086 priv->set_rf_pwr_state_in_progress = false;
1087 return bResult;
1088 }
1089
rtl92e_set_rf_power_state(struct net_device * dev,enum rt_rf_power_state rf_power_state)1090 bool rtl92e_set_rf_power_state(struct net_device *dev,
1091 enum rt_rf_power_state rf_power_state)
1092 {
1093 struct r8192_priv *priv = rtllib_priv(dev);
1094
1095 bool bResult = false;
1096
1097 if (rf_power_state == priv->rtllib->rf_power_state &&
1098 priv->hw_rf_off_action == 0) {
1099 return bResult;
1100 }
1101
1102 bResult = _rtl92e_set_rf_power_state(dev, rf_power_state);
1103 return bResult;
1104 }
1105
rtl92e_scan_op_backup(struct net_device * dev,u8 Operation)1106 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation)
1107 {
1108 struct r8192_priv *priv = rtllib_priv(dev);
1109
1110 if (priv->up) {
1111 switch (Operation) {
1112 case SCAN_OPT_BACKUP:
1113 priv->rtllib->init_gain_handler(dev, IG_Backup);
1114 break;
1115
1116 case SCAN_OPT_RESTORE:
1117 priv->rtllib->init_gain_handler(dev, IG_Restore);
1118 break;
1119 }
1120 }
1121 }
1122