1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * Based on the r8180 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
7 *
8 * Contact Information: wlanfae <wlanfae@realtek.com>
9 */
10 #include "rtl_core.h"
11 #include "r8192E_phy.h"
12 #include "r8192E_phyreg.h"
13 #include "r8190P_rtl8256.h"
14 #include "r8192E_cmdpkt.h"
15 #include "rtl_dm.h"
16 #include "rtl_wx.h"
17
18 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
19 EDCAPARA_VO};
20
rtl92e_start_beacon(struct net_device * dev)21 void rtl92e_start_beacon(struct net_device *dev)
22 {
23 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
24 struct rtllib_network *net = &priv->rtllib->current_network;
25 u16 BcnTimeCfg = 0;
26 u16 BcnCW = 6;
27 u16 BcnIFS = 0xf;
28
29 rtl92e_irq_disable(dev);
30
31 rtl92e_writew(dev, ATIMWND, 2);
32
33 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
34 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
35 rtl92e_writew(dev, BCN_DMATIME, 256);
36
37 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
38
39 BcnTimeCfg |= BcnCW << BCN_TCFG_CW_SHIFT;
40 BcnTimeCfg |= BcnIFS << BCN_TCFG_IFS;
41 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
42 rtl92e_irq_enable(dev);
43 }
44
_rtl92e_update_msr(struct net_device * dev)45 static void _rtl92e_update_msr(struct net_device *dev)
46 {
47 struct r8192_priv *priv = rtllib_priv(dev);
48 u8 msr;
49
50 msr = rtl92e_readb(dev, MSR);
51 msr &= ~MSR_LINK_MASK;
52
53 switch (priv->rtllib->iw_mode) {
54 case IW_MODE_INFRA:
55 if (priv->rtllib->link_state == MAC80211_LINKED)
56 msr |= MSR_LINK_MANAGED;
57 break;
58 case IW_MODE_ADHOC:
59 if (priv->rtllib->link_state == MAC80211_LINKED)
60 msr |= MSR_LINK_ADHOC;
61 break;
62 default:
63 break;
64 }
65
66 rtl92e_writeb(dev, MSR, msr);
67 }
68
rtl92e_set_reg(struct net_device * dev,u8 variable,u8 * val)69 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
70 {
71 struct r8192_priv *priv = rtllib_priv(dev);
72
73 switch (variable) {
74 case HW_VAR_BSSID:
75 /* BSSIDR 2 byte alignment */
76 rtl92e_writew(dev, BSSIDR, *(u16 *)val);
77 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2));
78 break;
79
80 case HW_VAR_MEDIA_STATUS:
81 {
82 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
83 u8 btMsr = rtl92e_readb(dev, MSR);
84
85 btMsr &= 0xfc;
86
87 switch (OpMode) {
88 case RT_OP_MODE_INFRASTRUCTURE:
89 btMsr |= MSR_INFRA;
90 break;
91
92 case RT_OP_MODE_IBSS:
93 btMsr |= MSR_ADHOC;
94 break;
95
96 case RT_OP_MODE_AP:
97 btMsr |= MSR_AP;
98 break;
99
100 default:
101 btMsr |= MSR_NOLINK;
102 break;
103 }
104
105 rtl92e_writeb(dev, MSR, btMsr);
106 }
107 break;
108
109 case HW_VAR_CECHK_BSSID:
110 {
111 u32 RegRCR, Type;
112
113 Type = val[0];
114 RegRCR = rtl92e_readl(dev, RCR);
115 priv->receive_config = RegRCR;
116
117 if (Type)
118 RegRCR |= (RCR_CBSSID);
119 else
120 RegRCR &= (~RCR_CBSSID);
121
122 rtl92e_writel(dev, RCR, RegRCR);
123 priv->receive_config = RegRCR;
124 }
125 break;
126
127 case HW_VAR_SLOT_TIME:
128
129 priv->slot_time = val[0];
130 rtl92e_writeb(dev, SLOT_TIME, val[0]);
131
132 break;
133
134 case HW_VAR_ACK_PREAMBLE:
135 {
136 u32 regTmp;
137
138 priv->short_preamble = (bool)*val;
139 regTmp = priv->basic_rate;
140 if (priv->short_preamble)
141 regTmp |= BRSR_AckShortPmb;
142 rtl92e_writel(dev, RRSR, regTmp);
143 break;
144 }
145
146 case HW_VAR_CPU_RST:
147 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
148 break;
149
150 case HW_VAR_AC_PARAM:
151 {
152 u8 pAcParam = *val;
153 u32 eACI = pAcParam;
154 u8 u1bAIFS;
155 u32 u4bAcParam;
156 u8 mode = priv->rtllib->mode;
157 struct rtllib_qos_parameters *qop =
158 &priv->rtllib->current_network.qos_data.parameters;
159
160 u1bAIFS = qop->aifs[pAcParam] *
161 ((mode & (WIRELESS_MODE_G | WIRELESS_MODE_N_24G)) ? 9 : 20) + aSifsTime;
162
163 rtl92e_dm_init_edca_turbo(dev);
164
165 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
166 AC_PARAM_TXOP_LIMIT_OFFSET) |
167 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
168 AC_PARAM_ECW_MAX_OFFSET) |
169 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
170 AC_PARAM_ECW_MIN_OFFSET) |
171 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
172
173 switch (eACI) {
174 case AC1_BK:
175 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
176 break;
177
178 case AC0_BE:
179 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
180 break;
181
182 case AC2_VI:
183 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
184 break;
185
186 case AC3_VO:
187 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
188 break;
189
190 default:
191 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
192 eACI);
193 break;
194 }
195 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
196 &pAcParam);
197 break;
198 }
199
200 case HW_VAR_ACM_CTRL:
201 {
202 struct rtllib_qos_parameters *qos_parameters =
203 &priv->rtllib->current_network.qos_data.parameters;
204 u8 pAcParam = *val;
205 u32 eACI = pAcParam;
206 union aci_aifsn *pAciAifsn = (union aci_aifsn *)&
207 (qos_parameters->aifs[0]);
208 u8 acm = pAciAifsn->f.acm;
209 u8 AcmCtrl = rtl92e_readb(dev, ACM_HW_CTRL);
210
211 if (acm) {
212 switch (eACI) {
213 case AC0_BE:
214 AcmCtrl |= ACM_HW_BEQ_EN;
215 break;
216
217 case AC2_VI:
218 AcmCtrl |= ACM_HW_VIQ_EN;
219 break;
220
221 case AC3_VO:
222 AcmCtrl |= ACM_HW_VOQ_EN;
223 break;
224 }
225 } else {
226 switch (eACI) {
227 case AC0_BE:
228 AcmCtrl &= (~ACM_HW_BEQ_EN);
229 break;
230
231 case AC2_VI:
232 AcmCtrl &= (~ACM_HW_VIQ_EN);
233 break;
234
235 case AC3_VO:
236 AcmCtrl &= (~ACM_HW_BEQ_EN);
237 break;
238
239 default:
240 break;
241 }
242 }
243 rtl92e_writeb(dev, ACM_HW_CTRL, AcmCtrl);
244 break;
245 }
246
247 case HW_VAR_SIFS:
248 rtl92e_writeb(dev, SIFS, val[0]);
249 rtl92e_writeb(dev, SIFS + 1, val[0]);
250 break;
251
252 case HW_VAR_RF_TIMING:
253 {
254 u8 Rf_Timing = *val;
255
256 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
257 break;
258 }
259
260 default:
261 break;
262 }
263 }
264
_rtl92e_read_eeprom_info(struct net_device * dev)265 static void _rtl92e_read_eeprom_info(struct net_device *dev)
266 {
267 struct r8192_priv *priv = rtllib_priv(dev);
268 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
269 u8 tempval;
270 u8 ICVer8192, ICVer8256;
271 u16 i, usValue, IC_Version;
272 u16 EEPROMId;
273
274 EEPROMId = rtl92e_eeprom_read(dev, 0);
275 if (EEPROMId != RTL8190_EEPROM_ID) {
276 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
277 EEPROMId);
278 priv->autoload_fail_flag = true;
279 } else {
280 priv->autoload_fail_flag = false;
281 }
282
283 if (!priv->autoload_fail_flag) {
284 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
285 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
286
287 usValue = rtl92e_eeprom_read(dev,
288 (EEPROM_Customer_ID >> 1)) >> 8;
289 priv->eeprom_customer_id = usValue & 0xff;
290 usValue = rtl92e_eeprom_read(dev,
291 EEPROM_ICVersion_ChannelPlan >> 1);
292 priv->eeprom_chnl_plan = usValue & 0xff;
293 IC_Version = (usValue & 0xff00) >> 8;
294
295 ICVer8192 = IC_Version & 0xf;
296 ICVer8256 = (IC_Version & 0xf0) >> 4;
297 if (ICVer8192 == 0x2) {
298 if (ICVer8256 == 0x5)
299 priv->card_8192_version = VERSION_8190_BE;
300 }
301 switch (priv->card_8192_version) {
302 case VERSION_8190_BD:
303 case VERSION_8190_BE:
304 break;
305 default:
306 priv->card_8192_version = VERSION_8190_BD;
307 break;
308 }
309 } else {
310 priv->card_8192_version = VERSION_8190_BD;
311 priv->eeprom_vid = 0;
312 priv->eeprom_did = 0;
313 priv->eeprom_customer_id = 0;
314 priv->eeprom_chnl_plan = 0;
315 }
316
317 if (!priv->autoload_fail_flag) {
318 u8 addr[ETH_ALEN];
319
320 for (i = 0; i < 6; i += 2) {
321 usValue = rtl92e_eeprom_read(dev,
322 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1);
323 *(u16 *)(&addr[i]) = usValue;
324 }
325 eth_hw_addr_set(dev, addr);
326 } else {
327 eth_hw_addr_set(dev, bMac_Tmp_Addr);
328 }
329
330 if (priv->card_8192_version > VERSION_8190_BD)
331 priv->tx_pwr_data_read_from_eeprom = true;
332 else
333 priv->tx_pwr_data_read_from_eeprom = false;
334
335 if (priv->card_8192_version > VERSION_8190_BD) {
336 if (!priv->autoload_fail_flag) {
337 tempval = (rtl92e_eeprom_read(dev,
338 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
339 priv->eeprom_legacy_ht_tx_pwr_diff = tempval & 0xf;
340 } else {
341 priv->eeprom_legacy_ht_tx_pwr_diff = 0x04;
342 }
343
344 if (!priv->autoload_fail_flag)
345 priv->eeprom_thermal_meter = ((rtl92e_eeprom_read(dev,
346 (EEPROM_ThermalMeter >> 1))) &
347 0xff00) >> 8;
348 else
349 priv->eeprom_thermal_meter = EEPROM_Default_ThermalMeter;
350 priv->tssi_13dBm = priv->eeprom_thermal_meter * 100;
351
352 if (priv->epromtype == EEPROM_93C46) {
353 if (!priv->autoload_fail_flag) {
354 usValue = rtl92e_eeprom_read(dev,
355 EEPROM_TxPwDiff_CrystalCap >> 1);
356 priv->eeprom_ant_pwr_diff = usValue & 0x0fff;
357 priv->eeprom_crystal_cap = (usValue & 0xf000)
358 >> 12;
359 } else {
360 priv->eeprom_ant_pwr_diff =
361 EEPROM_Default_AntTxPowerDiff;
362 priv->eeprom_crystal_cap =
363 EEPROM_Default_TxPwDiff_CrystalCap;
364 }
365
366 for (i = 0; i < 14; i += 2) {
367 if (!priv->autoload_fail_flag)
368 usValue = rtl92e_eeprom_read(dev,
369 (EEPROM_TxPwIndex_CCK + i) >> 1);
370 else
371 usValue = EEPROM_Default_TxPower;
372 *((u16 *)(&priv->eeprom_tx_pwr_level_cck[i])) =
373 usValue;
374 }
375 for (i = 0; i < 14; i += 2) {
376 if (!priv->autoload_fail_flag)
377 usValue = rtl92e_eeprom_read(dev,
378 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1);
379 else
380 usValue = EEPROM_Default_TxPower;
381 *((u16 *)(&priv->eeprom_tx_pwr_level_ofdm24g[i]))
382 = usValue;
383 }
384 }
385 if (priv->epromtype == EEPROM_93C46) {
386 for (i = 0; i < 14; i++) {
387 priv->tx_pwr_level_cck[i] =
388 priv->eeprom_tx_pwr_level_cck[i];
389 priv->tx_pwr_level_ofdm_24g[i] =
390 priv->eeprom_tx_pwr_level_ofdm24g[i];
391 }
392 priv->legacy_ht_tx_pwr_diff =
393 priv->eeprom_legacy_ht_tx_pwr_diff;
394 priv->antenna_tx_pwr_diff[0] = priv->eeprom_ant_pwr_diff & 0xf;
395 priv->antenna_tx_pwr_diff[1] = (priv->eeprom_ant_pwr_diff &
396 0xf0) >> 4;
397 priv->antenna_tx_pwr_diff[2] = (priv->eeprom_ant_pwr_diff &
398 0xf00) >> 8;
399 priv->crystal_cap = priv->eeprom_crystal_cap;
400 priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf;
401 priv->thermal_meter[1] = (priv->eeprom_thermal_meter &
402 0xf0) >> 4;
403 } else if (priv->epromtype == EEPROM_93C56) {
404 priv->legacy_ht_tx_pwr_diff =
405 priv->eeprom_legacy_ht_tx_pwr_diff;
406 priv->antenna_tx_pwr_diff[0] = 0;
407 priv->antenna_tx_pwr_diff[1] = 0;
408 priv->antenna_tx_pwr_diff[2] = 0;
409 priv->crystal_cap = priv->eeprom_crystal_cap;
410 priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf;
411 priv->thermal_meter[1] = (priv->eeprom_thermal_meter &
412 0xf0) >> 4;
413 }
414 }
415
416 rtl92e_init_adaptive_rate(dev);
417
418 priv->chnl_plan = priv->eeprom_chnl_plan;
419
420 switch (priv->eeprom_customer_id) {
421 case EEPROM_CID_NetCore:
422 priv->customer_id = RT_CID_819X_NETCORE;
423 break;
424 case EEPROM_CID_TOSHIBA:
425 priv->customer_id = RT_CID_TOSHIBA;
426 if (priv->eeprom_chnl_plan & 0x80)
427 priv->chnl_plan = priv->eeprom_chnl_plan & 0x7f;
428 else
429 priv->chnl_plan = 0x0;
430 break;
431 }
432
433 if (priv->chnl_plan > CHANNEL_PLAN_LEN - 1)
434 priv->chnl_plan = 0;
435 priv->chnl_plan = COUNTRY_CODE_WORLD_WIDE_13;
436
437 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
438 priv->rtllib->bSupportRemoteWakeUp = true;
439 else
440 priv->rtllib->bSupportRemoteWakeUp = false;
441 }
442
rtl92e_get_eeprom_size(struct net_device * dev)443 void rtl92e_get_eeprom_size(struct net_device *dev)
444 {
445 u16 curCR;
446 struct r8192_priv *priv = rtllib_priv(dev);
447
448 curCR = rtl92e_readw(dev, EPROM_CMD);
449 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
450 EEPROM_93C46;
451 _rtl92e_read_eeprom_info(dev);
452 }
453
_rtl92e_hwconfig(struct net_device * dev)454 static void _rtl92e_hwconfig(struct net_device *dev)
455 {
456 u32 regRATR = 0, regRRSR = 0;
457 u8 regBwOpMode = 0, regTmp = 0;
458 struct r8192_priv *priv = rtllib_priv(dev);
459
460 switch (priv->rtllib->mode) {
461 case WIRELESS_MODE_B:
462 regBwOpMode = BW_OPMODE_20MHZ;
463 regRATR = RATE_ALL_CCK;
464 regRRSR = RATE_ALL_CCK;
465 break;
466 case WIRELESS_MODE_AUTO:
467 case WIRELESS_MODE_N_24G:
468 regBwOpMode = BW_OPMODE_20MHZ;
469 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
470 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
471 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
472 break;
473 case WIRELESS_MODE_G:
474 default:
475 regBwOpMode = BW_OPMODE_20MHZ;
476 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
477 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
478 break;
479 }
480
481 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
482 {
483 u32 ratr_value;
484
485 ratr_value = regRATR;
486 ratr_value &= ~(RATE_ALL_OFDM_2SS);
487 rtl92e_writel(dev, RATR0, ratr_value);
488 rtl92e_writeb(dev, UFWP, 1);
489 }
490 regTmp = rtl92e_readb(dev, 0x313);
491 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
492 rtl92e_writel(dev, RRSR, regRRSR);
493
494 rtl92e_writew(dev, RETRY_LIMIT,
495 priv->short_retry_limit << RETRY_LIMIT_SHORT_SHIFT |
496 priv->long_retry_limit << RETRY_LIMIT_LONG_SHIFT);
497 }
498
rtl92e_start_adapter(struct net_device * dev)499 bool rtl92e_start_adapter(struct net_device *dev)
500 {
501 struct r8192_priv *priv = rtllib_priv(dev);
502 u32 ulRegRead;
503 bool rtStatus = true;
504 u8 tmpvalue;
505 u8 ICVersion, SwitchingRegulatorOutput;
506 bool bfirmwareok = true;
507 u32 tmpRegA, TempCCk;
508 int i = 0;
509 u32 retry_times = 0;
510
511 priv->being_init_adapter = true;
512
513 start:
514 rtl92e_reset_desc_ring(dev);
515 priv->rf_mode = RF_OP_By_SW_3wire;
516 if (priv->rst_progress == RESET_TYPE_NORESET) {
517 rtl92e_writeb(dev, ANAPAR, 0x37);
518 mdelay(500);
519 }
520 priv->fw_info->status = FW_STATUS_0_INIT;
521
522 ulRegRead = rtl92e_readl(dev, CPU_GEN);
523 if (priv->fw_info->status == FW_STATUS_0_INIT)
524 ulRegRead |= CPU_GEN_SYSTEM_RESET;
525 else if (priv->fw_info->status == FW_STATUS_5_READY)
526 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
527 else
528 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
529 __func__, priv->fw_info->status);
530
531 rtl92e_writel(dev, CPU_GEN, ulRegRead);
532
533 ICVersion = rtl92e_readb(dev, IC_VERRSION);
534 if (ICVersion >= 0x4) {
535 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
536 if (SwitchingRegulatorOutput != 0xb8) {
537 rtl92e_writeb(dev, SWREGULATOR, 0xa8);
538 mdelay(1);
539 rtl92e_writeb(dev, SWREGULATOR, 0xb8);
540 }
541 }
542 rtStatus = rtl92e_config_bb(dev);
543 if (!rtStatus) {
544 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
545 return rtStatus;
546 }
547
548 priv->loopback_mode = RTL819X_NO_LOOPBACK;
549 if (priv->rst_progress == RESET_TYPE_NORESET) {
550 ulRegRead = rtl92e_readl(dev, CPU_GEN);
551 if (priv->loopback_mode == RTL819X_NO_LOOPBACK)
552 ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
553 CPU_GEN_NO_LOOPBACK_SET;
554 else if (priv->loopback_mode == RTL819X_MAC_LOOPBACK)
555 ulRegRead |= CPU_CCK_LOOPBACK;
556 else
557 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
558 __func__);
559
560 rtl92e_writel(dev, CPU_GEN, ulRegRead);
561
562 udelay(500);
563 }
564 _rtl92e_hwconfig(dev);
565 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
566
567 rtl92e_writeb(dev, PCIF, ((MXDMA2_NO_LIMIT << MXDMA2_RX_SHIFT) |
568 (MXDMA2_NO_LIMIT << MXDMA2_TX_SHIFT)));
569 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
570 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
571 rtl92e_writel(dev, RCR, priv->receive_config);
572
573 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
574 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
575 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
576 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
577 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
578 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
579 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
580 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
581 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
582 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
583 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
584 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
585 RSVD_FW_QUEUE_PAGE_BCN_SHIFT |
586 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
587 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
588
589 rtl92e_tx_enable(dev);
590 rtl92e_rx_enable(dev);
591 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) |
592 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
593 rtl92e_writel(dev, RRSR, ulRegRead);
594 rtl92e_writel(dev, RATR0 + 4 * 7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
595
596 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
597
598 if (priv->rst_progress == RESET_TYPE_NORESET)
599 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
600 rtl92e_cam_reset(dev);
601 {
602 u8 SECR_value = 0x0;
603
604 SECR_value |= SCR_TxEncEnable;
605 SECR_value |= SCR_RxDecEnable;
606 SECR_value |= SCR_NoSKMC;
607 rtl92e_writeb(dev, SECR, SECR_value);
608 }
609 rtl92e_writew(dev, ATIMWND, 2);
610 rtl92e_writew(dev, BCN_INTERVAL, 100);
611
612 for (i = 0; i < QOS_QUEUE_NUM; i++)
613 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
614
615 rtl92e_writeb(dev, 0xbe, 0xc0);
616
617 rtl92e_config_mac(dev);
618
619 if (priv->card_8192_version > VERSION_8190_BD) {
620 rtl92e_get_tx_power(dev);
621 rtl92e_set_tx_power(dev, priv->chan);
622 }
623
624 tmpvalue = rtl92e_readb(dev, IC_VERRSION);
625 priv->ic_cut = tmpvalue;
626
627 bfirmwareok = rtl92e_init_fw(dev);
628 if (!bfirmwareok) {
629 if (retry_times < 10) {
630 retry_times++;
631 goto start;
632 } else {
633 rtStatus = false;
634 goto end;
635 }
636 }
637
638 if (priv->rst_progress == RESET_TYPE_NORESET) {
639 rtStatus = rtl92e_config_rf(dev);
640 if (!rtStatus) {
641 netdev_info(dev, "RF Config failed\n");
642 return rtStatus;
643 }
644 }
645
646 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
647 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
648
649 rtl92e_writeb(dev, 0x87, 0x0);
650
651 if (priv->rtllib->rf_off_reason > RF_CHANGE_BY_PS) {
652 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
653 } else if (priv->rtllib->rf_off_reason >= RF_CHANGE_BY_IPS) {
654 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
655 } else {
656 priv->rtllib->rf_power_state = rf_on;
657 priv->rtllib->rf_off_reason = 0;
658 }
659
660 if (priv->rtllib->FwRWRF)
661 priv->rf_mode = RF_OP_By_FW;
662 else
663 priv->rf_mode = RF_OP_By_SW_3wire;
664
665 if (priv->rst_progress == RESET_TYPE_NORESET) {
666 rtl92e_dm_init_txpower_tracking(dev);
667
668 if (priv->ic_cut >= IC_VersionCut_D) {
669 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
670 bMaskDWord);
671 rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord);
672
673 for (i = 0; i < TX_BB_GAIN_TABLE_LEN; i++) {
674 if (tmpRegA == dm_tx_bb_gain[i]) {
675 priv->rfa_txpowertrackingindex = i;
676 priv->rfa_txpowertrackingindex_real = i;
677 priv->rfa_txpowertracking_default =
678 priv->rfa_txpowertrackingindex;
679 break;
680 }
681 }
682
683 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
684 bMaskByte2);
685
686 for (i = 0; i < CCK_TX_BB_GAIN_TABLE_LEN; i++) {
687 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
688 priv->cck_present_attn_20m_def = i;
689 break;
690 }
691 }
692 priv->cck_present_attn_40m_def = 0;
693 priv->cck_present_attn_diff = 0;
694 priv->cck_present_attn =
695 priv->cck_present_attn_20m_def;
696 priv->btxpower_tracking = false;
697 }
698 }
699 rtl92e_irq_enable(dev);
700 end:
701 priv->being_init_adapter = false;
702 return rtStatus;
703 }
704
_rtl92e_net_update(struct net_device * dev)705 static void _rtl92e_net_update(struct net_device *dev)
706 {
707 struct r8192_priv *priv = rtllib_priv(dev);
708 struct rtllib_network *net;
709 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
710 u16 rate_config = 0;
711
712 net = &priv->rtllib->current_network;
713 rtl92e_config_rate(dev, &rate_config);
714 priv->dot11_current_preamble_mode = PREAMBLE_AUTO;
715 priv->basic_rate = rate_config &= 0x15f;
716 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid);
717 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2));
718
719 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
720 rtl92e_writew(dev, ATIMWND, 2);
721 rtl92e_writew(dev, BCN_DMATIME, 256);
722 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
723 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
724 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
725
726 BcnTimeCfg |= (BcnCW << BCN_TCFG_CW_SHIFT);
727 BcnTimeCfg |= BcnIFS << BCN_TCFG_IFS;
728
729 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
730 }
731 }
732
rtl92e_link_change(struct net_device * dev)733 void rtl92e_link_change(struct net_device *dev)
734 {
735 struct r8192_priv *priv = rtllib_priv(dev);
736 struct rtllib_device *ieee = priv->rtllib;
737
738 if (!priv->up)
739 return;
740
741 if (ieee->link_state == MAC80211_LINKED) {
742 _rtl92e_net_update(dev);
743 rtl92e_update_ratr_table(dev);
744 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
745 (ieee->pairwise_key_type == KEY_TYPE_WEP104))
746 rtl92e_enable_hw_security_config(dev);
747 } else {
748 rtl92e_writeb(dev, 0x173, 0);
749 }
750 _rtl92e_update_msr(dev);
751
752 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
753 u32 reg;
754
755 reg = rtl92e_readl(dev, RCR);
756 if (priv->rtllib->link_state == MAC80211_LINKED) {
757 if (ieee->intel_promiscuous_md_info.promiscuous_on)
758 ;
759 else
760 priv->receive_config = reg |= RCR_CBSSID;
761 } else {
762 priv->receive_config = reg &= ~RCR_CBSSID;
763 }
764
765 rtl92e_writel(dev, RCR, reg);
766 }
767 }
768
rtl92e_set_monitor_mode(struct net_device * dev,bool bAllowAllDA,bool WriteIntoReg)769 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
770 bool WriteIntoReg)
771 {
772 struct r8192_priv *priv = rtllib_priv(dev);
773
774 if (bAllowAllDA)
775 priv->receive_config |= RCR_AAP;
776 else
777 priv->receive_config &= ~RCR_AAP;
778
779 if (WriteIntoReg)
780 rtl92e_writel(dev, RCR, priv->receive_config);
781 }
782
_rtl92e_rate_mgn_to_hw(u8 rate)783 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
784 {
785 u8 ret = DESC90_RATE1M;
786
787 switch (rate) {
788 case MGN_1M:
789 ret = DESC90_RATE1M;
790 break;
791 case MGN_2M:
792 ret = DESC90_RATE2M;
793 break;
794 case MGN_5_5M:
795 ret = DESC90_RATE5_5M;
796 break;
797 case MGN_11M:
798 ret = DESC90_RATE11M;
799 break;
800 case MGN_6M:
801 ret = DESC90_RATE6M;
802 break;
803 case MGN_9M:
804 ret = DESC90_RATE9M;
805 break;
806 case MGN_12M:
807 ret = DESC90_RATE12M;
808 break;
809 case MGN_18M:
810 ret = DESC90_RATE18M;
811 break;
812 case MGN_24M:
813 ret = DESC90_RATE24M;
814 break;
815 case MGN_36M:
816 ret = DESC90_RATE36M;
817 break;
818 case MGN_48M:
819 ret = DESC90_RATE48M;
820 break;
821 case MGN_54M:
822 ret = DESC90_RATE54M;
823 break;
824 case MGN_MCS0:
825 ret = DESC90_RATEMCS0;
826 break;
827 case MGN_MCS1:
828 ret = DESC90_RATEMCS1;
829 break;
830 case MGN_MCS2:
831 ret = DESC90_RATEMCS2;
832 break;
833 case MGN_MCS3:
834 ret = DESC90_RATEMCS3;
835 break;
836 case MGN_MCS4:
837 ret = DESC90_RATEMCS4;
838 break;
839 case MGN_MCS5:
840 ret = DESC90_RATEMCS5;
841 break;
842 case MGN_MCS6:
843 ret = DESC90_RATEMCS6;
844 break;
845 case MGN_MCS7:
846 ret = DESC90_RATEMCS7;
847 break;
848 case MGN_MCS8:
849 ret = DESC90_RATEMCS8;
850 break;
851 case MGN_MCS9:
852 ret = DESC90_RATEMCS9;
853 break;
854 case MGN_MCS10:
855 ret = DESC90_RATEMCS10;
856 break;
857 case MGN_MCS11:
858 ret = DESC90_RATEMCS11;
859 break;
860 case MGN_MCS12:
861 ret = DESC90_RATEMCS12;
862 break;
863 case MGN_MCS13:
864 ret = DESC90_RATEMCS13;
865 break;
866 case MGN_MCS14:
867 ret = DESC90_RATEMCS14;
868 break;
869 case MGN_MCS15:
870 ret = DESC90_RATEMCS15;
871 break;
872 case (0x80 | 0x20):
873 ret = DESC90_RATEMCS32;
874 break;
875 default:
876 break;
877 }
878 return ret;
879 }
880
_rtl92e_hw_queue_to_fw_queue(struct net_device * dev,u8 QueueID,u8 priority)881 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
882 u8 priority)
883 {
884 u8 QueueSelect = 0x0;
885
886 switch (QueueID) {
887 case BE_QUEUE:
888 QueueSelect = QSLT_BE;
889 break;
890
891 case BK_QUEUE:
892 QueueSelect = QSLT_BK;
893 break;
894
895 case VO_QUEUE:
896 QueueSelect = QSLT_VO;
897 break;
898
899 case VI_QUEUE:
900 QueueSelect = QSLT_VI;
901 break;
902 case MGNT_QUEUE:
903 QueueSelect = QSLT_MGNT;
904 break;
905 case BEACON_QUEUE:
906 QueueSelect = QSLT_BEACON;
907 break;
908 case TXCMD_QUEUE:
909 QueueSelect = QSLT_CMD;
910 break;
911 case HIGH_QUEUE:
912 QueueSelect = QSLT_HIGH;
913 break;
914 default:
915 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
916 __func__, QueueID);
917 break;
918 }
919 return QueueSelect;
920 }
921
_rtl92e_query_is_short(u8 TxHT,u8 TxRate,struct cb_desc * tcb_desc)922 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
923 {
924 u8 tmp_Short;
925
926 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
927 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
928 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
929 tmp_Short = 0;
930
931 return tmp_Short;
932 }
933
rtl92e_fill_tx_desc(struct net_device * dev,struct tx_desc * pdesc,struct cb_desc * cb_desc,struct sk_buff * skb)934 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
935 struct cb_desc *cb_desc, struct sk_buff *skb)
936 {
937 struct r8192_priv *priv = rtllib_priv(dev);
938 dma_addr_t mapping;
939 struct tx_fwinfo_8190pci *pTxFwInfo;
940
941 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
942 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
943 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
944 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw(cb_desc->data_rate);
945 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
946 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
947 pTxFwInfo->TxRate, cb_desc);
948
949 if (cb_desc->bAMPDUEnable) {
950 pTxFwInfo->AllowAggregation = 1;
951 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
952 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
953 } else {
954 pTxFwInfo->AllowAggregation = 0;
955 pTxFwInfo->RxMF = 0;
956 pTxFwInfo->RxAMD = 0;
957 }
958
959 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
960 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
961 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
962 pTxFwInfo->RtsHT = (cb_desc->rts_rate & 0x80) ? 1 : 0;
963 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw(cb_desc->rts_rate);
964 pTxFwInfo->RtsBandwidth = 0;
965 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
966 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
967 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
968 (cb_desc->bRTSUseShortGI ? 1 : 0);
969 if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20_40) {
970 if (cb_desc->bPacketBW) {
971 pTxFwInfo->TxBandwidth = 1;
972 pTxFwInfo->TxSubCarrier = 0;
973 } else {
974 pTxFwInfo->TxBandwidth = 0;
975 pTxFwInfo->TxSubCarrier = priv->n_cur_40mhz_prime_sc;
976 }
977 } else {
978 pTxFwInfo->TxBandwidth = 0;
979 pTxFwInfo->TxSubCarrier = 0;
980 }
981
982 memset((u8 *)pdesc, 0, 12);
983
984 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
985 DMA_TO_DEVICE);
986 if (dma_mapping_error(&priv->pdev->dev, mapping)) {
987 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
988 return;
989 }
990
991 pdesc->LINIP = 0;
992 pdesc->CmdInit = 1;
993 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
994 pdesc->PktSize = skb->len - sizeof(struct tx_fwinfo_8190pci);
995
996 pdesc->SecCAMID = 0;
997 pdesc->RATid = cb_desc->ratr_index;
998
999 pdesc->NoEnc = 1;
1000 pdesc->SecType = 0x0;
1001 if (cb_desc->bHwSec) {
1002 static u8 tmp;
1003
1004 if (!tmp)
1005 tmp = 1;
1006 switch (priv->rtllib->pairwise_key_type) {
1007 case KEY_TYPE_WEP40:
1008 case KEY_TYPE_WEP104:
1009 pdesc->SecType = 0x1;
1010 pdesc->NoEnc = 0;
1011 break;
1012 case KEY_TYPE_TKIP:
1013 pdesc->SecType = 0x2;
1014 pdesc->NoEnc = 0;
1015 break;
1016 case KEY_TYPE_CCMP:
1017 pdesc->SecType = 0x3;
1018 pdesc->NoEnc = 0;
1019 break;
1020 case KEY_TYPE_NA:
1021 pdesc->SecType = 0x0;
1022 pdesc->NoEnc = 1;
1023 break;
1024 }
1025 }
1026
1027 pdesc->PktId = 0x0;
1028
1029 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1030 cb_desc->queue_index,
1031 cb_desc->priority);
1032 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1033
1034 pdesc->DISFB = cb_desc->tx_dis_rate_fallback;
1035 pdesc->USERATE = cb_desc->tx_use_drv_assinged_rate;
1036
1037 pdesc->FirstSeg = 1;
1038 pdesc->LastSeg = 1;
1039 pdesc->TxBufferSize = skb->len;
1040
1041 pdesc->TxBuffAddr = mapping;
1042 }
1043
rtl92e_fill_tx_cmd_desc(struct net_device * dev,struct tx_desc_cmd * entry,struct cb_desc * cb_desc,struct sk_buff * skb)1044 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1045 struct cb_desc *cb_desc, struct sk_buff *skb)
1046 {
1047 struct r8192_priv *priv = rtllib_priv(dev);
1048 dma_addr_t mapping = dma_map_single(&priv->pdev->dev, skb->data,
1049 skb->len, DMA_TO_DEVICE);
1050
1051 if (dma_mapping_error(&priv->pdev->dev, mapping))
1052 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1053 memset(entry, 0, 12);
1054 entry->LINIP = cb_desc->bLastIniPkt;
1055 entry->FirstSeg = 1;
1056 entry->LastSeg = 1;
1057 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1058 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1059 } else {
1060 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1061
1062 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1063 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1064 entry_tmp->PktSize = cb_desc->pkt_size + entry_tmp->Offset;
1065 entry_tmp->QueueSelect = QSLT_CMD;
1066 entry_tmp->TxFWInfoSize = 0x08;
1067 entry_tmp->RATid = DESC_PACKET_TYPE_INIT;
1068 }
1069 entry->TxBufferSize = skb->len;
1070 entry->TxBuffAddr = mapping;
1071 entry->OWN = 1;
1072 }
1073
_rtl92e_rate_hw_to_mgn(bool bIsHT,u8 rate)1074 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1075 {
1076 u8 ret_rate = 0x02;
1077
1078 if (!bIsHT) {
1079 switch (rate) {
1080 case DESC90_RATE1M:
1081 ret_rate = MGN_1M;
1082 break;
1083 case DESC90_RATE2M:
1084 ret_rate = MGN_2M;
1085 break;
1086 case DESC90_RATE5_5M:
1087 ret_rate = MGN_5_5M;
1088 break;
1089 case DESC90_RATE11M:
1090 ret_rate = MGN_11M;
1091 break;
1092 case DESC90_RATE6M:
1093 ret_rate = MGN_6M;
1094 break;
1095 case DESC90_RATE9M:
1096 ret_rate = MGN_9M;
1097 break;
1098 case DESC90_RATE12M:
1099 ret_rate = MGN_12M;
1100 break;
1101 case DESC90_RATE18M:
1102 ret_rate = MGN_18M;
1103 break;
1104 case DESC90_RATE24M:
1105 ret_rate = MGN_24M;
1106 break;
1107 case DESC90_RATE36M:
1108 ret_rate = MGN_36M;
1109 break;
1110 case DESC90_RATE48M:
1111 ret_rate = MGN_48M;
1112 break;
1113 case DESC90_RATE54M:
1114 ret_rate = MGN_54M;
1115 break;
1116 }
1117
1118 } else {
1119 switch (rate) {
1120 case DESC90_RATEMCS0:
1121 ret_rate = MGN_MCS0;
1122 break;
1123 case DESC90_RATEMCS1:
1124 ret_rate = MGN_MCS1;
1125 break;
1126 case DESC90_RATEMCS2:
1127 ret_rate = MGN_MCS2;
1128 break;
1129 case DESC90_RATEMCS3:
1130 ret_rate = MGN_MCS3;
1131 break;
1132 case DESC90_RATEMCS4:
1133 ret_rate = MGN_MCS4;
1134 break;
1135 case DESC90_RATEMCS5:
1136 ret_rate = MGN_MCS5;
1137 break;
1138 case DESC90_RATEMCS6:
1139 ret_rate = MGN_MCS6;
1140 break;
1141 case DESC90_RATEMCS7:
1142 ret_rate = MGN_MCS7;
1143 break;
1144 case DESC90_RATEMCS8:
1145 ret_rate = MGN_MCS8;
1146 break;
1147 case DESC90_RATEMCS9:
1148 ret_rate = MGN_MCS9;
1149 break;
1150 case DESC90_RATEMCS10:
1151 ret_rate = MGN_MCS10;
1152 break;
1153 case DESC90_RATEMCS11:
1154 ret_rate = MGN_MCS11;
1155 break;
1156 case DESC90_RATEMCS12:
1157 ret_rate = MGN_MCS12;
1158 break;
1159 case DESC90_RATEMCS13:
1160 ret_rate = MGN_MCS13;
1161 break;
1162 case DESC90_RATEMCS14:
1163 ret_rate = MGN_MCS14;
1164 break;
1165 case DESC90_RATEMCS15:
1166 ret_rate = MGN_MCS15;
1167 break;
1168 case DESC90_RATEMCS32:
1169 ret_rate = 0x80 | 0x20;
1170 break;
1171 }
1172 }
1173
1174 return ret_rate;
1175 }
1176
_rtl92e_signal_scale_mapping(struct r8192_priv * priv,long currsig)1177 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1178 {
1179 long retsig;
1180
1181 if (currsig >= 61 && currsig <= 100)
1182 retsig = 90 + ((currsig - 60) / 4);
1183 else if (currsig >= 41 && currsig <= 60)
1184 retsig = 78 + ((currsig - 40) / 2);
1185 else if (currsig >= 31 && currsig <= 40)
1186 retsig = 66 + (currsig - 30);
1187 else if (currsig >= 21 && currsig <= 30)
1188 retsig = 54 + (currsig - 20);
1189 else if (currsig >= 5 && currsig <= 20)
1190 retsig = 42 + (((currsig - 5) * 2) / 3);
1191 else if (currsig == 4)
1192 retsig = 36;
1193 else if (currsig == 3)
1194 retsig = 27;
1195 else if (currsig == 2)
1196 retsig = 18;
1197 else if (currsig == 1)
1198 retsig = 9;
1199 else
1200 retsig = currsig;
1201
1202 return retsig;
1203 }
1204
1205 #define rx_hal_is_cck_rate(_pdrvinfo)\
1206 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1207 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1208 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1209 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1210 !_pdrvinfo->RxHT)
1211
_rtl92e_query_rxphystatus(struct r8192_priv * priv,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo,struct rtllib_rx_stats * precord_stats,bool bpacket_match_bssid,bool bpacket_toself,bool bPacketBeacon,bool bToSelfBA)1212 static void _rtl92e_query_rxphystatus(
1213 struct r8192_priv *priv,
1214 struct rtllib_rx_stats *pstats,
1215 struct rx_desc *pdesc,
1216 struct rx_fwinfo *pdrvinfo,
1217 struct rtllib_rx_stats *precord_stats,
1218 bool bpacket_match_bssid,
1219 bool bpacket_toself,
1220 bool bPacketBeacon,
1221 bool bToSelfBA
1222 )
1223 {
1224 struct phy_sts_ofdm_819xpci *pofdm_buf;
1225 struct phy_sts_cck_819xpci *pcck_buf;
1226 u8 *prxpkt;
1227 u8 i, max_spatial_stream, tmp_rxevm;
1228 s8 rx_pwr[4], rx_pwr_all = 0;
1229 s8 rx_evmX;
1230 u8 evm, pwdb_all;
1231 u32 RSSI, total_rssi = 0;
1232 u8 is_cck_rate = 0;
1233 u8 rf_rx_num = 0;
1234 static u8 check_reg824;
1235 static u32 reg824_bit9;
1236
1237 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1238 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1239 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1240 bpacket_match_bssid;
1241 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1242 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1243 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1244 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1245 if (check_reg824 == 0) {
1246 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1247 rFPGA0_XA_HSSIParameter2,
1248 0x200);
1249 check_reg824 = 1;
1250 }
1251
1252 prxpkt = (u8 *)pdrvinfo;
1253
1254 prxpkt += sizeof(struct rx_fwinfo);
1255
1256 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1257 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1258
1259 pstats->RxMIMOSignalQuality[0] = -1;
1260 pstats->RxMIMOSignalQuality[1] = -1;
1261 precord_stats->RxMIMOSignalQuality[0] = -1;
1262 precord_stats->RxMIMOSignalQuality[1] = -1;
1263
1264 if (is_cck_rate) {
1265 u8 report;
1266
1267 if (!reg824_bit9) {
1268 report = pcck_buf->cck_agc_rpt & 0xc0;
1269 report >>= 6;
1270 switch (report) {
1271 case 0x3:
1272 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1273 0x3e);
1274 break;
1275 case 0x2:
1276 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1277 0x3e);
1278 break;
1279 case 0x1:
1280 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1281 0x3e);
1282 break;
1283 case 0x0:
1284 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1285 break;
1286 }
1287 } else {
1288 report = pcck_buf->cck_agc_rpt & 0x60;
1289 report >>= 5;
1290 switch (report) {
1291 case 0x3:
1292 rx_pwr_all = -35 -
1293 ((pcck_buf->cck_agc_rpt &
1294 0x1f) << 1);
1295 break;
1296 case 0x2:
1297 rx_pwr_all = -23 -
1298 ((pcck_buf->cck_agc_rpt &
1299 0x1f) << 1);
1300 break;
1301 case 0x1:
1302 rx_pwr_all = -11 -
1303 ((pcck_buf->cck_agc_rpt &
1304 0x1f) << 1);
1305 break;
1306 case 0x0:
1307 rx_pwr_all = -8 -
1308 ((pcck_buf->cck_agc_rpt &
1309 0x1f) << 1);
1310 break;
1311 }
1312 }
1313
1314 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1315 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1316 pstats->RecvSignalPower = rx_pwr_all;
1317
1318 if (bpacket_match_bssid) {
1319 u8 sq;
1320
1321 if (pstats->RxPWDBAll > 40) {
1322 sq = 100;
1323 } else {
1324 sq = pcck_buf->sq_rpt;
1325
1326 if (pcck_buf->sq_rpt > 64)
1327 sq = 0;
1328 else if (pcck_buf->sq_rpt < 20)
1329 sq = 100;
1330 else
1331 sq = ((64 - sq) * 100) / 44;
1332 }
1333 pstats->SignalQuality = sq;
1334 precord_stats->SignalQuality = sq;
1335 pstats->RxMIMOSignalQuality[0] = sq;
1336 precord_stats->RxMIMOSignalQuality[0] = sq;
1337 pstats->RxMIMOSignalQuality[1] = -1;
1338 precord_stats->RxMIMOSignalQuality[1] = -1;
1339 }
1340 } else {
1341 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1342 if (priv->brfpath_rxenable[i])
1343 rf_rx_num++;
1344
1345 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1346 2) - 110;
1347
1348 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1349 if (priv->brfpath_rxenable[i])
1350 total_rssi += RSSI;
1351
1352 if (bpacket_match_bssid) {
1353 pstats->RxMIMOSignalStrength[i] = RSSI;
1354 precord_stats->RxMIMOSignalStrength[i] = RSSI;
1355 }
1356 }
1357
1358 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1359 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1360
1361 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1362 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1363 pstats->RecvSignalPower = rx_pwr_all;
1364 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1365 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1366 max_spatial_stream = 2;
1367 else
1368 max_spatial_stream = 1;
1369
1370 for (i = 0; i < max_spatial_stream; i++) {
1371 tmp_rxevm = pofdm_buf->rxevm_X[i];
1372 rx_evmX = (s8)(tmp_rxevm);
1373
1374 rx_evmX /= 2;
1375
1376 evm = rtl92e_evm_db_to_percent(rx_evmX);
1377 if (bpacket_match_bssid) {
1378 if (i == 0) {
1379 pstats->SignalQuality = evm & 0xff;
1380 precord_stats->SignalQuality = evm & 0xff;
1381 }
1382 pstats->RxMIMOSignalQuality[i] = evm & 0xff;
1383 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff;
1384 }
1385 }
1386 }
1387
1388 if (is_cck_rate) {
1389 pstats->SignalStrength = precord_stats->SignalStrength =
1390 _rtl92e_signal_scale_mapping(priv,
1391 (long)pwdb_all);
1392
1393 } else {
1394 if (rf_rx_num != 0)
1395 pstats->SignalStrength = precord_stats->SignalStrength =
1396 _rtl92e_signal_scale_mapping(priv,
1397 (long)(total_rssi /= rf_rx_num));
1398 }
1399 }
1400
_rtl92e_process_phyinfo(struct r8192_priv * priv,u8 * buffer,struct rtllib_rx_stats * prev_st,struct rtllib_rx_stats * curr_st)1401 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1402 struct rtllib_rx_stats *prev_st,
1403 struct rtllib_rx_stats *curr_st)
1404 {
1405 bool bcheck = false;
1406 u8 rfpath;
1407 u32 ij, tmp_val;
1408 static u32 slide_rssi_index, slide_rssi_statistics;
1409 static u32 slide_evm_index, slide_evm_statistics;
1410 static u32 last_rssi, last_evm;
1411 static u32 slide_beacon_adc_pwdb_index;
1412 static u32 slide_beacon_adc_pwdb_statistics;
1413 static u32 last_beacon_adc_pwdb;
1414 struct rtllib_hdr_3addr *hdr;
1415 u16 sc;
1416 unsigned int seq;
1417
1418 hdr = (struct rtllib_hdr_3addr *)buffer;
1419 sc = le16_to_cpu(hdr->seq_ctl);
1420 seq = WLAN_GET_SEQ_SEQ(sc);
1421 curr_st->Seq_Num = seq;
1422 if (!prev_st->bIsAMPDU)
1423 bcheck = true;
1424
1425 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1426 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1427 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1428 priv->stats.slide_rssi_total -= last_rssi;
1429 }
1430 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1431
1432 priv->stats.slide_signal_strength[slide_rssi_index++] =
1433 prev_st->SignalStrength;
1434 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1435 slide_rssi_index = 0;
1436
1437 tmp_val = priv->stats.slide_rssi_total / slide_rssi_statistics;
1438 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv, tmp_val);
1439 curr_st->rssi = priv->stats.signal_strength;
1440 if (!prev_st->bPacketMatchBSSID) {
1441 if (!prev_st->bToSelfBA)
1442 return;
1443 }
1444
1445 if (!bcheck)
1446 return;
1447
1448 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1449 for (rfpath = RF90_PATH_A; rfpath < priv->num_total_rf_path; rfpath++) {
1450 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1451 priv->stats.rx_rssi_percentage[rfpath] =
1452 prev_st->RxMIMOSignalStrength[rfpath];
1453 }
1454 if (prev_st->RxMIMOSignalStrength[rfpath] >
1455 priv->stats.rx_rssi_percentage[rfpath]) {
1456 priv->stats.rx_rssi_percentage[rfpath] =
1457 ((priv->stats.rx_rssi_percentage[rfpath]
1458 * (RX_SMOOTH - 1)) +
1459 (prev_st->RxMIMOSignalStrength
1460 [rfpath])) / (RX_SMOOTH);
1461 priv->stats.rx_rssi_percentage[rfpath] =
1462 priv->stats.rx_rssi_percentage[rfpath]
1463 + 1;
1464 } else {
1465 priv->stats.rx_rssi_percentage[rfpath] =
1466 ((priv->stats.rx_rssi_percentage[rfpath] *
1467 (RX_SMOOTH - 1)) +
1468 (prev_st->RxMIMOSignalStrength[rfpath])) /
1469 (RX_SMOOTH);
1470 }
1471 }
1472 }
1473
1474 if (prev_st->bPacketBeacon) {
1475 if (slide_beacon_adc_pwdb_statistics++ >=
1476 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1477 slide_beacon_adc_pwdb_statistics =
1478 PHY_Beacon_RSSI_SLID_WIN_MAX;
1479 last_beacon_adc_pwdb = priv->stats.slide_beacon_pwdb
1480 [slide_beacon_adc_pwdb_index];
1481 priv->stats.slide_beacon_total -= last_beacon_adc_pwdb;
1482 }
1483 priv->stats.slide_beacon_total += prev_st->RxPWDBAll;
1484 priv->stats.slide_beacon_pwdb[slide_beacon_adc_pwdb_index] =
1485 prev_st->RxPWDBAll;
1486 slide_beacon_adc_pwdb_index++;
1487 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1488 slide_beacon_adc_pwdb_index = 0;
1489 prev_st->RxPWDBAll = priv->stats.slide_beacon_total /
1490 slide_beacon_adc_pwdb_statistics;
1491 if (prev_st->RxPWDBAll >= 3)
1492 prev_st->RxPWDBAll -= 3;
1493 }
1494 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1495 prev_st->bToSelfBA) {
1496 if (priv->undecorated_smoothed_pwdb < 0)
1497 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1498 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1499 priv->undecorated_smoothed_pwdb =
1500 (((priv->undecorated_smoothed_pwdb) *
1501 (RX_SMOOTH - 1)) +
1502 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1503 priv->undecorated_smoothed_pwdb =
1504 priv->undecorated_smoothed_pwdb + 1;
1505 } else {
1506 priv->undecorated_smoothed_pwdb =
1507 (((priv->undecorated_smoothed_pwdb) *
1508 (RX_SMOOTH - 1)) +
1509 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1510 }
1511 rtl92e_update_rx_statistics(priv, prev_st);
1512 }
1513
1514 if (prev_st->SignalQuality != 0) {
1515 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1516 prev_st->bToSelfBA) {
1517 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1518 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1519 last_evm =
1520 priv->stats.slide_evm[slide_evm_index];
1521 priv->stats.slide_evm_total -= last_evm;
1522 }
1523
1524 priv->stats.slide_evm_total += prev_st->SignalQuality;
1525
1526 priv->stats.slide_evm[slide_evm_index++] =
1527 prev_st->SignalQuality;
1528 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1529 slide_evm_index = 0;
1530
1531 tmp_val = priv->stats.slide_evm_total /
1532 slide_evm_statistics;
1533 priv->stats.last_signal_strength_inpercent = tmp_val;
1534 }
1535
1536 if (prev_st->bPacketToSelf ||
1537 prev_st->bPacketBeacon ||
1538 prev_st->bToSelfBA) {
1539 for (ij = 0; ij < 2; ij++) {
1540 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1541 if (priv->stats.rx_evm_percentage[ij] == 0)
1542 priv->stats.rx_evm_percentage[ij] =
1543 prev_st->RxMIMOSignalQuality[ij];
1544 priv->stats.rx_evm_percentage[ij] =
1545 ((priv->stats.rx_evm_percentage[ij] *
1546 (RX_SMOOTH - 1)) +
1547 (prev_st->RxMIMOSignalQuality[ij])) /
1548 (RX_SMOOTH);
1549 }
1550 }
1551 }
1552 }
1553 }
1554
_rtl92e_translate_rx_signal_stats(struct net_device * dev,struct sk_buff * skb,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo)1555 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1556 struct sk_buff *skb,
1557 struct rtllib_rx_stats *pstats,
1558 struct rx_desc *pdesc,
1559 struct rx_fwinfo *pdrvinfo)
1560 {
1561 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1562 bool bpacket_match_bssid, bpacket_toself;
1563 bool bPacketBeacon = false;
1564 struct rtllib_hdr_3addr *hdr;
1565 bool bToSelfBA = false;
1566 static struct rtllib_rx_stats previous_stats;
1567 u16 fc, type;
1568 u8 *tmp_buf;
1569 u8 *praddr;
1570
1571 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1572
1573 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1574 fc = le16_to_cpu(hdr->frame_ctl);
1575 type = WLAN_FC_GET_TYPE(fc);
1576 praddr = hdr->addr1;
1577
1578 bpacket_match_bssid =
1579 ((type != RTLLIB_FTYPE_CTL) &&
1580 ether_addr_equal(priv->rtllib->current_network.bssid,
1581 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1582 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1583 hdr->addr3) &&
1584 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1585 bpacket_toself = bpacket_match_bssid && /* check this */
1586 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1587 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1588 bPacketBeacon = true;
1589 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1590 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1591 &previous_stats, bpacket_match_bssid,
1592 bpacket_toself, bPacketBeacon, bToSelfBA);
1593 rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1594 }
1595
_rtl92e_update_received_rate_histogram_stats(struct net_device * dev,struct rtllib_rx_stats * pstats)1596 static void _rtl92e_update_received_rate_histogram_stats(
1597 struct net_device *dev,
1598 struct rtllib_rx_stats *pstats)
1599 {
1600 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1601 u32 rcvType = 1;
1602 u32 rateIndex;
1603
1604 if (pstats->bCRC)
1605 rcvType = 2;
1606 else if (pstats->bICV)
1607 rcvType = 3;
1608
1609 switch (pstats->rate) {
1610 case MGN_1M:
1611 rateIndex = 0;
1612 break;
1613 case MGN_2M:
1614 rateIndex = 1;
1615 break;
1616 case MGN_5_5M:
1617 rateIndex = 2;
1618 break;
1619 case MGN_11M:
1620 rateIndex = 3;
1621 break;
1622 case MGN_6M:
1623 rateIndex = 4;
1624 break;
1625 case MGN_9M:
1626 rateIndex = 5;
1627 break;
1628 case MGN_12M:
1629 rateIndex = 6;
1630 break;
1631 case MGN_18M:
1632 rateIndex = 7;
1633 break;
1634 case MGN_24M:
1635 rateIndex = 8;
1636 break;
1637 case MGN_36M:
1638 rateIndex = 9;
1639 break;
1640 case MGN_48M:
1641 rateIndex = 10;
1642 break;
1643 case MGN_54M:
1644 rateIndex = 11;
1645 break;
1646 case MGN_MCS0:
1647 rateIndex = 12;
1648 break;
1649 case MGN_MCS1:
1650 rateIndex = 13;
1651 break;
1652 case MGN_MCS2:
1653 rateIndex = 14;
1654 break;
1655 case MGN_MCS3:
1656 rateIndex = 15;
1657 break;
1658 case MGN_MCS4:
1659 rateIndex = 16;
1660 break;
1661 case MGN_MCS5:
1662 rateIndex = 17;
1663 break;
1664 case MGN_MCS6:
1665 rateIndex = 18;
1666 break;
1667 case MGN_MCS7:
1668 rateIndex = 19;
1669 break;
1670 case MGN_MCS8:
1671 rateIndex = 20;
1672 break;
1673 case MGN_MCS9:
1674 rateIndex = 21;
1675 break;
1676 case MGN_MCS10:
1677 rateIndex = 22;
1678 break;
1679 case MGN_MCS11:
1680 rateIndex = 23;
1681 break;
1682 case MGN_MCS12:
1683 rateIndex = 24;
1684 break;
1685 case MGN_MCS13:
1686 rateIndex = 25;
1687 break;
1688 case MGN_MCS14:
1689 rateIndex = 26;
1690 break;
1691 case MGN_MCS15:
1692 rateIndex = 27;
1693 break;
1694 default:
1695 rateIndex = 28;
1696 break;
1697 }
1698 priv->stats.received_rate_histogram[0][rateIndex]++;
1699 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
1700 }
1701
rtl92e_get_rx_stats(struct net_device * dev,struct rtllib_rx_stats * stats,struct rx_desc * pdesc,struct sk_buff * skb)1702 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
1703 struct rx_desc *pdesc, struct sk_buff *skb)
1704 {
1705 struct rx_fwinfo *pDrvInfo = NULL;
1706
1707 stats->bICV = pdesc->ICV;
1708 stats->bCRC = pdesc->CRC32;
1709 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
1710
1711 stats->Length = pdesc->Length;
1712 if (stats->Length < 24)
1713 stats->bHwError |= 1;
1714
1715 if (stats->bHwError) {
1716 stats->bShift = false;
1717 return false;
1718 }
1719
1720 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
1721 stats->RxBufShift = (pdesc->Shift) & 0x03;
1722 stats->Decrypted = !pdesc->SWDec;
1723
1724 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
1725
1726 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
1727 pDrvInfo->RxRate);
1728 stats->bShortPreamble = pDrvInfo->SPLCP;
1729
1730 _rtl92e_update_received_rate_histogram_stats(dev, stats);
1731
1732 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
1733 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
1734 (pDrvInfo->FirstAGGR == 1);
1735
1736 stats->TimeStampLow = pDrvInfo->TSFL;
1737 stats->TimeStampHigh = rtl92e_readl(dev, TSFR + 4);
1738
1739 rtl92e_update_rx_pkt_timestamp(dev, stats);
1740
1741 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
1742 stats->bShift = 1;
1743
1744 stats->RxIs40MHzPacket = pDrvInfo->BW;
1745
1746 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
1747 skb_trim(skb, skb->len - S_CRC_LEN);
1748
1749
1750 stats->packetlength = stats->Length - 4;
1751 stats->fraglength = stats->packetlength;
1752 stats->fragoffset = 0;
1753 stats->ntotalfrag = 1;
1754 return true;
1755 }
1756
rtl92e_stop_adapter(struct net_device * dev,bool reset)1757 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
1758 {
1759 struct r8192_priv *priv = rtllib_priv(dev);
1760 int i;
1761 u8 OpMode;
1762 u8 u1bTmp;
1763 u32 ulRegRead;
1764
1765 OpMode = RT_OP_MODE_NO_LINK;
1766 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
1767
1768 if (!priv->rtllib->bSupportRemoteWakeUp) {
1769 u1bTmp = 0x0;
1770 rtl92e_writeb(dev, CMDR, u1bTmp);
1771 }
1772
1773 mdelay(20);
1774
1775 if (!reset) {
1776 mdelay(150);
1777
1778 priv->hw_rf_off_action = 2;
1779
1780 if (!priv->rtllib->bSupportRemoteWakeUp) {
1781 rtl92e_set_rf_off(dev);
1782 ulRegRead = rtl92e_readl(dev, CPU_GEN);
1783 ulRegRead |= CPU_GEN_SYSTEM_RESET;
1784 rtl92e_writel(dev, CPU_GEN, ulRegRead);
1785 } else {
1786 rtl92e_writel(dev, WFCRC0, 0xffffffff);
1787 rtl92e_writel(dev, WFCRC1, 0xffffffff);
1788 rtl92e_writel(dev, WFCRC2, 0xffffffff);
1789
1790 rtl92e_writeb(dev, PMR, 0x5);
1791 rtl92e_writeb(dev, MAC_BLK_CTRL, 0xa);
1792 }
1793 }
1794
1795 for (i = 0; i < MAX_QUEUE_SIZE; i++)
1796 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
1797
1798 skb_queue_purge(&priv->skb_queue);
1799 }
1800
rtl92e_update_ratr_table(struct net_device * dev)1801 void rtl92e_update_ratr_table(struct net_device *dev)
1802 {
1803 struct r8192_priv *priv = rtllib_priv(dev);
1804 struct rtllib_device *ieee = priv->rtllib;
1805 u8 *pMcsRate = ieee->dot11ht_oper_rate_set;
1806 u32 ratr_value = 0;
1807 u16 rate_config = 0;
1808 u8 rate_index = 0;
1809
1810 rtl92e_config_rate(dev, &rate_config);
1811 ratr_value = rate_config | *pMcsRate << 12;
1812 switch (ieee->mode) {
1813 case WIRELESS_MODE_B:
1814 ratr_value &= 0x0000000F;
1815 break;
1816 case WIRELESS_MODE_G:
1817 case WIRELESS_MODE_G | WIRELESS_MODE_B:
1818 ratr_value &= 0x00000FF7;
1819 break;
1820 case WIRELESS_MODE_N_24G:
1821 if (ieee->ht_info->peer_mimo_ps == 0)
1822 ratr_value &= 0x0007F007;
1823 else
1824 ratr_value &= 0x000FF007;
1825 break;
1826 default:
1827 break;
1828 }
1829 ratr_value &= 0x0FFFFFFF;
1830 if (ieee->ht_info->cur_tx_bw40mhz &&
1831 ieee->ht_info->bCurShortGI40MHz)
1832 ratr_value |= 0x80000000;
1833 else if (!ieee->ht_info->cur_tx_bw40mhz &&
1834 ieee->ht_info->bCurShortGI20MHz)
1835 ratr_value |= 0x80000000;
1836 rtl92e_writel(dev, RATR0 + rate_index * 4, ratr_value);
1837 rtl92e_writeb(dev, UFWP, 1);
1838 }
1839
1840 void
rtl92e_init_variables(struct net_device * dev)1841 rtl92e_init_variables(struct net_device *dev)
1842 {
1843 struct r8192_priv *priv = rtllib_priv(dev);
1844
1845 strscpy(priv->nick, "rtl8192E", sizeof(priv->nick));
1846
1847 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
1848 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
1849 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
1850
1851 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
1852
1853 priv->short_retry_limit = 0x30;
1854 priv->long_retry_limit = 0x30;
1855
1856 priv->receive_config = RCR_ADD3 |
1857 RCR_AMF | RCR_ADF |
1858 RCR_AICV |
1859 RCR_AB | RCR_AM | RCR_APM |
1860 RCR_AAP | ((u32)7 << RCR_MXDMA_OFFSET) |
1861 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
1862
1863 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
1864 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
1865 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
1866 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
1867 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
1868 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
1869
1870 priv->bfirst_after_down = false;
1871 }
1872
rtl92e_enable_irq(struct net_device * dev)1873 void rtl92e_enable_irq(struct net_device *dev)
1874 {
1875 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1876
1877 priv->irq_enabled = 1;
1878
1879 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
1880 }
1881
rtl92e_disable_irq(struct net_device * dev)1882 void rtl92e_disable_irq(struct net_device *dev)
1883 {
1884 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1885
1886 rtl92e_writel(dev, INTA_MASK, 0);
1887
1888 priv->irq_enabled = 0;
1889 }
1890
rtl92e_enable_rx(struct net_device * dev)1891 void rtl92e_enable_rx(struct net_device *dev)
1892 {
1893 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1894
1895 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
1896 }
1897
1898 static const u32 TX_DESC_BASE[] = {
1899 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
1900 };
1901
rtl92e_enable_tx(struct net_device * dev)1902 void rtl92e_enable_tx(struct net_device *dev)
1903 {
1904 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1905 u32 i;
1906
1907 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
1908 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
1909 }
1910
rtl92e_ack_irq(struct net_device * dev,u32 * p_inta)1911 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta)
1912 {
1913 *p_inta = rtl92e_readl(dev, ISR);
1914 rtl92e_writel(dev, ISR, *p_inta);
1915 }
1916
rtl92e_is_rx_stuck(struct net_device * dev)1917 bool rtl92e_is_rx_stuck(struct net_device *dev)
1918 {
1919 struct r8192_priv *priv = rtllib_priv(dev);
1920 u16 RegRxCounter = rtl92e_readw(dev, 0x130);
1921 bool bStuck = false;
1922 static u8 rx_chk_cnt;
1923 u32 SlotIndex = 0, TotalRxStuckCount = 0;
1924 u8 i;
1925 u8 SilentResetRxSoltNum = 4;
1926
1927 rx_chk_cnt++;
1928 if (priv->undecorated_smoothed_pwdb >= (RATE_ADAPTIVE_TH_HIGH + 5)) {
1929 rx_chk_cnt = 0;
1930 } else if ((priv->undecorated_smoothed_pwdb < (RATE_ADAPTIVE_TH_HIGH + 5))
1931 && (((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) &&
1932 (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_40M))
1933 || ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) &&
1934 (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_20M)))) {
1935 if (rx_chk_cnt < 2)
1936 return bStuck;
1937 rx_chk_cnt = 0;
1938 } else if ((((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) &&
1939 (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_40M)) ||
1940 ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) &&
1941 (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_20M))) &&
1942 priv->undecorated_smoothed_pwdb >= VERY_LOW_RSSI) {
1943 if (rx_chk_cnt < 4)
1944 return bStuck;
1945 rx_chk_cnt = 0;
1946 } else {
1947 if (rx_chk_cnt < 8)
1948 return bStuck;
1949 rx_chk_cnt = 0;
1950 }
1951
1952
1953 SlotIndex = (priv->silent_reset_rx_slot_index++) % SilentResetRxSoltNum;
1954
1955 if (priv->rx_ctr == RegRxCounter) {
1956 priv->silent_reset_rx_stuck_event[SlotIndex] = 1;
1957
1958 for (i = 0; i < SilentResetRxSoltNum; i++)
1959 TotalRxStuckCount += priv->silent_reset_rx_stuck_event[i];
1960
1961 if (TotalRxStuckCount == SilentResetRxSoltNum) {
1962 bStuck = true;
1963 for (i = 0; i < SilentResetRxSoltNum; i++)
1964 TotalRxStuckCount +=
1965 priv->silent_reset_rx_stuck_event[i];
1966 }
1967 } else {
1968 priv->silent_reset_rx_stuck_event[SlotIndex] = 0;
1969 }
1970
1971 priv->rx_ctr = RegRxCounter;
1972
1973 return bStuck;
1974 }
1975
rtl92e_is_tx_stuck(struct net_device * dev)1976 bool rtl92e_is_tx_stuck(struct net_device *dev)
1977 {
1978 struct r8192_priv *priv = rtllib_priv(dev);
1979 bool bStuck = false;
1980 u16 RegTxCounter = rtl92e_readw(dev, 0x128);
1981
1982 if (priv->tx_counter == RegTxCounter)
1983 bStuck = true;
1984
1985 priv->tx_counter = RegTxCounter;
1986
1987 return bStuck;
1988 }
1989
rtl92e_get_nmode_support_by_sec(struct net_device * dev)1990 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
1991 {
1992 struct r8192_priv *priv = rtllib_priv(dev);
1993 struct rtllib_device *ieee = priv->rtllib;
1994
1995 if (ieee->rtllib_ap_sec_type &&
1996 (ieee->rtllib_ap_sec_type(priv->rtllib) & (SEC_ALG_WEP |
1997 SEC_ALG_TKIP))) {
1998 return false;
1999 } else {
2000 return true;
2001 }
2002 }
2003
rtl92e_is_halfn_supported_by_ap(struct net_device * dev)2004 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2005 {
2006 struct r8192_priv *priv = rtllib_priv(dev);
2007 struct rtllib_device *ieee = priv->rtllib;
2008
2009 return ieee->bHalfWirelessN24GMode;
2010 }
2011