1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "../rtl8192c/dm_common.h"
15 #include "../rtl8192c/fw_common.h"
16 #include "../rtl8192c/phy_common.h"
17 #include "dm.h"
18 #include "led.h"
19 #include "hw.h"
20 
21 #define LLT_CONFIG	5
22 
_rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)23 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
24 				      u8 set_bits, u8 clear_bits)
25 {
26 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
27 	struct rtl_priv *rtlpriv = rtl_priv(hw);
28 
29 	rtlpci->reg_bcn_ctrl_val |= set_bits;
30 	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
31 
32 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
33 }
34 
_rtl92ce_stop_tx_beacon(struct ieee80211_hw * hw)35 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
36 {
37 	struct rtl_priv *rtlpriv = rtl_priv(hw);
38 	u8 tmp1byte;
39 
40 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
41 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
42 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
43 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
44 	tmp1byte &= ~(BIT(0));
45 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
46 }
47 
_rtl92ce_resume_tx_beacon(struct ieee80211_hw * hw)48 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
49 {
50 	struct rtl_priv *rtlpriv = rtl_priv(hw);
51 	u8 tmp1byte;
52 
53 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
54 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
55 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
56 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
57 	tmp1byte |= BIT(0);
58 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
59 }
60 
_rtl92ce_enable_bcn_sub_func(struct ieee80211_hw * hw)61 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
62 {
63 	_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
64 }
65 
_rtl92ce_disable_bcn_sub_func(struct ieee80211_hw * hw)66 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
67 {
68 	_rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
69 }
70 
rtl92ce_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)71 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
72 {
73 	struct rtl_priv *rtlpriv = rtl_priv(hw);
74 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 
77 	switch (variable) {
78 	case HW_VAR_RCR:
79 		*((u32 *) (val)) = rtlpci->receive_config;
80 		break;
81 	case HW_VAR_RF_STATE:
82 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
83 		break;
84 	case HW_VAR_FWLPS_RF_ON:{
85 			enum rf_pwrstate rfstate;
86 			u32 val_rcr;
87 
88 			rtlpriv->cfg->ops->get_hw_reg(hw,
89 						      HW_VAR_RF_STATE,
90 						      (u8 *)(&rfstate));
91 			if (rfstate == ERFOFF) {
92 				*((bool *) (val)) = true;
93 			} else {
94 				val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
95 				val_rcr &= 0x00070000;
96 				if (val_rcr)
97 					*((bool *) (val)) = false;
98 				else
99 					*((bool *) (val)) = true;
100 			}
101 			break;
102 		}
103 	case HW_VAR_FW_PSMODE_STATUS:
104 		*((bool *) (val)) = ppsc->fw_current_inpsmode;
105 		break;
106 	case HW_VAR_CORRECT_TSF:{
107 		u64 tsf;
108 		u32 *ptsf_low = (u32 *)&tsf;
109 		u32 *ptsf_high = ((u32 *)&tsf) + 1;
110 
111 		*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
112 		*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
113 
114 		*((u64 *) (val)) = tsf;
115 
116 		break;
117 		}
118 	case HAL_DEF_WOWLAN:
119 		break;
120 	default:
121 		pr_err("switch case %#x not processed\n", variable);
122 		break;
123 	}
124 }
125 
rtl92ce_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)126 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
127 {
128 	struct rtl_priv *rtlpriv = rtl_priv(hw);
129 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
130 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
131 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
132 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
133 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
134 	u8 idx;
135 
136 	switch (variable) {
137 	case HW_VAR_ETHER_ADDR:{
138 			for (idx = 0; idx < ETH_ALEN; idx++) {
139 				rtl_write_byte(rtlpriv, (REG_MACID + idx),
140 					       val[idx]);
141 			}
142 			break;
143 		}
144 	case HW_VAR_BASIC_RATE:{
145 			u16 rate_cfg = ((u16 *) val)[0];
146 			u8 rate_index = 0;
147 
148 			rate_cfg &= 0x15f;
149 			rate_cfg |= 0x01;
150 			rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
151 			rtl_write_byte(rtlpriv, REG_RRSR + 1,
152 				       (rate_cfg >> 8) & 0xff);
153 			while (rate_cfg > 0x1) {
154 				rate_cfg = (rate_cfg >> 1);
155 				rate_index++;
156 			}
157 			rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
158 				       rate_index);
159 			break;
160 		}
161 	case HW_VAR_BSSID:{
162 			for (idx = 0; idx < ETH_ALEN; idx++) {
163 				rtl_write_byte(rtlpriv, (REG_BSSID + idx),
164 					       val[idx]);
165 			}
166 			break;
167 		}
168 	case HW_VAR_SIFS:{
169 			rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
170 			rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
171 
172 			rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
173 			rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
174 
175 			if (!mac->ht_enable)
176 				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
177 					       0x0e0e);
178 			else
179 				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
180 					       *((u16 *) val));
181 			break;
182 		}
183 	case HW_VAR_SLOT_TIME:{
184 			u8 e_aci;
185 
186 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
187 				"HW_VAR_SLOT_TIME %x\n", val[0]);
188 
189 			rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
190 
191 			for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
192 				rtlpriv->cfg->ops->set_hw_reg(hw,
193 							      HW_VAR_AC_PARAM,
194 							      &e_aci);
195 			}
196 			break;
197 		}
198 	case HW_VAR_ACK_PREAMBLE:{
199 			u8 reg_tmp;
200 			u8 short_preamble = (bool)*val;
201 
202 			reg_tmp = (mac->cur_40_prime_sc) << 5;
203 			if (short_preamble)
204 				reg_tmp |= 0x80;
205 
206 			rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
207 			break;
208 		}
209 	case HW_VAR_AMPDU_MIN_SPACE:{
210 			u8 min_spacing_to_set;
211 			u8 sec_min_space;
212 
213 			min_spacing_to_set = *val;
214 			if (min_spacing_to_set <= 7) {
215 				sec_min_space = 0;
216 
217 				if (min_spacing_to_set < sec_min_space)
218 					min_spacing_to_set = sec_min_space;
219 
220 				mac->min_space_cfg = ((mac->min_space_cfg &
221 						       0xf8) |
222 						      min_spacing_to_set);
223 
224 				*val = min_spacing_to_set;
225 
226 				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
227 					"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
228 					mac->min_space_cfg);
229 
230 				rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
231 					       mac->min_space_cfg);
232 			}
233 			break;
234 		}
235 	case HW_VAR_SHORTGI_DENSITY:{
236 			u8 density_to_set;
237 
238 			density_to_set = *val;
239 			mac->min_space_cfg |= (density_to_set << 3);
240 
241 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
242 				"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
243 				mac->min_space_cfg);
244 
245 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
246 				       mac->min_space_cfg);
247 
248 			break;
249 		}
250 	case HW_VAR_AMPDU_FACTOR:{
251 			u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
252 			u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
253 
254 			u8 factor_toset;
255 			u8 *p_regtoset = NULL;
256 			u8 index = 0;
257 
258 			if ((rtlpriv->btcoexist.bt_coexistence) &&
259 			    (rtlpriv->btcoexist.bt_coexist_type ==
260 			    BT_CSR_BC4))
261 				p_regtoset = regtoset_bt;
262 			else
263 				p_regtoset = regtoset_normal;
264 
265 			factor_toset = *(val);
266 			if (factor_toset <= 3) {
267 				factor_toset = (1 << (factor_toset + 2));
268 				if (factor_toset > 0xf)
269 					factor_toset = 0xf;
270 
271 				for (index = 0; index < 4; index++) {
272 					if ((p_regtoset[index] & 0xf0) >
273 					    (factor_toset << 4))
274 						p_regtoset[index] =
275 						    (p_regtoset[index] & 0x0f) |
276 						    (factor_toset << 4);
277 
278 					if ((p_regtoset[index] & 0x0f) >
279 					    factor_toset)
280 						p_regtoset[index] =
281 						    (p_regtoset[index] & 0xf0) |
282 						    (factor_toset);
283 
284 					rtl_write_byte(rtlpriv,
285 						       (REG_AGGLEN_LMT + index),
286 						       p_regtoset[index]);
287 
288 				}
289 
290 				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
291 					"Set HW_VAR_AMPDU_FACTOR: %#x\n",
292 					factor_toset);
293 			}
294 			break;
295 		}
296 	case HW_VAR_AC_PARAM:{
297 			u8 e_aci = *(val);
298 
299 			rtl92c_dm_init_edca_turbo(hw);
300 
301 			if (rtlpci->acm_method != EACMWAY2_SW)
302 				rtlpriv->cfg->ops->set_hw_reg(hw,
303 							      HW_VAR_ACM_CTRL,
304 							      (&e_aci));
305 			break;
306 		}
307 	case HW_VAR_ACM_CTRL:{
308 			u8 e_aci = *(val);
309 			union aci_aifsn *p_aci_aifsn =
310 			    (union aci_aifsn *)(&(mac->ac[0].aifs));
311 			u8 acm = p_aci_aifsn->f.acm;
312 			u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
313 
314 			acm_ctrl =
315 			    acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
316 
317 			if (acm) {
318 				switch (e_aci) {
319 				case AC0_BE:
320 					acm_ctrl |= ACMHW_BEQEN;
321 					break;
322 				case AC2_VI:
323 					acm_ctrl |= ACMHW_VIQEN;
324 					break;
325 				case AC3_VO:
326 					acm_ctrl |= ACMHW_VOQEN;
327 					break;
328 				default:
329 					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
330 						"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
331 						acm);
332 					break;
333 				}
334 			} else {
335 				switch (e_aci) {
336 				case AC0_BE:
337 					acm_ctrl &= (~ACMHW_BEQEN);
338 					break;
339 				case AC2_VI:
340 					acm_ctrl &= (~ACMHW_VIQEN);
341 					break;
342 				case AC3_VO:
343 					acm_ctrl &= (~ACMHW_VOQEN);
344 					break;
345 				default:
346 					pr_err("switch case %#x not processed\n",
347 					       e_aci);
348 					break;
349 				}
350 			}
351 
352 			rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
353 				"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
354 				acm_ctrl);
355 			rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
356 			break;
357 		}
358 	case HW_VAR_RCR:{
359 			rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
360 			rtlpci->receive_config = ((u32 *) (val))[0];
361 			break;
362 		}
363 	case HW_VAR_RETRY_LIMIT:{
364 			u8 retry_limit = val[0];
365 
366 			rtl_write_word(rtlpriv, REG_RL,
367 				       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
368 				       retry_limit << RETRY_LIMIT_LONG_SHIFT);
369 			break;
370 		}
371 	case HW_VAR_DUAL_TSF_RST:
372 		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
373 		break;
374 	case HW_VAR_EFUSE_BYTES:
375 		rtlefuse->efuse_usedbytes = *((u16 *) val);
376 		break;
377 	case HW_VAR_EFUSE_USAGE:
378 		rtlefuse->efuse_usedpercentage = *val;
379 		break;
380 	case HW_VAR_IO_CMD:
381 		rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
382 		break;
383 	case HW_VAR_WPA_CONFIG:
384 		rtl_write_byte(rtlpriv, REG_SECCFG, *val);
385 		break;
386 	case HW_VAR_SET_RPWM:{
387 			u8 rpwm_val;
388 
389 			rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
390 			udelay(1);
391 
392 			if (rpwm_val & BIT(7)) {
393 				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
394 			} else {
395 				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
396 					       *val | BIT(7));
397 			}
398 
399 			break;
400 		}
401 	case HW_VAR_H2C_FW_PWRMODE:{
402 			u8 psmode = *val;
403 
404 			if ((psmode != FW_PS_ACTIVE_MODE) &&
405 			    (!IS_92C_SERIAL(rtlhal->version))) {
406 				rtl92c_dm_rf_saving(hw, true);
407 			}
408 
409 			rtl92c_set_fw_pwrmode_cmd(hw, *val);
410 			break;
411 		}
412 	case HW_VAR_FW_PSMODE_STATUS:
413 		ppsc->fw_current_inpsmode = *((bool *) val);
414 		break;
415 	case HW_VAR_H2C_FW_JOINBSSRPT:{
416 			u8 mstatus = *val;
417 			u8 tmp_regcr, tmp_reg422;
418 			bool recover = false;
419 
420 			if (mstatus == RT_MEDIA_CONNECT) {
421 				rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
422 							      NULL);
423 
424 				tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
425 				rtl_write_byte(rtlpriv, REG_CR + 1,
426 					       (tmp_regcr | BIT(0)));
427 
428 				_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
429 				_rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
430 
431 				tmp_reg422 =
432 				    rtl_read_byte(rtlpriv,
433 						  REG_FWHW_TXQ_CTRL + 2);
434 				if (tmp_reg422 & BIT(6))
435 					recover = true;
436 				rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
437 					       tmp_reg422 & (~BIT(6)));
438 
439 				rtl92c_set_fw_rsvdpagepkt(hw, NULL);
440 
441 				_rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
442 				_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
443 
444 				if (recover) {
445 					rtl_write_byte(rtlpriv,
446 						       REG_FWHW_TXQ_CTRL + 2,
447 						       tmp_reg422);
448 				}
449 
450 				rtl_write_byte(rtlpriv, REG_CR + 1,
451 					       (tmp_regcr & ~(BIT(0))));
452 			}
453 			rtl92c_set_fw_joinbss_report_cmd(hw, *val);
454 
455 			break;
456 		}
457 	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
458 		rtl92c_set_p2p_ps_offload_cmd(hw, *val);
459 		break;
460 	case HW_VAR_AID:{
461 			u16 u2btmp;
462 
463 			u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
464 			u2btmp &= 0xC000;
465 			rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
466 						mac->assoc_id));
467 
468 			break;
469 		}
470 	case HW_VAR_CORRECT_TSF:{
471 			u8 btype_ibss = val[0];
472 
473 			if (btype_ibss)
474 				_rtl92ce_stop_tx_beacon(hw);
475 
476 			_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
477 
478 			rtl_write_dword(rtlpriv, REG_TSFTR,
479 					(u32) (mac->tsf & 0xffffffff));
480 			rtl_write_dword(rtlpriv, REG_TSFTR + 4,
481 					(u32) ((mac->tsf >> 32) & 0xffffffff));
482 
483 			_rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
484 
485 			if (btype_ibss)
486 				_rtl92ce_resume_tx_beacon(hw);
487 
488 			break;
489 
490 		}
491 	case HW_VAR_FW_LPS_ACTION: {
492 			bool enter_fwlps = *((bool *)val);
493 			u8 rpwm_val, fw_pwrmode;
494 			bool fw_current_inps;
495 
496 			if (enter_fwlps) {
497 				rpwm_val = 0x02;	/* RF off */
498 				fw_current_inps = true;
499 				rtlpriv->cfg->ops->set_hw_reg(hw,
500 						HW_VAR_FW_PSMODE_STATUS,
501 						(u8 *)(&fw_current_inps));
502 				rtlpriv->cfg->ops->set_hw_reg(hw,
503 						HW_VAR_H2C_FW_PWRMODE,
504 						&ppsc->fwctrl_psmode);
505 
506 				rtlpriv->cfg->ops->set_hw_reg(hw,
507 							      HW_VAR_SET_RPWM,
508 							      &rpwm_val);
509 			} else {
510 				rpwm_val = 0x0C;	/* RF on */
511 				fw_pwrmode = FW_PS_ACTIVE_MODE;
512 				fw_current_inps = false;
513 				rtlpriv->cfg->ops->set_hw_reg(hw,
514 							      HW_VAR_SET_RPWM,
515 							      &rpwm_val);
516 				rtlpriv->cfg->ops->set_hw_reg(hw,
517 						HW_VAR_H2C_FW_PWRMODE,
518 						&fw_pwrmode);
519 
520 				rtlpriv->cfg->ops->set_hw_reg(hw,
521 						HW_VAR_FW_PSMODE_STATUS,
522 						(u8 *)(&fw_current_inps));
523 			}
524 		break; }
525 	case HW_VAR_KEEP_ALIVE: {
526 		u8 array[2];
527 
528 		array[0] = 0xff;
529 		array[1] = *((u8 *)val);
530 		rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array);
531 		break; }
532 	default:
533 		pr_err("switch case %d not processed\n", variable);
534 		break;
535 	}
536 }
537 
_rtl92ce_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)538 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
539 {
540 	struct rtl_priv *rtlpriv = rtl_priv(hw);
541 	bool status = true;
542 	long count = 0;
543 	u32 value = _LLT_INIT_ADDR(address) |
544 	    _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
545 
546 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
547 
548 	do {
549 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
550 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
551 			break;
552 
553 		if (count > POLLING_LLT_THRESHOLD) {
554 			pr_err("Failed to polling write LLT done at address %d!\n",
555 			       address);
556 			status = false;
557 			break;
558 		}
559 	} while (++count);
560 
561 	return status;
562 }
563 
_rtl92ce_llt_table_init(struct ieee80211_hw * hw)564 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
565 {
566 	struct rtl_priv *rtlpriv = rtl_priv(hw);
567 	unsigned short i;
568 	u8 txpktbuf_bndy;
569 	u8 maxpage;
570 	bool status;
571 
572 #if LLT_CONFIG == 1
573 	maxpage = 255;
574 	txpktbuf_bndy = 252;
575 #elif LLT_CONFIG == 2
576 	maxpage = 127;
577 	txpktbuf_bndy = 124;
578 #elif LLT_CONFIG == 3
579 	maxpage = 255;
580 	txpktbuf_bndy = 174;
581 #elif LLT_CONFIG == 4
582 	maxpage = 255;
583 	txpktbuf_bndy = 246;
584 #elif LLT_CONFIG == 5
585 	maxpage = 255;
586 	txpktbuf_bndy = 246;
587 #endif
588 
589 #if LLT_CONFIG == 1
590 	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
591 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
592 #elif LLT_CONFIG == 2
593 	rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
594 #elif LLT_CONFIG == 3
595 	rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
596 #elif LLT_CONFIG == 4
597 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
598 #elif LLT_CONFIG == 5
599 	rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
600 
601 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
602 #endif
603 
604 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
605 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
606 
607 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
608 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
609 
610 	rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
611 	rtl_write_byte(rtlpriv, REG_PBP, 0x11);
612 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
613 
614 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
615 		status = _rtl92ce_llt_write(hw, i, i + 1);
616 		if (!status)
617 			return status;
618 	}
619 
620 	status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
621 	if (!status)
622 		return status;
623 
624 	for (i = txpktbuf_bndy; i < maxpage; i++) {
625 		status = _rtl92ce_llt_write(hw, i, (i + 1));
626 		if (!status)
627 			return status;
628 	}
629 
630 	status = _rtl92ce_llt_write(hw, maxpage, txpktbuf_bndy);
631 	if (!status)
632 		return status;
633 
634 	return true;
635 }
636 
_rtl92ce_gen_refresh_led_state(struct ieee80211_hw * hw)637 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
638 {
639 	struct rtl_priv *rtlpriv = rtl_priv(hw);
640 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
641 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
642 	enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
643 
644 	if (rtlpci->up_first_time)
645 		return;
646 
647 	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
648 		rtl92ce_sw_led_on(hw, pin0);
649 	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
650 		rtl92ce_sw_led_on(hw, pin0);
651 	else
652 		rtl92ce_sw_led_off(hw, pin0);
653 }
654 
_rtl92ce_init_mac(struct ieee80211_hw * hw)655 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
656 {
657 	struct rtl_priv *rtlpriv = rtl_priv(hw);
658 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
659 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
660 
661 	unsigned char bytetmp;
662 	unsigned short wordtmp;
663 	u16 retry;
664 
665 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
666 	if (rtlpriv->btcoexist.bt_coexistence) {
667 		u32 value32;
668 
669 		value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
670 		value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
671 		rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
672 	}
673 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
674 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
675 
676 	if (rtlpriv->btcoexist.bt_coexistence) {
677 		u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
678 
679 		u4b_tmp &= (~0x00024800);
680 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
681 	}
682 
683 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
684 	udelay(2);
685 
686 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
687 	udelay(2);
688 
689 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
690 	udelay(2);
691 
692 	retry = 0;
693 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
694 		rtl_read_dword(rtlpriv, 0xEC), bytetmp);
695 
696 	while ((bytetmp & BIT(0)) && retry < 1000) {
697 		retry++;
698 		udelay(50);
699 		bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
700 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
701 			rtl_read_dword(rtlpriv, 0xEC), bytetmp);
702 		udelay(50);
703 	}
704 
705 	rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
706 
707 	rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
708 	udelay(2);
709 
710 	if (rtlpriv->btcoexist.bt_coexistence) {
711 		bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
712 		rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
713 	}
714 
715 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
716 
717 	if (!_rtl92ce_llt_table_init(hw))
718 		return false;
719 
720 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
721 	rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
722 
723 	rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
724 
725 	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
726 	wordtmp &= 0xf;
727 	wordtmp |= 0xF771;
728 	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
729 
730 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
731 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
732 	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
733 
734 	rtl_write_byte(rtlpriv, 0x4d0, 0x0);
735 
736 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
737 			((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
738 			DMA_BIT_MASK(32));
739 	rtl_write_dword(rtlpriv, REG_MGQ_DESA,
740 			(u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
741 			DMA_BIT_MASK(32));
742 	rtl_write_dword(rtlpriv, REG_VOQ_DESA,
743 			(u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
744 	rtl_write_dword(rtlpriv, REG_VIQ_DESA,
745 			(u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
746 	rtl_write_dword(rtlpriv, REG_BEQ_DESA,
747 			(u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
748 	rtl_write_dword(rtlpriv, REG_BKQ_DESA,
749 			(u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
750 	rtl_write_dword(rtlpriv, REG_HQ_DESA,
751 			(u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
752 			DMA_BIT_MASK(32));
753 	rtl_write_dword(rtlpriv, REG_RX_DESA,
754 			(u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
755 			DMA_BIT_MASK(32));
756 
757 	if (IS_92C_SERIAL(rtlhal->version))
758 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
759 	else
760 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
761 
762 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
763 
764 	bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
765 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
766 	do {
767 		retry++;
768 		bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
769 	} while ((retry < 200) && (bytetmp & BIT(7)));
770 
771 	_rtl92ce_gen_refresh_led_state(hw);
772 
773 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
774 
775 	return true;
776 }
777 
_rtl92ce_hw_configure(struct ieee80211_hw * hw)778 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
779 {
780 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
781 	struct rtl_priv *rtlpriv = rtl_priv(hw);
782 	u8 reg_bw_opmode;
783 	u32 reg_prsr;
784 
785 	reg_bw_opmode = BW_OPMODE_20MHZ;
786 	reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
787 
788 	rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
789 
790 	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
791 
792 	rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
793 
794 	rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
795 
796 	rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
797 
798 	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
799 
800 	rtl_write_word(rtlpriv, REG_RL, 0x0707);
801 
802 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
803 
804 	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
805 
806 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
807 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
808 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
809 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
810 
811 	if ((rtlpriv->btcoexist.bt_coexistence) &&
812 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
813 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
814 	else
815 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
816 
817 	rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
818 
819 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
820 
821 	rtlpci->reg_bcn_ctrl_val = 0x1f;
822 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
823 
824 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
825 
826 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
827 
828 	rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
829 	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
830 
831 	if ((rtlpriv->btcoexist.bt_coexistence) &&
832 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
833 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
834 		rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
835 	} else {
836 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
837 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
838 	}
839 
840 	if ((rtlpriv->btcoexist.bt_coexistence) &&
841 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
842 		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
843 	else
844 		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
845 
846 	rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
847 
848 	rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
849 	rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
850 
851 	rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
852 
853 	rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
854 
855 	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
856 	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
857 
858 }
859 
_rtl92ce_enable_aspm_back_door(struct ieee80211_hw * hw)860 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
861 {
862 	struct rtl_priv *rtlpriv = rtl_priv(hw);
863 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
864 
865 	rtl_write_byte(rtlpriv, 0x34b, 0x93);
866 	rtl_write_word(rtlpriv, 0x350, 0x870c);
867 	rtl_write_byte(rtlpriv, 0x352, 0x1);
868 
869 	if (ppsc->support_backdoor)
870 		rtl_write_byte(rtlpriv, 0x349, 0x1b);
871 	else
872 		rtl_write_byte(rtlpriv, 0x349, 0x03);
873 
874 	rtl_write_word(rtlpriv, 0x350, 0x2718);
875 	rtl_write_byte(rtlpriv, 0x352, 0x1);
876 }
877 
rtl92ce_enable_hw_security_config(struct ieee80211_hw * hw)878 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
879 {
880 	struct rtl_priv *rtlpriv = rtl_priv(hw);
881 	u8 sec_reg_value;
882 
883 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
884 		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
885 		rtlpriv->sec.pairwise_enc_algorithm,
886 		rtlpriv->sec.group_enc_algorithm);
887 
888 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
889 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
890 			"not open hw encryption\n");
891 		return;
892 	}
893 
894 	sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
895 
896 	if (rtlpriv->sec.use_defaultkey) {
897 		sec_reg_value |= SCR_TXUSEDK;
898 		sec_reg_value |= SCR_RXUSEDK;
899 	}
900 
901 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
902 
903 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
904 
905 	rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
906 		"The SECR-value %x\n", sec_reg_value);
907 
908 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
909 
910 }
911 
rtl92ce_hw_init(struct ieee80211_hw * hw)912 int rtl92ce_hw_init(struct ieee80211_hw *hw)
913 {
914 	struct rtl_priv *rtlpriv = rtl_priv(hw);
915 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
916 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
917 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
918 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
919 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
920 	bool rtstatus = true;
921 	bool is92c;
922 	int err;
923 	u8 tmp_u1b;
924 	unsigned long flags;
925 
926 	rtlpci->being_init_adapter = true;
927 
928 	/* Since this function can take a very long time (up to 350 ms)
929 	 * and can be called with irqs disabled, reenable the irqs
930 	 * to let the other devices continue being serviced.
931 	 *
932 	 * It is safe doing so since our own interrupts will only be enabled
933 	 * in a subsequent step.
934 	 */
935 	local_save_flags(flags);
936 	local_irq_enable();
937 
938 	rtlhal->fw_ready = false;
939 	rtlpriv->intf_ops->disable_aspm(hw);
940 	rtstatus = _rtl92ce_init_mac(hw);
941 	if (!rtstatus) {
942 		pr_err("Init MAC failed\n");
943 		err = 1;
944 		goto exit;
945 	}
946 
947 	err = rtl92c_download_fw(hw);
948 	if (err) {
949 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
950 			"Failed to download FW. Init HW without FW now..\n");
951 		err = 1;
952 		goto exit;
953 	}
954 
955 	rtlhal->fw_ready = true;
956 	rtlhal->last_hmeboxnum = 0;
957 	rtl92c_phy_mac_config(hw);
958 	/* because last function modify RCR, so we update
959 	 * rcr var here, or TP will unstable for receive_config
960 	 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
961 	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
962 	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
963 	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
964 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
965 	rtl92c_phy_bb_config(hw);
966 	rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
967 	rtl92c_phy_rf_config(hw);
968 	if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
969 	    !IS_92C_SERIAL(rtlhal->version)) {
970 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
971 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
972 	} else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
973 		rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
974 		rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
975 		rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
976 		rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
977 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
978 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
979 	}
980 	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
981 						 RF_CHNLBW, RFREG_OFFSET_MASK);
982 	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
983 						 RF_CHNLBW, RFREG_OFFSET_MASK);
984 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
985 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
986 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
987 	_rtl92ce_hw_configure(hw);
988 	rtl_cam_reset_all_entry(hw);
989 	rtl92ce_enable_hw_security_config(hw);
990 
991 	ppsc->rfpwr_state = ERFON;
992 
993 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
994 	_rtl92ce_enable_aspm_back_door(hw);
995 	rtlpriv->intf_ops->enable_aspm(hw);
996 
997 	rtl8192ce_bt_hw_init(hw);
998 
999 	if (ppsc->rfpwr_state == ERFON) {
1000 		rtl92c_phy_set_rfpath_switch(hw, 1);
1001 		if (rtlphy->iqk_initialized) {
1002 			rtl92c_phy_iq_calibrate(hw, true);
1003 		} else {
1004 			rtl92c_phy_iq_calibrate(hw, false);
1005 			rtlphy->iqk_initialized = true;
1006 		}
1007 
1008 		rtl92c_dm_check_txpower_tracking(hw);
1009 		rtl92c_phy_lc_calibrate(hw);
1010 	}
1011 
1012 	is92c = IS_92C_SERIAL(rtlhal->version);
1013 	tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1014 	if (!(tmp_u1b & BIT(0))) {
1015 		rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1016 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1017 	}
1018 
1019 	if (!(tmp_u1b & BIT(1)) && is92c) {
1020 		rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1021 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1022 	}
1023 
1024 	if (!(tmp_u1b & BIT(4))) {
1025 		tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1026 		tmp_u1b &= 0x0F;
1027 		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1028 		udelay(10);
1029 		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1030 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1031 	}
1032 	rtl92c_dm_init(hw);
1033 exit:
1034 	local_irq_restore(flags);
1035 	rtlpci->being_init_adapter = false;
1036 	return err;
1037 }
1038 
_rtl92ce_read_chip_version(struct ieee80211_hw * hw)1039 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1040 {
1041 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1042 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1043 	enum version_8192c version = VERSION_UNKNOWN;
1044 	u32 value32;
1045 	const char *versionid;
1046 
1047 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1048 	if (value32 & TRP_VAUX_EN) {
1049 		version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1050 			   VERSION_A_CHIP_88C;
1051 	} else {
1052 		version = (enum version_8192c) (CHIP_VER_B |
1053 				((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1054 				((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1055 		if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1056 		     CHIP_VER_RTL_MASK)) {
1057 			version = (enum version_8192c)(version |
1058 				   ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1059 				   ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1060 				   CHIP_VENDOR_UMC));
1061 		}
1062 		if (IS_92C_SERIAL(version)) {
1063 			value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1064 			version = (enum version_8192c)(version |
1065 				   ((CHIP_BONDING_IDENTIFIER(value32)
1066 				   == CHIP_BONDING_92C_1T2R) ?
1067 				   RF_TYPE_1T2R : 0));
1068 		}
1069 	}
1070 
1071 	switch (version) {
1072 	case VERSION_B_CHIP_92C:
1073 		versionid = "B_CHIP_92C";
1074 		break;
1075 	case VERSION_B_CHIP_88C:
1076 		versionid = "B_CHIP_88C";
1077 		break;
1078 	case VERSION_A_CHIP_92C:
1079 		versionid = "A_CHIP_92C";
1080 		break;
1081 	case VERSION_A_CHIP_88C:
1082 		versionid = "A_CHIP_88C";
1083 		break;
1084 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1085 		versionid = "A_CUT_92C_1T2R";
1086 		break;
1087 	case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1088 		versionid = "A_CUT_92C";
1089 		break;
1090 	case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1091 		versionid = "A_CUT_88C";
1092 		break;
1093 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1094 		versionid = "B_CUT_92C_1T2R";
1095 		break;
1096 	case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1097 		versionid = "B_CUT_92C";
1098 		break;
1099 	case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1100 		versionid = "B_CUT_88C";
1101 		break;
1102 	default:
1103 		versionid = "Unknown. Bug?";
1104 		break;
1105 	}
1106 
1107 	pr_info("Chip Version ID: %s\n", versionid);
1108 
1109 	switch (version & 0x3) {
1110 	case CHIP_88C:
1111 		rtlphy->rf_type = RF_1T1R;
1112 		break;
1113 	case CHIP_92C:
1114 		rtlphy->rf_type = RF_2T2R;
1115 		break;
1116 	case CHIP_92C_1T2R:
1117 		rtlphy->rf_type = RF_1T2R;
1118 		break;
1119 	default:
1120 		rtlphy->rf_type = RF_1T1R;
1121 		pr_err("ERROR RF_Type is set!!\n");
1122 		break;
1123 	}
1124 
1125 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1126 		rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1127 
1128 	return version;
1129 }
1130 
_rtl92ce_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1131 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1132 				     enum nl80211_iftype type)
1133 {
1134 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1135 	u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1136 	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1137 	u8 mode = MSR_NOLINK;
1138 
1139 	bt_msr &= 0xfc;
1140 
1141 	switch (type) {
1142 	case NL80211_IFTYPE_UNSPECIFIED:
1143 		mode = MSR_NOLINK;
1144 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1145 			"Set Network type to NO LINK!\n");
1146 		break;
1147 	case NL80211_IFTYPE_ADHOC:
1148 		mode = MSR_ADHOC;
1149 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1150 			"Set Network type to Ad Hoc!\n");
1151 		break;
1152 	case NL80211_IFTYPE_STATION:
1153 		mode = MSR_INFRA;
1154 		ledaction = LED_CTL_LINK;
1155 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1156 			"Set Network type to STA!\n");
1157 		break;
1158 	case NL80211_IFTYPE_AP:
1159 		mode = MSR_AP;
1160 		ledaction = LED_CTL_LINK;
1161 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1162 			"Set Network type to AP!\n");
1163 		break;
1164 	case NL80211_IFTYPE_MESH_POINT:
1165 		mode = MSR_ADHOC;
1166 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1167 			"Set Network type to Mesh Point!\n");
1168 		break;
1169 	default:
1170 		pr_err("Network type %d not supported!\n", type);
1171 		return 1;
1172 
1173 	}
1174 
1175 	/* MSR_INFRA == Link in infrastructure network;
1176 	 * MSR_ADHOC == Link in ad hoc network;
1177 	 * Therefore, check link state is necessary.
1178 	 *
1179 	 * MSR_AP == AP mode; link state does not matter here.
1180 	 */
1181 	if (mode != MSR_AP &&
1182 	    rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1183 		mode = MSR_NOLINK;
1184 		ledaction = LED_CTL_NO_LINK;
1185 	}
1186 	if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1187 		_rtl92ce_stop_tx_beacon(hw);
1188 		_rtl92ce_enable_bcn_sub_func(hw);
1189 	} else if (mode == MSR_ADHOC || mode == MSR_AP) {
1190 		_rtl92ce_resume_tx_beacon(hw);
1191 		_rtl92ce_disable_bcn_sub_func(hw);
1192 	} else {
1193 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1194 			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1195 			mode);
1196 	}
1197 	rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1198 
1199 	rtlpriv->cfg->ops->led_control(hw, ledaction);
1200 	if (mode == MSR_AP)
1201 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1202 	else
1203 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1204 	return 0;
1205 }
1206 
rtl92ce_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1207 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1208 {
1209 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1210 	u32 reg_rcr;
1211 
1212 	if (rtlpriv->psc.rfpwr_state != ERFON)
1213 		return;
1214 
1215 	rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1216 
1217 	if (check_bssid) {
1218 		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1219 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1220 					      (u8 *) (&reg_rcr));
1221 		_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1222 	} else if (!check_bssid) {
1223 		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1224 		_rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1225 		rtlpriv->cfg->ops->set_hw_reg(hw,
1226 					      HW_VAR_RCR, (u8 *) (&reg_rcr));
1227 	}
1228 
1229 }
1230 
rtl92ce_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1231 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1232 {
1233 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 
1235 	if (_rtl92ce_set_media_status(hw, type))
1236 		return -EOPNOTSUPP;
1237 
1238 	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1239 		if (type != NL80211_IFTYPE_AP &&
1240 		    type != NL80211_IFTYPE_MESH_POINT)
1241 			rtl92ce_set_check_bssid(hw, true);
1242 	} else {
1243 		rtl92ce_set_check_bssid(hw, false);
1244 	}
1245 
1246 	return 0;
1247 }
1248 
1249 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
rtl92ce_set_qos(struct ieee80211_hw * hw,int aci)1250 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1251 {
1252 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1253 
1254 	rtl92c_dm_init_edca_turbo(hw);
1255 	switch (aci) {
1256 	case AC1_BK:
1257 		rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1258 		break;
1259 	case AC0_BE:
1260 		/* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1261 		break;
1262 	case AC2_VI:
1263 		rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1264 		break;
1265 	case AC3_VO:
1266 		rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1267 		break;
1268 	default:
1269 		WARN_ONCE(true, "rtl8192ce: invalid aci: %d !\n", aci);
1270 		break;
1271 	}
1272 }
1273 
rtl92ce_enable_interrupt(struct ieee80211_hw * hw)1274 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1275 {
1276 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1277 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1278 
1279 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1280 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1281 	rtlpci->irq_enabled = true;
1282 }
1283 
rtl92ce_disable_interrupt(struct ieee80211_hw * hw)1284 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1285 {
1286 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1287 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1288 
1289 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1290 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1291 	rtlpci->irq_enabled = false;
1292 }
1293 
_rtl92ce_poweroff_adapter(struct ieee80211_hw * hw)1294 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1295 {
1296 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1297 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1298 	u8 u1b_tmp;
1299 	u32 u4b_tmp;
1300 
1301 	rtlpriv->intf_ops->enable_aspm(hw);
1302 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1303 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1304 	rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1305 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1306 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1307 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1308 	if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1309 		rtl92c_firmware_selfreset(hw);
1310 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1311 	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1312 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1313 	u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1314 	if ((rtlpriv->btcoexist.bt_coexistence) &&
1315 	    ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
1316 	     (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8))) {
1317 		rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1318 				(u1b_tmp << 8));
1319 	} else {
1320 		rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1321 				(u1b_tmp << 8));
1322 	}
1323 	rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1324 	rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1325 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1326 	if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1327 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1328 	if (rtlpriv->btcoexist.bt_coexistence) {
1329 		u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1330 		u4b_tmp |= 0x03824800;
1331 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1332 	} else {
1333 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1334 	}
1335 
1336 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1337 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1338 }
1339 
rtl92ce_card_disable(struct ieee80211_hw * hw)1340 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1341 {
1342 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1343 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1344 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1345 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1346 	enum nl80211_iftype opmode;
1347 
1348 	mac->link_state = MAC80211_NOLINK;
1349 	opmode = NL80211_IFTYPE_UNSPECIFIED;
1350 	_rtl92ce_set_media_status(hw, opmode);
1351 	if (rtlpci->driver_is_goingto_unload ||
1352 	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1353 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1354 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1355 	_rtl92ce_poweroff_adapter(hw);
1356 
1357 	/* after power off we should do iqk again */
1358 	rtlpriv->phy.iqk_initialized = false;
1359 }
1360 
rtl92ce_interrupt_recognized(struct ieee80211_hw * hw,struct rtl_int * intvec)1361 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1362 				  struct rtl_int *intvec)
1363 {
1364 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1365 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1366 
1367 	intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1368 	rtl_write_dword(rtlpriv, ISR, intvec->inta);
1369 }
1370 
rtl92ce_set_beacon_related_registers(struct ieee80211_hw * hw)1371 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1372 {
1373 
1374 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1376 	u16 bcn_interval, atim_window;
1377 
1378 	bcn_interval = mac->beacon_interval;
1379 	atim_window = 2;	/*FIX MERGE */
1380 	rtl92ce_disable_interrupt(hw);
1381 	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1382 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1383 	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1384 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1385 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1386 	rtl_write_byte(rtlpriv, 0x606, 0x30);
1387 	rtl92ce_enable_interrupt(hw);
1388 }
1389 
rtl92ce_set_beacon_interval(struct ieee80211_hw * hw)1390 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1391 {
1392 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1393 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1394 	u16 bcn_interval = mac->beacon_interval;
1395 
1396 	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1397 		"beacon_interval:%d\n", bcn_interval);
1398 	rtl92ce_disable_interrupt(hw);
1399 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1400 	rtl92ce_enable_interrupt(hw);
1401 }
1402 
rtl92ce_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1403 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1404 				   u32 add_msr, u32 rm_msr)
1405 {
1406 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1407 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1408 
1409 	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1410 		add_msr, rm_msr);
1411 
1412 	if (add_msr)
1413 		rtlpci->irq_mask[0] |= add_msr;
1414 	if (rm_msr)
1415 		rtlpci->irq_mask[0] &= (~rm_msr);
1416 	rtl92ce_disable_interrupt(hw);
1417 	rtl92ce_enable_interrupt(hw);
1418 }
1419 
_rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)1420 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1421 						 bool autoload_fail,
1422 						 u8 *hwinfo)
1423 {
1424 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1425 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1426 	u8 rf_path, index, tempval;
1427 	u16 i;
1428 
1429 	for (rf_path = 0; rf_path < 2; rf_path++) {
1430 		for (i = 0; i < 3; i++) {
1431 			if (!autoload_fail &&
1432 			    hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i] != 0xff &&
1433 			    hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i] != 0xff) {
1434 				rtlefuse->
1435 				    eeprom_chnlarea_txpwr_cck[rf_path][i] =
1436 				    hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1437 				rtlefuse->
1438 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1439 				    hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1440 					   i];
1441 			} else {
1442 				rtlefuse->
1443 				    eeprom_chnlarea_txpwr_cck[rf_path][i] =
1444 				    EEPROM_DEFAULT_TXPOWERLEVEL;
1445 				rtlefuse->
1446 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1447 				    EEPROM_DEFAULT_TXPOWERLEVEL;
1448 			}
1449 		}
1450 	}
1451 
1452 	for (i = 0; i < 3; i++) {
1453 		if (!autoload_fail &&
1454 		    hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i] != 0xff)
1455 			tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1456 		else
1457 			tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1458 		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1459 		    (tempval & 0xf);
1460 		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1461 		    ((tempval & 0xf0) >> 4);
1462 	}
1463 
1464 	for (rf_path = 0; rf_path < 2; rf_path++)
1465 		for (i = 0; i < 3; i++)
1466 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1467 				"RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1468 				rf_path, i,
1469 				rtlefuse->
1470 				eeprom_chnlarea_txpwr_cck[rf_path][i]);
1471 	for (rf_path = 0; rf_path < 2; rf_path++)
1472 		for (i = 0; i < 3; i++)
1473 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1474 				"RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1475 				rf_path, i,
1476 				rtlefuse->
1477 				eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1478 	for (rf_path = 0; rf_path < 2; rf_path++)
1479 		for (i = 0; i < 3; i++)
1480 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1481 				"RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1482 				rf_path, i,
1483 				rtlefuse->
1484 				eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1485 
1486 	for (rf_path = 0; rf_path < 2; rf_path++) {
1487 		for (i = 0; i < 14; i++) {
1488 			index = rtl92c_get_chnl_group((u8)i);
1489 
1490 			rtlefuse->txpwrlevel_cck[rf_path][i] =
1491 			    rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1492 			rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1493 			    rtlefuse->
1494 			    eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1495 
1496 			if ((rtlefuse->
1497 			     eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1498 			     rtlefuse->
1499 			     eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1500 			    > 0) {
1501 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1502 				    rtlefuse->
1503 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1504 				    [index] -
1505 				    rtlefuse->
1506 				    eprom_chnl_txpwr_ht40_2sdf[rf_path]
1507 				    [index];
1508 			} else {
1509 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1510 			}
1511 		}
1512 
1513 		for (i = 0; i < 14; i++) {
1514 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1515 				"RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1516 				rf_path, i,
1517 				rtlefuse->txpwrlevel_cck[rf_path][i],
1518 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1519 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1520 		}
1521 	}
1522 
1523 	for (i = 0; i < 3; i++) {
1524 		if (!autoload_fail &&
1525 		    hwinfo[EEPROM_TXPWR_GROUP + i] != 0xff &&
1526 		    hwinfo[EEPROM_TXPWR_GROUP + 3 + i] != 0xff) {
1527 			rtlefuse->eeprom_pwrlimit_ht40[i] =
1528 			    hwinfo[EEPROM_TXPWR_GROUP + i];
1529 			rtlefuse->eeprom_pwrlimit_ht20[i] =
1530 			    hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1531 		} else {
1532 			rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1533 			rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1534 		}
1535 	}
1536 
1537 	for (rf_path = 0; rf_path < 2; rf_path++) {
1538 		for (i = 0; i < 14; i++) {
1539 			index = rtl92c_get_chnl_group((u8)i);
1540 
1541 			if (rf_path == RF90_PATH_A) {
1542 				rtlefuse->pwrgroup_ht20[rf_path][i] =
1543 				    (rtlefuse->eeprom_pwrlimit_ht20[index]
1544 				     & 0xf);
1545 				rtlefuse->pwrgroup_ht40[rf_path][i] =
1546 				    (rtlefuse->eeprom_pwrlimit_ht40[index]
1547 				     & 0xf);
1548 			} else if (rf_path == RF90_PATH_B) {
1549 				rtlefuse->pwrgroup_ht20[rf_path][i] =
1550 				    ((rtlefuse->eeprom_pwrlimit_ht20[index]
1551 				      & 0xf0) >> 4);
1552 				rtlefuse->pwrgroup_ht40[rf_path][i] =
1553 				    ((rtlefuse->eeprom_pwrlimit_ht40[index]
1554 				      & 0xf0) >> 4);
1555 			}
1556 
1557 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1558 				"RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1559 				rf_path, i,
1560 				rtlefuse->pwrgroup_ht20[rf_path][i]);
1561 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1562 				"RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1563 				rf_path, i,
1564 				rtlefuse->pwrgroup_ht40[rf_path][i]);
1565 		}
1566 	}
1567 
1568 	for (i = 0; i < 14; i++) {
1569 		index = rtl92c_get_chnl_group((u8)i);
1570 
1571 		if (!autoload_fail &&
1572 		    hwinfo[EEPROM_TXPOWERHT20DIFF + index] != 0xff)
1573 			tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1574 		else
1575 			tempval = EEPROM_DEFAULT_HT20_DIFF;
1576 
1577 		rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1578 		rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1579 		    ((tempval >> 4) & 0xF);
1580 
1581 		if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1582 			rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1583 
1584 		if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1585 			rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1586 
1587 		index = rtl92c_get_chnl_group((u8)i);
1588 
1589 		if (!autoload_fail &&
1590 		    hwinfo[EEPROM_TXPOWER_OFDMDIFF + index] != 0xff)
1591 			tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1592 		else
1593 			tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1594 
1595 		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1596 		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1597 		    ((tempval >> 4) & 0xF);
1598 	}
1599 
1600 	rtlefuse->legacy_ht_txpowerdiff =
1601 	    rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1602 
1603 	for (i = 0; i < 14; i++)
1604 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1605 			"RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1606 			i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1607 	for (i = 0; i < 14; i++)
1608 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1609 			"RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1610 			i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1611 	for (i = 0; i < 14; i++)
1612 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1613 			"RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1614 			i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1615 	for (i = 0; i < 14; i++)
1616 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1617 			"RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1618 			i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1619 
1620 	if (!autoload_fail && hwinfo[RF_OPTION1] != 0xff)
1621 		rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1622 	else
1623 		rtlefuse->eeprom_regulatory = 0;
1624 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1625 		"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1626 
1627 	if (!autoload_fail &&
1628 	    hwinfo[EEPROM_TSSI_A] != 0xff &&
1629 	    hwinfo[EEPROM_TSSI_B] != 0xff) {
1630 		rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1631 		rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1632 	} else {
1633 		rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1634 		rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1635 	}
1636 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1637 		rtlefuse->eeprom_tssi[RF90_PATH_A],
1638 		rtlefuse->eeprom_tssi[RF90_PATH_B]);
1639 
1640 	if (!autoload_fail && hwinfo[EEPROM_THERMAL_METER] != 0xff)
1641 		tempval = hwinfo[EEPROM_THERMAL_METER];
1642 	else
1643 		tempval = EEPROM_DEFAULT_THERMALMETER;
1644 	rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1645 
1646 	if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1647 		rtlefuse->apk_thermalmeterignore = true;
1648 
1649 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1650 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1651 		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1652 }
1653 
_rtl92ce_read_adapter_info(struct ieee80211_hw * hw)1654 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1655 {
1656 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1657 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1658 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1659 	int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1660 			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1661 			EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1662 			COUNTRY_CODE_WORLD_WIDE_13};
1663 	u8 *hwinfo;
1664 
1665 	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1666 	if (!hwinfo)
1667 		return;
1668 
1669 	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1670 		goto exit;
1671 
1672 	_rtl92ce_read_txpower_info_from_hwpg(hw,
1673 					     rtlefuse->autoload_failflag,
1674 					     hwinfo);
1675 
1676 	rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1677 						 rtlefuse->autoload_failflag,
1678 						 hwinfo);
1679 	if (rtlhal->oem_id == RT_CID_DEFAULT) {
1680 		switch (rtlefuse->eeprom_oemid) {
1681 		case EEPROM_CID_DEFAULT:
1682 			if (rtlefuse->eeprom_did == 0x8176) {
1683 				if ((rtlefuse->eeprom_svid == 0x103C &&
1684 				     rtlefuse->eeprom_smid == 0x1629))
1685 					rtlhal->oem_id = RT_CID_819X_HP;
1686 				else
1687 					rtlhal->oem_id = RT_CID_DEFAULT;
1688 			} else {
1689 				rtlhal->oem_id = RT_CID_DEFAULT;
1690 			}
1691 			break;
1692 		case EEPROM_CID_TOSHIBA:
1693 			rtlhal->oem_id = RT_CID_TOSHIBA;
1694 			break;
1695 		case EEPROM_CID_QMI:
1696 			rtlhal->oem_id = RT_CID_819X_QMI;
1697 			break;
1698 		case EEPROM_CID_WHQL:
1699 		default:
1700 			rtlhal->oem_id = RT_CID_DEFAULT;
1701 			break;
1702 		}
1703 	}
1704 exit:
1705 	kfree(hwinfo);
1706 }
1707 
_rtl92ce_hal_customized_behavior(struct ieee80211_hw * hw)1708 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1709 {
1710 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1711 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1712 
1713 	switch (rtlhal->oem_id) {
1714 	case RT_CID_819X_HP:
1715 		rtlpriv->ledctl.led_opendrain = true;
1716 		break;
1717 	case RT_CID_819X_LENOVO:
1718 	case RT_CID_DEFAULT:
1719 	case RT_CID_TOSHIBA:
1720 	case RT_CID_CCX:
1721 	case RT_CID_819X_ACER:
1722 	case RT_CID_WHQL:
1723 	default:
1724 		break;
1725 	}
1726 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1727 		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1728 }
1729 
rtl92ce_read_eeprom_info(struct ieee80211_hw * hw)1730 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1731 {
1732 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1733 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1734 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1735 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1736 	u8 tmp_u1b;
1737 
1738 	rtlhal->version = _rtl92ce_read_chip_version(hw);
1739 	if (get_rf_type(rtlphy) == RF_1T1R)
1740 		rtlpriv->dm.rfpath_rxenable[0] = true;
1741 	else
1742 		rtlpriv->dm.rfpath_rxenable[0] =
1743 		    rtlpriv->dm.rfpath_rxenable[1] = true;
1744 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1745 		rtlhal->version);
1746 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1747 	if (tmp_u1b & BIT(4)) {
1748 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1749 		rtlefuse->epromtype = EEPROM_93C46;
1750 	} else {
1751 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1752 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1753 	}
1754 	if (tmp_u1b & BIT(5)) {
1755 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1756 		rtlefuse->autoload_failflag = false;
1757 		_rtl92ce_read_adapter_info(hw);
1758 	} else {
1759 		pr_err("Autoload ERR!!\n");
1760 	}
1761 	_rtl92ce_hal_customized_behavior(hw);
1762 }
1763 
rtl92ce_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)1764 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1765 		struct ieee80211_sta *sta)
1766 {
1767 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1768 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1769 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1770 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1771 	u32 ratr_value;
1772 	u8 ratr_index = 0;
1773 	u8 nmode = mac->ht_enable;
1774 	u16 shortgi_rate;
1775 	u32 tmp_ratr_value;
1776 	u8 curtxbw_40mhz = mac->bw_40;
1777 	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1778 			       1 : 0;
1779 	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1780 			       1 : 0;
1781 	enum wireless_mode wirelessmode = mac->mode;
1782 	u32 ratr_mask;
1783 
1784 	if (rtlhal->current_bandtype == BAND_ON_5G)
1785 		ratr_value = sta->deflink.supp_rates[1] << 4;
1786 	else
1787 		ratr_value = sta->deflink.supp_rates[0];
1788 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1789 		ratr_value = 0xfff;
1790 
1791 	ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1792 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1793 	switch (wirelessmode) {
1794 	case WIRELESS_MODE_B:
1795 		if (ratr_value & 0x0000000c)
1796 			ratr_value &= 0x0000000d;
1797 		else
1798 			ratr_value &= 0x0000000f;
1799 		break;
1800 	case WIRELESS_MODE_G:
1801 		ratr_value &= 0x00000FF5;
1802 		break;
1803 	case WIRELESS_MODE_N_24G:
1804 	case WIRELESS_MODE_N_5G:
1805 		nmode = 1;
1806 		if (get_rf_type(rtlphy) == RF_1T2R ||
1807 		    get_rf_type(rtlphy) == RF_1T1R)
1808 			ratr_mask = 0x000ff005;
1809 		else
1810 			ratr_mask = 0x0f0ff005;
1811 
1812 		ratr_value &= ratr_mask;
1813 		break;
1814 	default:
1815 		if (rtlphy->rf_type == RF_1T2R)
1816 			ratr_value &= 0x000ff0ff;
1817 		else
1818 			ratr_value &= 0x0f0ff0ff;
1819 
1820 		break;
1821 	}
1822 
1823 	if ((rtlpriv->btcoexist.bt_coexistence) &&
1824 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1825 	    (rtlpriv->btcoexist.bt_cur_state) &&
1826 	    (rtlpriv->btcoexist.bt_ant_isolation) &&
1827 	    ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1828 	    (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1829 		ratr_value &= 0x0fffcfc0;
1830 	else
1831 		ratr_value &= 0x0FFFFFFF;
1832 
1833 	if (nmode && ((curtxbw_40mhz &&
1834 			 curshortgi_40mhz) || (!curtxbw_40mhz &&
1835 					       curshortgi_20mhz))) {
1836 
1837 		ratr_value |= 0x10000000;
1838 		tmp_ratr_value = (ratr_value >> 12);
1839 
1840 		for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1841 			if ((1 << shortgi_rate) & tmp_ratr_value)
1842 				break;
1843 		}
1844 
1845 		shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1846 		    (shortgi_rate << 4) | (shortgi_rate);
1847 	}
1848 
1849 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1850 
1851 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1852 		rtl_read_dword(rtlpriv, REG_ARFR0));
1853 }
1854 
rtl92ce_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)1855 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1856 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1857 {
1858 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1859 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1860 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1861 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1862 	struct rtl_sta_info *sta_entry = NULL;
1863 	u32 ratr_bitmap;
1864 	u8 ratr_index;
1865 	u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap &
1866 			    IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
1867 	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap &
1868 			       IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
1869 	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1870 				1 : 0;
1871 	enum wireless_mode wirelessmode = 0;
1872 	bool shortgi = false;
1873 	u8 rate_mask[5];
1874 	u8 macid = 0;
1875 
1876 	sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1877 	wirelessmode = sta_entry->wireless_mode;
1878 	if (mac->opmode == NL80211_IFTYPE_STATION ||
1879 	    mac->opmode == NL80211_IFTYPE_MESH_POINT)
1880 		curtxbw_40mhz = mac->bw_40;
1881 	else if (mac->opmode == NL80211_IFTYPE_AP ||
1882 		mac->opmode == NL80211_IFTYPE_ADHOC)
1883 		macid = sta->aid + 1;
1884 
1885 	if (rtlhal->current_bandtype == BAND_ON_5G)
1886 		ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1887 	else
1888 		ratr_bitmap = sta->deflink.supp_rates[0];
1889 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1890 		ratr_bitmap = 0xfff;
1891 	ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1892 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1893 	switch (wirelessmode) {
1894 	case WIRELESS_MODE_B:
1895 		ratr_index = RATR_INX_WIRELESS_B;
1896 		if (ratr_bitmap & 0x0000000c)
1897 			ratr_bitmap &= 0x0000000d;
1898 		else
1899 			ratr_bitmap &= 0x0000000f;
1900 		break;
1901 	case WIRELESS_MODE_G:
1902 		ratr_index = RATR_INX_WIRELESS_GB;
1903 
1904 		if (rssi_level == 1)
1905 			ratr_bitmap &= 0x00000f00;
1906 		else if (rssi_level == 2)
1907 			ratr_bitmap &= 0x00000ff0;
1908 		else
1909 			ratr_bitmap &= 0x00000ff5;
1910 		break;
1911 	case WIRELESS_MODE_A:
1912 		ratr_index = RATR_INX_WIRELESS_A;
1913 		ratr_bitmap &= 0x00000ff0;
1914 		break;
1915 	case WIRELESS_MODE_N_24G:
1916 	case WIRELESS_MODE_N_5G:
1917 		ratr_index = RATR_INX_WIRELESS_NGB;
1918 
1919 		if (rtlphy->rf_type == RF_1T2R ||
1920 		    rtlphy->rf_type == RF_1T1R) {
1921 			if (curtxbw_40mhz) {
1922 				if (rssi_level == 1)
1923 					ratr_bitmap &= 0x000f0000;
1924 				else if (rssi_level == 2)
1925 					ratr_bitmap &= 0x000ff000;
1926 				else
1927 					ratr_bitmap &= 0x000ff015;
1928 			} else {
1929 				if (rssi_level == 1)
1930 					ratr_bitmap &= 0x000f0000;
1931 				else if (rssi_level == 2)
1932 					ratr_bitmap &= 0x000ff000;
1933 				else
1934 					ratr_bitmap &= 0x000ff005;
1935 			}
1936 		} else {
1937 			if (curtxbw_40mhz) {
1938 				if (rssi_level == 1)
1939 					ratr_bitmap &= 0x0f0f0000;
1940 				else if (rssi_level == 2)
1941 					ratr_bitmap &= 0x0f0ff000;
1942 				else
1943 					ratr_bitmap &= 0x0f0ff015;
1944 			} else {
1945 				if (rssi_level == 1)
1946 					ratr_bitmap &= 0x0f0f0000;
1947 				else if (rssi_level == 2)
1948 					ratr_bitmap &= 0x0f0ff000;
1949 				else
1950 					ratr_bitmap &= 0x0f0ff005;
1951 			}
1952 		}
1953 
1954 		if ((curtxbw_40mhz && curshortgi_40mhz) ||
1955 		    (!curtxbw_40mhz && curshortgi_20mhz)) {
1956 
1957 			if (macid == 0)
1958 				shortgi = true;
1959 			else if (macid == 1)
1960 				shortgi = false;
1961 		}
1962 		break;
1963 	default:
1964 		ratr_index = RATR_INX_WIRELESS_NGB;
1965 
1966 		if (rtlphy->rf_type == RF_1T2R)
1967 			ratr_bitmap &= 0x000ff0ff;
1968 		else
1969 			ratr_bitmap &= 0x0f0ff0ff;
1970 		break;
1971 	}
1972 	sta_entry->ratr_index = ratr_index;
1973 
1974 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1975 		"ratr_bitmap :%x\n", ratr_bitmap);
1976 	*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1977 				     (ratr_index << 28);
1978 	rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1979 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1980 		"Rate_index:%x, ratr_val:%x, %5phC\n",
1981 		ratr_index, ratr_bitmap, rate_mask);
1982 	rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1983 }
1984 
rtl92ce_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)1985 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1986 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1987 {
1988 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1989 
1990 	if (rtlpriv->dm.useramask)
1991 		rtl92ce_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
1992 	else
1993 		rtl92ce_update_hal_rate_table(hw, sta);
1994 }
1995 
rtl92ce_update_channel_access_setting(struct ieee80211_hw * hw)1996 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1997 {
1998 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1999 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2000 	u16 sifs_timer;
2001 
2002 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2003 				      &mac->slot_time);
2004 	if (!mac->ht_enable)
2005 		sifs_timer = 0x0a0a;
2006 	else
2007 		sifs_timer = 0x1010;
2008 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2009 }
2010 
rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2011 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2012 {
2013 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2014 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2015 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2016 	enum rf_pwrstate e_rfpowerstate_toset;
2017 	u8 u1tmp;
2018 	bool actuallyset = false;
2019 	unsigned long flag;
2020 
2021 	if (rtlpci->being_init_adapter)
2022 		return false;
2023 
2024 	if (ppsc->swrf_processing)
2025 		return false;
2026 
2027 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2028 	if (ppsc->rfchange_inprogress) {
2029 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2030 		return false;
2031 	} else {
2032 		ppsc->rfchange_inprogress = true;
2033 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2034 	}
2035 
2036 	rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2037 		       REG_MAC_PINMUX_CFG)&~(BIT(3)));
2038 
2039 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2040 	e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2041 
2042 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2043 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2044 			"GPIOChangeRF  - HW Radio ON, RF ON\n");
2045 
2046 		e_rfpowerstate_toset = ERFON;
2047 		ppsc->hwradiooff = false;
2048 		actuallyset = true;
2049 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2050 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2051 			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2052 
2053 		e_rfpowerstate_toset = ERFOFF;
2054 		ppsc->hwradiooff = true;
2055 		actuallyset = true;
2056 	}
2057 
2058 	if (actuallyset) {
2059 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2060 		ppsc->rfchange_inprogress = false;
2061 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2062 	} else {
2063 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2064 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2065 
2066 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2067 		ppsc->rfchange_inprogress = false;
2068 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2069 	}
2070 
2071 	*valid = 1;
2072 	return !ppsc->hwradiooff;
2073 
2074 }
2075 
rtl92ce_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2076 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2077 		     u8 *p_macaddr, bool is_group, u8 enc_algo,
2078 		     bool is_wepkey, bool clear_all)
2079 {
2080 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2081 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2082 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2083 	u8 *macaddr = p_macaddr;
2084 	u32 entry_id = 0;
2085 	bool is_pairwise = false;
2086 
2087 	static u8 cam_const_addr[4][6] = {
2088 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2089 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2090 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2091 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2092 	};
2093 	static u8 cam_const_broad[] = {
2094 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2095 	};
2096 
2097 	if (clear_all) {
2098 		u8 idx = 0;
2099 		u8 cam_offset = 0;
2100 		u8 clear_number = 5;
2101 
2102 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2103 
2104 		for (idx = 0; idx < clear_number; idx++) {
2105 			rtl_cam_mark_invalid(hw, cam_offset + idx);
2106 			rtl_cam_empty_entry(hw, cam_offset + idx);
2107 
2108 			if (idx < 5) {
2109 				memset(rtlpriv->sec.key_buf[idx], 0,
2110 				       MAX_KEY_LEN);
2111 				rtlpriv->sec.key_len[idx] = 0;
2112 			}
2113 		}
2114 
2115 	} else {
2116 		switch (enc_algo) {
2117 		case WEP40_ENCRYPTION:
2118 			enc_algo = CAM_WEP40;
2119 			break;
2120 		case WEP104_ENCRYPTION:
2121 			enc_algo = CAM_WEP104;
2122 			break;
2123 		case TKIP_ENCRYPTION:
2124 			enc_algo = CAM_TKIP;
2125 			break;
2126 		case AESCCMP_ENCRYPTION:
2127 			enc_algo = CAM_AES;
2128 			break;
2129 		default:
2130 			pr_err("switch case %#x not processed\n",
2131 			       enc_algo);
2132 			enc_algo = CAM_TKIP;
2133 			break;
2134 		}
2135 
2136 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2137 			macaddr = cam_const_addr[key_index];
2138 			entry_id = key_index;
2139 		} else {
2140 			if (is_group) {
2141 				macaddr = cam_const_broad;
2142 				entry_id = key_index;
2143 			} else {
2144 				if (mac->opmode == NL80211_IFTYPE_AP ||
2145 				    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2146 					entry_id = rtl_cam_get_free_entry(hw,
2147 								 p_macaddr);
2148 					if (entry_id >=  TOTAL_CAM_ENTRY) {
2149 						pr_err("Can not find free hw security cam entry\n");
2150 						return;
2151 					}
2152 				} else {
2153 					entry_id = CAM_PAIRWISE_KEY_POSITION;
2154 				}
2155 
2156 				key_index = PAIRWISE_KEYIDX;
2157 				is_pairwise = true;
2158 			}
2159 		}
2160 
2161 		if (rtlpriv->sec.key_len[key_index] == 0) {
2162 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2163 				"delete one entry, entry_id is %d\n",
2164 				 entry_id);
2165 			if (mac->opmode == NL80211_IFTYPE_AP ||
2166 			    mac->opmode == NL80211_IFTYPE_MESH_POINT)
2167 				rtl_cam_del_entry(hw, p_macaddr);
2168 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2169 		} else {
2170 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2171 				"The insert KEY length is %d\n",
2172 				rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2173 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2174 				"The insert KEY is %x %x\n",
2175 				rtlpriv->sec.key_buf[0][0],
2176 				rtlpriv->sec.key_buf[0][1]);
2177 
2178 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2179 				"add one entry\n");
2180 			if (is_pairwise) {
2181 				RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2182 					      "Pairwise Key content",
2183 					      rtlpriv->sec.pairwise_key,
2184 					      rtlpriv->sec.
2185 					      key_len[PAIRWISE_KEYIDX]);
2186 
2187 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2188 					"set Pairwise key\n");
2189 
2190 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2191 						      entry_id, enc_algo,
2192 						      CAM_CONFIG_NO_USEDK,
2193 						      rtlpriv->sec.
2194 						      key_buf[key_index]);
2195 			} else {
2196 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2197 					"set group key\n");
2198 
2199 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2200 					rtl_cam_add_one_entry(hw,
2201 						rtlefuse->dev_addr,
2202 						PAIRWISE_KEYIDX,
2203 						CAM_PAIRWISE_KEY_POSITION,
2204 						enc_algo,
2205 						CAM_CONFIG_NO_USEDK,
2206 						rtlpriv->sec.key_buf
2207 						[entry_id]);
2208 				}
2209 
2210 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2211 						entry_id, enc_algo,
2212 						CAM_CONFIG_NO_USEDK,
2213 						rtlpriv->sec.key_buf[entry_id]);
2214 			}
2215 
2216 		}
2217 	}
2218 }
2219 
rtl8192ce_bt_var_init(struct ieee80211_hw * hw)2220 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2221 {
2222 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2223 
2224 	rtlpriv->btcoexist.bt_coexistence =
2225 			rtlpriv->btcoexist.eeprom_bt_coexist;
2226 	rtlpriv->btcoexist.bt_ant_num =
2227 			rtlpriv->btcoexist.eeprom_bt_ant_num;
2228 	rtlpriv->btcoexist.bt_coexist_type =
2229 			rtlpriv->btcoexist.eeprom_bt_type;
2230 
2231 	if (rtlpriv->btcoexist.reg_bt_iso == 2)
2232 		rtlpriv->btcoexist.bt_ant_isolation =
2233 			rtlpriv->btcoexist.eeprom_bt_ant_isol;
2234 	else
2235 		rtlpriv->btcoexist.bt_ant_isolation =
2236 			rtlpriv->btcoexist.reg_bt_iso;
2237 
2238 	rtlpriv->btcoexist.bt_radio_shared_type =
2239 			rtlpriv->btcoexist.eeprom_bt_radio_shared;
2240 
2241 	if (rtlpriv->btcoexist.bt_coexistence) {
2242 		if (rtlpriv->btcoexist.reg_bt_sco == 1)
2243 			rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2244 		else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2245 			rtlpriv->btcoexist.bt_service = BT_SCO;
2246 		else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2247 			rtlpriv->btcoexist.bt_service = BT_BUSY;
2248 		else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2249 			rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2250 		else
2251 			rtlpriv->btcoexist.bt_service = BT_IDLE;
2252 
2253 		rtlpriv->btcoexist.bt_edca_ul = 0;
2254 		rtlpriv->btcoexist.bt_edca_dl = 0;
2255 		rtlpriv->btcoexist.bt_rssi_state = 0xff;
2256 	}
2257 }
2258 
rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)2259 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2260 					      bool auto_load_fail, u8 *hwinfo)
2261 {
2262 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2263 	u8 val;
2264 
2265 	if (!auto_load_fail) {
2266 		rtlpriv->btcoexist.eeprom_bt_coexist =
2267 					((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2268 		val = hwinfo[RF_OPTION4];
2269 		rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1);
2270 		rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1);
2271 		rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2272 		rtlpriv->btcoexist.eeprom_bt_radio_shared =
2273 							 ((val & 0x20) >> 5);
2274 	} else {
2275 		rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2276 		rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2277 		rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2278 		rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2279 		rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2280 	}
2281 
2282 	rtl8192ce_bt_var_init(hw);
2283 }
2284 
rtl8192ce_bt_reg_init(struct ieee80211_hw * hw)2285 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2286 {
2287 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2288 
2289 	/* 0:Low, 1:High, 2:From Efuse. */
2290 	rtlpriv->btcoexist.reg_bt_iso = 2;
2291 	/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2292 	rtlpriv->btcoexist.reg_bt_sco = 3;
2293 	/* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2294 	rtlpriv->btcoexist.reg_bt_sco = 0;
2295 }
2296 
rtl8192ce_bt_hw_init(struct ieee80211_hw * hw)2297 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2298 {
2299 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2300 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2301 
2302 	u8 u1_tmp;
2303 
2304 	if (rtlpriv->btcoexist.bt_coexistence &&
2305 	    ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2306 	      rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2307 
2308 		if (rtlpriv->btcoexist.bt_ant_isolation)
2309 			rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2310 
2311 		u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0);
2312 		u1_tmp = u1_tmp |
2313 			 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2314 			 0 : BIT(1)) |
2315 			 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2316 			 0 : BIT(2));
2317 		rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2318 
2319 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2320 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2321 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2322 
2323 		/* Config to 1T1R. */
2324 		if (rtlphy->rf_type == RF_1T1R) {
2325 			u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2326 			u1_tmp &= ~(BIT(1));
2327 			rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2328 
2329 			u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2330 			u1_tmp &= ~(BIT(1));
2331 			rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2332 		}
2333 	}
2334 }
2335 
rtl92ce_suspend(struct ieee80211_hw * hw)2336 void rtl92ce_suspend(struct ieee80211_hw *hw)
2337 {
2338 }
2339 
rtl92ce_resume(struct ieee80211_hw * hw)2340 void rtl92ce_resume(struct ieee80211_hw *hw)
2341 {
2342 }
2343