1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../pci.h"
7 #include "../base.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "dm.h"
12 #include "../rtl8192c/dm_common.h"
13 #include "../rtl8192c/fw_common.h"
14 #include "../rtl8192c/phy_common.h"
15 #include "hw.h"
16 #include "rf.h"
17 #include "trx.h"
18 #include "led.h"
19
20 #include <linux/module.h>
21
rtl92c_init_aspm_vars(struct ieee80211_hw * hw)22 static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)
23 {
24 struct rtl_priv *rtlpriv = rtl_priv(hw);
25 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
26
27 /*close ASPM for AMD defaultly */
28 rtlpci->const_amdpci_aspm = 0;
29
30 /*
31 * ASPM PS mode.
32 * 0 - Disable ASPM,
33 * 1 - Enable ASPM without Clock Req,
34 * 2 - Enable ASPM with Clock Req,
35 * 3 - Alwyas Enable ASPM with Clock Req,
36 * 4 - Always Enable ASPM without Clock Req.
37 * set defult to RTL8192CE:3 RTL8192E:2
38 * */
39 rtlpci->const_pci_aspm = 3;
40
41 /*Setting for PCI-E device */
42 rtlpci->const_devicepci_aspm_setting = 0x03;
43
44 /*Setting for PCI-E bridge */
45 rtlpci->const_hostpci_aspm_setting = 0x02;
46
47 /*
48 * In Hw/Sw Radio Off situation.
49 * 0 - Default,
50 * 1 - From ASPM setting without low Mac Pwr,
51 * 2 - From ASPM setting with low Mac Pwr,
52 * 3 - Bus D3
53 * set default to RTL8192CE:0 RTL8192SE:2
54 */
55 rtlpci->const_hwsw_rfoff_d3 = 0;
56
57 /*
58 * This setting works for those device with
59 * backdoor ASPM setting such as EPHY setting.
60 * 0 - Not support ASPM,
61 * 1 - Support ASPM,
62 * 2 - According to chipset.
63 */
64 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
65 }
66
rtl92c_init_sw_vars(struct ieee80211_hw * hw)67 static int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
68 {
69 int err;
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
73 char *fw_name;
74
75 rtl8192ce_bt_reg_init(hw);
76
77 rtlpriv->dm.dm_initialgain_enable = true;
78 rtlpriv->dm.dm_flag = 0;
79 rtlpriv->dm.disable_framebursting = false;
80 rtlpriv->dm.thermalvalue = 0;
81 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
82
83 /* compatible 5G band 88ce just 2.4G band & smsp */
84 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
85 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
86 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
87
88 rtlpci->receive_config = (RCR_APPFCS |
89 RCR_AMF |
90 RCR_ADF |
91 RCR_APP_MIC |
92 RCR_APP_ICV |
93 RCR_AICV |
94 RCR_ACRC32 |
95 RCR_AB |
96 RCR_AM |
97 RCR_APM |
98 RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
99
100 rtlpci->irq_mask[0] =
101 (u32) (IMR_ROK |
102 IMR_VODOK |
103 IMR_VIDOK |
104 IMR_BEDOK |
105 IMR_BKDOK |
106 IMR_MGNTDOK |
107 IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
108
109 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
110
111 /* for LPS & IPS */
112 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
113 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
114 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
115 if (!rtlpriv->psc.inactiveps)
116 pr_info("rtl8192ce: Power Save off (module option)\n");
117 if (!rtlpriv->psc.fwctrl_lps)
118 pr_info("rtl8192ce: FW Power Save off (module option)\n");
119 rtlpriv->psc.reg_fwctrl_lps = 3;
120 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
121 /* for ASPM, you can close aspm through
122 * set const_support_pciaspm = 0 */
123 rtl92c_init_aspm_vars(hw);
124
125 if (rtlpriv->psc.reg_fwctrl_lps == 1)
126 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
127 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
128 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
129 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
130 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
131
132 /* for firmware buf */
133 rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
134 if (!rtlpriv->rtlhal.pfirmware) {
135 pr_err("Can't alloc buffer for fw\n");
136 return 1;
137 }
138
139 /* request fw */
140 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
141 !IS_92C_SERIAL(rtlhal->version))
142 fw_name = "rtlwifi/rtl8192cfwU.bin";
143 else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
144 fw_name = "rtlwifi/rtl8192cfwU_B.bin";
145 else
146 fw_name = "rtlwifi/rtl8192cfw.bin";
147
148 rtlpriv->max_fw_size = 0x4000;
149 pr_info("Using firmware %s\n", fw_name);
150 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
151 rtlpriv->io.dev, GFP_KERNEL, hw,
152 rtl_fw_cb);
153 if (err) {
154 pr_err("Failed to request firmware!\n");
155 vfree(rtlpriv->rtlhal.pfirmware);
156 rtlpriv->rtlhal.pfirmware = NULL;
157 return 1;
158 }
159
160 return 0;
161 }
162
rtl92c_deinit_sw_vars(struct ieee80211_hw * hw)163 static void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
164 {
165 struct rtl_priv *rtlpriv = rtl_priv(hw);
166
167 if (rtlpriv->rtlhal.pfirmware) {
168 vfree(rtlpriv->rtlhal.pfirmware);
169 rtlpriv->rtlhal.pfirmware = NULL;
170 }
171 }
172
173 static struct rtl_hal_ops rtl8192ce_hal_ops = {
174 .init_sw_vars = rtl92c_init_sw_vars,
175 .deinit_sw_vars = rtl92c_deinit_sw_vars,
176 .read_eeprom_info = rtl92ce_read_eeprom_info,
177 .interrupt_recognized = rtl92ce_interrupt_recognized,
178 .hw_init = rtl92ce_hw_init,
179 .hw_disable = rtl92ce_card_disable,
180 .hw_suspend = rtl92ce_suspend,
181 .hw_resume = rtl92ce_resume,
182 .enable_interrupt = rtl92ce_enable_interrupt,
183 .disable_interrupt = rtl92ce_disable_interrupt,
184 .set_network_type = rtl92ce_set_network_type,
185 .set_chk_bssid = rtl92ce_set_check_bssid,
186 .set_qos = rtl92ce_set_qos,
187 .set_bcn_reg = rtl92ce_set_beacon_related_registers,
188 .set_bcn_intv = rtl92ce_set_beacon_interval,
189 .update_interrupt_mask = rtl92ce_update_interrupt_mask,
190 .get_hw_reg = rtl92ce_get_hw_reg,
191 .set_hw_reg = rtl92ce_set_hw_reg,
192 .update_rate_tbl = rtl92ce_update_hal_rate_tbl,
193 .fill_tx_desc = rtl92ce_tx_fill_desc,
194 .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
195 .query_rx_desc = rtl92ce_rx_query_desc,
196 .set_channel_access = rtl92ce_update_channel_access_setting,
197 .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
198 .set_bw_mode = rtl92c_phy_set_bw_mode,
199 .switch_channel = rtl92c_phy_sw_chnl,
200 .dm_watchdog = rtl92c_dm_watchdog,
201 .scan_operation_backup = rtl_phy_scan_operation_backup,
202 .set_rf_power_state = rtl92c_phy_set_rf_power_state,
203 .led_control = rtl92ce_led_control,
204 .set_desc = rtl92ce_set_desc,
205 .get_desc = rtl92ce_get_desc,
206 .is_tx_desc_closed = rtl92ce_is_tx_desc_closed,
207 .tx_polling = rtl92ce_tx_polling,
208 .enable_hw_sec = rtl92ce_enable_hw_security_config,
209 .set_key = rtl92ce_set_key,
210 .get_bbreg = rtl92c_phy_query_bb_reg,
211 .set_bbreg = rtl92c_phy_set_bb_reg,
212 .set_rfreg = rtl92ce_phy_set_rf_reg,
213 .get_rfreg = rtl92c_phy_query_rf_reg,
214 .phy_rf6052_config = rtl92ce_phy_rf6052_config,
215 .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,
216 .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,
217 .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,
218 .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,
219 .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,
220 .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,
221 .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,
222 .get_btc_status = rtl_btc_status_false,
223 };
224
225 static struct rtl_mod_params rtl92ce_mod_params = {
226 .sw_crypto = false,
227 .inactiveps = true,
228 .swctrl_lps = false,
229 .fwctrl_lps = true,
230 .aspm_support = 1,
231 .debug_level = 0,
232 .debug_mask = 0,
233 };
234
235 static const struct rtl_hal_cfg rtl92ce_hal_cfg = {
236 .bar_id = 2,
237 .write_readback = true,
238 .name = "rtl92c_pci",
239 .ops = &rtl8192ce_hal_ops,
240 .mod_params = &rtl92ce_mod_params,
241
242 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
243 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
244 .maps[SYS_CLK] = REG_SYS_CLKR,
245 .maps[MAC_RCR_AM] = AM,
246 .maps[MAC_RCR_AB] = AB,
247 .maps[MAC_RCR_ACRC32] = ACRC32,
248 .maps[MAC_RCR_ACF] = ACF,
249 .maps[MAC_RCR_AAP] = AAP,
250 .maps[MAC_HIMR] = REG_HIMR,
251 .maps[MAC_HIMRE] = REG_HIMRE,
252
253 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
254 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
255 .maps[EFUSE_CLK] = 0,
256 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
257 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
258 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
259 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
260 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
261 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
262 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
263 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
264 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
265
266 .maps[RWCAM] = REG_CAMCMD,
267 .maps[WCAMI] = REG_CAMWRITE,
268 .maps[RCAMO] = REG_CAMREAD,
269 .maps[CAMDBG] = REG_CAMDBG,
270 .maps[SECR] = REG_SECCFG,
271 .maps[SEC_CAM_NONE] = CAM_NONE,
272 .maps[SEC_CAM_WEP40] = CAM_WEP40,
273 .maps[SEC_CAM_TKIP] = CAM_TKIP,
274 .maps[SEC_CAM_AES] = CAM_AES,
275 .maps[SEC_CAM_WEP104] = CAM_WEP104,
276
277 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
278 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
279 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
280 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
281 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
282 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
283 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
284 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
285 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
286 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
287 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
288 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
289 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
290 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
291 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
292 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
293
294 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
295 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
296 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
297 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
298 .maps[RTL_IMR_RDU] = IMR_RDU,
299 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
300 .maps[RTL_IMR_BDOK] = IMR_BDOK,
301 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
302 .maps[RTL_IMR_TBDER] = IMR_TBDER,
303 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
304 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
305 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
306 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
307 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
308 .maps[RTL_IMR_VODOK] = IMR_VODOK,
309 .maps[RTL_IMR_ROK] = IMR_ROK,
310 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
311
312 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
313 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
314 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
315 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
316 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
317 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
318 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
319 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
320 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
321 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
322 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
323 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
324
325 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
326 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
327 };
328
329 static const struct pci_device_id rtl92ce_pci_ids[] = {
330 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
331 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
332 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
333 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
334 {},
335 };
336
337 MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
338
339 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
340 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
341 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
342 MODULE_LICENSE("GPL");
343 MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
344 MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");
345 MODULE_FIRMWARE("rtlwifi/rtl8192cfwU.bin");
346 MODULE_FIRMWARE("rtlwifi/rtl8192cfwU_B.bin");
347
348 module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
349 module_param_named(debug_level, rtl92ce_mod_params.debug_level, int, 0644);
350 module_param_named(debug_mask, rtl92ce_mod_params.debug_mask, ullong, 0644);
351 module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444);
352 module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444);
353 module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444);
354 module_param_named(aspm, rtl92ce_mod_params.aspm_support, int, 0444);
355 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
356 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
357 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
358 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
359 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
360 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
361 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
362
363 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
364
365 static struct pci_driver rtl92ce_driver = {
366 .name = KBUILD_MODNAME,
367 .id_table = rtl92ce_pci_ids,
368 .probe = rtl_pci_probe,
369 .remove = rtl_pci_disconnect,
370 .driver.pm = &rtlwifi_pm_ops,
371 };
372
373 module_pci_driver(rtl92ce_driver);
374