1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "../rtl8723com/phy_common.h"
15 #include "dm.h"
16 #include "../rtl8723com/dm_common.h"
17 #include "fw.h"
18 #include "../rtl8723com/fw_common.h"
19 #include "led.h"
20 #include "hw.h"
21 #include "../pwrseqcmd.h"
22 #include "pwrseq.h"
23 #include "../btcoexist/rtl_btc.h"
24 #include <linux/kernel.h>
25 
26 #define LLT_CONFIG	5
27 
_rtl8723be_return_beacon_queue_skb(struct ieee80211_hw * hw)28 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
29 {
30 	struct rtl_priv *rtlpriv = rtl_priv(hw);
31 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
32 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
33 	struct sk_buff_head free_list;
34 	unsigned long flags;
35 
36 	skb_queue_head_init(&free_list);
37 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
38 	while (skb_queue_len(&ring->queue)) {
39 		struct rtl_tx_desc *entry = &ring->desc[ring->idx];
40 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
41 
42 		dma_unmap_single(&rtlpci->pdev->dev,
43 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
44 						true, HW_DESC_TXBUFF_ADDR),
45 				 skb->len, DMA_TO_DEVICE);
46 		__skb_queue_tail(&free_list, skb);
47 		ring->idx = (ring->idx + 1) % ring->entries;
48 	}
49 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
50 
51 	__skb_queue_purge(&free_list);
52 }
53 
_rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)54 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
55 					u8 set_bits, u8 clear_bits)
56 {
57 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
58 	struct rtl_priv *rtlpriv = rtl_priv(hw);
59 
60 	rtlpci->reg_bcn_ctrl_val |= set_bits;
61 	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
62 
63 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
64 }
65 
_rtl8723be_stop_tx_beacon(struct ieee80211_hw * hw)66 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
67 {
68 	struct rtl_priv *rtlpriv = rtl_priv(hw);
69 	u8 tmp1byte;
70 
71 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
72 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
73 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
74 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
75 	tmp1byte &= ~(BIT(0));
76 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
77 }
78 
_rtl8723be_resume_tx_beacon(struct ieee80211_hw * hw)79 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
80 {
81 	struct rtl_priv *rtlpriv = rtl_priv(hw);
82 	u8 tmp1byte;
83 
84 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
85 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
86 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
87 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
88 	tmp1byte |= BIT(1);
89 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
90 }
91 
_rtl8723be_enable_bcn_sub_func(struct ieee80211_hw * hw)92 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
93 {
94 	_rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
95 }
96 
_rtl8723be_disable_bcn_sub_func(struct ieee80211_hw * hw)97 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
98 {
99 	_rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
100 }
101 
_rtl8723be_set_fw_clock_on(struct ieee80211_hw * hw,u8 rpwm_val,bool b_need_turn_off_ckk)102 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
103 				       bool b_need_turn_off_ckk)
104 {
105 	struct rtl_priv *rtlpriv = rtl_priv(hw);
106 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
107 	bool b_support_remote_wake_up;
108 	u32 count = 0, isr_regaddr, content;
109 	bool b_schedule_timer = b_need_turn_off_ckk;
110 	rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
111 				      (u8 *)(&b_support_remote_wake_up));
112 
113 	if (!rtlhal->fw_ready)
114 		return;
115 	if (!rtlpriv->psc.fw_current_inpsmode)
116 		return;
117 
118 	while (1) {
119 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
120 		if (rtlhal->fw_clk_change_in_progress) {
121 			while (rtlhal->fw_clk_change_in_progress) {
122 				spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
123 				count++;
124 				udelay(100);
125 				if (count > 1000)
126 					return;
127 				spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
128 			}
129 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
130 		} else {
131 			rtlhal->fw_clk_change_in_progress = false;
132 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
133 			break;
134 		}
135 	}
136 
137 	if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
138 		rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
139 					      (u8 *)(&rpwm_val));
140 		if (FW_PS_IS_ACK(rpwm_val)) {
141 			isr_regaddr = REG_HISR;
142 			content = rtl_read_dword(rtlpriv, isr_regaddr);
143 			while (!(content & IMR_CPWM) && (count < 500)) {
144 				udelay(50);
145 				count++;
146 				content = rtl_read_dword(rtlpriv, isr_regaddr);
147 			}
148 
149 			if (content & IMR_CPWM) {
150 				rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
151 				rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
152 				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
153 					"Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
154 					rtlhal->fw_ps_state);
155 			}
156 		}
157 
158 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
159 		rtlhal->fw_clk_change_in_progress = false;
160 		spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
161 		if (b_schedule_timer)
162 			mod_timer(&rtlpriv->works.fw_clockoff_timer,
163 				  jiffies + MSECS(10));
164 	} else  {
165 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
166 		rtlhal->fw_clk_change_in_progress = false;
167 		spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
168 	}
169 }
170 
_rtl8723be_set_fw_clock_off(struct ieee80211_hw * hw,u8 rpwm_val)171 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
172 {
173 	struct rtl_priv *rtlpriv = rtl_priv(hw);
174 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
175 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
176 	struct rtl8192_tx_ring *ring;
177 	enum rf_pwrstate rtstate;
178 	bool b_schedule_timer = false;
179 	u8 queue;
180 
181 	if (!rtlhal->fw_ready)
182 		return;
183 	if (!rtlpriv->psc.fw_current_inpsmode)
184 		return;
185 	if (!rtlhal->allow_sw_to_change_hwclc)
186 		return;
187 	rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
188 	if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
189 		return;
190 
191 	for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
192 		ring = &rtlpci->tx_ring[queue];
193 		if (skb_queue_len(&ring->queue)) {
194 			b_schedule_timer = true;
195 			break;
196 		}
197 	}
198 
199 	if (b_schedule_timer) {
200 		mod_timer(&rtlpriv->works.fw_clockoff_timer,
201 			  jiffies + MSECS(10));
202 		return;
203 	}
204 
205 	if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
206 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
207 		if (!rtlhal->fw_clk_change_in_progress) {
208 			rtlhal->fw_clk_change_in_progress = true;
209 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
210 			rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
211 			rtl_write_word(rtlpriv, REG_HISR, 0x0100);
212 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
213 						      (u8 *)(&rpwm_val));
214 			spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
215 			rtlhal->fw_clk_change_in_progress = false;
216 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
217 		} else {
218 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
219 			mod_timer(&rtlpriv->works.fw_clockoff_timer,
220 				  jiffies + MSECS(10));
221 		}
222 	}
223 
224 }
225 
_rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw * hw)226 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
227 {
228 	u8 rpwm_val = 0;
229 	rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
230 	_rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
231 }
232 
_rtl8723be_fwlps_leave(struct ieee80211_hw * hw)233 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
234 {
235 	struct rtl_priv *rtlpriv = rtl_priv(hw);
236 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
237 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
238 	bool fw_current_inps = false;
239 	u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
240 
241 	if (ppsc->low_power_enable) {
242 		rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
243 		_rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
244 		rtlhal->allow_sw_to_change_hwclc = false;
245 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
246 					      (u8 *)(&fw_pwrmode));
247 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
248 					      (u8 *)(&fw_current_inps));
249 	} else {
250 		rpwm_val = FW_PS_STATE_ALL_ON;	/* RF on */
251 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
252 					      (u8 *)(&rpwm_val));
253 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
254 					      (u8 *)(&fw_pwrmode));
255 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
256 					      (u8 *)(&fw_current_inps));
257 	}
258 
259 }
260 
_rtl8723be_fwlps_enter(struct ieee80211_hw * hw)261 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
262 {
263 	struct rtl_priv *rtlpriv = rtl_priv(hw);
264 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
265 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
266 	bool fw_current_inps = true;
267 	u8 rpwm_val;
268 
269 	if (ppsc->low_power_enable) {
270 		rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;	/* RF off */
271 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
272 					      (u8 *)(&fw_current_inps));
273 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
274 					      (u8 *)(&ppsc->fwctrl_psmode));
275 		rtlhal->allow_sw_to_change_hwclc = true;
276 		_rtl8723be_set_fw_clock_off(hw, rpwm_val);
277 	} else {
278 		rpwm_val = FW_PS_STATE_RF_OFF;	/* RF off */
279 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
280 					      (u8 *)(&fw_current_inps));
281 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
282 					      (u8 *)(&ppsc->fwctrl_psmode));
283 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
284 					      (u8 *)(&rpwm_val));
285 	}
286 
287 }
288 
rtl8723be_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)289 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
290 {
291 	struct rtl_priv *rtlpriv = rtl_priv(hw);
292 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
293 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
294 
295 	switch (variable) {
296 	case HW_VAR_RCR:
297 		*((u32 *)(val)) = rtlpci->receive_config;
298 		break;
299 	case HW_VAR_RF_STATE:
300 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
301 		break;
302 	case HW_VAR_FWLPS_RF_ON:{
303 		enum rf_pwrstate rfstate;
304 		u32 val_rcr;
305 
306 		rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
307 					      (u8 *)(&rfstate));
308 		if (rfstate == ERFOFF) {
309 			*((bool *)(val)) = true;
310 		} else {
311 			val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
312 			val_rcr &= 0x00070000;
313 			if (val_rcr)
314 				*((bool *)(val)) = false;
315 			else
316 				*((bool *)(val)) = true;
317 		}
318 		}
319 		break;
320 	case HW_VAR_FW_PSMODE_STATUS:
321 		*((bool *)(val)) = ppsc->fw_current_inpsmode;
322 		break;
323 	case HW_VAR_CORRECT_TSF:{
324 		u64 tsf;
325 		u32 *ptsf_low = (u32 *)&tsf;
326 		u32 *ptsf_high = ((u32 *)&tsf) + 1;
327 
328 		*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
329 		*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
330 
331 		*((u64 *)(val)) = tsf;
332 		}
333 		break;
334 	case HAL_DEF_WOWLAN:
335 		break;
336 	default:
337 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
338 			"switch case %#x not processed\n", variable);
339 		break;
340 	}
341 }
342 
_rtl8723be_download_rsvd_page(struct ieee80211_hw * hw)343 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
344 {
345 	struct rtl_priv *rtlpriv = rtl_priv(hw);
346 	u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
347 	u8 count = 0, dlbcn_count = 0;
348 	bool b_recover = false;
349 
350 	tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
351 	rtl_write_byte(rtlpriv, REG_CR + 1,
352 		       (tmp_regcr | BIT(0)));
353 
354 	_rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
355 	_rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
356 
357 	tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
358 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
359 	if (tmp_reg422 & BIT(6))
360 		b_recover = true;
361 
362 	do {
363 		bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
364 		rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
365 			       (bcnvalid_reg | BIT(0)));
366 		_rtl8723be_return_beacon_queue_skb(hw);
367 
368 		rtl8723be_set_fw_rsvdpagepkt(hw, 0);
369 		bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
370 		count = 0;
371 		while (!(bcnvalid_reg & BIT(0)) && count < 20) {
372 			count++;
373 			udelay(10);
374 			bcnvalid_reg = rtl_read_byte(rtlpriv,
375 						     REG_TDECTRL + 2);
376 		}
377 		dlbcn_count++;
378 	} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
379 
380 	if (bcnvalid_reg & BIT(0))
381 		rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
382 
383 	_rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
384 	_rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
385 
386 	if (b_recover)
387 		rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
388 
389 	tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
390 	rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
391 }
392 
rtl8723be_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)393 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
394 {
395 	struct rtl_priv *rtlpriv = rtl_priv(hw);
396 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
397 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
398 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
399 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
400 	u8 idx;
401 
402 	switch (variable) {
403 	case HW_VAR_ETHER_ADDR:
404 		for (idx = 0; idx < ETH_ALEN; idx++)
405 			rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
406 		break;
407 	case HW_VAR_BASIC_RATE:{
408 		u16 b_rate_cfg = ((u16 *)val)[0];
409 		u8 rate_index = 0;
410 		b_rate_cfg = b_rate_cfg & 0x15f;
411 		b_rate_cfg |= 0x01;
412 		rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
413 		rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
414 		while (b_rate_cfg > 0x1) {
415 			b_rate_cfg = (b_rate_cfg >> 1);
416 			rate_index++;
417 		}
418 		rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
419 		}
420 		break;
421 	case HW_VAR_BSSID:
422 		for (idx = 0; idx < ETH_ALEN; idx++)
423 			rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
424 
425 		break;
426 	case HW_VAR_SIFS:
427 		rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
428 		rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
429 
430 		rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
431 		rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
432 
433 		if (!mac->ht_enable)
434 			rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
435 		else
436 			rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
437 				       *((u16 *)val));
438 		break;
439 	case HW_VAR_SLOT_TIME:{
440 		u8 e_aci;
441 
442 		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
443 			"HW_VAR_SLOT_TIME %x\n", val[0]);
444 
445 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
446 
447 		for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
448 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
449 						      (u8 *)(&e_aci));
450 		}
451 		}
452 		break;
453 	case HW_VAR_ACK_PREAMBLE:{
454 		u8 reg_tmp;
455 		u8 short_preamble = (bool)(*(u8 *)val);
456 		reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
457 		if (short_preamble) {
458 			reg_tmp |= 0x02;
459 			rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
460 		} else {
461 			reg_tmp &= 0xFD;
462 			rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
463 		}
464 		}
465 		break;
466 	case HW_VAR_WPA_CONFIG:
467 		rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
468 		break;
469 	case HW_VAR_AMPDU_MIN_SPACE:{
470 		u8 min_spacing_to_set;
471 		u8 sec_min_space;
472 
473 		min_spacing_to_set = *((u8 *)val);
474 		if (min_spacing_to_set <= 7) {
475 			sec_min_space = 0;
476 
477 			if (min_spacing_to_set < sec_min_space)
478 				min_spacing_to_set = sec_min_space;
479 
480 			mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
481 					      min_spacing_to_set);
482 
483 			*val = min_spacing_to_set;
484 
485 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
486 				"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
487 				mac->min_space_cfg);
488 
489 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
490 				       mac->min_space_cfg);
491 		}
492 		}
493 		break;
494 	case HW_VAR_SHORTGI_DENSITY:{
495 		u8 density_to_set;
496 
497 		density_to_set = *((u8 *)val);
498 		mac->min_space_cfg |= (density_to_set << 3);
499 
500 		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
501 			"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
502 			mac->min_space_cfg);
503 
504 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
505 			       mac->min_space_cfg);
506 		}
507 		break;
508 	case HW_VAR_AMPDU_FACTOR:{
509 		u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
510 		u8 factor_toset;
511 		u8 *p_regtoset = NULL;
512 		u8 index = 0;
513 
514 		p_regtoset = regtoset_normal;
515 
516 		factor_toset = *((u8 *)val);
517 		if (factor_toset <= 3) {
518 			factor_toset = (1 << (factor_toset + 2));
519 			if (factor_toset > 0xf)
520 				factor_toset = 0xf;
521 
522 			for (index = 0; index < 4; index++) {
523 				if ((p_regtoset[index] & 0xf0) >
524 				    (factor_toset << 4))
525 					p_regtoset[index] =
526 						(p_regtoset[index] & 0x0f) |
527 						(factor_toset << 4);
528 
529 				if ((p_regtoset[index] & 0x0f) > factor_toset)
530 					p_regtoset[index] =
531 						(p_regtoset[index] & 0xf0) |
532 						(factor_toset);
533 
534 				rtl_write_byte(rtlpriv,
535 					       (REG_AGGLEN_LMT + index),
536 					       p_regtoset[index]);
537 
538 			}
539 
540 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
541 				"Set HW_VAR_AMPDU_FACTOR: %#x\n",
542 				factor_toset);
543 		}
544 		}
545 		break;
546 	case HW_VAR_AC_PARAM:{
547 		u8 e_aci = *((u8 *)val);
548 		rtl8723_dm_init_edca_turbo(hw);
549 
550 		if (rtlpci->acm_method != EACMWAY2_SW)
551 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
552 						      (u8 *)(&e_aci));
553 		}
554 		break;
555 	case HW_VAR_ACM_CTRL:{
556 		u8 e_aci = *((u8 *)val);
557 		union aci_aifsn *p_aci_aifsn =
558 				(union aci_aifsn *)(&(mac->ac[0].aifs));
559 		u8 acm = p_aci_aifsn->f.acm;
560 		u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
561 
562 		acm_ctrl =
563 		    acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
564 
565 		if (acm) {
566 			switch (e_aci) {
567 			case AC0_BE:
568 				acm_ctrl |= ACMHW_BEQEN;
569 				break;
570 			case AC2_VI:
571 				acm_ctrl |= ACMHW_VIQEN;
572 				break;
573 			case AC3_VO:
574 				acm_ctrl |= ACMHW_VOQEN;
575 				break;
576 			default:
577 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
578 					"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
579 					acm);
580 				break;
581 			}
582 		} else {
583 			switch (e_aci) {
584 			case AC0_BE:
585 				acm_ctrl &= (~ACMHW_BEQEN);
586 				break;
587 			case AC2_VI:
588 				acm_ctrl &= (~ACMHW_VIQEN);
589 				break;
590 			case AC3_VO:
591 				acm_ctrl &= (~ACMHW_VOQEN);
592 				break;
593 			default:
594 				rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
595 					"switch case %#x not processed\n",
596 					e_aci);
597 				break;
598 			}
599 		}
600 
601 		rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
602 			"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
603 			acm_ctrl);
604 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
605 		}
606 		break;
607 	case HW_VAR_RCR:
608 		rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
609 		rtlpci->receive_config = ((u32 *)(val))[0];
610 		break;
611 	case HW_VAR_RETRY_LIMIT:{
612 		u8 retry_limit = ((u8 *)(val))[0];
613 
614 		rtl_write_word(rtlpriv, REG_RL,
615 			       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
616 			       retry_limit << RETRY_LIMIT_LONG_SHIFT);
617 		}
618 		break;
619 	case HW_VAR_DUAL_TSF_RST:
620 		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
621 		break;
622 	case HW_VAR_EFUSE_BYTES:
623 		rtlefuse->efuse_usedbytes = *((u16 *)val);
624 		break;
625 	case HW_VAR_EFUSE_USAGE:
626 		rtlefuse->efuse_usedpercentage = *((u8 *)val);
627 		break;
628 	case HW_VAR_IO_CMD:
629 		rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
630 		break;
631 	case HW_VAR_SET_RPWM:{
632 		u8 rpwm_val;
633 
634 		rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
635 		udelay(1);
636 
637 		if (rpwm_val & BIT(7)) {
638 			rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
639 		} else {
640 			rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
641 				       ((*(u8 *)val) | BIT(7)));
642 		}
643 		}
644 		break;
645 	case HW_VAR_H2C_FW_PWRMODE:
646 		rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
647 		break;
648 	case HW_VAR_FW_PSMODE_STATUS:
649 		ppsc->fw_current_inpsmode = *((bool *)val);
650 		break;
651 	case HW_VAR_RESUME_CLK_ON:
652 		_rtl8723be_set_fw_ps_rf_on(hw);
653 		break;
654 	case HW_VAR_FW_LPS_ACTION:{
655 		bool b_enter_fwlps = *((bool *)val);
656 
657 		if (b_enter_fwlps)
658 			_rtl8723be_fwlps_enter(hw);
659 		else
660 			_rtl8723be_fwlps_leave(hw);
661 		}
662 		break;
663 	case HW_VAR_H2C_FW_JOINBSSRPT:{
664 		u8 mstatus = (*(u8 *)val);
665 
666 		if (mstatus == RT_MEDIA_CONNECT) {
667 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
668 			_rtl8723be_download_rsvd_page(hw);
669 		}
670 		rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
671 		}
672 		break;
673 	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
674 		rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
675 		break;
676 	case HW_VAR_AID:{
677 		u16 u2btmp;
678 		u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
679 		u2btmp &= 0xC000;
680 		rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
681 			       (u2btmp | mac->assoc_id));
682 		}
683 		break;
684 	case HW_VAR_CORRECT_TSF:{
685 		u8 btype_ibss = ((u8 *)(val))[0];
686 
687 		if (btype_ibss)
688 			_rtl8723be_stop_tx_beacon(hw);
689 
690 		_rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
691 
692 		rtl_write_dword(rtlpriv, REG_TSFTR,
693 				(u32) (mac->tsf & 0xffffffff));
694 		rtl_write_dword(rtlpriv, REG_TSFTR + 4,
695 				(u32) ((mac->tsf >> 32) & 0xffffffff));
696 
697 		_rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
698 
699 		if (btype_ibss)
700 			_rtl8723be_resume_tx_beacon(hw);
701 		}
702 		break;
703 	case HW_VAR_KEEP_ALIVE:{
704 		u8 array[2];
705 		array[0] = 0xff;
706 		array[1] = *((u8 *)val);
707 		rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
708 		}
709 		break;
710 	default:
711 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
712 			"switch case %#x not processed\n", variable);
713 		break;
714 	}
715 }
716 
_rtl8723be_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)717 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
718 {
719 	struct rtl_priv *rtlpriv = rtl_priv(hw);
720 	bool status = true;
721 	long count = 0;
722 	u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
723 		    _LLT_OP(_LLT_WRITE_ACCESS);
724 
725 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
726 
727 	do {
728 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
729 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
730 			break;
731 
732 		if (count > POLLING_LLT_THRESHOLD) {
733 			pr_err("Failed to polling write LLT done at address %d!\n",
734 			       address);
735 			status = false;
736 			break;
737 		}
738 	} while (++count);
739 
740 	return status;
741 }
742 
_rtl8723be_llt_table_init(struct ieee80211_hw * hw)743 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
744 {
745 	struct rtl_priv *rtlpriv = rtl_priv(hw);
746 	unsigned short i;
747 	u8 txpktbuf_bndy;
748 	u8 maxpage;
749 	bool status;
750 
751 	maxpage = 255;
752 	txpktbuf_bndy = 245;
753 
754 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
755 			(0x27FF0000 | txpktbuf_bndy));
756 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
757 
758 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
759 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
760 
761 	rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
762 	rtl_write_byte(rtlpriv, REG_PBP, 0x31);
763 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
764 
765 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
766 		status = _rtl8723be_llt_write(hw, i, i + 1);
767 		if (!status)
768 			return status;
769 	}
770 
771 	status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
772 
773 	if (!status)
774 		return status;
775 
776 	for (i = txpktbuf_bndy; i < maxpage; i++) {
777 		status = _rtl8723be_llt_write(hw, i, (i + 1));
778 		if (!status)
779 			return status;
780 	}
781 
782 	status = _rtl8723be_llt_write(hw, maxpage, txpktbuf_bndy);
783 	if (!status)
784 		return status;
785 
786 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
787 	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
788 
789 	return true;
790 }
791 
_rtl8723be_gen_refresh_led_state(struct ieee80211_hw * hw)792 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
793 {
794 	struct rtl_priv *rtlpriv = rtl_priv(hw);
795 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
796 	enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
797 
798 	if (rtlpriv->rtlhal.up_first_time)
799 		return;
800 
801 	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
802 		rtl8723be_sw_led_on(hw, pin0);
803 	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
804 		rtl8723be_sw_led_on(hw, pin0);
805 	else
806 		rtl8723be_sw_led_off(hw, pin0);
807 }
808 
_rtl8723be_init_mac(struct ieee80211_hw * hw)809 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
810 {
811 	struct rtl_priv *rtlpriv = rtl_priv(hw);
812 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
813 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
814 	unsigned char bytetmp;
815 	unsigned short wordtmp;
816 
817 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
818 
819 	/*Auto Power Down to CHIP-off State*/
820 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
821 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
822 
823 	/* HW Power on sequence */
824 	if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
825 				      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
826 				      RTL8723_NIC_ENABLE_FLOW)) {
827 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
828 			"init MAC Fail as power on failure\n");
829 		return false;
830 	}
831 
832 	if (rtlpriv->cfg->ops->get_btc_status())
833 		rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
834 
835 	bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
836 	rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
837 
838 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
839 	rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
840 
841 	bytetmp = rtl_read_byte(rtlpriv, REG_CR);
842 	bytetmp = 0xff;
843 	rtl_write_byte(rtlpriv, REG_CR, bytetmp);
844 	mdelay(2);
845 
846 	bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
847 	bytetmp |= 0x7f;
848 	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
849 	mdelay(2);
850 
851 	bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
852 	if (bytetmp & BIT(0)) {
853 		bytetmp = rtl_read_byte(rtlpriv, 0x7c);
854 		rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
855 	}
856 
857 	bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
858 	rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
859 	bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
860 	rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
861 
862 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
863 
864 	if (!rtlhal->mac_func_enable) {
865 		if (!_rtl8723be_llt_table_init(hw))
866 			return false;
867 	}
868 
869 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
870 	rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
871 
872 	/* Enable FW Beamformer Interrupt */
873 	bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
874 	rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
875 
876 	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
877 	wordtmp &= 0xf;
878 	wordtmp |= 0xF5B1;
879 	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
880 
881 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
882 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
883 	rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
884 	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
885 
886 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
887 			((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
888 			DMA_BIT_MASK(32));
889 	rtl_write_dword(rtlpriv, REG_MGQ_DESA,
890 			(u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
891 			DMA_BIT_MASK(32));
892 	rtl_write_dword(rtlpriv, REG_VOQ_DESA,
893 			(u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
894 	rtl_write_dword(rtlpriv, REG_VIQ_DESA,
895 			(u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
896 	rtl_write_dword(rtlpriv, REG_BEQ_DESA,
897 			(u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
898 	rtl_write_dword(rtlpriv, REG_BKQ_DESA,
899 			(u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
900 	rtl_write_dword(rtlpriv, REG_HQ_DESA,
901 			(u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
902 			DMA_BIT_MASK(32));
903 	rtl_write_dword(rtlpriv, REG_RX_DESA,
904 			(u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
905 			DMA_BIT_MASK(32));
906 
907 	bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
908 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
909 
910 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
911 
912 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
913 
914 	rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
915 
916 	/* <20130114, Kordan> The following setting is
917 	 * only for DPDT and Fixed board type.
918 	 * TODO:  A better solution is configure it
919 	 * according EFUSE during the run-time.
920 	 */
921 	rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
922 	rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
923 	rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
924 	rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
925 	rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
926 	rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
927 	rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
928 	rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
929 
930 	bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
931 	rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
932 
933 	_rtl8723be_gen_refresh_led_state(hw);
934 	return true;
935 }
936 
_rtl8723be_hw_configure(struct ieee80211_hw * hw)937 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
938 {
939 	struct rtl_priv *rtlpriv = rtl_priv(hw);
940 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
941 	u32 reg_rrsr;
942 
943 	reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
944 	/* Init value for RRSR. */
945 	rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
946 
947 	/* ARFB table 9 for 11ac 5G 2SS */
948 	rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
949 
950 	/* ARFB table 10 for 11ac 5G 1SS */
951 	rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
952 
953 	/* CF-End setting. */
954 	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
955 
956 	/* 0x456 = 0x70, sugguested by Zhilin */
957 	rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
958 
959 	/* Set retry limit */
960 	rtl_write_word(rtlpriv, REG_RL, 0x0707);
961 
962 	/* Set Data / Response auto rate fallack retry count */
963 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
964 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
965 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
966 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
967 
968 	rtlpci->reg_bcn_ctrl_val = 0x1d;
969 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
970 
971 	/* TBTT prohibit hold time. Suggested by designer TimChen. */
972 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
973 
974 	rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
975 
976 	/*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
977 	rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
978 
979 	rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
980 
981 	rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
982 
983 	rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
984 }
985 
_rtl8723be_dbi_read(struct rtl_priv * rtlpriv,u16 addr)986 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
987 {
988 	u16 read_addr = addr & 0xfffc;
989 	u8 ret = 0, tmp = 0, count = 0;
990 
991 	rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
992 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
993 	tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
994 	count = 0;
995 	while (tmp && count < 20) {
996 		udelay(10);
997 		tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
998 		count++;
999 	}
1000 	if (0 == tmp) {
1001 		read_addr = REG_DBI_RDATA + addr % 4;
1002 		ret = rtl_read_byte(rtlpriv, read_addr);
1003 	}
1004 
1005 	return ret;
1006 }
1007 
_rtl8723be_dbi_write(struct rtl_priv * rtlpriv,u16 addr,u8 data)1008 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1009 {
1010 	u8 tmp = 0, count = 0;
1011 	u16 write_addr = 0, remainder = addr % 4;
1012 
1013 	/* Write DBI 1Byte Data */
1014 	write_addr = REG_DBI_WDATA + remainder;
1015 	rtl_write_byte(rtlpriv, write_addr, data);
1016 
1017 	/* Write DBI 2Byte Address & Write Enable */
1018 	write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1019 	rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1020 
1021 	/* Write DBI Write Flag */
1022 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1023 
1024 	tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1025 	count = 0;
1026 	while (tmp && count < 20) {
1027 		udelay(10);
1028 		tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1029 		count++;
1030 	}
1031 }
1032 
_rtl8723be_mdio_read(struct rtl_priv * rtlpriv,u8 addr)1033 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1034 {
1035 	u16 ret = 0;
1036 	u8 tmp = 0, count = 0;
1037 
1038 	rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1039 	tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1040 	count = 0;
1041 	while (tmp && count < 20) {
1042 		udelay(10);
1043 		tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1044 		count++;
1045 	}
1046 
1047 	if (0 == tmp)
1048 		ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1049 
1050 	return ret;
1051 }
1052 
_rtl8723be_mdio_write(struct rtl_priv * rtlpriv,u8 addr,u16 data)1053 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1054 {
1055 	u8 tmp = 0, count = 0;
1056 
1057 	rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1058 	rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1059 	tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1060 	count = 0;
1061 	while (tmp && count < 20) {
1062 		udelay(10);
1063 		tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1064 		count++;
1065 	}
1066 }
1067 
_rtl8723be_enable_aspm_back_door(struct ieee80211_hw * hw)1068 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1069 {
1070 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1071 	u8 tmp8 = 0;
1072 	u16 tmp16 = 0;
1073 
1074 	/* <Roger_Notes> Overwrite following ePHY parameter for
1075 	 * some platform compatibility issue,
1076 	 * especially when CLKReq is enabled, 2012.11.09.
1077 	 */
1078 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1079 	if (tmp16 != 0x0663)
1080 		_rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1081 
1082 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1083 	if (tmp16 != 0x7544)
1084 		_rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1085 
1086 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1087 	if (tmp16 != 0xB880)
1088 		_rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1089 
1090 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1091 	if (tmp16 != 0x4000)
1092 		_rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1093 
1094 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1095 	if (tmp16 != 0x9003)
1096 		_rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1097 
1098 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1099 	if (tmp16 != 0x0D03)
1100 		_rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1101 
1102 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1103 	if (tmp16 != 0x4037)
1104 		_rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1105 
1106 	tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1107 	if (tmp16 != 0x0070)
1108 		_rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1109 
1110 	/* Configuration Space offset 0x70f BIT7 is used to control L0S */
1111 	tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1112 	_rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
1113 			     ASPM_L1_LATENCY << 3);
1114 
1115 	/* Configuration Space offset 0x719 Bit3 is for L1
1116 	 * BIT4 is for clock request
1117 	 */
1118 	tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1119 	_rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1120 }
1121 
rtl8723be_enable_hw_security_config(struct ieee80211_hw * hw)1122 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1123 {
1124 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1125 	u8 sec_reg_value;
1126 
1127 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1128 		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1129 		rtlpriv->sec.pairwise_enc_algorithm,
1130 		rtlpriv->sec.group_enc_algorithm);
1131 
1132 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1133 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1134 			"not open hw encryption\n");
1135 		return;
1136 	}
1137 
1138 	sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1139 
1140 	if (rtlpriv->sec.use_defaultkey) {
1141 		sec_reg_value |= SCR_TXUSEDK;
1142 		sec_reg_value |= SCR_RXUSEDK;
1143 	}
1144 
1145 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1146 
1147 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1148 
1149 	rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1150 		"The SECR-value %x\n", sec_reg_value);
1151 
1152 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1153 }
1154 
_rtl8723be_poweroff_adapter(struct ieee80211_hw * hw)1155 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1156 {
1157 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1158 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1159 	u8 u1b_tmp;
1160 
1161 	rtlhal->mac_func_enable = false;
1162 	/* Combo (PCIe + USB) Card and PCIe-MF Card */
1163 	/* 1. Run LPS WL RFOFF flow */
1164 	rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1165 				 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1166 
1167 	/* 2. 0x1F[7:0] = 0 */
1168 	/* turn off RF */
1169 	/* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1170 	if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1171 	    rtlhal->fw_ready) {
1172 		rtl8723be_firmware_selfreset(hw);
1173 	}
1174 
1175 	/* Reset MCU. Suggested by Filen. */
1176 	u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1177 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1178 
1179 	/* g.	MCUFWDL 0x80[1:0]=0	 */
1180 	/* reset MCU ready status */
1181 	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1182 
1183 	/* HW card disable configuration. */
1184 	rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1185 				 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1186 
1187 	/* Reset MCU IO Wrapper */
1188 	u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1189 	rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1190 	u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1191 	rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1192 
1193 	/* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1194 	/* lock ISO/CLK/Power control register */
1195 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1196 }
1197 
_rtl8723be_check_pcie_dma_hang(struct rtl_priv * rtlpriv)1198 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1199 {
1200 	u8 tmp;
1201 
1202 	/* write reg 0x350 Bit[26]=1. Enable debug port. */
1203 	tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1204 	if (!(tmp & BIT(2))) {
1205 		rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1206 		mdelay(100); /* Suggested by DD Justin_tsai. */
1207 	}
1208 
1209 	/* read reg 0x350 Bit[25] if 1 : RX hang
1210 	 * read reg 0x350 Bit[24] if 1 : TX hang
1211 	 */
1212 	tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1213 	if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1214 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1215 			"CheckPcieDMAHang8723BE(): true!!\n");
1216 		return true;
1217 	}
1218 	return false;
1219 }
1220 
_rtl8723be_reset_pcie_interface_dma(struct rtl_priv * rtlpriv,bool mac_power_on)1221 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1222 						bool mac_power_on)
1223 {
1224 	u8 tmp;
1225 	bool release_mac_rx_pause;
1226 	u8 backup_pcie_dma_pause;
1227 
1228 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1229 		"ResetPcieInterfaceDMA8723BE()\n");
1230 
1231 	/* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1232 	 * released by SD1 Alan.
1233 	 * 2013.05.07, by tynli.
1234 	 */
1235 
1236 	/* 1. disable register write lock
1237 	 *	write 0x1C bit[1:0] = 2'h0
1238 	 *	write 0xCC bit[2] = 1'b1
1239 	 */
1240 	tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1241 	tmp &= ~(BIT(1) | BIT(0));
1242 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1243 	tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1244 	tmp |= BIT(2);
1245 	rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1246 
1247 	/* 2. Check and pause TRX DMA
1248 	 *	write 0x284 bit[18] = 1'b1
1249 	 *	write 0x301 = 0xFF
1250 	 */
1251 	tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1252 	if (tmp & BIT(2)) {
1253 		/* Already pause before the function for another purpose. */
1254 		release_mac_rx_pause = false;
1255 	} else {
1256 		rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1257 		release_mac_rx_pause = true;
1258 	}
1259 
1260 	backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1261 	if (backup_pcie_dma_pause != 0xFF)
1262 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1263 
1264 	if (mac_power_on) {
1265 		/* 3. reset TRX function
1266 		 *	write 0x100 = 0x00
1267 		 */
1268 		rtl_write_byte(rtlpriv, REG_CR, 0);
1269 	}
1270 
1271 	/* 4. Reset PCIe DMA
1272 	 *	write 0x003 bit[0] = 0
1273 	 */
1274 	tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1275 	tmp &= ~(BIT(0));
1276 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1277 
1278 	/* 5. Enable PCIe DMA
1279 	 *	write 0x003 bit[0] = 1
1280 	 */
1281 	tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1282 	tmp |= BIT(0);
1283 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1284 
1285 	if (mac_power_on) {
1286 		/* 6. enable TRX function
1287 		 *	write 0x100 = 0xFF
1288 		 */
1289 		rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1290 
1291 		/* We should init LLT & RQPN and
1292 		 * prepare Tx/Rx descrptor address later
1293 		 * because MAC function is reset.
1294 		 */
1295 	}
1296 
1297 	/* 7. Restore PCIe autoload down bit
1298 	 *	write 0xF8 bit[17] = 1'b1
1299 	 */
1300 	tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1301 	tmp |= BIT(1);
1302 	rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1303 
1304 	/* In MAC power on state, BB and RF maybe in ON state,
1305 	 * if we release TRx DMA here
1306 	 * it will cause packets to be started to Tx/Rx,
1307 	 * so we release Tx/Rx DMA later.
1308 	 */
1309 	if (!mac_power_on) {
1310 		/* 8. release TRX DMA
1311 		 *	write 0x284 bit[18] = 1'b0
1312 		 *	write 0x301 = 0x00
1313 		 */
1314 		if (release_mac_rx_pause) {
1315 			tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1316 			rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1317 				       (tmp & (~BIT(2))));
1318 		}
1319 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1320 			       backup_pcie_dma_pause);
1321 	}
1322 
1323 	/* 9. lock system register
1324 	 *	write 0xCC bit[2] = 1'b0
1325 	 */
1326 	tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1327 	tmp &= ~(BIT(2));
1328 	rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1329 }
1330 
rtl8723be_hw_init(struct ieee80211_hw * hw)1331 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1332 {
1333 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1334 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1335 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1336 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1337 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1338 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1339 	bool rtstatus = true;
1340 	int err;
1341 	u8 tmp_u1b;
1342 	unsigned long flags;
1343 
1344 	/* reenable interrupts to not interfere with other devices */
1345 	local_save_flags(flags);
1346 	local_irq_enable();
1347 
1348 	rtlhal->fw_ready = false;
1349 	rtlpriv->rtlhal.being_init_adapter = true;
1350 	rtlpriv->intf_ops->disable_aspm(hw);
1351 
1352 	tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1353 	if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1354 		rtlhal->mac_func_enable = true;
1355 	} else {
1356 		rtlhal->mac_func_enable = false;
1357 		rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1358 	}
1359 
1360 	if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1361 		_rtl8723be_reset_pcie_interface_dma(rtlpriv,
1362 						    rtlhal->mac_func_enable);
1363 		rtlhal->mac_func_enable = false;
1364 	}
1365 	if (rtlhal->mac_func_enable) {
1366 		_rtl8723be_poweroff_adapter(hw);
1367 		rtlhal->mac_func_enable = false;
1368 	}
1369 	rtstatus = _rtl8723be_init_mac(hw);
1370 	if (!rtstatus) {
1371 		pr_err("Init MAC failed\n");
1372 		err = 1;
1373 		goto exit;
1374 	}
1375 
1376 	tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1377 	rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1378 
1379 	err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1380 	if (err) {
1381 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1382 			"Failed to download FW. Init HW without FW now..\n");
1383 		err = 1;
1384 		goto exit;
1385 	}
1386 	rtlhal->fw_ready = true;
1387 
1388 	rtlhal->last_hmeboxnum = 0;
1389 	rtl8723be_phy_mac_config(hw);
1390 	/* because last function modify RCR, so we update
1391 	 * rcr var here, or TP will unstable for receive_config
1392 	 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1393 	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1394 	 */
1395 	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1396 	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1397 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1398 
1399 	rtl8723be_phy_bb_config(hw);
1400 	rtl8723be_phy_rf_config(hw);
1401 
1402 	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1403 						 RF_CHNLBW, RFREG_OFFSET_MASK);
1404 	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1405 						 RF_CHNLBW, RFREG_OFFSET_MASK);
1406 	rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1407 	rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1408 
1409 	_rtl8723be_hw_configure(hw);
1410 	rtlhal->mac_func_enable = true;
1411 	rtl_cam_reset_all_entry(hw);
1412 	rtl8723be_enable_hw_security_config(hw);
1413 
1414 	ppsc->rfpwr_state = ERFON;
1415 
1416 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1417 	_rtl8723be_enable_aspm_back_door(hw);
1418 	rtlpriv->intf_ops->enable_aspm(hw);
1419 
1420 	rtl8723be_bt_hw_init(hw);
1421 
1422 	if (ppsc->rfpwr_state == ERFON) {
1423 		rtl8723be_phy_set_rfpath_switch(hw, 1);
1424 		/* when use 1ant NIC, iqk will disturb BT music
1425 		 * root cause is not clear now, is something
1426 		 * related with 'mdelay' and Reg[0x948]
1427 		 */
1428 		if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1429 		    !rtlpriv->cfg->ops->get_btc_status()) {
1430 			rtl8723be_phy_iq_calibrate(hw,
1431 						   (rtlphy->iqk_initialized ?
1432 						    true : false));
1433 			rtlphy->iqk_initialized = true;
1434 		}
1435 		rtl8723be_dm_check_txpower_tracking(hw);
1436 		rtl8723be_phy_lc_calibrate(hw);
1437 	}
1438 	rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1439 
1440 	/* Release Rx DMA. */
1441 	tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1442 	if (tmp_u1b & BIT(2)) {
1443 		/* Release Rx DMA if needed */
1444 		tmp_u1b &= (~BIT(2));
1445 		rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1446 	}
1447 	/* Release Tx/Rx PCIE DMA. */
1448 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1449 
1450 	rtl8723be_dm_init(hw);
1451 exit:
1452 	local_irq_restore(flags);
1453 	rtlpriv->rtlhal.being_init_adapter = false;
1454 	return err;
1455 }
1456 
_rtl8723be_read_chip_version(struct ieee80211_hw * hw)1457 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1458 {
1459 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1460 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1461 	enum version_8723e version = VERSION_UNKNOWN;
1462 	u32 value32;
1463 
1464 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1465 	if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1466 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
1467 	else
1468 		version = (enum version_8723e)CHIP_8723B;
1469 
1470 	rtlphy->rf_type = RF_1T1R;
1471 
1472 	/* treat rtl8723be chip as  MP version in default */
1473 	version = (enum version_8723e)(version | NORMAL_CHIP);
1474 
1475 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1476 	/* cut version */
1477 	version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1478 	/* Manufacture */
1479 	if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1480 		version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1481 
1482 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1483 		"Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1484 		"RF_2T2R" : "RF_1T1R");
1485 
1486 	return version;
1487 }
1488 
_rtl8723be_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1489 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1490 				       enum nl80211_iftype type)
1491 {
1492 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1493 	u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1494 	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1495 	u8 mode = MSR_NOLINK;
1496 
1497 	switch (type) {
1498 	case NL80211_IFTYPE_UNSPECIFIED:
1499 		mode = MSR_NOLINK;
1500 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1501 			"Set Network type to NO LINK!\n");
1502 		break;
1503 	case NL80211_IFTYPE_ADHOC:
1504 	case NL80211_IFTYPE_MESH_POINT:
1505 		mode = MSR_ADHOC;
1506 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1507 			"Set Network type to Ad Hoc!\n");
1508 		break;
1509 	case NL80211_IFTYPE_STATION:
1510 		mode = MSR_INFRA;
1511 		ledaction = LED_CTL_LINK;
1512 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1513 			"Set Network type to STA!\n");
1514 		break;
1515 	case NL80211_IFTYPE_AP:
1516 		mode = MSR_AP;
1517 		ledaction = LED_CTL_LINK;
1518 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1519 			"Set Network type to AP!\n");
1520 		break;
1521 	default:
1522 		pr_err("Network type %d not support!\n", type);
1523 		return 1;
1524 	}
1525 
1526 	/* MSR_INFRA == Link in infrastructure network;
1527 	 * MSR_ADHOC == Link in ad hoc network;
1528 	 * Therefore, check link state is necessary.
1529 	 *
1530 	 * MSR_AP == AP mode; link state is not cared here.
1531 	 */
1532 	if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1533 		mode = MSR_NOLINK;
1534 		ledaction = LED_CTL_NO_LINK;
1535 	}
1536 
1537 	if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1538 		_rtl8723be_stop_tx_beacon(hw);
1539 		_rtl8723be_enable_bcn_sub_func(hw);
1540 	} else if (mode == MSR_ADHOC || mode == MSR_AP) {
1541 		_rtl8723be_resume_tx_beacon(hw);
1542 		_rtl8723be_disable_bcn_sub_func(hw);
1543 	} else {
1544 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1545 			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1546 			mode);
1547 	}
1548 
1549 	rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1550 	rtlpriv->cfg->ops->led_control(hw, ledaction);
1551 	if (mode == MSR_AP)
1552 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1553 	else
1554 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1555 	return 0;
1556 }
1557 
rtl8723be_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1558 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1559 {
1560 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1561 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1562 	u32 reg_rcr = rtlpci->receive_config;
1563 
1564 	if (rtlpriv->psc.rfpwr_state != ERFON)
1565 		return;
1566 
1567 	if (check_bssid) {
1568 		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1569 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1570 					      (u8 *)(&reg_rcr));
1571 		_rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1572 	} else if (!check_bssid) {
1573 		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1574 		_rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1575 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1576 					      (u8 *)(&reg_rcr));
1577 	}
1578 
1579 }
1580 
rtl8723be_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1581 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1582 			       enum nl80211_iftype type)
1583 {
1584 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1585 
1586 	if (_rtl8723be_set_media_status(hw, type))
1587 		return -EOPNOTSUPP;
1588 
1589 	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1590 		if (type != NL80211_IFTYPE_AP)
1591 			rtl8723be_set_check_bssid(hw, true);
1592 	} else {
1593 		rtl8723be_set_check_bssid(hw, false);
1594 	}
1595 
1596 	return 0;
1597 }
1598 
1599 /* don't set REG_EDCA_BE_PARAM here
1600  * because mac80211 will send pkt when scan
1601  */
rtl8723be_set_qos(struct ieee80211_hw * hw,int aci)1602 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1603 {
1604 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1605 
1606 	rtl8723_dm_init_edca_turbo(hw);
1607 	switch (aci) {
1608 	case AC1_BK:
1609 		rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1610 		break;
1611 	case AC0_BE:
1612 		break;
1613 	case AC2_VI:
1614 		rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1615 		break;
1616 	case AC3_VO:
1617 		rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1618 		break;
1619 	default:
1620 		WARN_ONCE(true, "rtl8723be: invalid aci: %d !\n", aci);
1621 		break;
1622 	}
1623 }
1624 
rtl8723be_enable_interrupt(struct ieee80211_hw * hw)1625 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1626 {
1627 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1628 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1629 
1630 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1631 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1632 	rtlpci->irq_enabled = true;
1633 
1634 	/*enable system interrupt*/
1635 	rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1636 }
1637 
rtl8723be_disable_interrupt(struct ieee80211_hw * hw)1638 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1639 {
1640 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1641 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1642 
1643 	rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1644 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1645 	rtlpci->irq_enabled = false;
1646 	/*synchronize_irq(rtlpci->pdev->irq);*/
1647 }
1648 
rtl8723be_card_disable(struct ieee80211_hw * hw)1649 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1650 {
1651 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1652 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1653 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1654 	enum nl80211_iftype opmode;
1655 
1656 	mac->link_state = MAC80211_NOLINK;
1657 	opmode = NL80211_IFTYPE_UNSPECIFIED;
1658 	_rtl8723be_set_media_status(hw, opmode);
1659 	if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1660 	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1661 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1662 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1663 	_rtl8723be_poweroff_adapter(hw);
1664 
1665 	/* after power off we should do iqk again */
1666 	if (!rtlpriv->cfg->ops->get_btc_status())
1667 		rtlpriv->phy.iqk_initialized = false;
1668 }
1669 
rtl8723be_interrupt_recognized(struct ieee80211_hw * hw,struct rtl_int * intvec)1670 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1671 				    struct rtl_int *intvec)
1672 {
1673 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1674 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1675 
1676 	intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1677 	rtl_write_dword(rtlpriv, ISR, intvec->inta);
1678 
1679 	intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1680 				      rtlpci->irq_mask[1];
1681 	rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
1682 }
1683 
rtl8723be_set_beacon_related_registers(struct ieee80211_hw * hw)1684 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1685 {
1686 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1687 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1688 	u16 bcn_interval, atim_window;
1689 
1690 	bcn_interval = mac->beacon_interval;
1691 	atim_window = 2;	/*FIX MERGE */
1692 	rtl8723be_disable_interrupt(hw);
1693 	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1694 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1695 	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1696 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1697 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1698 	rtl_write_byte(rtlpriv, 0x606, 0x30);
1699 	rtl8723be_enable_interrupt(hw);
1700 }
1701 
rtl8723be_set_beacon_interval(struct ieee80211_hw * hw)1702 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1703 {
1704 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1705 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1706 	u16 bcn_interval = mac->beacon_interval;
1707 
1708 	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1709 		"beacon_interval:%d\n", bcn_interval);
1710 	rtl8723be_disable_interrupt(hw);
1711 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1712 	rtl8723be_enable_interrupt(hw);
1713 }
1714 
rtl8723be_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1715 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1716 				   u32 add_msr, u32 rm_msr)
1717 {
1718 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1719 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1720 
1721 	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1722 		"add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1723 
1724 	if (add_msr)
1725 		rtlpci->irq_mask[0] |= add_msr;
1726 	if (rm_msr)
1727 		rtlpci->irq_mask[0] &= (~rm_msr);
1728 	rtl8723be_disable_interrupt(hw);
1729 	rtl8723be_enable_interrupt(hw);
1730 }
1731 
_rtl8723be_get_chnl_group(u8 chnl)1732 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1733 {
1734 	u8 group;
1735 
1736 	if (chnl < 3)
1737 		group = 0;
1738 	else if (chnl < 9)
1739 		group = 1;
1740 	else
1741 		group = 2;
1742 	return group;
1743 }
1744 
_rtl8723be_read_power_value_fromprom(struct ieee80211_hw * hw,struct txpower_info_2g * pw2g,struct txpower_info_5g * pw5g,bool autoload_fail,u8 * hwinfo)1745 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1746 					struct txpower_info_2g *pw2g,
1747 					struct txpower_info_5g *pw5g,
1748 					bool autoload_fail, u8 *hwinfo)
1749 {
1750 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1751 	u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1752 
1753 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1754 		"hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1755 		(addr + 1), hwinfo[addr + 1]);
1756 	if (0xFF == hwinfo[addr + 1])  /*YJ,add,120316*/
1757 		autoload_fail = true;
1758 
1759 	if (autoload_fail) {
1760 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1761 			"auto load fail : Use Default value!\n");
1762 		for (path = 0; path < MAX_RF_PATH; path++) {
1763 			/* 2.4G default value */
1764 			for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1765 				pw2g->index_cck_base[path][group] = 0x2D;
1766 				pw2g->index_bw40_base[path][group] = 0x2D;
1767 			}
1768 			for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1769 				if (cnt == 0) {
1770 					pw2g->bw20_diff[path][0] = 0x02;
1771 					pw2g->ofdm_diff[path][0] = 0x04;
1772 				} else {
1773 					pw2g->bw20_diff[path][cnt] = 0xFE;
1774 					pw2g->bw40_diff[path][cnt] = 0xFE;
1775 					pw2g->cck_diff[path][cnt] = 0xFE;
1776 					pw2g->ofdm_diff[path][cnt] = 0xFE;
1777 				}
1778 			}
1779 		}
1780 		return;
1781 	}
1782 
1783 	for (path = 0; path < MAX_RF_PATH; path++) {
1784 		/*2.4G default value*/
1785 		for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1786 			pw2g->index_cck_base[path][group] = hwinfo[addr++];
1787 			if (pw2g->index_cck_base[path][group] == 0xFF)
1788 				pw2g->index_cck_base[path][group] = 0x2D;
1789 
1790 		}
1791 		for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1792 			pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1793 			if (pw2g->index_bw40_base[path][group] == 0xFF)
1794 				pw2g->index_bw40_base[path][group] = 0x2D;
1795 		}
1796 		for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1797 			if (cnt == 0) {
1798 				pw2g->bw40_diff[path][cnt] = 0;
1799 				if (hwinfo[addr] == 0xFF) {
1800 					pw2g->bw20_diff[path][cnt] = 0x02;
1801 				} else {
1802 					pw2g->bw20_diff[path][cnt] =
1803 						(hwinfo[addr] & 0xf0) >> 4;
1804 					/*bit sign number to 8 bit sign number*/
1805 					if (pw2g->bw20_diff[path][cnt] & BIT(3))
1806 						pw2g->bw20_diff[path][cnt] |=
1807 									  0xF0;
1808 				}
1809 
1810 				if (hwinfo[addr] == 0xFF) {
1811 					pw2g->ofdm_diff[path][cnt] = 0x04;
1812 				} else {
1813 					pw2g->ofdm_diff[path][cnt] =
1814 							(hwinfo[addr] & 0x0f);
1815 					/*bit sign number to 8 bit sign number*/
1816 					if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1817 						pw2g->ofdm_diff[path][cnt] |=
1818 									  0xF0;
1819 				}
1820 				pw2g->cck_diff[path][cnt] = 0;
1821 				addr++;
1822 			} else {
1823 				if (hwinfo[addr] == 0xFF) {
1824 					pw2g->bw40_diff[path][cnt] = 0xFE;
1825 				} else {
1826 					pw2g->bw40_diff[path][cnt] =
1827 						(hwinfo[addr] & 0xf0) >> 4;
1828 					if (pw2g->bw40_diff[path][cnt] & BIT(3))
1829 						pw2g->bw40_diff[path][cnt] |=
1830 									  0xF0;
1831 				}
1832 
1833 				if (hwinfo[addr] == 0xFF) {
1834 					pw2g->bw20_diff[path][cnt] = 0xFE;
1835 				} else {
1836 					pw2g->bw20_diff[path][cnt] =
1837 							(hwinfo[addr] & 0x0f);
1838 					if (pw2g->bw20_diff[path][cnt] & BIT(3))
1839 						pw2g->bw20_diff[path][cnt] |=
1840 									  0xF0;
1841 				}
1842 				addr++;
1843 
1844 				if (hwinfo[addr] == 0xFF) {
1845 					pw2g->ofdm_diff[path][cnt] = 0xFE;
1846 				} else {
1847 					pw2g->ofdm_diff[path][cnt] =
1848 						(hwinfo[addr] & 0xf0) >> 4;
1849 					if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1850 						pw2g->ofdm_diff[path][cnt] |=
1851 									  0xF0;
1852 				}
1853 
1854 				if (hwinfo[addr] == 0xFF)
1855 					pw2g->cck_diff[path][cnt] = 0xFE;
1856 				else {
1857 					pw2g->cck_diff[path][cnt] =
1858 							(hwinfo[addr] & 0x0f);
1859 					if (pw2g->cck_diff[path][cnt] & BIT(3))
1860 						pw2g->cck_diff[path][cnt] |=
1861 									 0xF0;
1862 				}
1863 				addr++;
1864 			}
1865 		}
1866 
1867 		/*5G default value*/
1868 		for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1869 			pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1870 			if (pw5g->index_bw40_base[path][group] == 0xFF)
1871 				pw5g->index_bw40_base[path][group] = 0xFE;
1872 		}
1873 
1874 		for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1875 			if (cnt == 0) {
1876 				pw5g->bw40_diff[path][cnt] = 0;
1877 
1878 				if (hwinfo[addr] == 0xFF) {
1879 					pw5g->bw20_diff[path][cnt] = 0;
1880 				} else {
1881 					pw5g->bw20_diff[path][0] =
1882 						(hwinfo[addr] & 0xf0) >> 4;
1883 					if (pw5g->bw20_diff[path][cnt] & BIT(3))
1884 						pw5g->bw20_diff[path][cnt] |=
1885 									  0xF0;
1886 				}
1887 
1888 				if (hwinfo[addr] == 0xFF)
1889 					pw5g->ofdm_diff[path][cnt] = 0x04;
1890 				else {
1891 					pw5g->ofdm_diff[path][0] =
1892 							(hwinfo[addr] & 0x0f);
1893 					if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1894 						pw5g->ofdm_diff[path][cnt] |=
1895 									  0xF0;
1896 				}
1897 				addr++;
1898 			} else {
1899 				if (hwinfo[addr] == 0xFF) {
1900 					pw5g->bw40_diff[path][cnt] = 0xFE;
1901 				} else {
1902 					pw5g->bw40_diff[path][cnt] =
1903 						(hwinfo[addr] & 0xf0) >> 4;
1904 					if (pw5g->bw40_diff[path][cnt] & BIT(3))
1905 						pw5g->bw40_diff[path][cnt] |= 0xF0;
1906 				}
1907 
1908 				if (hwinfo[addr] == 0xFF) {
1909 					pw5g->bw20_diff[path][cnt] = 0xFE;
1910 				} else {
1911 					pw5g->bw20_diff[path][cnt] =
1912 							(hwinfo[addr] & 0x0f);
1913 					if (pw5g->bw20_diff[path][cnt] & BIT(3))
1914 						pw5g->bw20_diff[path][cnt] |= 0xF0;
1915 				}
1916 				addr++;
1917 			}
1918 		}
1919 
1920 		if (hwinfo[addr] == 0xFF) {
1921 			pw5g->ofdm_diff[path][1] = 0xFE;
1922 			pw5g->ofdm_diff[path][2] = 0xFE;
1923 		} else {
1924 			pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1925 			pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1926 		}
1927 		addr++;
1928 
1929 		if (hwinfo[addr] == 0xFF)
1930 			pw5g->ofdm_diff[path][3] = 0xFE;
1931 		else
1932 			pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1933 		addr++;
1934 
1935 		for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1936 			if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1937 				pw5g->ofdm_diff[path][cnt] = 0xFE;
1938 			else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1939 				pw5g->ofdm_diff[path][cnt] |= 0xF0;
1940 		}
1941 	}
1942 }
1943 
_rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)1944 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1945 						   bool autoload_fail,
1946 						   u8 *hwinfo)
1947 {
1948 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1949 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1950 	struct txpower_info_2g pw2g;
1951 	struct txpower_info_5g pw5g;
1952 	u8 rf_path, index;
1953 	u8 i;
1954 
1955 	_rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1956 					     hwinfo);
1957 
1958 	for (rf_path = 0; rf_path < 2; rf_path++) {
1959 		for (i = 0; i < 14; i++) {
1960 			index = _rtl8723be_get_chnl_group(i+1);
1961 
1962 			rtlefuse->txpwrlevel_cck[rf_path][i] =
1963 					pw2g.index_cck_base[rf_path][index];
1964 			rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1965 					pw2g.index_bw40_base[rf_path][index];
1966 		}
1967 		for (i = 0; i < MAX_TX_COUNT; i++) {
1968 			rtlefuse->txpwr_ht20diff[rf_path][i] =
1969 						pw2g.bw20_diff[rf_path][i];
1970 			rtlefuse->txpwr_ht40diff[rf_path][i] =
1971 						pw2g.bw40_diff[rf_path][i];
1972 			rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1973 						pw2g.ofdm_diff[rf_path][i];
1974 		}
1975 
1976 		for (i = 0; i < 14; i++) {
1977 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1978 				"RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1979 				rf_path, i,
1980 				rtlefuse->txpwrlevel_cck[rf_path][i],
1981 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1982 		}
1983 	}
1984 
1985 	if (!autoload_fail)
1986 		rtlefuse->eeprom_thermalmeter =
1987 					hwinfo[EEPROM_THERMAL_METER_88E];
1988 	else
1989 		rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1990 
1991 	if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1992 		rtlefuse->apk_thermalmeterignore = true;
1993 		rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1994 	}
1995 
1996 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1997 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1998 		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1999 
2000 	if (!autoload_fail) {
2001 		rtlefuse->eeprom_regulatory =
2002 			hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
2003 		if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2004 			rtlefuse->eeprom_regulatory = 0;
2005 	} else {
2006 		rtlefuse->eeprom_regulatory = 0;
2007 	}
2008 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2009 		"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2010 }
2011 
_rtl8723be_read_package_type(struct ieee80211_hw * hw)2012 static u8 _rtl8723be_read_package_type(struct ieee80211_hw *hw)
2013 {
2014 	u8 package_type;
2015 	u8 value;
2016 
2017 	efuse_power_switch(hw, false, true);
2018 	if (!efuse_one_byte_read(hw, 0x1FB, &value))
2019 		value = 0;
2020 	efuse_power_switch(hw, false, false);
2021 
2022 	switch (value & 0x7) {
2023 	case 0x4:
2024 		package_type = PACKAGE_TFBGA79;
2025 		break;
2026 	case 0x5:
2027 		package_type = PACKAGE_TFBGA90;
2028 		break;
2029 	case 0x6:
2030 		package_type = PACKAGE_QFN68;
2031 		break;
2032 	case 0x7:
2033 		package_type = PACKAGE_TFBGA80;
2034 		break;
2035 	default:
2036 		package_type = PACKAGE_DEFAULT;
2037 		break;
2038 	}
2039 
2040 	return package_type;
2041 }
2042 
_rtl8723be_read_adapter_info(struct ieee80211_hw * hw,bool pseudo_test)2043 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2044 					 bool pseudo_test)
2045 {
2046 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2047 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2048 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2049 	int params[] = {RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID,
2050 			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
2051 			EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
2052 			COUNTRY_CODE_WORLD_WIDE_13};
2053 	u8 *hwinfo;
2054 	int i;
2055 	bool is_toshiba_smid1 = false;
2056 	bool is_toshiba_smid2 = false;
2057 	bool is_samsung_smid = false;
2058 	bool is_lenovo_smid = false;
2059 	u16 toshiba_smid1[] = {
2060 		0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2061 		0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2062 		0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2063 		0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2064 	};
2065 	u16 toshiba_smid2[] = {
2066 		0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2067 		0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2068 	};
2069 	u16 samsung_smid[] = {
2070 		0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2071 		0x8193, 0x9191, 0x9192, 0x9193
2072 	};
2073 	u16 lenovo_smid[] = {
2074 		0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2075 	};
2076 
2077 	if (pseudo_test) {
2078 		/* needs to be added */
2079 		return;
2080 	}
2081 
2082 	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
2083 	if (!hwinfo)
2084 		return;
2085 
2086 	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
2087 		goto exit;
2088 
2089 	/*parse xtal*/
2090 	rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2091 	if (rtlefuse->crystalcap == 0xFF)
2092 		rtlefuse->crystalcap = 0x20;
2093 
2094 	_rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2095 					       hwinfo);
2096 
2097 	rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2098 						 rtlefuse->autoload_failflag,
2099 						 hwinfo);
2100 
2101 	if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
2102 		rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
2103 
2104 	rtlhal->board_type = rtlefuse->board_type;
2105 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2106 		"board_type = 0x%x\n", rtlefuse->board_type);
2107 
2108 	rtlhal->package_type = _rtl8723be_read_package_type(hw);
2109 
2110 	/* set channel plan from efuse */
2111 	rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2112 
2113 	if (rtlhal->oem_id == RT_CID_DEFAULT) {
2114 		/* Does this one have a Toshiba SMID from group 1? */
2115 		for (i = 0; i < ARRAY_SIZE(toshiba_smid1); i++) {
2116 			if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2117 				is_toshiba_smid1 = true;
2118 				break;
2119 			}
2120 		}
2121 		/* Does this one have a Toshiba SMID from group 2? */
2122 		for (i = 0; i < ARRAY_SIZE(toshiba_smid2); i++) {
2123 			if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2124 				is_toshiba_smid2 = true;
2125 				break;
2126 			}
2127 		}
2128 		/* Does this one have a Samsung SMID? */
2129 		for (i = 0; i < ARRAY_SIZE(samsung_smid); i++) {
2130 			if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2131 				is_samsung_smid = true;
2132 				break;
2133 			}
2134 		}
2135 		/* Does this one have a Lenovo SMID? */
2136 		for (i = 0; i < ARRAY_SIZE(lenovo_smid); i++) {
2137 			if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2138 				is_lenovo_smid = true;
2139 				break;
2140 			}
2141 		}
2142 		switch (rtlefuse->eeprom_oemid) {
2143 		case EEPROM_CID_DEFAULT:
2144 			if (rtlefuse->eeprom_did == 0x8176) {
2145 				if (rtlefuse->eeprom_svid == 0x10EC &&
2146 				    is_toshiba_smid1) {
2147 					rtlhal->oem_id = RT_CID_TOSHIBA;
2148 				} else if (rtlefuse->eeprom_svid == 0x1025) {
2149 					rtlhal->oem_id = RT_CID_819X_ACER;
2150 				} else if (rtlefuse->eeprom_svid == 0x10EC &&
2151 					   is_samsung_smid) {
2152 					rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2153 				} else if (rtlefuse->eeprom_svid == 0x10EC &&
2154 					   is_lenovo_smid) {
2155 					rtlhal->oem_id = RT_CID_819X_LENOVO;
2156 				} else if ((rtlefuse->eeprom_svid == 0x10EC &&
2157 					    rtlefuse->eeprom_smid == 0x8197) ||
2158 					   (rtlefuse->eeprom_svid == 0x10EC &&
2159 					    rtlefuse->eeprom_smid == 0x9196)) {
2160 					rtlhal->oem_id = RT_CID_819X_CLEVO;
2161 				} else if ((rtlefuse->eeprom_svid == 0x1028 &&
2162 					    rtlefuse->eeprom_smid == 0x8194) ||
2163 					   (rtlefuse->eeprom_svid == 0x1028 &&
2164 					    rtlefuse->eeprom_smid == 0x8198) ||
2165 					   (rtlefuse->eeprom_svid == 0x1028 &&
2166 					    rtlefuse->eeprom_smid == 0x9197) ||
2167 					   (rtlefuse->eeprom_svid == 0x1028 &&
2168 					    rtlefuse->eeprom_smid == 0x9198)) {
2169 					rtlhal->oem_id = RT_CID_819X_DELL;
2170 				} else if ((rtlefuse->eeprom_svid == 0x103C &&
2171 					    rtlefuse->eeprom_smid == 0x1629)) {
2172 					rtlhal->oem_id = RT_CID_819X_HP;
2173 				} else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2174 					   rtlefuse->eeprom_smid == 0x2315)) {
2175 					rtlhal->oem_id = RT_CID_819X_QMI;
2176 				} else if ((rtlefuse->eeprom_svid == 0x10EC &&
2177 					   rtlefuse->eeprom_smid == 0x8203)) {
2178 					rtlhal->oem_id = RT_CID_819X_PRONETS;
2179 				} else if ((rtlefuse->eeprom_svid == 0x1043 &&
2180 					   rtlefuse->eeprom_smid == 0x84B5)) {
2181 					rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2182 				} else {
2183 					rtlhal->oem_id = RT_CID_DEFAULT;
2184 				}
2185 			} else if (rtlefuse->eeprom_did == 0x8178) {
2186 				if (rtlefuse->eeprom_svid == 0x10EC &&
2187 				    is_toshiba_smid2)
2188 					rtlhal->oem_id = RT_CID_TOSHIBA;
2189 				else if (rtlefuse->eeprom_svid == 0x1025)
2190 					rtlhal->oem_id = RT_CID_819X_ACER;
2191 				else if ((rtlefuse->eeprom_svid == 0x10EC &&
2192 					  rtlefuse->eeprom_smid == 0x8186))
2193 					rtlhal->oem_id = RT_CID_819X_PRONETS;
2194 				else if ((rtlefuse->eeprom_svid == 0x1043 &&
2195 					  rtlefuse->eeprom_smid == 0x84B6))
2196 					rtlhal->oem_id =
2197 							RT_CID_819X_EDIMAX_ASUS;
2198 				else
2199 					rtlhal->oem_id = RT_CID_DEFAULT;
2200 			} else {
2201 					rtlhal->oem_id = RT_CID_DEFAULT;
2202 			}
2203 			break;
2204 		case EEPROM_CID_TOSHIBA:
2205 			rtlhal->oem_id = RT_CID_TOSHIBA;
2206 			break;
2207 		case EEPROM_CID_CCX:
2208 			rtlhal->oem_id = RT_CID_CCX;
2209 			break;
2210 		case EEPROM_CID_QMI:
2211 			rtlhal->oem_id = RT_CID_819X_QMI;
2212 			break;
2213 		case EEPROM_CID_WHQL:
2214 			break;
2215 		default:
2216 			rtlhal->oem_id = RT_CID_DEFAULT;
2217 			break;
2218 		}
2219 	}
2220 exit:
2221 	kfree(hwinfo);
2222 }
2223 
_rtl8723be_hal_customized_behavior(struct ieee80211_hw * hw)2224 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2225 {
2226 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2227 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2228 
2229 	rtlpriv->ledctl.led_opendrain = true;
2230 	switch (rtlhal->oem_id) {
2231 	case RT_CID_819X_HP:
2232 		rtlpriv->ledctl.led_opendrain = true;
2233 		break;
2234 	case RT_CID_819X_LENOVO:
2235 	case RT_CID_DEFAULT:
2236 	case RT_CID_TOSHIBA:
2237 	case RT_CID_CCX:
2238 	case RT_CID_819X_ACER:
2239 	case RT_CID_WHQL:
2240 	default:
2241 		break;
2242 	}
2243 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2244 		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2245 }
2246 
rtl8723be_read_eeprom_info(struct ieee80211_hw * hw)2247 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2248 {
2249 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2250 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2251 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2252 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2253 	u8 tmp_u1b;
2254 
2255 	rtlhal->version = _rtl8723be_read_chip_version(hw);
2256 	if (get_rf_type(rtlphy) == RF_1T1R)
2257 		rtlpriv->dm.rfpath_rxenable[0] = true;
2258 	else
2259 		rtlpriv->dm.rfpath_rxenable[0] =
2260 		    rtlpriv->dm.rfpath_rxenable[1] = true;
2261 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2262 		rtlhal->version);
2263 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2264 	if (tmp_u1b & BIT(4)) {
2265 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2266 		rtlefuse->epromtype = EEPROM_93C46;
2267 	} else {
2268 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2269 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2270 	}
2271 	if (tmp_u1b & BIT(5)) {
2272 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2273 		rtlefuse->autoload_failflag = false;
2274 		_rtl8723be_read_adapter_info(hw, false);
2275 	} else {
2276 		pr_err("Autoload ERR!!\n");
2277 	}
2278 	_rtl8723be_hal_customized_behavior(hw);
2279 }
2280 
_rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw * hw,u8 rate_index)2281 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2282 					  u8 rate_index)
2283 {
2284 	u8 ret = 0;
2285 	switch (rate_index) {
2286 	case RATR_INX_WIRELESS_NGB:
2287 		ret = 1;
2288 		break;
2289 	case RATR_INX_WIRELESS_N:
2290 	case RATR_INX_WIRELESS_NG:
2291 		ret = 5;
2292 		break;
2293 	case RATR_INX_WIRELESS_NB:
2294 		ret = 3;
2295 		break;
2296 	case RATR_INX_WIRELESS_GB:
2297 		ret = 6;
2298 		break;
2299 	case RATR_INX_WIRELESS_G:
2300 		ret = 7;
2301 		break;
2302 	case RATR_INX_WIRELESS_B:
2303 		ret = 8;
2304 		break;
2305 	default:
2306 		ret = 0;
2307 		break;
2308 	}
2309 	return ret;
2310 }
2311 
rtl8723be_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2312 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2313 					   struct ieee80211_sta *sta,
2314 					   u8 rssi_level, bool update_bw)
2315 {
2316 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2317 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2318 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2319 	struct rtl_sta_info *sta_entry = NULL;
2320 	u32 ratr_bitmap;
2321 	u8 ratr_index;
2322 	u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap &
2323 			      IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2324 	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2325 				1 : 0;
2326 	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2327 				1 : 0;
2328 	enum wireless_mode wirelessmode = 0;
2329 	bool shortgi = false;
2330 	u8 rate_mask[7];
2331 	u8 macid = 0;
2332 
2333 	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2334 	wirelessmode = sta_entry->wireless_mode;
2335 	if (mac->opmode == NL80211_IFTYPE_STATION ||
2336 	    mac->opmode == NL80211_IFTYPE_MESH_POINT)
2337 		curtxbw_40mhz = mac->bw_40;
2338 	else if (mac->opmode == NL80211_IFTYPE_AP ||
2339 		 mac->opmode == NL80211_IFTYPE_ADHOC)
2340 		macid = sta->aid + 1;
2341 
2342 	ratr_bitmap = sta->deflink.supp_rates[0];
2343 
2344 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
2345 		ratr_bitmap = 0xfff;
2346 
2347 	ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
2348 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
2349 	switch (wirelessmode) {
2350 	case WIRELESS_MODE_B:
2351 		ratr_index = RATR_INX_WIRELESS_B;
2352 		if (ratr_bitmap & 0x0000000c)
2353 			ratr_bitmap &= 0x0000000d;
2354 		else
2355 			ratr_bitmap &= 0x0000000f;
2356 		break;
2357 	case WIRELESS_MODE_G:
2358 		ratr_index = RATR_INX_WIRELESS_GB;
2359 
2360 		if (rssi_level == 1)
2361 			ratr_bitmap &= 0x00000f00;
2362 		else if (rssi_level == 2)
2363 			ratr_bitmap &= 0x00000ff0;
2364 		else
2365 			ratr_bitmap &= 0x00000ff5;
2366 		break;
2367 	case WIRELESS_MODE_N_24G:
2368 	case WIRELESS_MODE_N_5G:
2369 		ratr_index = RATR_INX_WIRELESS_NGB;
2370 		if (rtlphy->rf_type == RF_1T1R) {
2371 			if (curtxbw_40mhz) {
2372 				if (rssi_level == 1)
2373 					ratr_bitmap &= 0x000f0000;
2374 				else if (rssi_level == 2)
2375 					ratr_bitmap &= 0x000ff000;
2376 				else
2377 					ratr_bitmap &= 0x000ff015;
2378 			} else {
2379 				if (rssi_level == 1)
2380 					ratr_bitmap &= 0x000f0000;
2381 				else if (rssi_level == 2)
2382 					ratr_bitmap &= 0x000ff000;
2383 				else
2384 					ratr_bitmap &= 0x000ff005;
2385 			}
2386 		} else {
2387 			if (curtxbw_40mhz) {
2388 				if (rssi_level == 1)
2389 					ratr_bitmap &= 0x0f8f0000;
2390 				else if (rssi_level == 2)
2391 					ratr_bitmap &= 0x0f8ff000;
2392 				else
2393 					ratr_bitmap &= 0x0f8ff015;
2394 			} else {
2395 				if (rssi_level == 1)
2396 					ratr_bitmap &= 0x0f8f0000;
2397 				else if (rssi_level == 2)
2398 					ratr_bitmap &= 0x0f8ff000;
2399 				else
2400 					ratr_bitmap &= 0x0f8ff005;
2401 			}
2402 		}
2403 		if ((curtxbw_40mhz && curshortgi_40mhz) ||
2404 		    (!curtxbw_40mhz && curshortgi_20mhz)) {
2405 			if (macid == 0)
2406 				shortgi = true;
2407 			else if (macid == 1)
2408 				shortgi = false;
2409 		}
2410 		break;
2411 	default:
2412 		ratr_index = RATR_INX_WIRELESS_NGB;
2413 
2414 		if (rtlphy->rf_type == RF_1T2R)
2415 			ratr_bitmap &= 0x000ff0ff;
2416 		else
2417 			ratr_bitmap &= 0x0f0ff0ff;
2418 		break;
2419 	}
2420 
2421 	sta_entry->ratr_index = ratr_index;
2422 
2423 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2424 		"ratr_bitmap :%x\n", ratr_bitmap);
2425 	*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2426 				       (ratr_index << 28);
2427 	rate_mask[0] = macid;
2428 	rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2429 						      (shortgi ? 0x80 : 0x00);
2430 	rate_mask[2] = curtxbw_40mhz | ((!update_bw) << 3);
2431 
2432 	rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2433 	rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2434 	rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2435 	rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2436 
2437 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2438 		"Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2439 		ratr_index, ratr_bitmap,
2440 		rate_mask[0], rate_mask[1],
2441 		rate_mask[2], rate_mask[3],
2442 		rate_mask[4], rate_mask[5],
2443 		rate_mask[6]);
2444 	rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2445 	_rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2446 }
2447 
rtl8723be_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2448 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2449 				   struct ieee80211_sta *sta,
2450 				   u8 rssi_level, bool update_bw)
2451 {
2452 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2453 	if (rtlpriv->dm.useramask)
2454 		rtl8723be_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2455 }
2456 
rtl8723be_update_channel_access_setting(struct ieee80211_hw * hw)2457 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2458 {
2459 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2460 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2461 	u16 sifs_timer;
2462 
2463 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2464 	if (!mac->ht_enable)
2465 		sifs_timer = 0x0a0a;
2466 	else
2467 		sifs_timer = 0x0e0e;
2468 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2469 }
2470 
rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2471 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2472 {
2473 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2474 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2475 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2476 	enum rf_pwrstate e_rfpowerstate_toset;
2477 	u8 u1tmp;
2478 	bool b_actuallyset = false;
2479 
2480 	if (rtlpriv->rtlhal.being_init_adapter)
2481 		return false;
2482 
2483 	if (ppsc->swrf_processing)
2484 		return false;
2485 
2486 	spin_lock(&rtlpriv->locks.rf_ps_lock);
2487 	if (ppsc->rfchange_inprogress) {
2488 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2489 		return false;
2490 	} else {
2491 		ppsc->rfchange_inprogress = true;
2492 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2493 	}
2494 
2495 	rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2496 		       rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2497 
2498 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2499 
2500 	if (rtlphy->polarity_ctl)
2501 		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2502 	else
2503 		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2504 
2505 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2506 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2507 			"GPIOChangeRF  - HW Radio ON, RF ON\n");
2508 
2509 		e_rfpowerstate_toset = ERFON;
2510 		ppsc->hwradiooff = false;
2511 		b_actuallyset = true;
2512 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2513 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2514 			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2515 
2516 		e_rfpowerstate_toset = ERFOFF;
2517 		ppsc->hwradiooff = true;
2518 		b_actuallyset = true;
2519 	}
2520 
2521 	if (b_actuallyset) {
2522 		spin_lock(&rtlpriv->locks.rf_ps_lock);
2523 		ppsc->rfchange_inprogress = false;
2524 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2525 	} else {
2526 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2527 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2528 
2529 		spin_lock(&rtlpriv->locks.rf_ps_lock);
2530 		ppsc->rfchange_inprogress = false;
2531 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2532 	}
2533 
2534 	*valid = 1;
2535 	return !ppsc->hwradiooff;
2536 
2537 }
2538 
rtl8723be_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2539 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2540 		       u8 *p_macaddr, bool is_group, u8 enc_algo,
2541 		       bool is_wepkey, bool clear_all)
2542 {
2543 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2544 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2545 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2546 	u8 *macaddr = p_macaddr;
2547 	u32 entry_id = 0;
2548 	bool is_pairwise = false;
2549 
2550 	static u8 cam_const_addr[4][6] = {
2551 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2552 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2553 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2554 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2555 	};
2556 	static u8 cam_const_broad[] = {
2557 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2558 	};
2559 
2560 	if (clear_all) {
2561 		u8 idx = 0;
2562 		u8 cam_offset = 0;
2563 		u8 clear_number = 5;
2564 
2565 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2566 
2567 		for (idx = 0; idx < clear_number; idx++) {
2568 			rtl_cam_mark_invalid(hw, cam_offset + idx);
2569 			rtl_cam_empty_entry(hw, cam_offset + idx);
2570 
2571 			if (idx < 5) {
2572 				memset(rtlpriv->sec.key_buf[idx], 0,
2573 				       MAX_KEY_LEN);
2574 				rtlpriv->sec.key_len[idx] = 0;
2575 			}
2576 		}
2577 
2578 	} else {
2579 		switch (enc_algo) {
2580 		case WEP40_ENCRYPTION:
2581 			enc_algo = CAM_WEP40;
2582 			break;
2583 		case WEP104_ENCRYPTION:
2584 			enc_algo = CAM_WEP104;
2585 			break;
2586 		case TKIP_ENCRYPTION:
2587 			enc_algo = CAM_TKIP;
2588 			break;
2589 		case AESCCMP_ENCRYPTION:
2590 			enc_algo = CAM_AES;
2591 			break;
2592 		default:
2593 			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2594 				"switch case %#x not processed\n", enc_algo);
2595 			enc_algo = CAM_TKIP;
2596 			break;
2597 		}
2598 
2599 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2600 			macaddr = cam_const_addr[key_index];
2601 			entry_id = key_index;
2602 		} else {
2603 			if (is_group) {
2604 				macaddr = cam_const_broad;
2605 				entry_id = key_index;
2606 			} else {
2607 				if (mac->opmode == NL80211_IFTYPE_AP) {
2608 					entry_id = rtl_cam_get_free_entry(hw,
2609 								p_macaddr);
2610 					if (entry_id >=  TOTAL_CAM_ENTRY) {
2611 						pr_err("Can not find free hw security cam entry\n");
2612 						return;
2613 					}
2614 				} else {
2615 					entry_id = CAM_PAIRWISE_KEY_POSITION;
2616 				}
2617 
2618 				key_index = PAIRWISE_KEYIDX;
2619 				is_pairwise = true;
2620 			}
2621 		}
2622 
2623 		if (rtlpriv->sec.key_len[key_index] == 0) {
2624 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2625 				"delete one entry, entry_id is %d\n",
2626 				entry_id);
2627 			if (mac->opmode == NL80211_IFTYPE_AP)
2628 				rtl_cam_del_entry(hw, p_macaddr);
2629 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2630 		} else {
2631 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2632 				"add one entry\n");
2633 			if (is_pairwise) {
2634 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2635 					"set Pairwise key\n");
2636 
2637 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2638 					       entry_id, enc_algo,
2639 					       CAM_CONFIG_NO_USEDK,
2640 					       rtlpriv->sec.key_buf[key_index]);
2641 			} else {
2642 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2643 					"set group key\n");
2644 
2645 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2646 					rtl_cam_add_one_entry(hw,
2647 						rtlefuse->dev_addr,
2648 						PAIRWISE_KEYIDX,
2649 						CAM_PAIRWISE_KEY_POSITION,
2650 						enc_algo,
2651 						CAM_CONFIG_NO_USEDK,
2652 						rtlpriv->sec.key_buf
2653 						[entry_id]);
2654 				}
2655 
2656 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2657 						entry_id, enc_algo,
2658 						CAM_CONFIG_NO_USEDK,
2659 						rtlpriv->sec.key_buf[entry_id]);
2660 			}
2661 		}
2662 	}
2663 }
2664 
rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)2665 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2666 					      bool auto_load_fail, u8 *hwinfo)
2667 {
2668 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2669 	struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
2670 	u8 value;
2671 	u32 tmpu_32;
2672 
2673 	if (!auto_load_fail) {
2674 		tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2675 		if (tmpu_32 & BIT(18))
2676 			rtlpriv->btcoexist.btc_info.btcoexist = 1;
2677 		else
2678 			rtlpriv->btcoexist.btc_info.btcoexist = 0;
2679 		value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2680 		rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2681 		rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2682 		rtlpriv->btcoexist.btc_info.single_ant_path =
2683 			 (value & 0x40 ? ANT_AUX : ANT_MAIN);	/*0xc3[6]*/
2684 	} else {
2685 		rtlpriv->btcoexist.btc_info.btcoexist = 0;
2686 		rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2687 		rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2688 		rtlpriv->btcoexist.btc_info.single_ant_path = ANT_MAIN;
2689 	}
2690 
2691 	/* override ant_num / ant_path */
2692 	if (mod_params->ant_sel) {
2693 		rtlpriv->btcoexist.btc_info.ant_num =
2694 			(mod_params->ant_sel == 1 ? ANT_X1 : ANT_X2);
2695 
2696 		rtlpriv->btcoexist.btc_info.single_ant_path =
2697 			(mod_params->ant_sel == 1 ? ANT_AUX : ANT_MAIN);
2698 	}
2699 }
2700 
rtl8723be_bt_reg_init(struct ieee80211_hw * hw)2701 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2702 {
2703 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2704 
2705 	/* 0:Low, 1:High, 2:From Efuse. */
2706 	rtlpriv->btcoexist.reg_bt_iso = 2;
2707 	/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2708 	rtlpriv->btcoexist.reg_bt_sco = 3;
2709 	/* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2710 	rtlpriv->btcoexist.reg_bt_sco = 0;
2711 }
2712 
rtl8723be_bt_hw_init(struct ieee80211_hw * hw)2713 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2714 {
2715 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2716 
2717 	if (rtlpriv->cfg->ops->get_btc_status())
2718 		rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2719 
2720 }
2721 
rtl8723be_suspend(struct ieee80211_hw * hw)2722 void rtl8723be_suspend(struct ieee80211_hw *hw)
2723 {
2724 }
2725 
rtl8723be_resume(struct ieee80211_hw * hw)2726 void rtl8723be_resume(struct ieee80211_hw *hw)
2727 {
2728 }
2729