1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../pci.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "../rtl8723com/phy_common.h"
11 #include "dm.h"
12 #include "../rtl8723com/dm_common.h"
13 #include "hw.h"
14 #include "fw.h"
15 #include "../rtl8723com/fw_common.h"
16 #include "trx.h"
17 #include "led.h"
18 #include "table.h"
19 #include "../btcoexist/rtl_btc.h"
20
21 #include <linux/vmalloc.h>
22 #include <linux/module.h>
23
rtl8723be_init_aspm_vars(struct ieee80211_hw * hw)24 static void rtl8723be_init_aspm_vars(struct ieee80211_hw *hw)
25 {
26 struct rtl_priv *rtlpriv = rtl_priv(hw);
27 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
28
29 /*close ASPM for AMD defaultly */
30 rtlpci->const_amdpci_aspm = 0;
31
32 /* ASPM PS mode.
33 * 0 - Disable ASPM,
34 * 1 - Enable ASPM without Clock Req,
35 * 2 - Enable ASPM with Clock Req,
36 * 3 - Alwyas Enable ASPM with Clock Req,
37 * 4 - Always Enable ASPM without Clock Req.
38 * set defult to RTL8192CE:3 RTL8192E:2
39 */
40 rtlpci->const_pci_aspm = 3;
41
42 /*Setting for PCI-E device */
43 rtlpci->const_devicepci_aspm_setting = 0x03;
44
45 /*Setting for PCI-E bridge */
46 rtlpci->const_hostpci_aspm_setting = 0x02;
47
48 /* In Hw/Sw Radio Off situation.
49 * 0 - Default,
50 * 1 - From ASPM setting without low Mac Pwr,
51 * 2 - From ASPM setting with low Mac Pwr,
52 * 3 - Bus D3
53 * set default to RTL8192CE:0 RTL8192SE:2
54 */
55 rtlpci->const_hwsw_rfoff_d3 = 0;
56
57 /* This setting works for those device with
58 * backdoor ASPM setting such as EPHY setting.
59 * 0 - Not support ASPM,
60 * 1 - Support ASPM,
61 * 2 - According to chipset.
62 */
63 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
64 }
65
rtl8723be_init_sw_vars(struct ieee80211_hw * hw)66 static int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
67 {
68 int err = 0;
69 struct rtl_priv *rtlpriv = rtl_priv(hw);
70 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
71 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
72 char *fw_name = "rtlwifi/rtl8723befw_36.bin";
73
74 rtl8723be_bt_reg_init(hw);
75 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
76
77 rtlpriv->dm.dm_initialgain_enable = true;
78 rtlpriv->dm.dm_flag = 0;
79 rtlpriv->dm.disable_framebursting = false;
80 rtlpriv->dm.thermalvalue = 0;
81 rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
82
83 rtlpriv->phy.lck_inprogress = false;
84
85 mac->ht_enable = true;
86
87 /* compatible 5G band 88ce just 2.4G band & smsp */
88 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
89 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
90 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
91
92 rtlpci->receive_config = (RCR_APPFCS |
93 RCR_APP_MIC |
94 RCR_APP_ICV |
95 RCR_APP_PHYST_RXFF |
96 RCR_HTC_LOC_CTRL |
97 RCR_AMF |
98 RCR_ACF |
99 RCR_ADF |
100 RCR_AICV |
101 RCR_AB |
102 RCR_AM |
103 RCR_APM |
104 0);
105
106 rtlpci->irq_mask[0] = (u32) (IMR_PSTIMEOUT |
107 IMR_HSISR_IND_ON_INT |
108 IMR_C2HCMD |
109 IMR_HIGHDOK |
110 IMR_MGNTDOK |
111 IMR_BKDOK |
112 IMR_BEDOK |
113 IMR_VIDOK |
114 IMR_VODOK |
115 IMR_RDU |
116 IMR_ROK |
117 0);
118
119 rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
120
121 rtlpci->sys_irq_mask = (u32)(HSIMR_PDN_INT_EN |
122 HSIMR_RON_INT_EN |
123 0);
124
125 /* for LPS & IPS */
126 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
127 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
128 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
129 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
130 if (rtlpriv->cfg->mod_params->disable_watchdog)
131 pr_info("watchdog disabled\n");
132 rtlpriv->psc.reg_fwctrl_lps = 2;
133 rtlpriv->psc.reg_max_lps_awakeintvl = 2;
134 /* for ASPM, you can close aspm through
135 * set const_support_pciaspm = 0
136 */
137 rtl8723be_init_aspm_vars(hw);
138
139 if (rtlpriv->psc.reg_fwctrl_lps == 1)
140 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
141 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
142 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
143 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
144 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
145
146 /*low power: Disable 32k */
147 rtlpriv->psc.low_power_enable = false;
148
149 rtlpriv->rtlhal.earlymode_enable = false;
150
151 /* for firmware buf */
152 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
153 if (!rtlpriv->rtlhal.pfirmware) {
154 pr_err("Can't alloc buffer for fw.\n");
155 return 1;
156 }
157
158 rtlpriv->max_fw_size = 0x8000;
159 pr_info("Using firmware %s\n", fw_name);
160 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
161 rtlpriv->io.dev, GFP_KERNEL, hw,
162 rtl_fw_cb);
163 if (err) {
164 pr_err("Failed to request firmware!\n");
165 vfree(rtlpriv->rtlhal.pfirmware);
166 rtlpriv->rtlhal.pfirmware = NULL;
167 return 1;
168 }
169 return 0;
170 }
171
rtl8723be_deinit_sw_vars(struct ieee80211_hw * hw)172 static void rtl8723be_deinit_sw_vars(struct ieee80211_hw *hw)
173 {
174 struct rtl_priv *rtlpriv = rtl_priv(hw);
175
176 if (rtlpriv->rtlhal.pfirmware) {
177 vfree(rtlpriv->rtlhal.pfirmware);
178 rtlpriv->rtlhal.pfirmware = NULL;
179 }
180 }
181
182 /* get bt coexist status */
rtl8723be_get_btc_status(void)183 static bool rtl8723be_get_btc_status(void)
184 {
185 return true;
186 }
187
is_fw_header(struct rtlwifi_firmware_header * hdr)188 static bool is_fw_header(struct rtlwifi_firmware_header *hdr)
189 {
190 return (le16_to_cpu(hdr->signature) & 0xfff0) == 0x5300;
191 }
192
193 static struct rtl_hal_ops rtl8723be_hal_ops = {
194 .init_sw_vars = rtl8723be_init_sw_vars,
195 .deinit_sw_vars = rtl8723be_deinit_sw_vars,
196 .read_eeprom_info = rtl8723be_read_eeprom_info,
197 .interrupt_recognized = rtl8723be_interrupt_recognized,
198 .hw_init = rtl8723be_hw_init,
199 .hw_disable = rtl8723be_card_disable,
200 .hw_suspend = rtl8723be_suspend,
201 .hw_resume = rtl8723be_resume,
202 .enable_interrupt = rtl8723be_enable_interrupt,
203 .disable_interrupt = rtl8723be_disable_interrupt,
204 .set_network_type = rtl8723be_set_network_type,
205 .set_chk_bssid = rtl8723be_set_check_bssid,
206 .set_qos = rtl8723be_set_qos,
207 .set_bcn_reg = rtl8723be_set_beacon_related_registers,
208 .set_bcn_intv = rtl8723be_set_beacon_interval,
209 .update_interrupt_mask = rtl8723be_update_interrupt_mask,
210 .get_hw_reg = rtl8723be_get_hw_reg,
211 .set_hw_reg = rtl8723be_set_hw_reg,
212 .update_rate_tbl = rtl8723be_update_hal_rate_tbl,
213 .fill_tx_desc = rtl8723be_tx_fill_desc,
214 .fill_tx_cmddesc = rtl8723be_tx_fill_cmddesc,
215 .query_rx_desc = rtl8723be_rx_query_desc,
216 .set_channel_access = rtl8723be_update_channel_access_setting,
217 .radio_onoff_checking = rtl8723be_gpio_radio_on_off_checking,
218 .set_bw_mode = rtl8723be_phy_set_bw_mode,
219 .switch_channel = rtl8723be_phy_sw_chnl,
220 .dm_watchdog = rtl8723be_dm_watchdog,
221 .scan_operation_backup = rtl8723be_phy_scan_operation_backup,
222 .set_rf_power_state = rtl8723be_phy_set_rf_power_state,
223 .led_control = rtl8723be_led_control,
224 .set_desc = rtl8723be_set_desc,
225 .get_desc = rtl8723be_get_desc,
226 .is_tx_desc_closed = rtl8723be_is_tx_desc_closed,
227 .tx_polling = rtl8723be_tx_polling,
228 .enable_hw_sec = rtl8723be_enable_hw_security_config,
229 .set_key = rtl8723be_set_key,
230 .get_bbreg = rtl8723_phy_query_bb_reg,
231 .set_bbreg = rtl8723_phy_set_bb_reg,
232 .get_rfreg = rtl8723be_phy_query_rf_reg,
233 .set_rfreg = rtl8723be_phy_set_rf_reg,
234 .fill_h2c_cmd = rtl8723be_fill_h2c_cmd,
235 .get_btc_status = rtl8723be_get_btc_status,
236 .is_fw_header = is_fw_header,
237 };
238
239 static struct rtl_mod_params rtl8723be_mod_params = {
240 .sw_crypto = false,
241 .inactiveps = true,
242 .swctrl_lps = false,
243 .fwctrl_lps = true,
244 .msi_support = false,
245 .aspm_support = 1,
246 .disable_watchdog = false,
247 .debug_level = 0,
248 .debug_mask = 0,
249 .ant_sel = 0,
250 };
251
252 static const struct rtl_hal_cfg rtl8723be_hal_cfg = {
253 .bar_id = 2,
254 .write_readback = true,
255 .name = "rtl8723be_pci",
256 .alt_fw_name = "rtlwifi/rtl8723befw.bin",
257 .ops = &rtl8723be_hal_ops,
258 .mod_params = &rtl8723be_mod_params,
259 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
260 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
261 .maps[SYS_CLK] = REG_SYS_CLKR,
262 .maps[MAC_RCR_AM] = AM,
263 .maps[MAC_RCR_AB] = AB,
264 .maps[MAC_RCR_ACRC32] = ACRC32,
265 .maps[MAC_RCR_ACF] = ACF,
266 .maps[MAC_RCR_AAP] = AAP,
267 .maps[MAC_HIMR] = REG_HIMR,
268 .maps[MAC_HIMRE] = REG_HIMRE,
269 .maps[MAC_HSISR] = REG_HSISR,
270
271 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
272
273 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
274 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
275 .maps[EFUSE_CLK] = 0,
276 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
277 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
278 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
279 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
280 .maps[EFUSE_ANA8M] = ANA8M,
281 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
282 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
283 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
284 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
285
286 .maps[RWCAM] = REG_CAMCMD,
287 .maps[WCAMI] = REG_CAMWRITE,
288 .maps[RCAMO] = REG_CAMREAD,
289 .maps[CAMDBG] = REG_CAMDBG,
290 .maps[SECR] = REG_SECCFG,
291 .maps[SEC_CAM_NONE] = CAM_NONE,
292 .maps[SEC_CAM_WEP40] = CAM_WEP40,
293 .maps[SEC_CAM_TKIP] = CAM_TKIP,
294 .maps[SEC_CAM_AES] = CAM_AES,
295 .maps[SEC_CAM_WEP104] = CAM_WEP104,
296
297 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
298 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
299 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
300 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
301 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
302 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
303 /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
304 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
305 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
306 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
307 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
308 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
309 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
310 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
311 /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
312 /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
313
314 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
315 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
316 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
317 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
318 .maps[RTL_IMR_RDU] = IMR_RDU,
319 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
320 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
321 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
322 .maps[RTL_IMR_TBDER] = IMR_TBDER,
323 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
324 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
325 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
326 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
327 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
328 .maps[RTL_IMR_VODOK] = IMR_VODOK,
329 .maps[RTL_IMR_ROK] = IMR_ROK,
330 .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
331 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
332
333 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
334 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
335 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
336 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
337 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
338 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
339 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
340 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
341 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
342 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
343 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
344 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
345
346 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
347 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
348 };
349
350 static const struct pci_device_id rtl8723be_pci_ids[] = {
351 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xB723, rtl8723be_hal_cfg)},
352 {},
353 };
354
355 MODULE_DEVICE_TABLE(pci, rtl8723be_pci_ids);
356
357 MODULE_AUTHOR("PageHe <page_he@realsil.com.cn>");
358 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
359 MODULE_LICENSE("GPL");
360 MODULE_DESCRIPTION("Realtek 8723BE 802.11n PCI wireless");
361 MODULE_FIRMWARE("rtlwifi/rtl8723befw.bin");
362 MODULE_FIRMWARE("rtlwifi/rtl8723befw_36.bin");
363
364 module_param_named(swenc, rtl8723be_mod_params.sw_crypto, bool, 0444);
365 module_param_named(debug_level, rtl8723be_mod_params.debug_level, int, 0644);
366 module_param_named(debug_mask, rtl8723be_mod_params.debug_mask, ullong, 0644);
367 module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444);
368 module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444);
369 module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444);
370 module_param_named(msi, rtl8723be_mod_params.msi_support, bool, 0444);
371 module_param_named(aspm, rtl8723be_mod_params.aspm_support, int, 0444);
372 module_param_named(disable_watchdog, rtl8723be_mod_params.disable_watchdog,
373 bool, 0444);
374 module_param_named(ant_sel, rtl8723be_mod_params.ant_sel, int, 0444);
375 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
376 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
377 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
378 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
379 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
380 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
381 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
382 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
383 MODULE_PARM_DESC(disable_watchdog,
384 "Set to 1 to disable the watchdog (default 0)\n");
385 MODULE_PARM_DESC(ant_sel, "Set to 1 or 2 to force antenna number (default 0)\n");
386
387 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
388
389 static struct pci_driver rtl8723be_driver = {
390 .name = KBUILD_MODNAME,
391 .id_table = rtl8723be_pci_ids,
392 .probe = rtl_pci_probe,
393 .remove = rtl_pci_disconnect,
394 .driver.pm = &rtlwifi_pm_ops,
395 };
396
397 module_pci_driver(rtl8723be_driver);
398