1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MTMIPS SoCs Clock Driver
4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/clk-provider.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/reset-controller.h>
13 #include <linux/slab.h>
14
15 /* Configuration registers */
16 #define SYSC_REG_SYSTEM_CONFIG 0x10
17 #define SYSC_REG_CLKCFG0 0x2c
18 #define SYSC_REG_RESET_CTRL 0x34
19 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c
20 #define SYSC_REG_CPLL_CONFIG0 0x54
21 #define SYSC_REG_CPLL_CONFIG1 0x58
22
23 /* RT2880 SoC */
24 #define RT2880_CONFIG_CPUCLK_SHIFT 20
25 #define RT2880_CONFIG_CPUCLK_MASK 0x3
26 #define RT2880_CONFIG_CPUCLK_250 0x0
27 #define RT2880_CONFIG_CPUCLK_266 0x1
28 #define RT2880_CONFIG_CPUCLK_280 0x2
29 #define RT2880_CONFIG_CPUCLK_300 0x3
30
31 /* RT305X SoC */
32 #define RT305X_SYSCFG_CPUCLK_SHIFT 18
33 #define RT305X_SYSCFG_CPUCLK_MASK 0x1
34 #define RT305X_SYSCFG_CPUCLK_LOW 0x0
35 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1
36
37 /* RT3352 SoC */
38 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8
39 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1
40 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0
41 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
42
43 /* RT3383 SoC */
44 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
45 #define RT3883_SYSCFG0_CPUCLK_SHIFT 8
46 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3
47 #define RT3883_SYSCFG0_CPUCLK_250 0x0
48 #define RT3883_SYSCFG0_CPUCLK_384 0x1
49 #define RT3883_SYSCFG0_CPUCLK_480 0x2
50 #define RT3883_SYSCFG0_CPUCLK_500 0x3
51
52 /* RT5350 SoC */
53 #define RT5350_CLKCFG0_XTAL_SEL BIT(20)
54 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8
55 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3
56 #define RT5350_SYSCFG0_CPUCLK_360 0x0
57 #define RT5350_SYSCFG0_CPUCLK_320 0x2
58 #define RT5350_SYSCFG0_CPUCLK_300 0x3
59
60 /* MT7620 and MT76x8 SoCs */
61 #define MT7620_XTAL_FREQ_SEL BIT(6)
62 #define CPLL_CFG0_SW_CFG BIT(31)
63 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
64 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
65 #define CPLL_CFG0_LC_CURFCK BIT(15)
66 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
67 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
68 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
69 #define CPLL_CFG1_CPU_AUX1 BIT(25)
70 #define CPLL_CFG1_CPU_AUX0 BIT(24)
71 #define CLKCFG0_PERI_CLK_SEL BIT(4)
72 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
73 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
74 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
75 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
76 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
77 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
78 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
79 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
80 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
81 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
82 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
83 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
84 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
85 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
86 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
87
88 /* clock scaling */
89 #define CLKCFG_FDIV_MASK 0x1f00
90 #define CLKCFG_FDIV_USB_VAL 0x0300
91 #define CLKCFG_FFRAC_MASK 0x001f
92 #define CLKCFG_FFRAC_USB_VAL 0x0003
93
94 struct mtmips_clk;
95 struct mtmips_clk_fixed;
96 struct mtmips_clk_factor;
97
98 struct mtmips_clk_data {
99 struct mtmips_clk *clk_base;
100 size_t num_clk_base;
101 struct mtmips_clk_fixed *clk_fixed;
102 size_t num_clk_fixed;
103 struct mtmips_clk_factor *clk_factor;
104 size_t num_clk_factor;
105 struct mtmips_clk *clk_periph;
106 size_t num_clk_periph;
107 };
108
109 struct mtmips_clk_priv {
110 struct regmap *sysc;
111 const struct mtmips_clk_data *data;
112 };
113
114 struct mtmips_clk {
115 struct clk_hw hw;
116 struct mtmips_clk_priv *priv;
117 };
118
119 struct mtmips_clk_fixed {
120 const char *name;
121 const char *parent;
122 unsigned long rate;
123 struct clk_hw *hw;
124 };
125
126 struct mtmips_clk_factor {
127 const char *name;
128 const char *parent;
129 int mult;
130 int div;
131 unsigned long flags;
132 struct clk_hw *hw;
133 };
134
mtmips_pherip_clk_rate(struct clk_hw * hw,unsigned long parent_rate)135 static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
136 unsigned long parent_rate)
137 {
138 return parent_rate;
139 }
140
141 static const struct clk_ops mtmips_periph_clk_ops = {
142 .recalc_rate = mtmips_pherip_clk_rate,
143 };
144
145 #define CLK_PERIPH(_name, _parent) { \
146 .init = &(const struct clk_init_data) { \
147 .name = _name, \
148 .ops = &mtmips_periph_clk_ops, \
149 .parent_data = &(const struct clk_parent_data) {\
150 .name = _parent, \
151 .fw_name = _parent \
152 }, \
153 .num_parents = 1, \
154 /* \
155 * There are drivers for these SoCs that are \
156 * older than clock driver and are not prepared \
157 * for the clock. We don't want the kernel to \
158 * disable anything so we add CLK_IS_CRITICAL \
159 * flag here. \
160 */ \
161 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \
162 }, \
163 }
164
165 static struct mtmips_clk rt2880_pherip_clks[] = {
166 { CLK_PERIPH("300100.timer", "bus") },
167 { CLK_PERIPH("300120.watchdog", "bus") },
168 { CLK_PERIPH("300500.uart", "bus") },
169 { CLK_PERIPH("300900.i2c", "bus") },
170 { CLK_PERIPH("300c00.uartlite", "bus") },
171 { CLK_PERIPH("400000.ethernet", "bus") },
172 { CLK_PERIPH("480000.wmac", "xtal") }
173 };
174
175 static struct mtmips_clk rt305x_pherip_clks[] = {
176 { CLK_PERIPH("10000100.timer", "bus") },
177 { CLK_PERIPH("10000120.watchdog", "bus") },
178 { CLK_PERIPH("10000500.uart", "bus") },
179 { CLK_PERIPH("10000900.i2c", "bus") },
180 { CLK_PERIPH("10000a00.i2s", "bus") },
181 { CLK_PERIPH("10000b00.spi", "bus") },
182 { CLK_PERIPH("10000b40.spi", "bus") },
183 { CLK_PERIPH("10000c00.uartlite", "bus") },
184 { CLK_PERIPH("10100000.ethernet", "bus") },
185 { CLK_PERIPH("10180000.wmac", "xtal") }
186 };
187
188 static struct mtmips_clk rt5350_pherip_clks[] = {
189 { CLK_PERIPH("10000100.timer", "bus") },
190 { CLK_PERIPH("10000120.watchdog", "bus") },
191 { CLK_PERIPH("10000500.uart", "periph") },
192 { CLK_PERIPH("10000900.i2c", "periph") },
193 { CLK_PERIPH("10000a00.i2s", "periph") },
194 { CLK_PERIPH("10000b00.spi", "bus") },
195 { CLK_PERIPH("10000b40.spi", "bus") },
196 { CLK_PERIPH("10000c00.uartlite", "periph") },
197 { CLK_PERIPH("10100000.ethernet", "bus") },
198 { CLK_PERIPH("10180000.wmac", "xtal") }
199 };
200
201 static struct mtmips_clk mt7620_pherip_clks[] = {
202 { CLK_PERIPH("10000100.timer", "periph") },
203 { CLK_PERIPH("10000120.watchdog", "periph") },
204 { CLK_PERIPH("10000500.uart", "periph") },
205 { CLK_PERIPH("10000900.i2c", "periph") },
206 { CLK_PERIPH("10000a00.i2s", "periph") },
207 { CLK_PERIPH("10000b00.spi", "bus") },
208 { CLK_PERIPH("10000b40.spi", "bus") },
209 { CLK_PERIPH("10000c00.uartlite", "periph") },
210 { CLK_PERIPH("10180000.wmac", "xtal") }
211 };
212
213 static struct mtmips_clk mt76x8_pherip_clks[] = {
214 { CLK_PERIPH("10000100.timer", "periph") },
215 { CLK_PERIPH("10000120.watchdog", "periph") },
216 { CLK_PERIPH("10000900.i2c", "periph") },
217 { CLK_PERIPH("10000a00.i2s", "pcmi2s") },
218 { CLK_PERIPH("10000b00.spi", "bus") },
219 { CLK_PERIPH("10000b40.spi", "bus") },
220 { CLK_PERIPH("10000c00.uart0", "periph") },
221 { CLK_PERIPH("10000d00.uart1", "periph") },
222 { CLK_PERIPH("10000e00.uart2", "periph") },
223 { CLK_PERIPH("10300000.wmac", "xtal") }
224 };
225
mtmips_register_pherip_clocks(struct device_node * np,struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)226 static int mtmips_register_pherip_clocks(struct device_node *np,
227 struct clk_hw_onecell_data *clk_data,
228 struct mtmips_clk_priv *priv)
229 {
230 struct clk_hw **hws = clk_data->hws;
231 struct mtmips_clk *sclk;
232 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
233 priv->data->num_clk_factor;
234 int ret, i;
235
236 for (i = 0; i < priv->data->num_clk_periph; i++) {
237 int idx = idx_start + i;
238
239 sclk = &priv->data->clk_periph[i];
240 ret = of_clk_hw_register(np, &sclk->hw);
241 if (ret) {
242 pr_err("Couldn't register peripheral clock %d\n", idx);
243 goto err_clk_unreg;
244 }
245
246 hws[idx] = &sclk->hw;
247 }
248
249 return 0;
250
251 err_clk_unreg:
252 while (--i >= 0) {
253 sclk = &priv->data->clk_periph[i];
254 clk_hw_unregister(&sclk->hw);
255 }
256 return ret;
257 }
258
259 #define CLK_FIXED(_name, _parent, _rate) \
260 { \
261 .name = _name, \
262 .parent = _parent, \
263 .rate = _rate \
264 }
265
266 static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
267 CLK_FIXED("periph", "xtal", 40000000)
268 };
269
270 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
271 CLK_FIXED("periph", "xtal", 40000000)
272 };
273
274 static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
275 CLK_FIXED("pcmi2s", "xtal", 480000000),
276 CLK_FIXED("periph", "xtal", 40000000)
277 };
278
mtmips_register_fixed_clocks(struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)279 static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
280 struct mtmips_clk_priv *priv)
281 {
282 struct clk_hw **hws = clk_data->hws;
283 struct mtmips_clk_fixed *sclk;
284 size_t idx_start = priv->data->num_clk_base;
285 int ret, i;
286
287 for (i = 0; i < priv->data->num_clk_fixed; i++) {
288 int idx = idx_start + i;
289
290 sclk = &priv->data->clk_fixed[i];
291 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
292 sclk->parent, 0,
293 sclk->rate);
294 if (IS_ERR(sclk->hw)) {
295 ret = PTR_ERR(sclk->hw);
296 pr_err("Couldn't register fixed clock %d\n", idx);
297 goto err_clk_unreg;
298 }
299
300 hws[idx] = sclk->hw;
301 }
302
303 return 0;
304
305 err_clk_unreg:
306 while (--i >= 0) {
307 sclk = &priv->data->clk_fixed[i];
308 clk_hw_unregister_fixed_rate(sclk->hw);
309 }
310 return ret;
311 }
312
313 #define CLK_FACTOR(_name, _parent, _mult, _div) \
314 { \
315 .name = _name, \
316 .parent = _parent, \
317 .mult = _mult, \
318 .div = _div, \
319 .flags = CLK_SET_RATE_PARENT \
320 }
321
322 static struct mtmips_clk_factor rt2880_factor_clocks[] = {
323 CLK_FACTOR("bus", "cpu", 1, 2)
324 };
325
326 static struct mtmips_clk_factor rt305x_factor_clocks[] = {
327 CLK_FACTOR("bus", "cpu", 1, 3)
328 };
329
mtmips_register_factor_clocks(struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)330 static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
331 struct mtmips_clk_priv *priv)
332 {
333 struct clk_hw **hws = clk_data->hws;
334 struct mtmips_clk_factor *sclk;
335 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
336 int ret, i;
337
338 for (i = 0; i < priv->data->num_clk_factor; i++) {
339 int idx = idx_start + i;
340
341 sclk = &priv->data->clk_factor[i];
342 sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
343 sclk->parent, sclk->flags,
344 sclk->mult, sclk->div);
345 if (IS_ERR(sclk->hw)) {
346 ret = PTR_ERR(sclk->hw);
347 pr_err("Couldn't register factor clock %d\n", idx);
348 goto err_clk_unreg;
349 }
350
351 hws[idx] = sclk->hw;
352 }
353
354 return 0;
355
356 err_clk_unreg:
357 while (--i >= 0) {
358 sclk = &priv->data->clk_factor[i];
359 clk_hw_unregister_fixed_factor(sclk->hw);
360 }
361 return ret;
362 }
363
to_mtmips_clk(struct clk_hw * hw)364 static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
365 {
366 return container_of(hw, struct mtmips_clk, hw);
367 }
368
rt2880_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)369 static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw,
370 unsigned long parent_rate)
371 {
372 return 40000000;
373 }
374
rt5350_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)375 static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
376 unsigned long parent_rate)
377 {
378 struct mtmips_clk *clk = to_mtmips_clk(hw);
379 struct regmap *sysc = clk->priv->sysc;
380 u32 val;
381
382 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
383 if (!(val & RT5350_CLKCFG0_XTAL_SEL))
384 return 20000000;
385
386 return 40000000;
387 }
388
rt5350_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)389 static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
390 unsigned long xtal_clk)
391 {
392 struct mtmips_clk *clk = to_mtmips_clk(hw);
393 struct regmap *sysc = clk->priv->sysc;
394 u32 t;
395
396 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
397 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
398
399 switch (t) {
400 case RT5350_SYSCFG0_CPUCLK_360:
401 return 360000000;
402 case RT5350_SYSCFG0_CPUCLK_320:
403 return 320000000;
404 case RT5350_SYSCFG0_CPUCLK_300:
405 return 300000000;
406 default:
407 BUG();
408 }
409 }
410
rt5350_bus_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)411 static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
412 unsigned long parent_rate)
413 {
414 if (parent_rate == 320000000)
415 return parent_rate / 4;
416
417 return parent_rate / 3;
418 }
419
rt3352_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)420 static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
421 unsigned long xtal_clk)
422 {
423 struct mtmips_clk *clk = to_mtmips_clk(hw);
424 struct regmap *sysc = clk->priv->sysc;
425 u32 t;
426
427 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
428 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
429
430 switch (t) {
431 case RT3352_SYSCFG0_CPUCLK_LOW:
432 return 384000000;
433 case RT3352_SYSCFG0_CPUCLK_HIGH:
434 return 400000000;
435 default:
436 BUG();
437 }
438 }
439
rt305x_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)440 static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
441 unsigned long xtal_clk)
442 {
443 struct mtmips_clk *clk = to_mtmips_clk(hw);
444 struct regmap *sysc = clk->priv->sysc;
445 u32 t;
446
447 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
448 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
449
450 switch (t) {
451 case RT305X_SYSCFG_CPUCLK_LOW:
452 return 320000000;
453 case RT305X_SYSCFG_CPUCLK_HIGH:
454 return 384000000;
455 default:
456 BUG();
457 }
458 }
459
rt3883_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)460 static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
461 unsigned long xtal_clk)
462 {
463 struct mtmips_clk *clk = to_mtmips_clk(hw);
464 struct regmap *sysc = clk->priv->sysc;
465 u32 t;
466
467 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
468 t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
469
470 switch (t) {
471 case RT3883_SYSCFG0_CPUCLK_250:
472 return 250000000;
473 case RT3883_SYSCFG0_CPUCLK_384:
474 return 384000000;
475 case RT3883_SYSCFG0_CPUCLK_480:
476 return 480000000;
477 case RT3883_SYSCFG0_CPUCLK_500:
478 return 500000000;
479 default:
480 BUG();
481 }
482 }
483
rt3883_bus_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)484 static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
485 unsigned long parent_rate)
486 {
487 struct mtmips_clk *clk = to_mtmips_clk(hw);
488 struct regmap *sysc = clk->priv->sysc;
489 u32 ddr2;
490 u32 t;
491
492 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
493 ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
494
495 switch (parent_rate) {
496 case 250000000:
497 return (ddr2) ? 125000000 : 83000000;
498 case 384000000:
499 return (ddr2) ? 128000000 : 96000000;
500 case 480000000:
501 return (ddr2) ? 160000000 : 120000000;
502 case 500000000:
503 return (ddr2) ? 166000000 : 125000000;
504 default:
505 WARN_ON_ONCE(parent_rate == 0);
506 return parent_rate / 4;
507 }
508 }
509
rt2880_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)510 static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
511 unsigned long xtal_clk)
512 {
513 struct mtmips_clk *clk = to_mtmips_clk(hw);
514 struct regmap *sysc = clk->priv->sysc;
515 u32 t;
516
517 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
518 t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
519
520 switch (t) {
521 case RT2880_CONFIG_CPUCLK_250:
522 return 250000000;
523 case RT2880_CONFIG_CPUCLK_266:
524 return 266000000;
525 case RT2880_CONFIG_CPUCLK_280:
526 return 280000000;
527 case RT2880_CONFIG_CPUCLK_300:
528 return 300000000;
529 default:
530 BUG();
531 }
532 }
533
mt7620_calc_rate(u32 ref_rate,u32 mul,u32 div)534 static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
535 {
536 u64 t;
537
538 t = ref_rate;
539 t *= mul;
540 t = div_u64(t, div);
541
542 return t;
543 }
544
mt7620_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)545 static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
546 unsigned long parent_rate)
547 {
548 static const u32 clk_divider[] = { 2, 3, 4, 8 };
549 struct mtmips_clk *clk = to_mtmips_clk(hw);
550 struct regmap *sysc = clk->priv->sysc;
551 unsigned long cpu_pll;
552 u32 t;
553 u32 mul;
554 u32 div;
555
556 regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
557 if (t & CPLL_CFG0_BYPASS_REF_CLK) {
558 cpu_pll = parent_rate;
559 } else if ((t & CPLL_CFG0_SW_CFG) == 0) {
560 cpu_pll = 600000000;
561 } else {
562 mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
563 CPLL_CFG0_PLL_MULT_RATIO_MASK;
564 mul += 24;
565 if (t & CPLL_CFG0_LC_CURFCK)
566 mul *= 2;
567
568 div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
569 CPLL_CFG0_PLL_DIV_RATIO_MASK;
570
571 WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
572
573 cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
574 }
575
576 regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
577 if (t & CPLL_CFG1_CPU_AUX1)
578 return parent_rate;
579
580 if (t & CPLL_CFG1_CPU_AUX0)
581 return 480000000;
582
583 return cpu_pll;
584 }
585
mt7620_cpu_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)586 static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
587 unsigned long parent_rate)
588 {
589 struct mtmips_clk *clk = to_mtmips_clk(hw);
590 struct regmap *sysc = clk->priv->sysc;
591 u32 t;
592 u32 mul;
593 u32 div;
594
595 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
596 mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
597 div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
598 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
599
600 return mt7620_calc_rate(parent_rate, mul, div);
601 }
602
mt7620_bus_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)603 static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
604 unsigned long parent_rate)
605 {
606 static const u32 ocp_dividers[16] = {
607 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
608 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
609 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
610 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
611 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
612 };
613 struct mtmips_clk *clk = to_mtmips_clk(hw);
614 struct regmap *sysc = clk->priv->sysc;
615 u32 t;
616 u32 ocp_ratio;
617 u32 div;
618
619 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
620 ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
621 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
622
623 if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
624 return parent_rate;
625
626 div = ocp_dividers[ocp_ratio];
627
628 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
629 return parent_rate;
630
631 return parent_rate / div;
632 }
633
mt7620_periph_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)634 static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
635 unsigned long parent_rate)
636 {
637 struct mtmips_clk *clk = to_mtmips_clk(hw);
638 struct regmap *sysc = clk->priv->sysc;
639 u32 t;
640
641 regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
642 if (t & CLKCFG0_PERI_CLK_SEL)
643 return parent_rate;
644
645 return 40000000;
646 }
647
mt76x8_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)648 static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
649 unsigned long parent_rate)
650 {
651 struct mtmips_clk *clk = to_mtmips_clk(hw);
652 struct regmap *sysc = clk->priv->sysc;
653 u32 t;
654
655 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
656 if (t & MT7620_XTAL_FREQ_SEL)
657 return 40000000;
658
659 return 20000000;
660 }
661
mt76x8_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)662 static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
663 unsigned long xtal_clk)
664 {
665 if (xtal_clk == 40000000)
666 return 580000000;
667
668 return 575000000;
669 }
670
671 #define CLK_BASE(_name, _parent, _recalc) { \
672 .init = &(const struct clk_init_data) { \
673 .name = _name, \
674 .ops = &(const struct clk_ops) { \
675 .recalc_rate = _recalc, \
676 }, \
677 .parent_data = &(const struct clk_parent_data) { \
678 .name = _parent, \
679 .fw_name = _parent \
680 }, \
681 .num_parents = _parent ? 1 : 0 \
682 }, \
683 }
684
685 static struct mtmips_clk rt2880_clks_base[] = {
686 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
687 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
688 };
689
690 static struct mtmips_clk rt305x_clks_base[] = {
691 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
692 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
693 };
694
695 static struct mtmips_clk rt3352_clks_base[] = {
696 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
697 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
698 };
699
700 static struct mtmips_clk rt3883_clks_base[] = {
701 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
702 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
703 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
704 };
705
706 static struct mtmips_clk rt5350_clks_base[] = {
707 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
708 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
709 { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
710 };
711
712 static struct mtmips_clk mt7620_clks_base[] = {
713 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
714 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
715 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
716 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
717 { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
718 };
719
720 static struct mtmips_clk mt76x8_clks_base[] = {
721 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
722 { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
723 };
724
mtmips_register_clocks(struct device_node * np,struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)725 static int mtmips_register_clocks(struct device_node *np,
726 struct clk_hw_onecell_data *clk_data,
727 struct mtmips_clk_priv *priv)
728 {
729 struct clk_hw **hws = clk_data->hws;
730 struct mtmips_clk *sclk;
731 int ret, i;
732
733 for (i = 0; i < priv->data->num_clk_base; i++) {
734 sclk = &priv->data->clk_base[i];
735 sclk->priv = priv;
736 ret = of_clk_hw_register(np, &sclk->hw);
737 if (ret) {
738 pr_err("Couldn't register top clock %i\n", i);
739 goto err_clk_unreg;
740 }
741
742 hws[i] = &sclk->hw;
743 }
744
745 return 0;
746
747 err_clk_unreg:
748 while (--i >= 0) {
749 sclk = &priv->data->clk_base[i];
750 clk_hw_unregister(&sclk->hw);
751 }
752 return ret;
753 }
754
755 static const struct mtmips_clk_data rt2880_clk_data = {
756 .clk_base = rt2880_clks_base,
757 .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
758 .clk_fixed = NULL,
759 .num_clk_fixed = 0,
760 .clk_factor = rt2880_factor_clocks,
761 .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
762 .clk_periph = rt2880_pherip_clks,
763 .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
764 };
765
766 static const struct mtmips_clk_data rt305x_clk_data = {
767 .clk_base = rt305x_clks_base,
768 .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
769 .clk_fixed = NULL,
770 .num_clk_fixed = 0,
771 .clk_factor = rt305x_factor_clocks,
772 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
773 .clk_periph = rt305x_pherip_clks,
774 .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
775 };
776
777 static const struct mtmips_clk_data rt3352_clk_data = {
778 .clk_base = rt3352_clks_base,
779 .num_clk_base = ARRAY_SIZE(rt3352_clks_base),
780 .clk_fixed = rt3352_fixed_clocks,
781 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
782 .clk_factor = rt305x_factor_clocks,
783 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
784 .clk_periph = rt5350_pherip_clks,
785 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
786 };
787
788 static const struct mtmips_clk_data rt3883_clk_data = {
789 .clk_base = rt3883_clks_base,
790 .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
791 .clk_fixed = rt3883_fixed_clocks,
792 .num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),
793 .clk_factor = NULL,
794 .num_clk_factor = 0,
795 .clk_periph = rt5350_pherip_clks,
796 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
797 };
798
799 static const struct mtmips_clk_data rt5350_clk_data = {
800 .clk_base = rt5350_clks_base,
801 .num_clk_base = ARRAY_SIZE(rt5350_clks_base),
802 .clk_fixed = rt3352_fixed_clocks,
803 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
804 .clk_factor = NULL,
805 .num_clk_factor = 0,
806 .clk_periph = rt5350_pherip_clks,
807 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
808 };
809
810 static const struct mtmips_clk_data mt7620_clk_data = {
811 .clk_base = mt7620_clks_base,
812 .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
813 .clk_fixed = NULL,
814 .num_clk_fixed = 0,
815 .clk_factor = NULL,
816 .num_clk_factor = 0,
817 .clk_periph = mt7620_pherip_clks,
818 .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
819 };
820
821 static const struct mtmips_clk_data mt76x8_clk_data = {
822 .clk_base = mt76x8_clks_base,
823 .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
824 .clk_fixed = mt76x8_fixed_clocks,
825 .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
826 .clk_factor = rt305x_factor_clocks,
827 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
828 .clk_periph = mt76x8_pherip_clks,
829 .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
830 };
831
832 static const struct of_device_id mtmips_of_match[] = {
833 {
834 .compatible = "ralink,rt2880-reset",
835 .data = NULL,
836 },
837 {
838 .compatible = "ralink,rt2880-sysc",
839 .data = &rt2880_clk_data,
840 },
841 {
842 .compatible = "ralink,rt3050-sysc",
843 .data = &rt305x_clk_data,
844 },
845 {
846 .compatible = "ralink,rt3052-sysc",
847 .data = &rt305x_clk_data,
848 },
849 {
850 .compatible = "ralink,rt3352-sysc",
851 .data = &rt3352_clk_data,
852 },
853 {
854 .compatible = "ralink,rt3883-sysc",
855 .data = &rt3883_clk_data,
856 },
857 {
858 .compatible = "ralink,rt5350-sysc",
859 .data = &rt5350_clk_data,
860 },
861 {
862 .compatible = "ralink,mt7620-sysc",
863 .data = &mt7620_clk_data,
864 },
865 {
866 .compatible = "ralink,mt7628-sysc",
867 .data = &mt76x8_clk_data,
868 },
869 {
870 .compatible = "ralink,mt7688-sysc",
871 .data = &mt76x8_clk_data,
872 },
873 {}
874 };
875
mtmips_clk_regs_init(struct device_node * node,struct mtmips_clk_priv * priv)876 static void __init mtmips_clk_regs_init(struct device_node *node,
877 struct mtmips_clk_priv *priv)
878 {
879 u32 t;
880
881 if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
882 return;
883
884 /*
885 * When the CPU goes into sleep mode, the BUS
886 * clock will be too low for USB to function properly.
887 * Adjust the busses fractional divider to fix this
888 */
889 regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
890 t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
891 t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
892 regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
893 }
894
mtmips_clk_init(struct device_node * node)895 static void __init mtmips_clk_init(struct device_node *node)
896 {
897 const struct of_device_id *match;
898 const struct mtmips_clk_data *data;
899 struct mtmips_clk_priv *priv;
900 struct clk_hw_onecell_data *clk_data;
901 int ret, i, count;
902
903 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
904 if (!priv)
905 return;
906
907 priv->sysc = syscon_node_to_regmap(node);
908 if (IS_ERR(priv->sysc)) {
909 pr_err("Could not get sysc syscon regmap\n");
910 goto free_clk_priv;
911 }
912
913 mtmips_clk_regs_init(node, priv);
914
915 match = of_match_node(mtmips_of_match, node);
916 if (WARN_ON(!match))
917 return;
918
919 data = match->data;
920 priv->data = data;
921 count = priv->data->num_clk_base + priv->data->num_clk_fixed +
922 priv->data->num_clk_factor + priv->data->num_clk_periph;
923 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
924 if (!clk_data)
925 goto free_clk_priv;
926
927 ret = mtmips_register_clocks(node, clk_data, priv);
928 if (ret) {
929 pr_err("Couldn't register top clocks\n");
930 goto free_clk_data;
931 }
932
933 ret = mtmips_register_fixed_clocks(clk_data, priv);
934 if (ret) {
935 pr_err("Couldn't register fixed clocks\n");
936 goto unreg_clk_top;
937 }
938
939 ret = mtmips_register_factor_clocks(clk_data, priv);
940 if (ret) {
941 pr_err("Couldn't register factor clocks\n");
942 goto unreg_clk_fixed;
943 }
944
945 ret = mtmips_register_pherip_clocks(node, clk_data, priv);
946 if (ret) {
947 pr_err("Couldn't register peripheral clocks\n");
948 goto unreg_clk_factor;
949 }
950
951 clk_data->num = count;
952
953 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
954 if (ret) {
955 pr_err("Couldn't add clk hw provider\n");
956 goto unreg_clk_periph;
957 }
958
959 return;
960
961 unreg_clk_periph:
962 for (i = 0; i < priv->data->num_clk_periph; i++) {
963 struct mtmips_clk *sclk = &priv->data->clk_periph[i];
964
965 clk_hw_unregister(&sclk->hw);
966 }
967
968 unreg_clk_factor:
969 for (i = 0; i < priv->data->num_clk_factor; i++) {
970 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
971
972 clk_hw_unregister_fixed_factor(sclk->hw);
973 }
974
975 unreg_clk_fixed:
976 for (i = 0; i < priv->data->num_clk_fixed; i++) {
977 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
978
979 clk_hw_unregister_fixed_rate(sclk->hw);
980 }
981
982 unreg_clk_top:
983 for (i = 0; i < priv->data->num_clk_base; i++) {
984 struct mtmips_clk *sclk = &priv->data->clk_base[i];
985
986 clk_hw_unregister(&sclk->hw);
987 }
988
989 free_clk_data:
990 kfree(clk_data);
991
992 free_clk_priv:
993 kfree(priv);
994 }
995 CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
996 CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
997 CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
998 CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
999 CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
1000 CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
1001 CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
1002 CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
1003 CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
1004
1005 struct mtmips_rst {
1006 struct reset_controller_dev rcdev;
1007 struct regmap *sysc;
1008 };
1009
to_mtmips_rst(struct reset_controller_dev * dev)1010 static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
1011 {
1012 return container_of(dev, struct mtmips_rst, rcdev);
1013 }
1014
mtmips_assert_device(struct reset_controller_dev * rcdev,unsigned long id)1015 static int mtmips_assert_device(struct reset_controller_dev *rcdev,
1016 unsigned long id)
1017 {
1018 struct mtmips_rst *data = to_mtmips_rst(rcdev);
1019 struct regmap *sysc = data->sysc;
1020
1021 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
1022 }
1023
mtmips_deassert_device(struct reset_controller_dev * rcdev,unsigned long id)1024 static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
1025 unsigned long id)
1026 {
1027 struct mtmips_rst *data = to_mtmips_rst(rcdev);
1028 struct regmap *sysc = data->sysc;
1029
1030 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
1031 }
1032
mtmips_reset_device(struct reset_controller_dev * rcdev,unsigned long id)1033 static int mtmips_reset_device(struct reset_controller_dev *rcdev,
1034 unsigned long id)
1035 {
1036 int ret;
1037
1038 ret = mtmips_assert_device(rcdev, id);
1039 if (ret < 0)
1040 return ret;
1041
1042 return mtmips_deassert_device(rcdev, id);
1043 }
1044
mtmips_rst_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)1045 static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
1046 const struct of_phandle_args *reset_spec)
1047 {
1048 unsigned long id = reset_spec->args[0];
1049
1050 if (id == 0 || id >= rcdev->nr_resets)
1051 return -EINVAL;
1052
1053 return id;
1054 }
1055
1056 static const struct reset_control_ops reset_ops = {
1057 .reset = mtmips_reset_device,
1058 .assert = mtmips_assert_device,
1059 .deassert = mtmips_deassert_device
1060 };
1061
mtmips_reset_init(struct device * dev,struct regmap * sysc)1062 static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
1063 {
1064 struct mtmips_rst *rst_data;
1065
1066 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
1067 if (!rst_data)
1068 return -ENOMEM;
1069
1070 rst_data->sysc = sysc;
1071 rst_data->rcdev.ops = &reset_ops;
1072 rst_data->rcdev.owner = THIS_MODULE;
1073 rst_data->rcdev.nr_resets = 32;
1074 rst_data->rcdev.of_reset_n_cells = 1;
1075 rst_data->rcdev.of_xlate = mtmips_rst_xlate;
1076 rst_data->rcdev.of_node = dev_of_node(dev);
1077
1078 return devm_reset_controller_register(dev, &rst_data->rcdev);
1079 }
1080
mtmips_clk_probe(struct platform_device * pdev)1081 static int mtmips_clk_probe(struct platform_device *pdev)
1082 {
1083 struct device_node *np = pdev->dev.of_node;
1084 struct device *dev = &pdev->dev;
1085 struct mtmips_clk_priv *priv;
1086 int ret;
1087
1088 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1089 if (!priv)
1090 return -ENOMEM;
1091
1092 priv->sysc = syscon_node_to_regmap(np);
1093 if (IS_ERR(priv->sysc))
1094 return dev_err_probe(dev, PTR_ERR(priv->sysc),
1095 "Could not get sysc syscon regmap\n");
1096
1097 ret = mtmips_reset_init(dev, priv->sysc);
1098 if (ret)
1099 return dev_err_probe(dev, ret, "Could not init reset controller\n");
1100
1101 return 0;
1102 }
1103
1104 static struct platform_driver mtmips_clk_driver = {
1105 .probe = mtmips_clk_probe,
1106 .driver = {
1107 .name = "mtmips-clk",
1108 .of_match_table = mtmips_of_match,
1109 },
1110 };
1111
mtmips_clk_reset_init(void)1112 static int __init mtmips_clk_reset_init(void)
1113 {
1114 return platform_driver_register(&mtmips_clk_driver);
1115 }
1116 arch_initcall(mtmips_clk_reset_init);
1117