xref: /openbmc/linux/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004) 
1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
4   */
5  
6  #ifndef _SUN8I_DW_HDMI_H_
7  #define _SUN8I_DW_HDMI_H_
8  
9  #include <drm/bridge/dw_hdmi.h>
10  #include <drm/drm_encoder.h>
11  #include <linux/clk.h>
12  #include <linux/regmap.h>
13  #include <linux/regulator/consumer.h>
14  #include <linux/reset.h>
15  
16  #define SUN8I_HDMI_PHY_DBG_CTRL_REG	0x0000
17  #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK		BIT(0)
18  #define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK	GENMASK(15, 8)
19  #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC	BIT(8)
20  #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC	BIT(9)
21  #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK	GENMASK(23, 16)
22  #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr)	(addr << 16)
23  
24  #define SUN8I_HDMI_PHY_REXT_CTRL_REG	0x0004
25  #define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN	BIT(31)
26  
27  #define SUN8I_HDMI_PHY_READ_EN_REG	0x0010
28  #define SUN8I_HDMI_PHY_READ_EN_MAGIC		0x54524545
29  
30  #define SUN8I_HDMI_PHY_UNSCRAMBLE_REG	0x0014
31  #define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC		0x42494E47
32  
33  #define SUN8I_HDMI_PHY_ANA_CFG1_REG	0x0020
34  #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI		BIT(31)
35  #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND	BIT(30)
36  #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC	BIT(29)
37  #define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW	BIT(28)
38  #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVRCAL(x)	((x) << 26)
39  #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(x)	((x) << 24)
40  #define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT		BIT(23)
41  #define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT		BIT(22)
42  #define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT	BIT(21)
43  #define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT	BIT(20)
44  #define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL		BIT(19)
45  #define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG		BIT(18)
46  #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS	BIT(17)
47  #define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN	BIT(16)
48  #define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK	GENMASK(15, 12)
49  #define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL	(0xf << 12)
50  #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK	BIT(11)
51  #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2	BIT(10)
52  #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1	BIT(9)
53  #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0	BIT(8)
54  #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK	BIT(7)
55  #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2	BIT(6)
56  #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1	BIT(5)
57  #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0	BIT(4)
58  #define SUN8I_HDMI_PHY_ANA_CFG1_CKEN		BIT(3)
59  #define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN		BIT(2)
60  #define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS		BIT(1)
61  #define SUN8I_HDMI_PHY_ANA_CFG1_ENBI		BIT(0)
62  
63  #define SUN8I_HDMI_PHY_ANA_CFG2_REG	0x0024
64  #define SUN8I_HDMI_PHY_ANA_CFG2_M_EN		BIT(31)
65  #define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN		BIT(30)
66  #define SUN8I_HDMI_PHY_ANA_CFG2_SEN		BIT(29)
67  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD	BIT(28)
68  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN	BIT(27)
69  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK	BIT(26)
70  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLR(x)	((x) << 23)
71  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK	BIT(22)
72  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN		BIT(21)
73  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_CD(x)	((x) << 19)
74  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(x)	((x) << 17)
75  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK	BIT(16)
76  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW	BIT(15)
77  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(x)	((x) << 13)
78  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(x)	((x) << 10)
79  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOSTCK(x)	((x) << 8)
80  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOST(x)	((x) << 6)
81  #define SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(x)	((x) << 0)
82  
83  #define SUN8I_HDMI_PHY_ANA_CFG3_REG	0x0028
84  #define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOWCK(x)	((x) << 30)
85  #define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOW(x)	((x) << 28)
86  #define SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(x)	((x) << 18)
87  #define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(x)	((x) << 14)
88  #define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMPCK(x)	((x) << 11)
89  #define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(x)	((x) << 7)
90  #define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(x)	((x) << 4)
91  #define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD		BIT(3)
92  #define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN		BIT(2)
93  #define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD		BIT(1)
94  #define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN		BIT(0)
95  
96  #define SUN8I_HDMI_PHY_PLL_CFG1_REG	0x002c
97  #define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1		BIT(31)
98  #define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD		BIT(30)
99  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN		BIT(29)
100  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN		BIT(28)
101  #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33	BIT(27)
102  #define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK	BIT(26)
103  #define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT	26
104  #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN		BIT(25)
105  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x)	((x) << 22)
106  #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x)	((x) << 20)
107  #define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN		BIT(19)
108  #define SUN8I_HDMI_PHY_PLL_CFG1_CS		BIT(18)
109  #define SUN8I_HDMI_PHY_PLL_CFG1_CP_S(x)		((x) << 13)
110  #define SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(x)	((x) << 7)
111  #define SUN8I_HDMI_PHY_PLL_CFG1_BWS		BIT(6)
112  #define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK	GENMASK(5, 0)
113  #define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT	0
114  
115  #define SUN8I_HDMI_PHY_PLL_CFG2_REG	0x0030
116  #define SUN8I_HDMI_PHY_PLL_CFG2_SV_H		BIT(31)
117  #define SUN8I_HDMI_PHY_PLL_CFG2_PDCLKSEL(x)	((x) << 29)
118  #define SUN8I_HDMI_PHY_PLL_CFG2_CLKSTEP(x)	((x) << 27)
119  #define SUN8I_HDMI_PHY_PLL_CFG2_PSET(x)		((x) << 24)
120  #define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL	BIT(23)
121  #define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS	BIT(22)
122  #define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN	BIT(21)
123  #define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN	BIT(20)
124  #define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN	BIT(19)
125  #define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN(x)	((x) << 16)
126  #define SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(x)	((x) << 12)
127  #define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN	BIT(11)
128  #define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC	BIT(10)
129  #define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2		BIT(9)
130  #define SUN8I_HDMI_PHY_PLL_CFG2_S(x)		((x) << 6)
131  #define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5	BIT(5)
132  #define SUN8I_HDMI_PHY_PLL_CFG2_S5_7		BIT(4)
133  #define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK	GENMASK(3, 0)
134  #define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT	0
135  #define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(x)	(((x) - 1) << 0)
136  
137  #define SUN8I_HDMI_PHY_PLL_CFG3_REG	0x0034
138  #define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2	BIT(0)
139  
140  #define SUN8I_HDMI_PHY_ANA_STS_REG	0x0038
141  #define SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT	11
142  #define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK	GENMASK(16, 11)
143  #define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D	BIT(7)
144  #define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK	GENMASK(5, 0)
145  
146  #define SUN8I_HDMI_PHY_CEC_REG		0x003c
147  
148  struct sun8i_hdmi_phy;
149  
150  struct sun8i_hdmi_phy_variant {
151  	bool has_phy_clk;
152  	bool has_second_pll;
153  	const struct dw_hdmi_curr_ctrl *cur_ctr;
154  	const struct dw_hdmi_mpll_config *mpll_cfg;
155  	const struct dw_hdmi_phy_config *phy_cfg;
156  	const struct dw_hdmi_phy_ops *phy_ops;
157  	void (*phy_init)(struct sun8i_hdmi_phy *phy);
158  };
159  
160  struct sun8i_hdmi_phy {
161  	struct clk			*clk_bus;
162  	struct clk			*clk_mod;
163  	struct clk			*clk_phy;
164  	struct clk			*clk_pll0;
165  	struct clk			*clk_pll1;
166  	struct device			*dev;
167  	unsigned int			rcal;
168  	struct regmap			*regs;
169  	struct reset_control		*rst_phy;
170  	const struct sun8i_hdmi_phy_variant *variant;
171  };
172  
173  struct sun8i_dw_hdmi_quirks {
174  	enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data,
175  					   const struct drm_display_info *info,
176  					   const struct drm_display_mode *mode);
177  	unsigned int use_drm_infoframe : 1;
178  };
179  
180  struct sun8i_dw_hdmi {
181  	struct clk			*clk_tmds;
182  	struct device			*dev;
183  	struct dw_hdmi			*hdmi;
184  	struct drm_encoder		encoder;
185  	struct sun8i_hdmi_phy		*phy;
186  	struct dw_hdmi_plat_data	plat_data;
187  	struct regulator		*regulator;
188  	const struct sun8i_dw_hdmi_quirks *quirks;
189  	struct reset_control		*rst_ctrl;
190  };
191  
192  extern struct platform_driver sun8i_hdmi_phy_driver;
193  
194  static inline struct sun8i_dw_hdmi *
encoder_to_sun8i_dw_hdmi(struct drm_encoder * encoder)195  encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
196  {
197  	return container_of(encoder, struct sun8i_dw_hdmi, encoder);
198  }
199  
200  int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
201  
202  int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
203  void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy);
204  void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
205  			    struct dw_hdmi_plat_data *plat_data);
206  
207  int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
208  			 bool second_parent);
209  
210  #endif /* _SUN8I_DW_HDMI_H_ */
211