1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 - 2018 Xilinx, Inc.
4  */
5 
6 #define VERSAL_CRL_APB_BASEADDR	0xFF5E0000
7 
8 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	BIT(25)
9 
10 #define IOU_SWITCH_CTRL_CLKACT_BIT	BIT(25)
11 #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT	8
12 
13 struct crlapb_regs {
14 	u32 reserved0[67];
15 	u32 cpu_r5_ctrl;
16 	u32 reserved;
17 	u32 iou_switch_ctrl; /* 0x114 */
18 	u32 reserved1[13];
19 	u32 timestamp_ref_ctrl; /* 0x14c */
20 	u32 reserved3[108];
21 	u32 rst_cpu_r5;
22 	u32 reserved2[17];
23 	u32 rst_timestamp; /* 0x348 */
24 };
25 
26 #define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR)
27 
28 #define VERSAL_IOU_SCNTR_SECURE	0xFF140000
29 
30 #define IOU_SCNTRS_CONTROL_EN	1
31 
32 struct iou_scntrs_regs {
33 	u32 counter_control_register; /* 0x0 */
34 	u32 reserved0[7];
35 	u32 base_frequency_id_register; /* 0x20 */
36 };
37 
38 #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE)
39 
40 #define VERSAL_TCM_BASE_ADDR	0xFFE00000
41 #define VERSAL_TCM_SIZE		0x40000
42 
43 #define VERSAL_RPU_BASEADDR	0xFF9A0000
44 
45 struct rpu_regs {
46 	u32 rpu_glbl_ctrl;
47 	u32 reserved0[63];
48 	u32 rpu0_cfg; /* 0x100 */
49 	u32 reserved1[63];
50 	u32 rpu1_cfg; /* 0x200 */
51 };
52 
53 #define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR)
54