1 /* 2 * OMAP44xx EMIF header 3 * 4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 5 * 6 * Aneesh V <aneesh@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef _EMIF_H_ 14 #define _EMIF_H_ 15 #include <asm/types.h> 16 #include <common.h> 17 #include <asm/io.h> 18 19 /* Base address */ 20 #ifndef EMIF1_BASE 21 #define EMIF1_BASE 0x4c000000 22 #endif 23 #define EMIF2_BASE 0x4d000000 24 25 #define EMIF_4D 0x4 26 #define EMIF_4D5 0x5 27 28 /* Registers shifts, masks and values */ 29 30 /* EMIF_MOD_ID_REV */ 31 #define EMIF_REG_SCHEME_SHIFT 30 32 #define EMIF_REG_SCHEME_MASK (0x3 << 30) 33 #define EMIF_REG_MODULE_ID_SHIFT 16 34 #define EMIF_REG_MODULE_ID_MASK (0xfff << 16) 35 #define EMIF_REG_RTL_VERSION_SHIFT 11 36 #define EMIF_REG_RTL_VERSION_MASK (0x1f << 11) 37 #define EMIF_REG_MAJOR_REVISION_SHIFT 8 38 #define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) 39 #define EMIF_REG_MINOR_REVISION_SHIFT 0 40 #define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0) 41 42 /* STATUS */ 43 #define EMIF_REG_BE_SHIFT 31 44 #define EMIF_REG_BE_MASK (1 << 31) 45 #define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 46 #define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) 47 #define EMIF_REG_FAST_INIT_SHIFT 29 48 #define EMIF_REG_FAST_INIT_MASK (1 << 29) 49 #define EMIF_REG_LEVLING_TO_SHIFT 4 50 #define EMIF_REG_LEVELING_TO_MASK (7 << 4) 51 #define EMIF_REG_PHY_DLL_READY_SHIFT 2 52 #define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) 53 54 /* SDRAM_CONFIG */ 55 #define EMIF_REG_SDRAM_TYPE_SHIFT 29 56 #define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) 57 #define EMIF_REG_SDRAM_TYPE_DDR1 0 58 #define EMIF_REG_SDRAM_TYPE_LPDDR1 1 59 #define EMIF_REG_SDRAM_TYPE_DDR2 2 60 #define EMIF_REG_SDRAM_TYPE_DDR3 3 61 #define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4 62 #define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5 63 #define EMIF_REG_IBANK_POS_SHIFT 27 64 #define EMIF_REG_IBANK_POS_MASK (0x3 << 27) 65 #define EMIF_REG_DDR_TERM_SHIFT 24 66 #define EMIF_REG_DDR_TERM_MASK (0x7 << 24) 67 #define EMIF_REG_DDR2_DDQS_SHIFT 23 68 #define EMIF_REG_DDR2_DDQS_MASK (1 << 23) 69 #define EMIF_REG_DYN_ODT_SHIFT 21 70 #define EMIF_REG_DYN_ODT_MASK (0x3 << 21) 71 #define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 72 #define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) 73 #define EMIF_REG_SDRAM_DRIVE_SHIFT 18 74 #define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) 75 #define EMIF_REG_CWL_SHIFT 16 76 #define EMIF_REG_CWL_MASK (0x3 << 16) 77 #define EMIF_REG_NARROW_MODE_SHIFT 14 78 #define EMIF_REG_NARROW_MODE_MASK (0x3 << 14) 79 #define EMIF_REG_CL_SHIFT 10 80 #define EMIF_REG_CL_MASK (0xf << 10) 81 #define EMIF_REG_ROWSIZE_SHIFT 7 82 #define EMIF_REG_ROWSIZE_MASK (0x7 << 7) 83 #define EMIF_REG_IBANK_SHIFT 4 84 #define EMIF_REG_IBANK_MASK (0x7 << 4) 85 #define EMIF_REG_EBANK_SHIFT 3 86 #define EMIF_REG_EBANK_MASK (1 << 3) 87 #define EMIF_REG_PAGESIZE_SHIFT 0 88 #define EMIF_REG_PAGESIZE_MASK (0x7 << 0) 89 90 /* SDRAM_CONFIG_2 */ 91 #define EMIF_REG_CS1NVMEN_SHIFT 30 92 #define EMIF_REG_CS1NVMEN_MASK (1 << 30) 93 #define EMIF_REG_EBANK_POS_SHIFT 27 94 #define EMIF_REG_EBANK_POS_MASK (1 << 27) 95 #define EMIF_REG_RDBNUM_SHIFT 4 96 #define EMIF_REG_RDBNUM_MASK (0x3 << 4) 97 #define EMIF_REG_RDBSIZE_SHIFT 0 98 #define EMIF_REG_RDBSIZE_MASK (0x7 << 0) 99 100 /* SDRAM_REF_CTRL */ 101 #define EMIF_REG_INITREF_DIS_SHIFT 31 102 #define EMIF_REG_INITREF_DIS_MASK (1 << 31) 103 #define EMIF_REG_SRT_SHIFT 29 104 #define EMIF_REG_SRT_MASK (1 << 29) 105 #define EMIF_REG_ASR_SHIFT 28 106 #define EMIF_REG_ASR_MASK (1 << 28) 107 #define EMIF_REG_PASR_SHIFT 24 108 #define EMIF_REG_PASR_MASK (0x7 << 24) 109 #define EMIF_REG_REFRESH_RATE_SHIFT 0 110 #define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0) 111 112 /* SDRAM_REF_CTRL_SHDW */ 113 #define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0 114 #define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) 115 116 /* SDRAM_TIM_1 */ 117 #define EMIF_REG_T_RP_SHIFT 25 118 #define EMIF_REG_T_RP_MASK (0xf << 25) 119 #define EMIF_REG_T_RCD_SHIFT 21 120 #define EMIF_REG_T_RCD_MASK (0xf << 21) 121 #define EMIF_REG_T_WR_SHIFT 17 122 #define EMIF_REG_T_WR_MASK (0xf << 17) 123 #define EMIF_REG_T_RAS_SHIFT 12 124 #define EMIF_REG_T_RAS_MASK (0x1f << 12) 125 #define EMIF_REG_T_RC_SHIFT 6 126 #define EMIF_REG_T_RC_MASK (0x3f << 6) 127 #define EMIF_REG_T_RRD_SHIFT 3 128 #define EMIF_REG_T_RRD_MASK (0x7 << 3) 129 #define EMIF_REG_T_WTR_SHIFT 0 130 #define EMIF_REG_T_WTR_MASK (0x7 << 0) 131 132 /* SDRAM_TIM_1_SHDW */ 133 #define EMIF_REG_T_RP_SHDW_SHIFT 25 134 #define EMIF_REG_T_RP_SHDW_MASK (0xf << 25) 135 #define EMIF_REG_T_RCD_SHDW_SHIFT 21 136 #define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21) 137 #define EMIF_REG_T_WR_SHDW_SHIFT 17 138 #define EMIF_REG_T_WR_SHDW_MASK (0xf << 17) 139 #define EMIF_REG_T_RAS_SHDW_SHIFT 12 140 #define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12) 141 #define EMIF_REG_T_RC_SHDW_SHIFT 6 142 #define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6) 143 #define EMIF_REG_T_RRD_SHDW_SHIFT 3 144 #define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3) 145 #define EMIF_REG_T_WTR_SHDW_SHIFT 0 146 #define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0) 147 148 /* SDRAM_TIM_2 */ 149 #define EMIF_REG_T_XP_SHIFT 28 150 #define EMIF_REG_T_XP_MASK (0x7 << 28) 151 #define EMIF_REG_T_ODT_SHIFT 25 152 #define EMIF_REG_T_ODT_MASK (0x7 << 25) 153 #define EMIF_REG_T_XSNR_SHIFT 16 154 #define EMIF_REG_T_XSNR_MASK (0x1ff << 16) 155 #define EMIF_REG_T_XSRD_SHIFT 6 156 #define EMIF_REG_T_XSRD_MASK (0x3ff << 6) 157 #define EMIF_REG_T_RTP_SHIFT 3 158 #define EMIF_REG_T_RTP_MASK (0x7 << 3) 159 #define EMIF_REG_T_CKE_SHIFT 0 160 #define EMIF_REG_T_CKE_MASK (0x7 << 0) 161 162 /* SDRAM_TIM_2_SHDW */ 163 #define EMIF_REG_T_XP_SHDW_SHIFT 28 164 #define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28) 165 #define EMIF_REG_T_ODT_SHDW_SHIFT 25 166 #define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25) 167 #define EMIF_REG_T_XSNR_SHDW_SHIFT 16 168 #define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16) 169 #define EMIF_REG_T_XSRD_SHDW_SHIFT 6 170 #define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6) 171 #define EMIF_REG_T_RTP_SHDW_SHIFT 3 172 #define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3) 173 #define EMIF_REG_T_CKE_SHDW_SHIFT 0 174 #define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0) 175 176 /* SDRAM_TIM_3 */ 177 #define EMIF_REG_T_CKESR_SHIFT 21 178 #define EMIF_REG_T_CKESR_MASK (0x7 << 21) 179 #define EMIF_REG_ZQ_ZQCS_SHIFT 15 180 #define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15) 181 #define EMIF_REG_T_TDQSCKMAX_SHIFT 13 182 #define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13) 183 #define EMIF_REG_T_RFC_SHIFT 4 184 #define EMIF_REG_T_RFC_MASK (0x1ff << 4) 185 #define EMIF_REG_T_RAS_MAX_SHIFT 0 186 #define EMIF_REG_T_RAS_MAX_MASK (0xf << 0) 187 188 /* SDRAM_TIM_3_SHDW */ 189 #define EMIF_REG_T_CKESR_SHDW_SHIFT 21 190 #define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21) 191 #define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15 192 #define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) 193 #define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13 194 #define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) 195 #define EMIF_REG_T_RFC_SHDW_SHIFT 4 196 #define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4) 197 #define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0 198 #define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) 199 200 /* LPDDR2_NVM_TIM */ 201 #define EMIF_REG_NVM_T_XP_SHIFT 28 202 #define EMIF_REG_NVM_T_XP_MASK (0x7 << 28) 203 #define EMIF_REG_NVM_T_WTR_SHIFT 24 204 #define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24) 205 #define EMIF_REG_NVM_T_RP_SHIFT 20 206 #define EMIF_REG_NVM_T_RP_MASK (0xf << 20) 207 #define EMIF_REG_NVM_T_WRA_SHIFT 16 208 #define EMIF_REG_NVM_T_WRA_MASK (0xf << 16) 209 #define EMIF_REG_NVM_T_RRD_SHIFT 8 210 #define EMIF_REG_NVM_T_RRD_MASK (0xff << 8) 211 #define EMIF_REG_NVM_T_RCDMIN_SHIFT 0 212 #define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0) 213 214 /* LPDDR2_NVM_TIM_SHDW */ 215 #define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28 216 #define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) 217 #define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24 218 #define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) 219 #define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20 220 #define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20) 221 #define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16 222 #define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) 223 #define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8 224 #define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) 225 #define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 226 #define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) 227 228 /* PWR_MGMT_CTRL */ 229 #define EMIF_REG_IDLEMODE_SHIFT 30 230 #define EMIF_REG_IDLEMODE_MASK (0x3 << 30) 231 #define EMIF_REG_PD_TIM_SHIFT 12 232 #define EMIF_REG_PD_TIM_MASK (0xf << 12) 233 #define EMIF_REG_DPD_EN_SHIFT 11 234 #define EMIF_REG_DPD_EN_MASK (1 << 11) 235 #define EMIF_REG_LP_MODE_SHIFT 8 236 #define EMIF_REG_LP_MODE_MASK (0x7 << 8) 237 #define EMIF_REG_SR_TIM_SHIFT 4 238 #define EMIF_REG_SR_TIM_MASK (0xf << 4) 239 #define EMIF_REG_CS_TIM_SHIFT 0 240 #define EMIF_REG_CS_TIM_MASK (0xf << 0) 241 242 /* PWR_MGMT_CTRL_SHDW */ 243 #define EMIF_REG_PD_TIM_SHDW_SHIFT 12 244 #define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12) 245 #define EMIF_REG_SR_TIM_SHDW_SHIFT 4 246 #define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) 247 #define EMIF_REG_CS_TIM_SHDW_SHIFT 0 248 #define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0) 249 250 /* LPDDR2_MODE_REG_DATA */ 251 #define EMIF_REG_VALUE_0_SHIFT 0 252 #define EMIF_REG_VALUE_0_MASK (0x7f << 0) 253 254 /* LPDDR2_MODE_REG_CFG */ 255 #define EMIF_REG_CS_SHIFT 31 256 #define EMIF_REG_CS_MASK (1 << 31) 257 #define EMIF_REG_REFRESH_EN_SHIFT 30 258 #define EMIF_REG_REFRESH_EN_MASK (1 << 30) 259 #define EMIF_REG_ADDRESS_SHIFT 0 260 #define EMIF_REG_ADDRESS_MASK (0xff << 0) 261 262 /* OCP_CONFIG */ 263 #define EMIF_REG_SYS_THRESH_MAX_SHIFT 24 264 #define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24) 265 #define EMIF_REG_MPU_THRESH_MAX_SHIFT 20 266 #define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20) 267 #define EMIF_REG_LL_THRESH_MAX_SHIFT 16 268 #define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16) 269 #define EMIF_REG_PR_OLD_COUNT_SHIFT 0 270 #define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0) 271 272 /* OCP_CFG_VAL_1 */ 273 #define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30 274 #define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) 275 #define EMIF_REG_LL_BUS_WIDTH_SHIFT 28 276 #define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28) 277 #define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8 278 #define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8) 279 #define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0 280 #define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) 281 282 /* OCP_CFG_VAL_2 */ 283 #define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16 284 #define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) 285 #define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8 286 #define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) 287 #define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0 288 #define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) 289 290 /* IODFT_TLGC */ 291 #define EMIF_REG_TLEC_SHIFT 16 292 #define EMIF_REG_TLEC_MASK (0xffff << 16) 293 #define EMIF_REG_MT_SHIFT 14 294 #define EMIF_REG_MT_MASK (1 << 14) 295 #define EMIF_REG_ACT_CAP_EN_SHIFT 13 296 #define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) 297 #define EMIF_REG_OPG_LD_SHIFT 12 298 #define EMIF_REG_OPG_LD_MASK (1 << 12) 299 #define EMIF_REG_RESET_PHY_SHIFT 10 300 #define EMIF_REG_RESET_PHY_MASK (1 << 10) 301 #define EMIF_REG_MMS_SHIFT 8 302 #define EMIF_REG_MMS_MASK (1 << 8) 303 #define EMIF_REG_MC_SHIFT 4 304 #define EMIF_REG_MC_MASK (0x3 << 4) 305 #define EMIF_REG_PC_SHIFT 1 306 #define EMIF_REG_PC_MASK (0x7 << 1) 307 #define EMIF_REG_TM_SHIFT 0 308 #define EMIF_REG_TM_MASK (1 << 0) 309 310 /* IODFT_CTRL_MISR_RSLT */ 311 #define EMIF_REG_DQM_TLMR_SHIFT 16 312 #define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16) 313 #define EMIF_REG_CTL_TLMR_SHIFT 0 314 #define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0) 315 316 /* IODFT_ADDR_MISR_RSLT */ 317 #define EMIF_REG_ADDR_TLMR_SHIFT 0 318 #define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0) 319 320 /* IODFT_DATA_MISR_RSLT_1 */ 321 #define EMIF_REG_DATA_TLMR_31_0_SHIFT 0 322 #define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) 323 324 /* IODFT_DATA_MISR_RSLT_2 */ 325 #define EMIF_REG_DATA_TLMR_63_32_SHIFT 0 326 #define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) 327 328 /* IODFT_DATA_MISR_RSLT_3 */ 329 #define EMIF_REG_DATA_TLMR_66_64_SHIFT 0 330 #define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0) 331 332 /* PERF_CNT_1 */ 333 #define EMIF_REG_COUNTER1_SHIFT 0 334 #define EMIF_REG_COUNTER1_MASK (0xffffffff << 0) 335 336 /* PERF_CNT_2 */ 337 #define EMIF_REG_COUNTER2_SHIFT 0 338 #define EMIF_REG_COUNTER2_MASK (0xffffffff << 0) 339 340 /* PERF_CNT_CFG */ 341 #define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 342 #define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) 343 #define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 344 #define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) 345 #define EMIF_REG_CNTR2_CFG_SHIFT 16 346 #define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) 347 #define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 348 #define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) 349 #define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 350 #define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) 351 #define EMIF_REG_CNTR1_CFG_SHIFT 0 352 #define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) 353 354 /* PERF_CNT_SEL */ 355 #define EMIF_REG_MCONNID2_SHIFT 24 356 #define EMIF_REG_MCONNID2_MASK (0xff << 24) 357 #define EMIF_REG_REGION_SEL2_SHIFT 16 358 #define EMIF_REG_REGION_SEL2_MASK (0x3 << 16) 359 #define EMIF_REG_MCONNID1_SHIFT 8 360 #define EMIF_REG_MCONNID1_MASK (0xff << 8) 361 #define EMIF_REG_REGION_SEL1_SHIFT 0 362 #define EMIF_REG_REGION_SEL1_MASK (0x3 << 0) 363 364 /* PERF_CNT_TIM */ 365 #define EMIF_REG_TOTAL_TIME_SHIFT 0 366 #define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0) 367 368 /* READ_IDLE_CTRL */ 369 #define EMIF_REG_READ_IDLE_LEN_SHIFT 16 370 #define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16) 371 #define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0 372 #define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) 373 374 /* READ_IDLE_CTRL_SHDW */ 375 #define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16 376 #define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) 377 #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 378 #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) 379 380 /* IRQ_EOI */ 381 #define EMIF_REG_EOI_SHIFT 0 382 #define EMIF_REG_EOI_MASK (1 << 0) 383 384 /* IRQSTATUS_RAW_SYS */ 385 #define EMIF_REG_DNV_SYS_SHIFT 2 386 #define EMIF_REG_DNV_SYS_MASK (1 << 2) 387 #define EMIF_REG_TA_SYS_SHIFT 1 388 #define EMIF_REG_TA_SYS_MASK (1 << 1) 389 #define EMIF_REG_ERR_SYS_SHIFT 0 390 #define EMIF_REG_ERR_SYS_MASK (1 << 0) 391 392 /* IRQSTATUS_RAW_LL */ 393 #define EMIF_REG_DNV_LL_SHIFT 2 394 #define EMIF_REG_DNV_LL_MASK (1 << 2) 395 #define EMIF_REG_TA_LL_SHIFT 1 396 #define EMIF_REG_TA_LL_MASK (1 << 1) 397 #define EMIF_REG_ERR_LL_SHIFT 0 398 #define EMIF_REG_ERR_LL_MASK (1 << 0) 399 400 /* IRQSTATUS_SYS */ 401 402 /* IRQSTATUS_LL */ 403 404 /* IRQENABLE_SET_SYS */ 405 #define EMIF_REG_EN_DNV_SYS_SHIFT 2 406 #define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) 407 #define EMIF_REG_EN_TA_SYS_SHIFT 1 408 #define EMIF_REG_EN_TA_SYS_MASK (1 << 1) 409 #define EMIF_REG_EN_ERR_SYS_SHIFT 0 410 #define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) 411 412 /* IRQENABLE_SET_LL */ 413 #define EMIF_REG_EN_DNV_LL_SHIFT 2 414 #define EMIF_REG_EN_DNV_LL_MASK (1 << 2) 415 #define EMIF_REG_EN_TA_LL_SHIFT 1 416 #define EMIF_REG_EN_TA_LL_MASK (1 << 1) 417 #define EMIF_REG_EN_ERR_LL_SHIFT 0 418 #define EMIF_REG_EN_ERR_LL_MASK (1 << 0) 419 420 /* IRQENABLE_CLR_SYS */ 421 422 /* IRQENABLE_CLR_LL */ 423 424 /* ZQ_CONFIG */ 425 #define EMIF_REG_ZQ_CS1EN_SHIFT 31 426 #define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) 427 #define EMIF_REG_ZQ_CS0EN_SHIFT 30 428 #define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) 429 #define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 430 #define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) 431 #define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 432 #define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) 433 #define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 434 #define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) 435 #define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 436 #define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) 437 #define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0 438 #define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) 439 440 /* TEMP_ALERT_CONFIG */ 441 #define EMIF_REG_TA_CS1EN_SHIFT 31 442 #define EMIF_REG_TA_CS1EN_MASK (1 << 31) 443 #define EMIF_REG_TA_CS0EN_SHIFT 30 444 #define EMIF_REG_TA_CS0EN_MASK (1 << 30) 445 #define EMIF_REG_TA_SFEXITEN_SHIFT 28 446 #define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) 447 #define EMIF_REG_TA_DEVWDT_SHIFT 26 448 #define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) 449 #define EMIF_REG_TA_DEVCNT_SHIFT 24 450 #define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24) 451 #define EMIF_REG_TA_REFINTERVAL_SHIFT 0 452 #define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) 453 454 /* OCP_ERR_LOG */ 455 #define EMIF_REG_MADDRSPACE_SHIFT 14 456 #define EMIF_REG_MADDRSPACE_MASK (0x3 << 14) 457 #define EMIF_REG_MBURSTSEQ_SHIFT 11 458 #define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11) 459 #define EMIF_REG_MCMD_SHIFT 8 460 #define EMIF_REG_MCMD_MASK (0x7 << 8) 461 #define EMIF_REG_MCONNID_SHIFT 0 462 #define EMIF_REG_MCONNID_MASK (0xff << 0) 463 464 /* DDR_PHY_CTRL_1 */ 465 #define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4 466 #define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) 467 #define EMIF_REG_READ_LATENCY_SHIFT 0 468 #define EMIF_REG_READ_LATENCY_MASK (0xf << 0) 469 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 470 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) 471 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 472 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) 473 474 /* DDR_PHY_CTRL_1_SHDW */ 475 #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 476 #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) 477 #define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0 478 #define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0) 479 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 480 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) 481 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 482 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) 483 #define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT 25 484 #define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK (1 << 25) 485 #define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT 26 486 #define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK (1 << 26) 487 #define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT 27 488 #define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK (1 << 27) 489 490 /* DDR_PHY_CTRL_2 */ 491 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 492 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) 493 494 /*EMIF_READ_WRITE_LEVELING_CONTROL*/ 495 #define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 496 #define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) 497 #define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 498 #define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) 499 #define EMIF_REG_RDLVLINC_INT_SHIFT 16 500 #define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) 501 #define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 502 #define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) 503 #define EMIF_REG_WRLVLINC_INT_SHIFT 0 504 #define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) 505 506 /*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ 507 #define EMIF_REG_RDWRLVL_EN_SHIFT 31 508 #define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) 509 #define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 510 #define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) 511 #define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 512 #define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) 513 #define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 514 #define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) 515 #define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 516 #define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) 517 518 /*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ 519 #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 520 #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) 521 522 /* EMIF_PHY_CTRL_36 */ 523 #define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8) 524 525 #define PHY_RDDQS_RATIO_REGS 5 526 #define PHY_FIFO_WE_SLAVE_RATIO_REGS 5 527 #define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10 528 529 /*Leveling Fields */ 530 #define DDR3_WR_LVL_INT 0x73 531 #define DDR3_RD_LVL_INT 0x33 532 #define DDR3_RD_LVL_GATE_INT 0x59 533 #define RD_RW_LVL_INC_PRE 0x0 534 #define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) 535 536 #define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ 537 | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ 538 | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ 539 | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) 540 541 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 542 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 543 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 544 545 /* DMM */ 546 #define DMM_BASE 0x4E000040 547 548 /* Memory Adapter */ 549 #define MA_BASE 0x482AF040 550 #define MA_PRIORITY 0x482A2000 551 #define MA_HIMEM_INTERLEAVE_UN_SHIFT 8 552 #define MA_HIMEM_INTERLEAVE_UN_MASK (1 << 8) 553 554 /* DMM_LISA_MAP */ 555 #define EMIF_SYS_ADDR_SHIFT 24 556 #define EMIF_SYS_ADDR_MASK (0xff << 24) 557 #define EMIF_SYS_SIZE_SHIFT 20 558 #define EMIF_SYS_SIZE_MASK (0x7 << 20) 559 #define EMIF_SDRC_INTL_SHIFT 18 560 #define EMIF_SDRC_INTL_MASK (0x3 << 18) 561 #define EMIF_SDRC_ADDRSPC_SHIFT 16 562 #define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16) 563 #define EMIF_SDRC_MAP_SHIFT 8 564 #define EMIF_SDRC_MAP_MASK (0x3 << 8) 565 #define EMIF_SDRC_ADDR_SHIFT 0 566 #define EMIF_SDRC_ADDR_MASK (0xff << 0) 567 568 /* DMM_LISA_MAP fields */ 569 #define DMM_SDRC_MAP_UNMAPPED 0 570 #define DMM_SDRC_MAP_EMIF1_ONLY 1 571 #define DMM_SDRC_MAP_EMIF2_ONLY 2 572 #define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 573 574 #define DMM_SDRC_INTL_NONE 0 575 #define DMM_SDRC_INTL_128B 1 576 #define DMM_SDRC_INTL_256B 2 577 #define DMM_SDRC_INTL_512 3 578 579 #define DMM_SDRC_ADDR_SPC_SDRAM 0 580 #define DMM_SDRC_ADDR_SPC_NVM 1 581 #define DMM_SDRC_ADDR_SPC_INVALID 2 582 583 #define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ 584 (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ 585 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ 586 (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ 587 (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) 588 589 #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ 590 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ 591 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ 592 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) 593 594 #define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ 595 (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\ 596 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ 597 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) 598 599 /* Trap for invalid TILER PAT entries */ 600 #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ 601 (0 << EMIF_SDRC_ADDR_SHIFT) |\ 602 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ 603 (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\ 604 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ 605 (0xFF << EMIF_SYS_ADDR_SHIFT)) 606 607 #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 608 609 /* EMIF ECC CTRL reg */ 610 #define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31 611 #define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31) 612 #define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30 613 #define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30) 614 #define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29 615 #define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29) 616 #define EMIF_ECC_REG_RMW_EN_SHIFT 28 617 #define EMIF_ECC_REG_RMW_EN_MASK (1 << 28) 618 #define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1 619 #define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1) 620 #define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0 621 #define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0) 622 623 /* EMIF ECC ADDRESS RANGE */ 624 #define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16 625 #define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16) 626 #define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0 627 #define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0) 628 629 /* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */ 630 #define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5 631 #define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5) 632 #define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4 633 #define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4) 634 #define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3 635 #define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3) 636 637 /* Reg mapping structure */ 638 struct emif_reg_struct { 639 u32 emif_mod_id_rev; 640 u32 emif_status; 641 u32 emif_sdram_config; 642 u32 emif_lpddr2_nvm_config; 643 u32 emif_sdram_ref_ctrl; 644 u32 emif_sdram_ref_ctrl_shdw; 645 u32 emif_sdram_tim_1; 646 u32 emif_sdram_tim_1_shdw; 647 u32 emif_sdram_tim_2; 648 u32 emif_sdram_tim_2_shdw; 649 u32 emif_sdram_tim_3; 650 u32 emif_sdram_tim_3_shdw; 651 u32 emif_lpddr2_nvm_tim; 652 u32 emif_lpddr2_nvm_tim_shdw; 653 u32 emif_pwr_mgmt_ctrl; 654 u32 emif_pwr_mgmt_ctrl_shdw; 655 u32 emif_lpddr2_mode_reg_data; 656 u32 padding1[1]; 657 u32 emif_lpddr2_mode_reg_data_es2; 658 u32 padding11[1]; 659 u32 emif_lpddr2_mode_reg_cfg; 660 u32 emif_l3_config; 661 u32 emif_l3_cfg_val_1; 662 u32 emif_l3_cfg_val_2; 663 u32 emif_iodft_tlgc; 664 u32 padding2[7]; 665 u32 emif_perf_cnt_1; 666 u32 emif_perf_cnt_2; 667 u32 emif_perf_cnt_cfg; 668 u32 emif_perf_cnt_sel; 669 u32 emif_perf_cnt_tim; 670 u32 padding3; 671 u32 emif_read_idlectrl; 672 u32 emif_read_idlectrl_shdw; 673 u32 padding4; 674 u32 emif_irqstatus_raw_sys; 675 u32 emif_irqstatus_raw_ll; 676 u32 emif_irqstatus_sys; 677 u32 emif_irqstatus_ll; 678 u32 emif_irqenable_set_sys; 679 u32 emif_irqenable_set_ll; 680 u32 emif_irqenable_clr_sys; 681 u32 emif_irqenable_clr_ll; 682 u32 padding5; 683 u32 emif_zq_config; 684 u32 emif_temp_alert_config; 685 u32 emif_l3_err_log; 686 u32 emif_rd_wr_lvl_rmp_win; 687 u32 emif_rd_wr_lvl_rmp_ctl; 688 u32 emif_rd_wr_lvl_ctl; 689 u32 padding6[1]; 690 u32 emif_ddr_phy_ctrl_1; 691 u32 emif_ddr_phy_ctrl_1_shdw; 692 u32 emif_ddr_phy_ctrl_2; 693 u32 padding7[4]; 694 u32 emif_prio_class_serv_map; 695 u32 emif_connect_id_serv_1_map; 696 u32 emif_connect_id_serv_2_map; 697 u32 padding8; 698 u32 emif_ecc_ctrl_reg; 699 u32 emif_ecc_address_range_1; 700 u32 emif_ecc_address_range_2; 701 u32 padding8_1; 702 u32 emif_rd_wr_exec_thresh; 703 u32 emif_cos_config; 704 #if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE) 705 u32 padding9[2]; 706 u32 emif_1b_ecc_err_cnt; 707 u32 emif_1b_ecc_err_thrush; 708 u32 emif_1b_ecc_err_dist_1; 709 u32 emif_1b_ecc_err_addr_log; 710 u32 emif_2b_ecc_err_addr_log; 711 u32 emif_ddr_phy_status[28]; 712 u32 padding10[19]; 713 #else 714 u32 padding9[6]; 715 u32 emif_ddr_phy_status[28]; 716 u32 padding10[20]; 717 #endif 718 u32 emif_ddr_ext_phy_ctrl_1; 719 u32 emif_ddr_ext_phy_ctrl_1_shdw; 720 u32 emif_ddr_ext_phy_ctrl_2; 721 u32 emif_ddr_ext_phy_ctrl_2_shdw; 722 u32 emif_ddr_ext_phy_ctrl_3; 723 u32 emif_ddr_ext_phy_ctrl_3_shdw; 724 u32 emif_ddr_ext_phy_ctrl_4; 725 u32 emif_ddr_ext_phy_ctrl_4_shdw; 726 u32 emif_ddr_ext_phy_ctrl_5; 727 u32 emif_ddr_ext_phy_ctrl_5_shdw; 728 u32 emif_ddr_ext_phy_ctrl_6; 729 u32 emif_ddr_ext_phy_ctrl_6_shdw; 730 u32 emif_ddr_ext_phy_ctrl_7; 731 u32 emif_ddr_ext_phy_ctrl_7_shdw; 732 u32 emif_ddr_ext_phy_ctrl_8; 733 u32 emif_ddr_ext_phy_ctrl_8_shdw; 734 u32 emif_ddr_ext_phy_ctrl_9; 735 u32 emif_ddr_ext_phy_ctrl_9_shdw; 736 u32 emif_ddr_ext_phy_ctrl_10; 737 u32 emif_ddr_ext_phy_ctrl_10_shdw; 738 u32 emif_ddr_ext_phy_ctrl_11; 739 u32 emif_ddr_ext_phy_ctrl_11_shdw; 740 u32 emif_ddr_ext_phy_ctrl_12; 741 u32 emif_ddr_ext_phy_ctrl_12_shdw; 742 u32 emif_ddr_ext_phy_ctrl_13; 743 u32 emif_ddr_ext_phy_ctrl_13_shdw; 744 u32 emif_ddr_ext_phy_ctrl_14; 745 u32 emif_ddr_ext_phy_ctrl_14_shdw; 746 u32 emif_ddr_ext_phy_ctrl_15; 747 u32 emif_ddr_ext_phy_ctrl_15_shdw; 748 u32 emif_ddr_ext_phy_ctrl_16; 749 u32 emif_ddr_ext_phy_ctrl_16_shdw; 750 u32 emif_ddr_ext_phy_ctrl_17; 751 u32 emif_ddr_ext_phy_ctrl_17_shdw; 752 u32 emif_ddr_ext_phy_ctrl_18; 753 u32 emif_ddr_ext_phy_ctrl_18_shdw; 754 u32 emif_ddr_ext_phy_ctrl_19; 755 u32 emif_ddr_ext_phy_ctrl_19_shdw; 756 u32 emif_ddr_ext_phy_ctrl_20; 757 u32 emif_ddr_ext_phy_ctrl_20_shdw; 758 u32 emif_ddr_ext_phy_ctrl_21; 759 u32 emif_ddr_ext_phy_ctrl_21_shdw; 760 u32 emif_ddr_ext_phy_ctrl_22; 761 u32 emif_ddr_ext_phy_ctrl_22_shdw; 762 u32 emif_ddr_ext_phy_ctrl_23; 763 u32 emif_ddr_ext_phy_ctrl_23_shdw; 764 u32 emif_ddr_ext_phy_ctrl_24; 765 u32 emif_ddr_ext_phy_ctrl_24_shdw; 766 u32 emif_ddr_ext_phy_ctrl_25; 767 u32 emif_ddr_ext_phy_ctrl_25_shdw; 768 u32 emif_ddr_ext_phy_ctrl_26; 769 u32 emif_ddr_ext_phy_ctrl_26_shdw; 770 u32 emif_ddr_ext_phy_ctrl_27; 771 u32 emif_ddr_ext_phy_ctrl_27_shdw; 772 u32 emif_ddr_ext_phy_ctrl_28; 773 u32 emif_ddr_ext_phy_ctrl_28_shdw; 774 u32 emif_ddr_ext_phy_ctrl_29; 775 u32 emif_ddr_ext_phy_ctrl_29_shdw; 776 u32 emif_ddr_ext_phy_ctrl_30; 777 u32 emif_ddr_ext_phy_ctrl_30_shdw; 778 u32 emif_ddr_ext_phy_ctrl_31; 779 u32 emif_ddr_ext_phy_ctrl_31_shdw; 780 u32 emif_ddr_ext_phy_ctrl_32; 781 u32 emif_ddr_ext_phy_ctrl_32_shdw; 782 u32 emif_ddr_ext_phy_ctrl_33; 783 u32 emif_ddr_ext_phy_ctrl_33_shdw; 784 u32 emif_ddr_ext_phy_ctrl_34; 785 u32 emif_ddr_ext_phy_ctrl_34_shdw; 786 u32 emif_ddr_ext_phy_ctrl_35; 787 u32 emif_ddr_ext_phy_ctrl_35_shdw; 788 union { 789 u32 emif_ddr_ext_phy_ctrl_36; 790 u32 emif_ddr_fifo_misaligned_clear_1; 791 }; 792 union { 793 u32 emif_ddr_ext_phy_ctrl_36_shdw; 794 u32 emif_ddr_fifo_misaligned_clear_2; 795 }; 796 }; 797 798 struct dmm_lisa_map_regs { 799 u32 dmm_lisa_map_0; 800 u32 dmm_lisa_map_1; 801 u32 dmm_lisa_map_2; 802 u32 dmm_lisa_map_3; 803 u8 is_ma_present; 804 }; 805 806 #define CS0 0 807 #define CS1 1 808 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ 809 #define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ 810 811 /* 812 * The period of DDR clk is represented as numerator and denominator for 813 * better accuracy in integer based calculations. However, if the numerator 814 * and denominator are very huge there may be chances of overflow in 815 * calculations. So, as a trade-off keep denominator(and consequently 816 * numerator) within a limit sacrificing some accuracy - but not much 817 * If denominator and numerator are already small (such as at 400 MHz) 818 * no adjustment is needed 819 */ 820 #define EMIF_PERIOD_DEN_LIMIT 1000 821 /* 822 * Maximum number of different frequencies supported by EMIF driver 823 * Determines the number of entries in the pointer array for register 824 * cache 825 */ 826 #define EMIF_MAX_NUM_FREQUENCIES 6 827 /* 828 * Indices into the Addressing Table array. 829 * One entry each for all the different types of devices with different 830 * addressing schemes 831 */ 832 #define ADDR_TABLE_INDEX64M 0 833 #define ADDR_TABLE_INDEX128M 1 834 #define ADDR_TABLE_INDEX256M 2 835 #define ADDR_TABLE_INDEX512M 3 836 #define ADDR_TABLE_INDEX1GS4 4 837 #define ADDR_TABLE_INDEX2GS4 5 838 #define ADDR_TABLE_INDEX4G 6 839 #define ADDR_TABLE_INDEX8G 7 840 #define ADDR_TABLE_INDEX1GS2 8 841 #define ADDR_TABLE_INDEX2GS2 9 842 #define ADDR_TABLE_INDEXMAX 10 843 844 /* Number of Row bits */ 845 #define ROW_9 0 846 #define ROW_10 1 847 #define ROW_11 2 848 #define ROW_12 3 849 #define ROW_13 4 850 #define ROW_14 5 851 #define ROW_15 6 852 #define ROW_16 7 853 854 /* Number of Column bits */ 855 #define COL_8 0 856 #define COL_9 1 857 #define COL_10 2 858 #define COL_11 3 859 #define COL_7 4 /*Not supported by OMAP included for completeness */ 860 861 /* Number of Banks*/ 862 #define BANKS1 0 863 #define BANKS2 1 864 #define BANKS4 2 865 #define BANKS8 3 866 867 /* Refresh rate in micro seconds x 10 */ 868 #define T_REFI_15_6 156 869 #define T_REFI_7_8 78 870 #define T_REFI_3_9 39 871 872 #define EBANK_CS1_DIS 0 873 #define EBANK_CS1_EN 1 874 875 /* Read Latency used by the device at reset */ 876 #define RL_BOOT 3 877 /* Read Latency for the highest frequency you want to use */ 878 #ifdef CONFIG_OMAP54XX 879 #define RL_FINAL 8 880 #else 881 #define RL_FINAL 6 882 #endif 883 884 885 /* Interleaving policies at EMIF level- between banks and Chip Selects */ 886 #define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 887 #define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 888 889 /* 890 * Interleaving policy to be used 891 * Currently set to MAX interleaving for better performance 892 */ 893 #define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 894 895 /* State of the core voltage: 896 * This is important for some parameters such as read idle control and 897 * ZQ calibration timings. Timings are much stricter when voltage ramp 898 * is happening compared to when the voltage is stable. 899 * We need to calculate two sets of values for these parameters and use 900 * them accordingly 901 */ 902 #define LPDDR2_VOLTAGE_STABLE 0 903 #define LPDDR2_VOLTAGE_RAMPING 1 904 905 /* Length of the forced read idle period in terms of cycles */ 906 #define EMIF_REG_READ_IDLE_LEN_VAL 5 907 908 /* Interval between forced 'read idles' */ 909 /* To be used when voltage is changed for DPS/DVFS - 1us */ 910 #define READ_IDLE_INTERVAL_DVFS (1*1000) 911 /* 912 * To be used when voltage is not scaled except by Smart Reflex 913 * 50us - or maximum value will do 914 */ 915 #define READ_IDLE_INTERVAL_NORMAL (50*1000) 916 917 918 /* 919 * Unless voltage is changing due to DVFS one ZQCS command every 50ms should 920 * be enough. This shoule be enough also in the case when voltage is changing 921 * due to smart-reflex. 922 */ 923 #define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) 924 /* 925 * If voltage is changing due to DVFS ZQCS should be performed more 926 * often(every 50us) 927 */ 928 #define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 929 930 /* The interval between ZQCL commands as a multiple of ZQCS interval */ 931 #define REG_ZQ_ZQCL_MULT 4 932 /* The interval between ZQINIT commands as a multiple of ZQCL interval */ 933 #define REG_ZQ_ZQINIT_MULT 3 934 /* Enable ZQ Calibration on exiting Self-refresh */ 935 #define REG_ZQ_SFEXITEN_ENABLE 1 936 /* 937 * ZQ Calibration simultaneously on both chip-selects: 938 * Needs one calibration resistor per CS 939 * None of the boards that we know of have this capability 940 * So disabled by default 941 */ 942 #define REG_ZQ_DUALCALEN_DISABLE 0 943 /* 944 * Enable ZQ Calibration by default on CS0. If we are asked to program 945 * the EMIF there will be something connected to CS0 for sure 946 */ 947 #define REG_ZQ_CS0EN_ENABLE 1 948 949 /* EMIF_PWR_MGMT_CTRL register */ 950 /* Low power modes */ 951 #define LP_MODE_DISABLE 0 952 #define LP_MODE_CLOCK_STOP 1 953 #define LP_MODE_SELF_REFRESH 2 954 #define LP_MODE_PWR_DN 3 955 956 /* REG_DPD_EN */ 957 #define DPD_DISABLE 0 958 #define DPD_ENABLE 1 959 960 /* Maximum delay before Low Power Modes */ 961 #define REG_CS_TIM 0x0 962 #define REG_SR_TIM 0xF 963 #define REG_PD_TIM 0xF 964 965 966 /* EMIF_PWR_MGMT_CTRL register */ 967 #define EMIF_PWR_MGMT_CTRL (\ 968 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ 969 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ 970 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ 971 ((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\ 972 & EMIF_REG_LP_MODE_MASK) |\ 973 ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ 974 & EMIF_REG_DPD_EN_MASK))\ 975 976 #define EMIF_PWR_MGMT_CTRL_SHDW (\ 977 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\ 978 & EMIF_REG_CS_TIM_SHDW_MASK) |\ 979 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ 980 & EMIF_REG_SR_TIM_SHDW_MASK) |\ 981 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ 982 & EMIF_REG_PD_TIM_SHDW_MASK)) 983 984 /* EMIF_L3_CONFIG register value */ 985 #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF 986 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 987 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000 988 989 /* 990 * Value of bits 12:31 of DDR_PHY_CTRL_1 register: 991 * All these fields have magic values dependent on frequency and 992 * determined by PHY and DLL integration with EMIF. Setting the magic 993 * values suggested by hw team. 994 */ 995 #define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF 996 #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 997 #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 998 #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF 999 1000 /* 1001 * MR1 value: 1002 * Burst length : 8 1003 * Burst type : sequential 1004 * Wrap : enabled 1005 * nWR : 3(default). EMIF does not do pre-charge. 1006 * : So nWR is don't care 1007 */ 1008 #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 1009 #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3 1010 1011 /* MR2 */ 1012 #define MR2_RL3_WL1 1 1013 #define MR2_RL4_WL2 2 1014 #define MR2_RL5_WL2 3 1015 #define MR2_RL6_WL3 4 1016 1017 /* MR10: ZQ calibration codes */ 1018 #define MR10_ZQ_ZQCS 0x56 1019 #define MR10_ZQ_ZQCL 0xAB 1020 #define MR10_ZQ_ZQINIT 0xFF 1021 #define MR10_ZQ_ZQRESET 0xC3 1022 1023 /* TEMP_ALERT_CONFIG */ 1024 #define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ 1025 #define TEMP_ALERT_CONFIG_DEVCT_1 0 1026 #define TEMP_ALERT_CONFIG_DEVWDT_32 2 1027 1028 /* MR16 value: refresh full array(no partial array self refresh) */ 1029 #define MR16_REF_FULL_ARRAY 0 1030 1031 /* 1032 * Maximum number of entries we keep in our array of timing tables 1033 * We need not keep all the speed bins supported by the device 1034 * We need to keep timing tables for only the speed bins that we 1035 * are interested in 1036 */ 1037 #define MAX_NUM_SPEEDBINS 4 1038 1039 /* LPDDR2 Densities */ 1040 #define LPDDR2_DENSITY_64Mb 0 1041 #define LPDDR2_DENSITY_128Mb 1 1042 #define LPDDR2_DENSITY_256Mb 2 1043 #define LPDDR2_DENSITY_512Mb 3 1044 #define LPDDR2_DENSITY_1Gb 4 1045 #define LPDDR2_DENSITY_2Gb 5 1046 #define LPDDR2_DENSITY_4Gb 6 1047 #define LPDDR2_DENSITY_8Gb 7 1048 #define LPDDR2_DENSITY_16Gb 8 1049 #define LPDDR2_DENSITY_32Gb 9 1050 1051 /* LPDDR2 type */ 1052 #define LPDDR2_TYPE_S4 0 1053 #define LPDDR2_TYPE_S2 1 1054 #define LPDDR2_TYPE_NVM 2 1055 1056 /* LPDDR2 IO width */ 1057 #define LPDDR2_IO_WIDTH_32 0 1058 #define LPDDR2_IO_WIDTH_16 1 1059 #define LPDDR2_IO_WIDTH_8 2 1060 1061 /* Mode register numbers */ 1062 #define LPDDR2_MR0 0 1063 #define LPDDR2_MR1 1 1064 #define LPDDR2_MR2 2 1065 #define LPDDR2_MR3 3 1066 #define LPDDR2_MR4 4 1067 #define LPDDR2_MR5 5 1068 #define LPDDR2_MR6 6 1069 #define LPDDR2_MR7 7 1070 #define LPDDR2_MR8 8 1071 #define LPDDR2_MR9 9 1072 #define LPDDR2_MR10 10 1073 #define LPDDR2_MR11 11 1074 #define LPDDR2_MR16 16 1075 #define LPDDR2_MR17 17 1076 #define LPDDR2_MR18 18 1077 1078 /* MR0 */ 1079 #define LPDDR2_MR0_DAI_SHIFT 0 1080 #define LPDDR2_MR0_DAI_MASK 1 1081 #define LPDDR2_MR0_DI_SHIFT 1 1082 #define LPDDR2_MR0_DI_MASK (1 << 1) 1083 #define LPDDR2_MR0_DNVI_SHIFT 2 1084 #define LPDDR2_MR0_DNVI_MASK (1 << 2) 1085 1086 /* MR4 */ 1087 #define MR4_SDRAM_REF_RATE_SHIFT 0 1088 #define MR4_SDRAM_REF_RATE_MASK 7 1089 #define MR4_TUF_SHIFT 7 1090 #define MR4_TUF_MASK (1 << 7) 1091 1092 /* MR4 SDRAM Refresh Rate field values */ 1093 #define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 1094 #define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 1095 #define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 1096 #define SDRAM_TEMP_NOMINAL 0x3 1097 #define SDRAM_TEMP_RESERVED_4 0x4 1098 #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 1099 #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 1100 #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 1101 1102 #define LPDDR2_MANUFACTURER_SAMSUNG 1 1103 #define LPDDR2_MANUFACTURER_QIMONDA 2 1104 #define LPDDR2_MANUFACTURER_ELPIDA 3 1105 #define LPDDR2_MANUFACTURER_ETRON 4 1106 #define LPDDR2_MANUFACTURER_NANYA 5 1107 #define LPDDR2_MANUFACTURER_HYNIX 6 1108 #define LPDDR2_MANUFACTURER_MOSEL 7 1109 #define LPDDR2_MANUFACTURER_WINBOND 8 1110 #define LPDDR2_MANUFACTURER_ESMT 9 1111 #define LPDDR2_MANUFACTURER_SPANSION 11 1112 #define LPDDR2_MANUFACTURER_SST 12 1113 #define LPDDR2_MANUFACTURER_ZMOS 13 1114 #define LPDDR2_MANUFACTURER_INTEL 14 1115 #define LPDDR2_MANUFACTURER_NUMONYX 254 1116 #define LPDDR2_MANUFACTURER_MICRON 255 1117 1118 /* MR8 register fields */ 1119 #define MR8_TYPE_SHIFT 0x0 1120 #define MR8_TYPE_MASK 0x3 1121 #define MR8_DENSITY_SHIFT 0x2 1122 #define MR8_DENSITY_MASK (0xF << 0x2) 1123 #define MR8_IO_WIDTH_SHIFT 0x6 1124 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) 1125 1126 /* SDRAM TYPE */ 1127 #define EMIF_SDRAM_TYPE_DDR2 0x2 1128 #define EMIF_SDRAM_TYPE_DDR3 0x3 1129 #define EMIF_SDRAM_TYPE_LPDDR2 0x4 1130 1131 struct lpddr2_addressing { 1132 u8 num_banks; 1133 u8 t_REFI_us_x10; 1134 u8 row_sz[2]; /* One entry each for x32 and x16 */ 1135 u8 col_sz[2]; /* One entry each for x32 and x16 */ 1136 }; 1137 1138 /* Structure for timings from the DDR datasheet */ 1139 struct lpddr2_ac_timings { 1140 u32 max_freq; 1141 u8 RL; 1142 u8 tRPab; 1143 u8 tRCD; 1144 u8 tWR; 1145 u8 tRASmin; 1146 u8 tRRD; 1147 u8 tWTRx2; 1148 u8 tXSR; 1149 u8 tXPx2; 1150 u8 tRFCab; 1151 u8 tRTPx2; 1152 u8 tCKE; 1153 u8 tCKESR; 1154 u8 tZQCS; 1155 u32 tZQCL; 1156 u32 tZQINIT; 1157 u8 tDQSCKMAXx2; 1158 u8 tRASmax; 1159 u8 tFAW; 1160 1161 }; 1162 1163 /* 1164 * Min tCK values for some of the parameters: 1165 * If the calculated clock cycles for the respective parameter is 1166 * less than the corresponding min tCK value, we need to set the min 1167 * tCK value. This may happen at lower frequencies. 1168 */ 1169 struct lpddr2_min_tck { 1170 u32 tRL; 1171 u32 tRP_AB; 1172 u32 tRCD; 1173 u32 tWR; 1174 u32 tRAS_MIN; 1175 u32 tRRD; 1176 u32 tWTR; 1177 u32 tXP; 1178 u32 tRTP; 1179 u8 tCKE; 1180 u32 tCKESR; 1181 u32 tFAW; 1182 }; 1183 1184 struct lpddr2_device_details { 1185 u8 type; 1186 u8 density; 1187 u8 io_width; 1188 u8 manufacturer; 1189 }; 1190 1191 struct lpddr2_device_timings { 1192 const struct lpddr2_ac_timings **ac_timings; 1193 const struct lpddr2_min_tck *min_tck; 1194 }; 1195 1196 /* Details of the devices connected to each chip-select of an EMIF instance */ 1197 struct emif_device_details { 1198 const struct lpddr2_device_details *cs0_device_details; 1199 const struct lpddr2_device_details *cs1_device_details; 1200 const struct lpddr2_device_timings *cs0_device_timings; 1201 const struct lpddr2_device_timings *cs1_device_timings; 1202 }; 1203 1204 /* 1205 * Structure containing shadow of important registers in EMIF 1206 * The calculation function fills in this structure to be later used for 1207 * initialization and DVFS 1208 */ 1209 struct emif_regs { 1210 u32 freq; 1211 u32 sdram_config_init; 1212 u32 sdram_config; 1213 u32 sdram_config2; 1214 u32 ref_ctrl; 1215 u32 ref_ctrl_final; 1216 u32 sdram_tim1; 1217 u32 sdram_tim2; 1218 u32 sdram_tim3; 1219 u32 ocp_config; 1220 u32 read_idle_ctrl; 1221 u32 zq_config; 1222 u32 temp_alert_config; 1223 u32 emif_ddr_phy_ctlr_1_init; 1224 u32 emif_ddr_phy_ctlr_1; 1225 u32 emif_ddr_ext_phy_ctrl_1; 1226 u32 emif_ddr_ext_phy_ctrl_2; 1227 u32 emif_ddr_ext_phy_ctrl_3; 1228 u32 emif_ddr_ext_phy_ctrl_4; 1229 u32 emif_ddr_ext_phy_ctrl_5; 1230 u32 emif_rd_wr_lvl_rmp_win; 1231 u32 emif_rd_wr_lvl_rmp_ctl; 1232 u32 emif_rd_wr_lvl_ctl; 1233 u32 emif_rd_wr_exec_thresh; 1234 u32 emif_prio_class_serv_map; 1235 u32 emif_connect_id_serv_1_map; 1236 u32 emif_connect_id_serv_2_map; 1237 u32 emif_cos_config; 1238 u32 emif_ecc_ctrl_reg; 1239 u32 emif_ecc_address_range_1; 1240 u32 emif_ecc_address_range_2; 1241 }; 1242 1243 struct lpddr2_mr_regs { 1244 s8 mr1; 1245 s8 mr2; 1246 s8 mr3; 1247 s8 mr10; 1248 s8 mr16; 1249 }; 1250 1251 struct read_write_regs { 1252 u32 read_reg; 1253 u32 write_reg; 1254 }; 1255 get_emif_rev(u32 base)1256 static inline u32 get_emif_rev(u32 base) 1257 { 1258 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 1259 1260 return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) 1261 >> EMIF_REG_MAJOR_REVISION_SHIFT; 1262 } 1263 1264 /* 1265 * Get SDRAM type connected to EMIF. 1266 * Assuming similar SDRAM parts are connected to both EMIF's 1267 * which is typically the case. So it is sufficient to get 1268 * SDRAM type from EMIF1. 1269 */ emif_sdram_type(u32 sdram_config)1270 static inline u32 emif_sdram_type(u32 sdram_config) 1271 { 1272 return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK) 1273 >> EMIF_REG_SDRAM_TYPE_SHIFT; 1274 } 1275 1276 /* assert macros */ 1277 #if defined(DEBUG) 1278 #define emif_assert(c) ({ if (!(c)) for (;;); }) 1279 #else 1280 #define emif_assert(c) ({ if (0) hang(); }) 1281 #endif 1282 1283 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1284 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); 1285 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); 1286 #else 1287 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, 1288 struct lpddr2_device_details *lpddr2_dev_details); 1289 void emif_get_device_timings(u32 emif_nr, 1290 const struct lpddr2_device_timings **cs0_device_timings, 1291 const struct lpddr2_device_timings **cs1_device_timings); 1292 #endif 1293 1294 void do_ext_phy_settings(u32 base, const struct emif_regs *regs); 1295 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); 1296 1297 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1298 extern u32 *const T_num; 1299 extern u32 *const T_den; 1300 #endif 1301 1302 void config_data_eye_leveling_samples(u32 emif_base); 1303 const struct read_write_regs *get_bug_regs(u32 *iterations); 1304 #endif 1305