1 /* 2 * Overview: 3 * This is the generic MTD driver for NAND flash devices. It should be 4 * capable of working with almost all NAND chips currently available. 5 * 6 * Additional technical information is available on 7 * http://www.linux-mtd.infradead.org/doc/nand.html 8 * 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 11 * 12 * Credits: 13 * David Woodhouse for adding multichip support 14 * 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 16 * rework for 2K page size chips 17 * 18 * TODO: 19 * Enable cached programming for 2k page size chips 20 * Check, if mtd->ecctype should be set to MTD_ECC_HW 21 * if we have HW ECC support. 22 * BBT table is not serialized, has to be fixed 23 * 24 * This program is free software; you can redistribute it and/or modify 25 * it under the terms of the GNU General Public License version 2 as 26 * published by the Free Software Foundation. 27 * 28 */ 29 30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 31 #include <common.h> 32 #if CONFIG_IS_ENABLED(OF_CONTROL) 33 #include <fdtdec.h> 34 #endif 35 #include <malloc.h> 36 #include <watchdog.h> 37 #include <linux/err.h> 38 #include <linux/compat.h> 39 #include <linux/mtd/mtd.h> 40 #include <linux/mtd/rawnand.h> 41 #include <linux/mtd/nand_ecc.h> 42 #include <linux/mtd/nand_bch.h> 43 #ifdef CONFIG_MTD_PARTITIONS 44 #include <linux/mtd/partitions.h> 45 #endif 46 #include <asm/io.h> 47 #include <linux/errno.h> 48 49 /* Define default oob placement schemes for large and small page devices */ 50 #ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT 51 static struct nand_ecclayout nand_oob_8 = { 52 .eccbytes = 3, 53 .eccpos = {0, 1, 2}, 54 .oobfree = { 55 {.offset = 3, 56 .length = 2}, 57 {.offset = 6, 58 .length = 2} } 59 }; 60 61 static struct nand_ecclayout nand_oob_16 = { 62 .eccbytes = 6, 63 .eccpos = {0, 1, 2, 3, 6, 7}, 64 .oobfree = { 65 {.offset = 8, 66 . length = 8} } 67 }; 68 69 static struct nand_ecclayout nand_oob_64 = { 70 .eccbytes = 24, 71 .eccpos = { 72 40, 41, 42, 43, 44, 45, 46, 47, 73 48, 49, 50, 51, 52, 53, 54, 55, 74 56, 57, 58, 59, 60, 61, 62, 63}, 75 .oobfree = { 76 {.offset = 2, 77 .length = 38} } 78 }; 79 80 static struct nand_ecclayout nand_oob_128 = { 81 .eccbytes = 48, 82 .eccpos = { 83 80, 81, 82, 83, 84, 85, 86, 87, 84 88, 89, 90, 91, 92, 93, 94, 95, 85 96, 97, 98, 99, 100, 101, 102, 103, 86 104, 105, 106, 107, 108, 109, 110, 111, 87 112, 113, 114, 115, 116, 117, 118, 119, 88 120, 121, 122, 123, 124, 125, 126, 127}, 89 .oobfree = { 90 {.offset = 2, 91 .length = 78} } 92 }; 93 #endif 94 95 static int nand_get_device(struct mtd_info *mtd, int new_state); 96 97 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 98 struct mtd_oob_ops *ops); 99 100 /* 101 * For devices which display every fart in the system on a separate LED. Is 102 * compiled away when LED support is disabled. 103 */ 104 DEFINE_LED_TRIGGER(nand_led_trigger); 105 check_offs_len(struct mtd_info * mtd,loff_t ofs,uint64_t len)106 static int check_offs_len(struct mtd_info *mtd, 107 loff_t ofs, uint64_t len) 108 { 109 struct nand_chip *chip = mtd_to_nand(mtd); 110 int ret = 0; 111 112 /* Start address must align on block boundary */ 113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { 114 pr_debug("%s: unaligned address\n", __func__); 115 ret = -EINVAL; 116 } 117 118 /* Length must align on block boundary */ 119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { 120 pr_debug("%s: length not block aligned\n", __func__); 121 ret = -EINVAL; 122 } 123 124 return ret; 125 } 126 127 /** 128 * nand_release_device - [GENERIC] release chip 129 * @mtd: MTD device structure 130 * 131 * Release chip lock and wake up anyone waiting on the device. 132 */ nand_release_device(struct mtd_info * mtd)133 static void nand_release_device(struct mtd_info *mtd) 134 { 135 struct nand_chip *chip = mtd_to_nand(mtd); 136 137 /* De-select the NAND device */ 138 chip->select_chip(mtd, -1); 139 } 140 141 /** 142 * nand_read_byte - [DEFAULT] read one byte from the chip 143 * @mtd: MTD device structure 144 * 145 * Default read function for 8bit buswidth 146 */ nand_read_byte(struct mtd_info * mtd)147 uint8_t nand_read_byte(struct mtd_info *mtd) 148 { 149 struct nand_chip *chip = mtd_to_nand(mtd); 150 return readb(chip->IO_ADDR_R); 151 } 152 153 /** 154 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip 155 * @mtd: MTD device structure 156 * 157 * Default read function for 16bit buswidth with endianness conversion. 158 * 159 */ nand_read_byte16(struct mtd_info * mtd)160 static uint8_t nand_read_byte16(struct mtd_info *mtd) 161 { 162 struct nand_chip *chip = mtd_to_nand(mtd); 163 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); 164 } 165 166 /** 167 * nand_read_word - [DEFAULT] read one word from the chip 168 * @mtd: MTD device structure 169 * 170 * Default read function for 16bit buswidth without endianness conversion. 171 */ nand_read_word(struct mtd_info * mtd)172 static u16 nand_read_word(struct mtd_info *mtd) 173 { 174 struct nand_chip *chip = mtd_to_nand(mtd); 175 return readw(chip->IO_ADDR_R); 176 } 177 178 /** 179 * nand_select_chip - [DEFAULT] control CE line 180 * @mtd: MTD device structure 181 * @chipnr: chipnumber to select, -1 for deselect 182 * 183 * Default select function for 1 chip devices. 184 */ nand_select_chip(struct mtd_info * mtd,int chipnr)185 static void nand_select_chip(struct mtd_info *mtd, int chipnr) 186 { 187 struct nand_chip *chip = mtd_to_nand(mtd); 188 189 switch (chipnr) { 190 case -1: 191 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 192 break; 193 case 0: 194 break; 195 196 default: 197 BUG(); 198 } 199 } 200 201 /** 202 * nand_write_byte - [DEFAULT] write single byte to chip 203 * @mtd: MTD device structure 204 * @byte: value to write 205 * 206 * Default function to write a byte to I/O[7:0] 207 */ nand_write_byte(struct mtd_info * mtd,uint8_t byte)208 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) 209 { 210 struct nand_chip *chip = mtd_to_nand(mtd); 211 212 chip->write_buf(mtd, &byte, 1); 213 } 214 215 /** 216 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 217 * @mtd: MTD device structure 218 * @byte: value to write 219 * 220 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. 221 */ nand_write_byte16(struct mtd_info * mtd,uint8_t byte)222 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) 223 { 224 struct nand_chip *chip = mtd_to_nand(mtd); 225 uint16_t word = byte; 226 227 /* 228 * It's not entirely clear what should happen to I/O[15:8] when writing 229 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: 230 * 231 * When the host supports a 16-bit bus width, only data is 232 * transferred at the 16-bit width. All address and command line 233 * transfers shall use only the lower 8-bits of the data bus. During 234 * command transfers, the host may place any value on the upper 235 * 8-bits of the data bus. During address transfers, the host shall 236 * set the upper 8-bits of the data bus to 00h. 237 * 238 * One user of the write_byte callback is nand_onfi_set_features. The 239 * four parameters are specified to be written to I/O[7:0], but this is 240 * neither an address nor a command transfer. Let's assume a 0 on the 241 * upper I/O lines is OK. 242 */ 243 chip->write_buf(mtd, (uint8_t *)&word, 2); 244 } 245 iowrite8_rep(void * addr,const uint8_t * buf,int len)246 static void iowrite8_rep(void *addr, const uint8_t *buf, int len) 247 { 248 int i; 249 250 for (i = 0; i < len; i++) 251 writeb(buf[i], addr); 252 } ioread8_rep(void * addr,uint8_t * buf,int len)253 static void ioread8_rep(void *addr, uint8_t *buf, int len) 254 { 255 int i; 256 257 for (i = 0; i < len; i++) 258 buf[i] = readb(addr); 259 } 260 ioread16_rep(void * addr,void * buf,int len)261 static void ioread16_rep(void *addr, void *buf, int len) 262 { 263 int i; 264 u16 *p = (u16 *) buf; 265 266 for (i = 0; i < len; i++) 267 p[i] = readw(addr); 268 } 269 iowrite16_rep(void * addr,void * buf,int len)270 static void iowrite16_rep(void *addr, void *buf, int len) 271 { 272 int i; 273 u16 *p = (u16 *) buf; 274 275 for (i = 0; i < len; i++) 276 writew(p[i], addr); 277 } 278 279 /** 280 * nand_write_buf - [DEFAULT] write buffer to chip 281 * @mtd: MTD device structure 282 * @buf: data buffer 283 * @len: number of bytes to write 284 * 285 * Default write function for 8bit buswidth. 286 */ nand_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)287 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 288 { 289 struct nand_chip *chip = mtd_to_nand(mtd); 290 291 iowrite8_rep(chip->IO_ADDR_W, buf, len); 292 } 293 294 /** 295 * nand_read_buf - [DEFAULT] read chip data into buffer 296 * @mtd: MTD device structure 297 * @buf: buffer to store date 298 * @len: number of bytes to read 299 * 300 * Default read function for 8bit buswidth. 301 */ nand_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)302 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 303 { 304 struct nand_chip *chip = mtd_to_nand(mtd); 305 306 ioread8_rep(chip->IO_ADDR_R, buf, len); 307 } 308 309 /** 310 * nand_write_buf16 - [DEFAULT] write buffer to chip 311 * @mtd: MTD device structure 312 * @buf: data buffer 313 * @len: number of bytes to write 314 * 315 * Default write function for 16bit buswidth. 316 */ nand_write_buf16(struct mtd_info * mtd,const uint8_t * buf,int len)317 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) 318 { 319 struct nand_chip *chip = mtd_to_nand(mtd); 320 u16 *p = (u16 *) buf; 321 322 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); 323 } 324 325 /** 326 * nand_read_buf16 - [DEFAULT] read chip data into buffer 327 * @mtd: MTD device structure 328 * @buf: buffer to store date 329 * @len: number of bytes to read 330 * 331 * Default read function for 16bit buswidth. 332 */ nand_read_buf16(struct mtd_info * mtd,uint8_t * buf,int len)333 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 334 { 335 struct nand_chip *chip = mtd_to_nand(mtd); 336 u16 *p = (u16 *) buf; 337 338 ioread16_rep(chip->IO_ADDR_R, p, len >> 1); 339 } 340 341 /** 342 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 343 * @mtd: MTD device structure 344 * @ofs: offset from device start 345 * 346 * Check, if the block is bad. 347 */ nand_block_bad(struct mtd_info * mtd,loff_t ofs)348 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) 349 { 350 int page, res = 0, i = 0; 351 struct nand_chip *chip = mtd_to_nand(mtd); 352 u16 bad; 353 354 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) 355 ofs += mtd->erasesize - mtd->writesize; 356 357 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 358 359 do { 360 if (chip->options & NAND_BUSWIDTH_16) { 361 chip->cmdfunc(mtd, NAND_CMD_READOOB, 362 chip->badblockpos & 0xFE, page); 363 bad = cpu_to_le16(chip->read_word(mtd)); 364 if (chip->badblockpos & 0x1) 365 bad >>= 8; 366 else 367 bad &= 0xFF; 368 } else { 369 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, 370 page); 371 bad = chip->read_byte(mtd); 372 } 373 374 if (likely(chip->badblockbits == 8)) 375 res = bad != 0xFF; 376 else 377 res = hweight8(bad) < chip->badblockbits; 378 ofs += mtd->writesize; 379 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 380 i++; 381 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); 382 383 return res; 384 } 385 386 /** 387 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker 388 * @mtd: MTD device structure 389 * @ofs: offset from device start 390 * 391 * This is the default implementation, which can be overridden by a hardware 392 * specific driver. It provides the details for writing a bad block marker to a 393 * block. 394 */ nand_default_block_markbad(struct mtd_info * mtd,loff_t ofs)395 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) 396 { 397 struct nand_chip *chip = mtd_to_nand(mtd); 398 struct mtd_oob_ops ops; 399 uint8_t buf[2] = { 0, 0 }; 400 int ret = 0, res, i = 0; 401 402 memset(&ops, 0, sizeof(ops)); 403 ops.oobbuf = buf; 404 ops.ooboffs = chip->badblockpos; 405 if (chip->options & NAND_BUSWIDTH_16) { 406 ops.ooboffs &= ~0x01; 407 ops.len = ops.ooblen = 2; 408 } else { 409 ops.len = ops.ooblen = 1; 410 } 411 ops.mode = MTD_OPS_PLACE_OOB; 412 413 /* Write to first/last page(s) if necessary */ 414 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) 415 ofs += mtd->erasesize - mtd->writesize; 416 do { 417 res = nand_do_write_oob(mtd, ofs, &ops); 418 if (!ret) 419 ret = res; 420 421 i++; 422 ofs += mtd->writesize; 423 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); 424 425 return ret; 426 } 427 428 /** 429 * nand_block_markbad_lowlevel - mark a block bad 430 * @mtd: MTD device structure 431 * @ofs: offset from device start 432 * 433 * This function performs the generic NAND bad block marking steps (i.e., bad 434 * block table(s) and/or marker(s)). We only allow the hardware driver to 435 * specify how to write bad block markers to OOB (chip->block_markbad). 436 * 437 * We try operations in the following order: 438 * (1) erase the affected block, to allow OOB marker to be written cleanly 439 * (2) write bad block marker to OOB area of affected block (unless flag 440 * NAND_BBT_NO_OOB_BBM is present) 441 * (3) update the BBT 442 * Note that we retain the first error encountered in (2) or (3), finish the 443 * procedures, and dump the error in the end. 444 */ nand_block_markbad_lowlevel(struct mtd_info * mtd,loff_t ofs)445 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) 446 { 447 struct nand_chip *chip = mtd_to_nand(mtd); 448 int res, ret = 0; 449 450 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { 451 struct erase_info einfo; 452 453 /* Attempt erase before marking OOB */ 454 memset(&einfo, 0, sizeof(einfo)); 455 einfo.mtd = mtd; 456 einfo.addr = ofs; 457 einfo.len = 1ULL << chip->phys_erase_shift; 458 nand_erase_nand(mtd, &einfo, 0); 459 460 /* Write bad block marker to OOB */ 461 nand_get_device(mtd, FL_WRITING); 462 ret = chip->block_markbad(mtd, ofs); 463 nand_release_device(mtd); 464 } 465 466 /* Mark block bad in BBT */ 467 if (chip->bbt) { 468 res = nand_markbad_bbt(mtd, ofs); 469 if (!ret) 470 ret = res; 471 } 472 473 if (!ret) 474 mtd->ecc_stats.badblocks++; 475 476 return ret; 477 } 478 479 /** 480 * nand_check_wp - [GENERIC] check if the chip is write protected 481 * @mtd: MTD device structure 482 * 483 * Check, if the device is write protected. The function expects, that the 484 * device is already selected. 485 */ nand_check_wp(struct mtd_info * mtd)486 static int nand_check_wp(struct mtd_info *mtd) 487 { 488 struct nand_chip *chip = mtd_to_nand(mtd); 489 490 /* Broken xD cards report WP despite being writable */ 491 if (chip->options & NAND_BROKEN_XD) 492 return 0; 493 494 /* Check the WP bit */ 495 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 496 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; 497 } 498 499 /** 500 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. 501 * @mtd: MTD device structure 502 * @ofs: offset from device start 503 * 504 * Check if the block is marked as reserved. 505 */ nand_block_isreserved(struct mtd_info * mtd,loff_t ofs)506 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) 507 { 508 struct nand_chip *chip = mtd_to_nand(mtd); 509 510 if (!chip->bbt) 511 return 0; 512 /* Return info from the table */ 513 return nand_isreserved_bbt(mtd, ofs); 514 } 515 516 /** 517 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 518 * @mtd: MTD device structure 519 * @ofs: offset from device start 520 * @allowbbt: 1, if its allowed to access the bbt area 521 * 522 * Check, if the block is bad. Either by reading the bad block table or 523 * calling of the scan function. 524 */ nand_block_checkbad(struct mtd_info * mtd,loff_t ofs,int allowbbt)525 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) 526 { 527 struct nand_chip *chip = mtd_to_nand(mtd); 528 529 if (!(chip->options & NAND_SKIP_BBTSCAN) && 530 !(chip->options & NAND_BBT_SCANNED)) { 531 chip->options |= NAND_BBT_SCANNED; 532 chip->scan_bbt(mtd); 533 } 534 535 if (!chip->bbt) 536 return chip->block_bad(mtd, ofs); 537 538 /* Return info from the table */ 539 return nand_isbad_bbt(mtd, ofs, allowbbt); 540 } 541 542 /** 543 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. 544 * @mtd: MTD device structure 545 * 546 * Wait for the ready pin after a command, and warn if a timeout occurs. 547 */ nand_wait_ready(struct mtd_info * mtd)548 void nand_wait_ready(struct mtd_info *mtd) 549 { 550 struct nand_chip *chip = mtd_to_nand(mtd); 551 u32 timeo = (CONFIG_SYS_HZ * 400) / 1000; 552 u32 time_start; 553 554 time_start = get_timer(0); 555 /* Wait until command is processed or timeout occurs */ 556 while (get_timer(time_start) < timeo) { 557 if (chip->dev_ready) 558 if (chip->dev_ready(mtd)) 559 break; 560 } 561 562 if (!chip->dev_ready(mtd)) 563 pr_warn("timeout while waiting for chip to become ready\n"); 564 } 565 EXPORT_SYMBOL_GPL(nand_wait_ready); 566 567 /** 568 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. 569 * @mtd: MTD device structure 570 * @timeo: Timeout in ms 571 * 572 * Wait for status ready (i.e. command done) or timeout. 573 */ nand_wait_status_ready(struct mtd_info * mtd,unsigned long timeo)574 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) 575 { 576 register struct nand_chip *chip = mtd_to_nand(mtd); 577 u32 time_start; 578 579 timeo = (CONFIG_SYS_HZ * timeo) / 1000; 580 time_start = get_timer(0); 581 while (get_timer(time_start) < timeo) { 582 if ((chip->read_byte(mtd) & NAND_STATUS_READY)) 583 break; 584 WATCHDOG_RESET(); 585 } 586 }; 587 588 /** 589 * nand_command - [DEFAULT] Send command to NAND device 590 * @mtd: MTD device structure 591 * @command: the command to be sent 592 * @column: the column address for this command, -1 if none 593 * @page_addr: the page address for this command, -1 if none 594 * 595 * Send command to NAND device. This function is used for small page devices 596 * (512 Bytes per page). 597 */ nand_command(struct mtd_info * mtd,unsigned int command,int column,int page_addr)598 static void nand_command(struct mtd_info *mtd, unsigned int command, 599 int column, int page_addr) 600 { 601 register struct nand_chip *chip = mtd_to_nand(mtd); 602 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; 603 604 /* Write out the command to the device */ 605 if (command == NAND_CMD_SEQIN) { 606 int readcmd; 607 608 if (column >= mtd->writesize) { 609 /* OOB area */ 610 column -= mtd->writesize; 611 readcmd = NAND_CMD_READOOB; 612 } else if (column < 256) { 613 /* First 256 bytes --> READ0 */ 614 readcmd = NAND_CMD_READ0; 615 } else { 616 column -= 256; 617 readcmd = NAND_CMD_READ1; 618 } 619 chip->cmd_ctrl(mtd, readcmd, ctrl); 620 ctrl &= ~NAND_CTRL_CHANGE; 621 } 622 chip->cmd_ctrl(mtd, command, ctrl); 623 624 /* Address cycle, when necessary */ 625 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; 626 /* Serially input address */ 627 if (column != -1) { 628 /* Adjust columns for 16 bit buswidth */ 629 if (chip->options & NAND_BUSWIDTH_16 && 630 !nand_opcode_8bits(command)) 631 column >>= 1; 632 chip->cmd_ctrl(mtd, column, ctrl); 633 ctrl &= ~NAND_CTRL_CHANGE; 634 } 635 if (page_addr != -1) { 636 chip->cmd_ctrl(mtd, page_addr, ctrl); 637 ctrl &= ~NAND_CTRL_CHANGE; 638 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); 639 if (chip->options & NAND_ROW_ADDR_3) 640 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); 641 } 642 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 643 644 /* 645 * Program and erase have their own busy handlers status and sequential 646 * in needs no delay 647 */ 648 switch (command) { 649 650 case NAND_CMD_PAGEPROG: 651 case NAND_CMD_ERASE1: 652 case NAND_CMD_ERASE2: 653 case NAND_CMD_SEQIN: 654 case NAND_CMD_STATUS: 655 case NAND_CMD_READID: 656 case NAND_CMD_SET_FEATURES: 657 return; 658 659 case NAND_CMD_RESET: 660 if (chip->dev_ready) 661 break; 662 udelay(chip->chip_delay); 663 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 664 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 665 chip->cmd_ctrl(mtd, 666 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 667 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ 668 nand_wait_status_ready(mtd, 250); 669 return; 670 671 /* This applies to read commands */ 672 default: 673 /* 674 * If we don't have access to the busy pin, we apply the given 675 * command delay 676 */ 677 if (!chip->dev_ready) { 678 udelay(chip->chip_delay); 679 return; 680 } 681 } 682 /* 683 * Apply this short delay always to ensure that we do wait tWB in 684 * any case on any machine. 685 */ 686 ndelay(100); 687 688 nand_wait_ready(mtd); 689 } 690 691 /** 692 * nand_command_lp - [DEFAULT] Send command to NAND large page device 693 * @mtd: MTD device structure 694 * @command: the command to be sent 695 * @column: the column address for this command, -1 if none 696 * @page_addr: the page address for this command, -1 if none 697 * 698 * Send command to NAND device. This is the version for the new large page 699 * devices. We don't have the separate regions as we have in the small page 700 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. 701 */ nand_command_lp(struct mtd_info * mtd,unsigned int command,int column,int page_addr)702 static void nand_command_lp(struct mtd_info *mtd, unsigned int command, 703 int column, int page_addr) 704 { 705 register struct nand_chip *chip = mtd_to_nand(mtd); 706 707 /* Emulate NAND_CMD_READOOB */ 708 if (command == NAND_CMD_READOOB) { 709 column += mtd->writesize; 710 command = NAND_CMD_READ0; 711 } 712 713 /* Command latch cycle */ 714 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 715 716 if (column != -1 || page_addr != -1) { 717 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; 718 719 /* Serially input address */ 720 if (column != -1) { 721 /* Adjust columns for 16 bit buswidth */ 722 if (chip->options & NAND_BUSWIDTH_16 && 723 !nand_opcode_8bits(command)) 724 column >>= 1; 725 chip->cmd_ctrl(mtd, column, ctrl); 726 ctrl &= ~NAND_CTRL_CHANGE; 727 chip->cmd_ctrl(mtd, column >> 8, ctrl); 728 } 729 if (page_addr != -1) { 730 chip->cmd_ctrl(mtd, page_addr, ctrl); 731 chip->cmd_ctrl(mtd, page_addr >> 8, 732 NAND_NCE | NAND_ALE); 733 if (chip->options & NAND_ROW_ADDR_3) 734 chip->cmd_ctrl(mtd, page_addr >> 16, 735 NAND_NCE | NAND_ALE); 736 } 737 } 738 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 739 740 /* 741 * Program and erase have their own busy handlers status, sequential 742 * in and status need no delay. 743 */ 744 switch (command) { 745 746 case NAND_CMD_CACHEDPROG: 747 case NAND_CMD_PAGEPROG: 748 case NAND_CMD_ERASE1: 749 case NAND_CMD_ERASE2: 750 case NAND_CMD_SEQIN: 751 case NAND_CMD_RNDIN: 752 case NAND_CMD_STATUS: 753 case NAND_CMD_READID: 754 case NAND_CMD_SET_FEATURES: 755 return; 756 757 case NAND_CMD_RESET: 758 if (chip->dev_ready) 759 break; 760 udelay(chip->chip_delay); 761 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 762 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 763 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 764 NAND_NCE | NAND_CTRL_CHANGE); 765 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ 766 nand_wait_status_ready(mtd, 250); 767 return; 768 769 case NAND_CMD_RNDOUT: 770 /* No ready / busy check necessary */ 771 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, 772 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 773 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 774 NAND_NCE | NAND_CTRL_CHANGE); 775 return; 776 777 case NAND_CMD_READ0: 778 chip->cmd_ctrl(mtd, NAND_CMD_READSTART, 779 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 780 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 781 NAND_NCE | NAND_CTRL_CHANGE); 782 783 /* This applies to read commands */ 784 default: 785 /* 786 * If we don't have access to the busy pin, we apply the given 787 * command delay. 788 */ 789 if (!chip->dev_ready) { 790 udelay(chip->chip_delay); 791 return; 792 } 793 } 794 795 /* 796 * Apply this short delay always to ensure that we do wait tWB in 797 * any case on any machine. 798 */ 799 ndelay(100); 800 801 nand_wait_ready(mtd); 802 } 803 804 /** 805 * panic_nand_get_device - [GENERIC] Get chip for selected access 806 * @chip: the nand chip descriptor 807 * @mtd: MTD device structure 808 * @new_state: the state which is requested 809 * 810 * Used when in panic, no locks are taken. 811 */ panic_nand_get_device(struct nand_chip * chip,struct mtd_info * mtd,int new_state)812 static void panic_nand_get_device(struct nand_chip *chip, 813 struct mtd_info *mtd, int new_state) 814 { 815 /* Hardware controller shared among independent devices */ 816 chip->controller->active = chip; 817 chip->state = new_state; 818 } 819 820 /** 821 * nand_get_device - [GENERIC] Get chip for selected access 822 * @mtd: MTD device structure 823 * @new_state: the state which is requested 824 * 825 * Get the device and lock it for exclusive access 826 */ 827 static int nand_get_device(struct mtd_info * mtd,int new_state)828 nand_get_device(struct mtd_info *mtd, int new_state) 829 { 830 struct nand_chip *chip = mtd_to_nand(mtd); 831 chip->state = new_state; 832 return 0; 833 } 834 835 /** 836 * panic_nand_wait - [GENERIC] wait until the command is done 837 * @mtd: MTD device structure 838 * @chip: NAND chip structure 839 * @timeo: timeout 840 * 841 * Wait for command done. This is a helper function for nand_wait used when 842 * we are in interrupt context. May happen when in panic and trying to write 843 * an oops through mtdoops. 844 */ panic_nand_wait(struct mtd_info * mtd,struct nand_chip * chip,unsigned long timeo)845 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, 846 unsigned long timeo) 847 { 848 int i; 849 for (i = 0; i < timeo; i++) { 850 if (chip->dev_ready) { 851 if (chip->dev_ready(mtd)) 852 break; 853 } else { 854 if (chip->read_byte(mtd) & NAND_STATUS_READY) 855 break; 856 } 857 mdelay(1); 858 } 859 } 860 861 /** 862 * nand_wait - [DEFAULT] wait until the command is done 863 * @mtd: MTD device structure 864 * @chip: NAND chip structure 865 * 866 * Wait for command done. This applies to erase and program only. 867 */ nand_wait(struct mtd_info * mtd,struct nand_chip * chip)868 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) 869 { 870 int status; 871 unsigned long timeo = 400; 872 873 led_trigger_event(nand_led_trigger, LED_FULL); 874 875 /* 876 * Apply this short delay always to ensure that we do wait tWB in any 877 * case on any machine. 878 */ 879 ndelay(100); 880 881 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 882 883 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; 884 u32 time_start; 885 886 time_start = get_timer(0); 887 while (get_timer(time_start) < timer) { 888 if (chip->dev_ready) { 889 if (chip->dev_ready(mtd)) 890 break; 891 } else { 892 if (chip->read_byte(mtd) & NAND_STATUS_READY) 893 break; 894 } 895 } 896 led_trigger_event(nand_led_trigger, LED_OFF); 897 898 status = (int)chip->read_byte(mtd); 899 /* This can happen if in case of timeout or buggy dev_ready */ 900 WARN_ON(!(status & NAND_STATUS_READY)); 901 return status; 902 } 903 904 /** 905 * nand_reset_data_interface - Reset data interface and timings 906 * @chip: The NAND chip 907 * @chipnr: Internal die id 908 * 909 * Reset the Data interface and timings to ONFI mode 0. 910 * 911 * Returns 0 for success or negative error code otherwise. 912 */ nand_reset_data_interface(struct nand_chip * chip,int chipnr)913 static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) 914 { 915 struct mtd_info *mtd = nand_to_mtd(chip); 916 const struct nand_data_interface *conf; 917 int ret; 918 919 if (!chip->setup_data_interface) 920 return 0; 921 922 /* 923 * The ONFI specification says: 924 * " 925 * To transition from NV-DDR or NV-DDR2 to the SDR data 926 * interface, the host shall use the Reset (FFh) command 927 * using SDR timing mode 0. A device in any timing mode is 928 * required to recognize Reset (FFh) command issued in SDR 929 * timing mode 0. 930 * " 931 * 932 * Configure the data interface in SDR mode and set the 933 * timings to timing mode 0. 934 */ 935 936 conf = nand_get_default_data_interface(); 937 ret = chip->setup_data_interface(mtd, chipnr, conf); 938 if (ret) 939 pr_err("Failed to configure data interface to SDR timing mode 0\n"); 940 941 return ret; 942 } 943 944 /** 945 * nand_setup_data_interface - Setup the best data interface and timings 946 * @chip: The NAND chip 947 * @chipnr: Internal die id 948 * 949 * Find and configure the best data interface and NAND timings supported by 950 * the chip and the driver. 951 * First tries to retrieve supported timing modes from ONFI information, 952 * and if the NAND chip does not support ONFI, relies on the 953 * ->onfi_timing_mode_default specified in the nand_ids table. 954 * 955 * Returns 0 for success or negative error code otherwise. 956 */ nand_setup_data_interface(struct nand_chip * chip,int chipnr)957 static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) 958 { 959 struct mtd_info *mtd = nand_to_mtd(chip); 960 int ret; 961 962 if (!chip->setup_data_interface || !chip->data_interface) 963 return 0; 964 965 /* 966 * Ensure the timing mode has been changed on the chip side 967 * before changing timings on the controller side. 968 */ 969 if (chip->onfi_version) { 970 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { 971 chip->onfi_timing_mode_default, 972 }; 973 974 ret = chip->onfi_set_features(mtd, chip, 975 ONFI_FEATURE_ADDR_TIMING_MODE, 976 tmode_param); 977 if (ret) 978 goto err; 979 } 980 981 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); 982 err: 983 return ret; 984 } 985 986 /** 987 * nand_init_data_interface - find the best data interface and timings 988 * @chip: The NAND chip 989 * 990 * Find the best data interface and NAND timings supported by the chip 991 * and the driver. 992 * First tries to retrieve supported timing modes from ONFI information, 993 * and if the NAND chip does not support ONFI, relies on the 994 * ->onfi_timing_mode_default specified in the nand_ids table. After this 995 * function nand_chip->data_interface is initialized with the best timing mode 996 * available. 997 * 998 * Returns 0 for success or negative error code otherwise. 999 */ nand_init_data_interface(struct nand_chip * chip)1000 static int nand_init_data_interface(struct nand_chip *chip) 1001 { 1002 struct mtd_info *mtd = nand_to_mtd(chip); 1003 int modes, mode, ret; 1004 1005 if (!chip->setup_data_interface) 1006 return 0; 1007 1008 /* 1009 * First try to identify the best timings from ONFI parameters and 1010 * if the NAND does not support ONFI, fallback to the default ONFI 1011 * timing mode. 1012 */ 1013 modes = onfi_get_async_timing_mode(chip); 1014 if (modes == ONFI_TIMING_MODE_UNKNOWN) { 1015 if (!chip->onfi_timing_mode_default) 1016 return 0; 1017 1018 modes = GENMASK(chip->onfi_timing_mode_default, 0); 1019 } 1020 1021 chip->data_interface = kzalloc(sizeof(*chip->data_interface), 1022 GFP_KERNEL); 1023 if (!chip->data_interface) 1024 return -ENOMEM; 1025 1026 for (mode = fls(modes) - 1; mode >= 0; mode--) { 1027 ret = onfi_init_data_interface(chip, chip->data_interface, 1028 NAND_SDR_IFACE, mode); 1029 if (ret) 1030 continue; 1031 1032 /* Pass -1 to only */ 1033 ret = chip->setup_data_interface(mtd, 1034 NAND_DATA_IFACE_CHECK_ONLY, 1035 chip->data_interface); 1036 if (!ret) { 1037 chip->onfi_timing_mode_default = mode; 1038 break; 1039 } 1040 } 1041 1042 return 0; 1043 } 1044 nand_release_data_interface(struct nand_chip * chip)1045 static void __maybe_unused nand_release_data_interface(struct nand_chip *chip) 1046 { 1047 kfree(chip->data_interface); 1048 } 1049 1050 /** 1051 * nand_reset - Reset and initialize a NAND device 1052 * @chip: The NAND chip 1053 * @chipnr: Internal die id 1054 * 1055 * Returns 0 for success or negative error code otherwise 1056 */ nand_reset(struct nand_chip * chip,int chipnr)1057 int nand_reset(struct nand_chip *chip, int chipnr) 1058 { 1059 struct mtd_info *mtd = nand_to_mtd(chip); 1060 int ret; 1061 1062 ret = nand_reset_data_interface(chip, chipnr); 1063 if (ret) 1064 return ret; 1065 1066 /* 1067 * The CS line has to be released before we can apply the new NAND 1068 * interface settings, hence this weird ->select_chip() dance. 1069 */ 1070 chip->select_chip(mtd, chipnr); 1071 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1072 chip->select_chip(mtd, -1); 1073 1074 chip->select_chip(mtd, chipnr); 1075 ret = nand_setup_data_interface(chip, chipnr); 1076 chip->select_chip(mtd, -1); 1077 if (ret) 1078 return ret; 1079 1080 return 0; 1081 } 1082 1083 /** 1084 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data 1085 * @buf: buffer to test 1086 * @len: buffer length 1087 * @bitflips_threshold: maximum number of bitflips 1088 * 1089 * Check if a buffer contains only 0xff, which means the underlying region 1090 * has been erased and is ready to be programmed. 1091 * The bitflips_threshold specify the maximum number of bitflips before 1092 * considering the region is not erased. 1093 * Note: The logic of this function has been extracted from the memweight 1094 * implementation, except that nand_check_erased_buf function exit before 1095 * testing the whole buffer if the number of bitflips exceed the 1096 * bitflips_threshold value. 1097 * 1098 * Returns a positive number of bitflips less than or equal to 1099 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 1100 * threshold. 1101 */ nand_check_erased_buf(void * buf,int len,int bitflips_threshold)1102 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) 1103 { 1104 const unsigned char *bitmap = buf; 1105 int bitflips = 0; 1106 int weight; 1107 1108 for (; len && ((uintptr_t)bitmap) % sizeof(long); 1109 len--, bitmap++) { 1110 weight = hweight8(*bitmap); 1111 bitflips += BITS_PER_BYTE - weight; 1112 if (unlikely(bitflips > bitflips_threshold)) 1113 return -EBADMSG; 1114 } 1115 1116 for (; len >= 4; len -= 4, bitmap += 4) { 1117 weight = hweight32(*((u32 *)bitmap)); 1118 bitflips += 32 - weight; 1119 if (unlikely(bitflips > bitflips_threshold)) 1120 return -EBADMSG; 1121 } 1122 1123 for (; len > 0; len--, bitmap++) { 1124 weight = hweight8(*bitmap); 1125 bitflips += BITS_PER_BYTE - weight; 1126 if (unlikely(bitflips > bitflips_threshold)) 1127 return -EBADMSG; 1128 } 1129 1130 return bitflips; 1131 } 1132 1133 /** 1134 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only 1135 * 0xff data 1136 * @data: data buffer to test 1137 * @datalen: data length 1138 * @ecc: ECC buffer 1139 * @ecclen: ECC length 1140 * @extraoob: extra OOB buffer 1141 * @extraooblen: extra OOB length 1142 * @bitflips_threshold: maximum number of bitflips 1143 * 1144 * Check if a data buffer and its associated ECC and OOB data contains only 1145 * 0xff pattern, which means the underlying region has been erased and is 1146 * ready to be programmed. 1147 * The bitflips_threshold specify the maximum number of bitflips before 1148 * considering the region as not erased. 1149 * 1150 * Note: 1151 * 1/ ECC algorithms are working on pre-defined block sizes which are usually 1152 * different from the NAND page size. When fixing bitflips, ECC engines will 1153 * report the number of errors per chunk, and the NAND core infrastructure 1154 * expect you to return the maximum number of bitflips for the whole page. 1155 * This is why you should always use this function on a single chunk and 1156 * not on the whole page. After checking each chunk you should update your 1157 * max_bitflips value accordingly. 1158 * 2/ When checking for bitflips in erased pages you should not only check 1159 * the payload data but also their associated ECC data, because a user might 1160 * have programmed almost all bits to 1 but a few. In this case, we 1161 * shouldn't consider the chunk as erased, and checking ECC bytes prevent 1162 * this case. 1163 * 3/ The extraoob argument is optional, and should be used if some of your OOB 1164 * data are protected by the ECC engine. 1165 * It could also be used if you support subpages and want to attach some 1166 * extra OOB data to an ECC chunk. 1167 * 1168 * Returns a positive number of bitflips less than or equal to 1169 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 1170 * threshold. In case of success, the passed buffers are filled with 0xff. 1171 */ nand_check_erased_ecc_chunk(void * data,int datalen,void * ecc,int ecclen,void * extraoob,int extraooblen,int bitflips_threshold)1172 int nand_check_erased_ecc_chunk(void *data, int datalen, 1173 void *ecc, int ecclen, 1174 void *extraoob, int extraooblen, 1175 int bitflips_threshold) 1176 { 1177 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; 1178 1179 data_bitflips = nand_check_erased_buf(data, datalen, 1180 bitflips_threshold); 1181 if (data_bitflips < 0) 1182 return data_bitflips; 1183 1184 bitflips_threshold -= data_bitflips; 1185 1186 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); 1187 if (ecc_bitflips < 0) 1188 return ecc_bitflips; 1189 1190 bitflips_threshold -= ecc_bitflips; 1191 1192 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, 1193 bitflips_threshold); 1194 if (extraoob_bitflips < 0) 1195 return extraoob_bitflips; 1196 1197 if (data_bitflips) 1198 memset(data, 0xff, datalen); 1199 1200 if (ecc_bitflips) 1201 memset(ecc, 0xff, ecclen); 1202 1203 if (extraoob_bitflips) 1204 memset(extraoob, 0xff, extraooblen); 1205 1206 return data_bitflips + ecc_bitflips + extraoob_bitflips; 1207 } 1208 EXPORT_SYMBOL(nand_check_erased_ecc_chunk); 1209 1210 /** 1211 * nand_read_page_raw - [INTERN] read raw page data without ecc 1212 * @mtd: mtd info structure 1213 * @chip: nand chip info structure 1214 * @buf: buffer to store read data 1215 * @oob_required: caller requires OOB data read to chip->oob_poi 1216 * @page: page number to read 1217 * 1218 * Not for syndrome calculating ECC controllers, which use a special oob layout. 1219 */ nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1220 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1221 uint8_t *buf, int oob_required, int page) 1222 { 1223 chip->read_buf(mtd, buf, mtd->writesize); 1224 if (oob_required) 1225 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1226 return 0; 1227 } 1228 1229 /** 1230 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc 1231 * @mtd: mtd info structure 1232 * @chip: nand chip info structure 1233 * @buf: buffer to store read data 1234 * @oob_required: caller requires OOB data read to chip->oob_poi 1235 * @page: page number to read 1236 * 1237 * We need a special oob layout and handling even when OOB isn't used. 1238 */ nand_read_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1239 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, 1240 struct nand_chip *chip, uint8_t *buf, 1241 int oob_required, int page) 1242 { 1243 int eccsize = chip->ecc.size; 1244 int eccbytes = chip->ecc.bytes; 1245 uint8_t *oob = chip->oob_poi; 1246 int steps, size; 1247 1248 for (steps = chip->ecc.steps; steps > 0; steps--) { 1249 chip->read_buf(mtd, buf, eccsize); 1250 buf += eccsize; 1251 1252 if (chip->ecc.prepad) { 1253 chip->read_buf(mtd, oob, chip->ecc.prepad); 1254 oob += chip->ecc.prepad; 1255 } 1256 1257 chip->read_buf(mtd, oob, eccbytes); 1258 oob += eccbytes; 1259 1260 if (chip->ecc.postpad) { 1261 chip->read_buf(mtd, oob, chip->ecc.postpad); 1262 oob += chip->ecc.postpad; 1263 } 1264 } 1265 1266 size = mtd->oobsize - (oob - chip->oob_poi); 1267 if (size) 1268 chip->read_buf(mtd, oob, size); 1269 1270 return 0; 1271 } 1272 1273 /** 1274 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function 1275 * @mtd: mtd info structure 1276 * @chip: nand chip info structure 1277 * @buf: buffer to store read data 1278 * @oob_required: caller requires OOB data read to chip->oob_poi 1279 * @page: page number to read 1280 */ nand_read_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1281 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 1282 uint8_t *buf, int oob_required, int page) 1283 { 1284 int i, eccsize = chip->ecc.size; 1285 int eccbytes = chip->ecc.bytes; 1286 int eccsteps = chip->ecc.steps; 1287 uint8_t *p = buf; 1288 uint8_t *ecc_calc = chip->buffers->ecccalc; 1289 uint8_t *ecc_code = chip->buffers->ecccode; 1290 uint32_t *eccpos = chip->ecc.layout->eccpos; 1291 unsigned int max_bitflips = 0; 1292 1293 chip->ecc.read_page_raw(mtd, chip, buf, 1, page); 1294 1295 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 1296 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1297 1298 for (i = 0; i < chip->ecc.total; i++) 1299 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1300 1301 eccsteps = chip->ecc.steps; 1302 p = buf; 1303 1304 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1305 int stat; 1306 1307 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 1308 if (stat < 0) { 1309 mtd->ecc_stats.failed++; 1310 } else { 1311 mtd->ecc_stats.corrected += stat; 1312 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1313 } 1314 } 1315 return max_bitflips; 1316 } 1317 1318 /** 1319 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function 1320 * @mtd: mtd info structure 1321 * @chip: nand chip info structure 1322 * @data_offs: offset of requested data within the page 1323 * @readlen: data length 1324 * @bufpoi: buffer to store read data 1325 * @page: page number to read 1326 */ nand_read_subpage(struct mtd_info * mtd,struct nand_chip * chip,uint32_t data_offs,uint32_t readlen,uint8_t * bufpoi,int page)1327 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, 1328 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, 1329 int page) 1330 { 1331 int start_step, end_step, num_steps; 1332 uint32_t *eccpos = chip->ecc.layout->eccpos; 1333 uint8_t *p; 1334 int data_col_addr, i, gaps = 0; 1335 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 1336 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 1337 int index; 1338 unsigned int max_bitflips = 0; 1339 1340 /* Column address within the page aligned to ECC size (256bytes) */ 1341 start_step = data_offs / chip->ecc.size; 1342 end_step = (data_offs + readlen - 1) / chip->ecc.size; 1343 num_steps = end_step - start_step + 1; 1344 index = start_step * chip->ecc.bytes; 1345 1346 /* Data size aligned to ECC ecc.size */ 1347 datafrag_len = num_steps * chip->ecc.size; 1348 eccfrag_len = num_steps * chip->ecc.bytes; 1349 1350 data_col_addr = start_step * chip->ecc.size; 1351 /* If we read not a page aligned data */ 1352 if (data_col_addr != 0) 1353 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); 1354 1355 p = bufpoi + data_col_addr; 1356 chip->read_buf(mtd, p, datafrag_len); 1357 1358 /* Calculate ECC */ 1359 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 1360 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); 1361 1362 /* 1363 * The performance is faster if we position offsets according to 1364 * ecc.pos. Let's make sure that there are no gaps in ECC positions. 1365 */ 1366 for (i = 0; i < eccfrag_len - 1; i++) { 1367 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { 1368 gaps = 1; 1369 break; 1370 } 1371 } 1372 if (gaps) { 1373 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); 1374 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1375 } else { 1376 /* 1377 * Send the command to read the particular ECC bytes take care 1378 * about buswidth alignment in read_buf. 1379 */ 1380 aligned_pos = eccpos[index] & ~(busw - 1); 1381 aligned_len = eccfrag_len; 1382 if (eccpos[index] & (busw - 1)) 1383 aligned_len++; 1384 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) 1385 aligned_len++; 1386 1387 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 1388 mtd->writesize + aligned_pos, -1); 1389 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); 1390 } 1391 1392 for (i = 0; i < eccfrag_len; i++) 1393 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; 1394 1395 p = bufpoi + data_col_addr; 1396 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 1397 int stat; 1398 1399 stat = chip->ecc.correct(mtd, p, 1400 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); 1401 if (stat == -EBADMSG && 1402 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 1403 /* check for empty pages with bitflips */ 1404 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 1405 &chip->buffers->ecccode[i], 1406 chip->ecc.bytes, 1407 NULL, 0, 1408 chip->ecc.strength); 1409 } 1410 1411 if (stat < 0) { 1412 mtd->ecc_stats.failed++; 1413 } else { 1414 mtd->ecc_stats.corrected += stat; 1415 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1416 } 1417 } 1418 return max_bitflips; 1419 } 1420 1421 /** 1422 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function 1423 * @mtd: mtd info structure 1424 * @chip: nand chip info structure 1425 * @buf: buffer to store read data 1426 * @oob_required: caller requires OOB data read to chip->oob_poi 1427 * @page: page number to read 1428 * 1429 * Not for syndrome calculating ECC controllers which need a special oob layout. 1430 */ nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1431 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 1432 uint8_t *buf, int oob_required, int page) 1433 { 1434 int i, eccsize = chip->ecc.size; 1435 int eccbytes = chip->ecc.bytes; 1436 int eccsteps = chip->ecc.steps; 1437 uint8_t *p = buf; 1438 uint8_t *ecc_calc = chip->buffers->ecccalc; 1439 uint8_t *ecc_code = chip->buffers->ecccode; 1440 uint32_t *eccpos = chip->ecc.layout->eccpos; 1441 unsigned int max_bitflips = 0; 1442 1443 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1444 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1445 chip->read_buf(mtd, p, eccsize); 1446 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1447 } 1448 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1449 1450 for (i = 0; i < chip->ecc.total; i++) 1451 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1452 1453 eccsteps = chip->ecc.steps; 1454 p = buf; 1455 1456 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1457 int stat; 1458 1459 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 1460 if (stat == -EBADMSG && 1461 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 1462 /* check for empty pages with bitflips */ 1463 stat = nand_check_erased_ecc_chunk(p, eccsize, 1464 &ecc_code[i], eccbytes, 1465 NULL, 0, 1466 chip->ecc.strength); 1467 } 1468 1469 if (stat < 0) { 1470 mtd->ecc_stats.failed++; 1471 } else { 1472 mtd->ecc_stats.corrected += stat; 1473 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1474 } 1475 } 1476 return max_bitflips; 1477 } 1478 1479 /** 1480 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first 1481 * @mtd: mtd info structure 1482 * @chip: nand chip info structure 1483 * @buf: buffer to store read data 1484 * @oob_required: caller requires OOB data read to chip->oob_poi 1485 * @page: page number to read 1486 * 1487 * Hardware ECC for large page chips, require OOB to be read first. For this 1488 * ECC mode, the write_page method is re-used from ECC_HW. These methods 1489 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with 1490 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from 1491 * the data area, by overwriting the NAND manufacturer bad block markings. 1492 */ nand_read_page_hwecc_oob_first(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1493 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, 1494 struct nand_chip *chip, uint8_t *buf, int oob_required, int page) 1495 { 1496 int i, eccsize = chip->ecc.size; 1497 int eccbytes = chip->ecc.bytes; 1498 int eccsteps = chip->ecc.steps; 1499 uint8_t *p = buf; 1500 uint8_t *ecc_code = chip->buffers->ecccode; 1501 uint32_t *eccpos = chip->ecc.layout->eccpos; 1502 uint8_t *ecc_calc = chip->buffers->ecccalc; 1503 unsigned int max_bitflips = 0; 1504 1505 /* Read the OOB area first */ 1506 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 1507 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1508 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); 1509 1510 for (i = 0; i < chip->ecc.total; i++) 1511 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1512 1513 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1514 int stat; 1515 1516 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1517 chip->read_buf(mtd, p, eccsize); 1518 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1519 1520 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); 1521 if (stat == -EBADMSG && 1522 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 1523 /* check for empty pages with bitflips */ 1524 stat = nand_check_erased_ecc_chunk(p, eccsize, 1525 &ecc_code[i], eccbytes, 1526 NULL, 0, 1527 chip->ecc.strength); 1528 } 1529 1530 if (stat < 0) { 1531 mtd->ecc_stats.failed++; 1532 } else { 1533 mtd->ecc_stats.corrected += stat; 1534 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1535 } 1536 } 1537 return max_bitflips; 1538 } 1539 1540 /** 1541 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read 1542 * @mtd: mtd info structure 1543 * @chip: nand chip info structure 1544 * @buf: buffer to store read data 1545 * @oob_required: caller requires OOB data read to chip->oob_poi 1546 * @page: page number to read 1547 * 1548 * The hw generator calculates the error syndrome automatically. Therefore we 1549 * need a special oob layout and handling. 1550 */ nand_read_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1551 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1552 uint8_t *buf, int oob_required, int page) 1553 { 1554 int i, eccsize = chip->ecc.size; 1555 int eccbytes = chip->ecc.bytes; 1556 int eccsteps = chip->ecc.steps; 1557 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 1558 uint8_t *p = buf; 1559 uint8_t *oob = chip->oob_poi; 1560 unsigned int max_bitflips = 0; 1561 1562 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1563 int stat; 1564 1565 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1566 chip->read_buf(mtd, p, eccsize); 1567 1568 if (chip->ecc.prepad) { 1569 chip->read_buf(mtd, oob, chip->ecc.prepad); 1570 oob += chip->ecc.prepad; 1571 } 1572 1573 chip->ecc.hwctl(mtd, NAND_ECC_READSYN); 1574 chip->read_buf(mtd, oob, eccbytes); 1575 stat = chip->ecc.correct(mtd, p, oob, NULL); 1576 1577 oob += eccbytes; 1578 1579 if (chip->ecc.postpad) { 1580 chip->read_buf(mtd, oob, chip->ecc.postpad); 1581 oob += chip->ecc.postpad; 1582 } 1583 1584 if (stat == -EBADMSG && 1585 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 1586 /* check for empty pages with bitflips */ 1587 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 1588 oob - eccpadbytes, 1589 eccpadbytes, 1590 NULL, 0, 1591 chip->ecc.strength); 1592 } 1593 1594 if (stat < 0) { 1595 mtd->ecc_stats.failed++; 1596 } else { 1597 mtd->ecc_stats.corrected += stat; 1598 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1599 } 1600 } 1601 1602 /* Calculate remaining oob bytes */ 1603 i = mtd->oobsize - (oob - chip->oob_poi); 1604 if (i) 1605 chip->read_buf(mtd, oob, i); 1606 1607 return max_bitflips; 1608 } 1609 1610 /** 1611 * nand_transfer_oob - [INTERN] Transfer oob to client buffer 1612 * @chip: nand chip structure 1613 * @oob: oob destination address 1614 * @ops: oob ops structure 1615 * @len: size of oob to transfer 1616 */ nand_transfer_oob(struct nand_chip * chip,uint8_t * oob,struct mtd_oob_ops * ops,size_t len)1617 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 1618 struct mtd_oob_ops *ops, size_t len) 1619 { 1620 switch (ops->mode) { 1621 1622 case MTD_OPS_PLACE_OOB: 1623 case MTD_OPS_RAW: 1624 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 1625 return oob + len; 1626 1627 case MTD_OPS_AUTO_OOB: { 1628 struct nand_oobfree *free = chip->ecc.layout->oobfree; 1629 uint32_t boffs = 0, roffs = ops->ooboffs; 1630 size_t bytes = 0; 1631 1632 for (; free->length && len; free++, len -= bytes) { 1633 /* Read request not from offset 0? */ 1634 if (unlikely(roffs)) { 1635 if (roffs >= free->length) { 1636 roffs -= free->length; 1637 continue; 1638 } 1639 boffs = free->offset + roffs; 1640 bytes = min_t(size_t, len, 1641 (free->length - roffs)); 1642 roffs = 0; 1643 } else { 1644 bytes = min_t(size_t, len, free->length); 1645 boffs = free->offset; 1646 } 1647 memcpy(oob, chip->oob_poi + boffs, bytes); 1648 oob += bytes; 1649 } 1650 return oob; 1651 } 1652 default: 1653 BUG(); 1654 } 1655 return NULL; 1656 } 1657 1658 /** 1659 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode 1660 * @mtd: MTD device structure 1661 * @retry_mode: the retry mode to use 1662 * 1663 * Some vendors supply a special command to shift the Vt threshold, to be used 1664 * when there are too many bitflips in a page (i.e., ECC error). After setting 1665 * a new threshold, the host should retry reading the page. 1666 */ nand_setup_read_retry(struct mtd_info * mtd,int retry_mode)1667 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) 1668 { 1669 struct nand_chip *chip = mtd_to_nand(mtd); 1670 1671 pr_debug("setting READ RETRY mode %d\n", retry_mode); 1672 1673 if (retry_mode >= chip->read_retries) 1674 return -EINVAL; 1675 1676 if (!chip->setup_read_retry) 1677 return -EOPNOTSUPP; 1678 1679 return chip->setup_read_retry(mtd, retry_mode); 1680 } 1681 1682 /** 1683 * nand_do_read_ops - [INTERN] Read data with ECC 1684 * @mtd: MTD device structure 1685 * @from: offset to read from 1686 * @ops: oob ops structure 1687 * 1688 * Internal function. Called with chip held. 1689 */ nand_do_read_ops(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)1690 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, 1691 struct mtd_oob_ops *ops) 1692 { 1693 int chipnr, page, realpage, col, bytes, aligned, oob_required; 1694 struct nand_chip *chip = mtd_to_nand(mtd); 1695 int ret = 0; 1696 uint32_t readlen = ops->len; 1697 uint32_t oobreadlen = ops->ooblen; 1698 uint32_t max_oobsize = mtd_oobavail(mtd, ops); 1699 1700 uint8_t *bufpoi, *oob, *buf; 1701 int use_bufpoi; 1702 unsigned int max_bitflips = 0; 1703 int retry_mode = 0; 1704 bool ecc_fail = false; 1705 1706 chipnr = (int)(from >> chip->chip_shift); 1707 chip->select_chip(mtd, chipnr); 1708 1709 realpage = (int)(from >> chip->page_shift); 1710 page = realpage & chip->pagemask; 1711 1712 col = (int)(from & (mtd->writesize - 1)); 1713 1714 buf = ops->datbuf; 1715 oob = ops->oobbuf; 1716 oob_required = oob ? 1 : 0; 1717 1718 while (1) { 1719 unsigned int ecc_failures = mtd->ecc_stats.failed; 1720 1721 WATCHDOG_RESET(); 1722 bytes = min(mtd->writesize - col, readlen); 1723 aligned = (bytes == mtd->writesize); 1724 1725 if (!aligned) 1726 use_bufpoi = 1; 1727 else if (chip->options & NAND_USE_BOUNCE_BUFFER) 1728 use_bufpoi = !IS_ALIGNED((unsigned long)buf, 1729 chip->buf_align); 1730 else 1731 use_bufpoi = 0; 1732 1733 /* Is the current page in the buffer? */ 1734 if (realpage != chip->pagebuf || oob) { 1735 bufpoi = use_bufpoi ? chip->buffers->databuf : buf; 1736 1737 if (use_bufpoi && aligned) 1738 pr_debug("%s: using read bounce buffer for buf@%p\n", 1739 __func__, buf); 1740 1741 read_retry: 1742 if (nand_standard_page_accessors(&chip->ecc)) 1743 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 1744 1745 /* 1746 * Now read the page into the buffer. Absent an error, 1747 * the read methods return max bitflips per ecc step. 1748 */ 1749 if (unlikely(ops->mode == MTD_OPS_RAW)) 1750 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, 1751 oob_required, 1752 page); 1753 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && 1754 !oob) 1755 ret = chip->ecc.read_subpage(mtd, chip, 1756 col, bytes, bufpoi, 1757 page); 1758 else 1759 ret = chip->ecc.read_page(mtd, chip, bufpoi, 1760 oob_required, page); 1761 if (ret < 0) { 1762 if (use_bufpoi) 1763 /* Invalidate page cache */ 1764 chip->pagebuf = -1; 1765 break; 1766 } 1767 1768 max_bitflips = max_t(unsigned int, max_bitflips, ret); 1769 1770 /* Transfer not aligned data */ 1771 if (use_bufpoi) { 1772 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && 1773 !(mtd->ecc_stats.failed - ecc_failures) && 1774 (ops->mode != MTD_OPS_RAW)) { 1775 chip->pagebuf = realpage; 1776 chip->pagebuf_bitflips = ret; 1777 } else { 1778 /* Invalidate page cache */ 1779 chip->pagebuf = -1; 1780 } 1781 memcpy(buf, chip->buffers->databuf + col, bytes); 1782 } 1783 1784 if (unlikely(oob)) { 1785 int toread = min(oobreadlen, max_oobsize); 1786 1787 if (toread) { 1788 oob = nand_transfer_oob(chip, 1789 oob, ops, toread); 1790 oobreadlen -= toread; 1791 } 1792 } 1793 1794 if (chip->options & NAND_NEED_READRDY) { 1795 /* Apply delay or wait for ready/busy pin */ 1796 if (!chip->dev_ready) 1797 udelay(chip->chip_delay); 1798 else 1799 nand_wait_ready(mtd); 1800 } 1801 1802 if (mtd->ecc_stats.failed - ecc_failures) { 1803 if (retry_mode + 1 < chip->read_retries) { 1804 retry_mode++; 1805 ret = nand_setup_read_retry(mtd, 1806 retry_mode); 1807 if (ret < 0) 1808 break; 1809 1810 /* Reset failures; retry */ 1811 mtd->ecc_stats.failed = ecc_failures; 1812 goto read_retry; 1813 } else { 1814 /* No more retry modes; real failure */ 1815 ecc_fail = true; 1816 } 1817 } 1818 1819 buf += bytes; 1820 } else { 1821 memcpy(buf, chip->buffers->databuf + col, bytes); 1822 buf += bytes; 1823 max_bitflips = max_t(unsigned int, max_bitflips, 1824 chip->pagebuf_bitflips); 1825 } 1826 1827 readlen -= bytes; 1828 1829 /* Reset to retry mode 0 */ 1830 if (retry_mode) { 1831 ret = nand_setup_read_retry(mtd, 0); 1832 if (ret < 0) 1833 break; 1834 retry_mode = 0; 1835 } 1836 1837 if (!readlen) 1838 break; 1839 1840 /* For subsequent reads align to page boundary */ 1841 col = 0; 1842 /* Increment page address */ 1843 realpage++; 1844 1845 page = realpage & chip->pagemask; 1846 /* Check, if we cross a chip boundary */ 1847 if (!page) { 1848 chipnr++; 1849 chip->select_chip(mtd, -1); 1850 chip->select_chip(mtd, chipnr); 1851 } 1852 } 1853 chip->select_chip(mtd, -1); 1854 1855 ops->retlen = ops->len - (size_t) readlen; 1856 if (oob) 1857 ops->oobretlen = ops->ooblen - oobreadlen; 1858 1859 if (ret < 0) 1860 return ret; 1861 1862 if (ecc_fail) 1863 return -EBADMSG; 1864 1865 return max_bitflips; 1866 } 1867 1868 /** 1869 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function 1870 * @mtd: mtd info structure 1871 * @chip: nand chip info structure 1872 * @page: page number to read 1873 */ nand_read_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)1874 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1875 int page) 1876 { 1877 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 1878 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1879 return 0; 1880 } 1881 1882 /** 1883 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC 1884 * with syndromes 1885 * @mtd: mtd info structure 1886 * @chip: nand chip info structure 1887 * @page: page number to read 1888 */ nand_read_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)1889 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1890 int page) 1891 { 1892 int length = mtd->oobsize; 1893 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1894 int eccsize = chip->ecc.size; 1895 uint8_t *bufpoi = chip->oob_poi; 1896 int i, toread, sndrnd = 0, pos; 1897 1898 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); 1899 for (i = 0; i < chip->ecc.steps; i++) { 1900 if (sndrnd) { 1901 pos = eccsize + i * (eccsize + chunk); 1902 if (mtd->writesize > 512) 1903 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); 1904 else 1905 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); 1906 } else 1907 sndrnd = 1; 1908 toread = min_t(int, length, chunk); 1909 chip->read_buf(mtd, bufpoi, toread); 1910 bufpoi += toread; 1911 length -= toread; 1912 } 1913 if (length > 0) 1914 chip->read_buf(mtd, bufpoi, length); 1915 1916 return 0; 1917 } 1918 1919 /** 1920 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function 1921 * @mtd: mtd info structure 1922 * @chip: nand chip info structure 1923 * @page: page number to write 1924 */ nand_write_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)1925 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1926 int page) 1927 { 1928 int status = 0; 1929 const uint8_t *buf = chip->oob_poi; 1930 int length = mtd->oobsize; 1931 1932 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 1933 chip->write_buf(mtd, buf, length); 1934 /* Send command to program the OOB data */ 1935 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1936 1937 status = chip->waitfunc(mtd, chip); 1938 1939 return status & NAND_STATUS_FAIL ? -EIO : 0; 1940 } 1941 1942 /** 1943 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC 1944 * with syndrome - only for large page flash 1945 * @mtd: mtd info structure 1946 * @chip: nand chip info structure 1947 * @page: page number to write 1948 */ nand_write_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)1949 static int nand_write_oob_syndrome(struct mtd_info *mtd, 1950 struct nand_chip *chip, int page) 1951 { 1952 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1953 int eccsize = chip->ecc.size, length = mtd->oobsize; 1954 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; 1955 const uint8_t *bufpoi = chip->oob_poi; 1956 1957 /* 1958 * data-ecc-data-ecc ... ecc-oob 1959 * or 1960 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 1961 */ 1962 if (!chip->ecc.prepad && !chip->ecc.postpad) { 1963 pos = steps * (eccsize + chunk); 1964 steps = 0; 1965 } else 1966 pos = eccsize; 1967 1968 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); 1969 for (i = 0; i < steps; i++) { 1970 if (sndcmd) { 1971 if (mtd->writesize <= 512) { 1972 uint32_t fill = 0xFFFFFFFF; 1973 1974 len = eccsize; 1975 while (len > 0) { 1976 int num = min_t(int, len, 4); 1977 chip->write_buf(mtd, (uint8_t *)&fill, 1978 num); 1979 len -= num; 1980 } 1981 } else { 1982 pos = eccsize + i * (eccsize + chunk); 1983 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); 1984 } 1985 } else 1986 sndcmd = 1; 1987 len = min_t(int, length, chunk); 1988 chip->write_buf(mtd, bufpoi, len); 1989 bufpoi += len; 1990 length -= len; 1991 } 1992 if (length > 0) 1993 chip->write_buf(mtd, bufpoi, length); 1994 1995 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1996 status = chip->waitfunc(mtd, chip); 1997 1998 return status & NAND_STATUS_FAIL ? -EIO : 0; 1999 } 2000 2001 /** 2002 * nand_do_read_oob - [INTERN] NAND read out-of-band 2003 * @mtd: MTD device structure 2004 * @from: offset to read from 2005 * @ops: oob operations description structure 2006 * 2007 * NAND read out-of-band data from the spare area. 2008 */ nand_do_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2009 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, 2010 struct mtd_oob_ops *ops) 2011 { 2012 int page, realpage, chipnr; 2013 struct nand_chip *chip = mtd_to_nand(mtd); 2014 struct mtd_ecc_stats stats; 2015 int readlen = ops->ooblen; 2016 int len; 2017 uint8_t *buf = ops->oobbuf; 2018 int ret = 0; 2019 2020 pr_debug("%s: from = 0x%08Lx, len = %i\n", 2021 __func__, (unsigned long long)from, readlen); 2022 2023 stats = mtd->ecc_stats; 2024 2025 len = mtd_oobavail(mtd, ops); 2026 2027 if (unlikely(ops->ooboffs >= len)) { 2028 pr_debug("%s: attempt to start read outside oob\n", 2029 __func__); 2030 return -EINVAL; 2031 } 2032 2033 /* Do not allow reads past end of device */ 2034 if (unlikely(from >= mtd->size || 2035 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - 2036 (from >> chip->page_shift)) * len)) { 2037 pr_debug("%s: attempt to read beyond end of device\n", 2038 __func__); 2039 return -EINVAL; 2040 } 2041 2042 chipnr = (int)(from >> chip->chip_shift); 2043 chip->select_chip(mtd, chipnr); 2044 2045 /* Shift to get page */ 2046 realpage = (int)(from >> chip->page_shift); 2047 page = realpage & chip->pagemask; 2048 2049 while (1) { 2050 WATCHDOG_RESET(); 2051 2052 if (ops->mode == MTD_OPS_RAW) 2053 ret = chip->ecc.read_oob_raw(mtd, chip, page); 2054 else 2055 ret = chip->ecc.read_oob(mtd, chip, page); 2056 2057 if (ret < 0) 2058 break; 2059 2060 len = min(len, readlen); 2061 buf = nand_transfer_oob(chip, buf, ops, len); 2062 2063 if (chip->options & NAND_NEED_READRDY) { 2064 /* Apply delay or wait for ready/busy pin */ 2065 if (!chip->dev_ready) 2066 udelay(chip->chip_delay); 2067 else 2068 nand_wait_ready(mtd); 2069 } 2070 2071 readlen -= len; 2072 if (!readlen) 2073 break; 2074 2075 /* Increment page address */ 2076 realpage++; 2077 2078 page = realpage & chip->pagemask; 2079 /* Check, if we cross a chip boundary */ 2080 if (!page) { 2081 chipnr++; 2082 chip->select_chip(mtd, -1); 2083 chip->select_chip(mtd, chipnr); 2084 } 2085 } 2086 chip->select_chip(mtd, -1); 2087 2088 ops->oobretlen = ops->ooblen - readlen; 2089 2090 if (ret < 0) 2091 return ret; 2092 2093 if (mtd->ecc_stats.failed - stats.failed) 2094 return -EBADMSG; 2095 2096 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; 2097 } 2098 2099 /** 2100 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 2101 * @mtd: MTD device structure 2102 * @from: offset to read from 2103 * @ops: oob operation description structure 2104 * 2105 * NAND read data and/or out-of-band data. 2106 */ nand_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2107 static int nand_read_oob(struct mtd_info *mtd, loff_t from, 2108 struct mtd_oob_ops *ops) 2109 { 2110 int ret = -ENOTSUPP; 2111 2112 ops->retlen = 0; 2113 2114 /* Do not allow reads past end of device */ 2115 if (ops->datbuf && (from + ops->len) > mtd->size) { 2116 pr_debug("%s: attempt to read beyond end of device\n", 2117 __func__); 2118 return -EINVAL; 2119 } 2120 2121 nand_get_device(mtd, FL_READING); 2122 2123 switch (ops->mode) { 2124 case MTD_OPS_PLACE_OOB: 2125 case MTD_OPS_AUTO_OOB: 2126 case MTD_OPS_RAW: 2127 break; 2128 2129 default: 2130 goto out; 2131 } 2132 2133 if (!ops->datbuf) 2134 ret = nand_do_read_oob(mtd, from, ops); 2135 else 2136 ret = nand_do_read_ops(mtd, from, ops); 2137 2138 out: 2139 nand_release_device(mtd); 2140 return ret; 2141 } 2142 2143 2144 /** 2145 * nand_write_page_raw - [INTERN] raw page write function 2146 * @mtd: mtd info structure 2147 * @chip: nand chip info structure 2148 * @buf: data buffer 2149 * @oob_required: must write chip->oob_poi to OOB 2150 * @page: page number to write 2151 * 2152 * Not for syndrome calculating ECC controllers, which use a special oob layout. 2153 */ nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2154 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 2155 const uint8_t *buf, int oob_required, int page) 2156 { 2157 chip->write_buf(mtd, buf, mtd->writesize); 2158 if (oob_required) 2159 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 2160 2161 return 0; 2162 } 2163 2164 /** 2165 * nand_write_page_raw_syndrome - [INTERN] raw page write function 2166 * @mtd: mtd info structure 2167 * @chip: nand chip info structure 2168 * @buf: data buffer 2169 * @oob_required: must write chip->oob_poi to OOB 2170 * @page: page number to write 2171 * 2172 * We need a special oob layout and handling even when ECC isn't checked. 2173 */ nand_write_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2174 static int nand_write_page_raw_syndrome(struct mtd_info *mtd, 2175 struct nand_chip *chip, 2176 const uint8_t *buf, int oob_required, 2177 int page) 2178 { 2179 int eccsize = chip->ecc.size; 2180 int eccbytes = chip->ecc.bytes; 2181 uint8_t *oob = chip->oob_poi; 2182 int steps, size; 2183 2184 for (steps = chip->ecc.steps; steps > 0; steps--) { 2185 chip->write_buf(mtd, buf, eccsize); 2186 buf += eccsize; 2187 2188 if (chip->ecc.prepad) { 2189 chip->write_buf(mtd, oob, chip->ecc.prepad); 2190 oob += chip->ecc.prepad; 2191 } 2192 2193 chip->write_buf(mtd, oob, eccbytes); 2194 oob += eccbytes; 2195 2196 if (chip->ecc.postpad) { 2197 chip->write_buf(mtd, oob, chip->ecc.postpad); 2198 oob += chip->ecc.postpad; 2199 } 2200 } 2201 2202 size = mtd->oobsize - (oob - chip->oob_poi); 2203 if (size) 2204 chip->write_buf(mtd, oob, size); 2205 2206 return 0; 2207 } 2208 /** 2209 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function 2210 * @mtd: mtd info structure 2211 * @chip: nand chip info structure 2212 * @buf: data buffer 2213 * @oob_required: must write chip->oob_poi to OOB 2214 * @page: page number to write 2215 */ nand_write_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2216 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 2217 const uint8_t *buf, int oob_required, 2218 int page) 2219 { 2220 int i, eccsize = chip->ecc.size; 2221 int eccbytes = chip->ecc.bytes; 2222 int eccsteps = chip->ecc.steps; 2223 uint8_t *ecc_calc = chip->buffers->ecccalc; 2224 const uint8_t *p = buf; 2225 uint32_t *eccpos = chip->ecc.layout->eccpos; 2226 2227 /* Software ECC calculation */ 2228 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 2229 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2230 2231 for (i = 0; i < chip->ecc.total; i++) 2232 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2233 2234 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); 2235 } 2236 2237 /** 2238 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function 2239 * @mtd: mtd info structure 2240 * @chip: nand chip info structure 2241 * @buf: data buffer 2242 * @oob_required: must write chip->oob_poi to OOB 2243 * @page: page number to write 2244 */ nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2245 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 2246 const uint8_t *buf, int oob_required, 2247 int page) 2248 { 2249 int i, eccsize = chip->ecc.size; 2250 int eccbytes = chip->ecc.bytes; 2251 int eccsteps = chip->ecc.steps; 2252 uint8_t *ecc_calc = chip->buffers->ecccalc; 2253 const uint8_t *p = buf; 2254 uint32_t *eccpos = chip->ecc.layout->eccpos; 2255 2256 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2257 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2258 chip->write_buf(mtd, p, eccsize); 2259 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2260 } 2261 2262 for (i = 0; i < chip->ecc.total; i++) 2263 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2264 2265 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 2266 2267 return 0; 2268 } 2269 2270 2271 /** 2272 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write 2273 * @mtd: mtd info structure 2274 * @chip: nand chip info structure 2275 * @offset: column address of subpage within the page 2276 * @data_len: data length 2277 * @buf: data buffer 2278 * @oob_required: must write chip->oob_poi to OOB 2279 * @page: page number to write 2280 */ nand_write_subpage_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,uint32_t data_len,const uint8_t * buf,int oob_required,int page)2281 static int nand_write_subpage_hwecc(struct mtd_info *mtd, 2282 struct nand_chip *chip, uint32_t offset, 2283 uint32_t data_len, const uint8_t *buf, 2284 int oob_required, int page) 2285 { 2286 uint8_t *oob_buf = chip->oob_poi; 2287 uint8_t *ecc_calc = chip->buffers->ecccalc; 2288 int ecc_size = chip->ecc.size; 2289 int ecc_bytes = chip->ecc.bytes; 2290 int ecc_steps = chip->ecc.steps; 2291 uint32_t *eccpos = chip->ecc.layout->eccpos; 2292 uint32_t start_step = offset / ecc_size; 2293 uint32_t end_step = (offset + data_len - 1) / ecc_size; 2294 int oob_bytes = mtd->oobsize / ecc_steps; 2295 int step, i; 2296 2297 for (step = 0; step < ecc_steps; step++) { 2298 /* configure controller for WRITE access */ 2299 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2300 2301 /* write data (untouched subpages already masked by 0xFF) */ 2302 chip->write_buf(mtd, buf, ecc_size); 2303 2304 /* mask ECC of un-touched subpages by padding 0xFF */ 2305 if ((step < start_step) || (step > end_step)) 2306 memset(ecc_calc, 0xff, ecc_bytes); 2307 else 2308 chip->ecc.calculate(mtd, buf, ecc_calc); 2309 2310 /* mask OOB of un-touched subpages by padding 0xFF */ 2311 /* if oob_required, preserve OOB metadata of written subpage */ 2312 if (!oob_required || (step < start_step) || (step > end_step)) 2313 memset(oob_buf, 0xff, oob_bytes); 2314 2315 buf += ecc_size; 2316 ecc_calc += ecc_bytes; 2317 oob_buf += oob_bytes; 2318 } 2319 2320 /* copy calculated ECC for whole page to chip->buffer->oob */ 2321 /* this include masked-value(0xFF) for unwritten subpages */ 2322 ecc_calc = chip->buffers->ecccalc; 2323 for (i = 0; i < chip->ecc.total; i++) 2324 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2325 2326 /* write OOB buffer to NAND device */ 2327 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 2328 2329 return 0; 2330 } 2331 2332 2333 /** 2334 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write 2335 * @mtd: mtd info structure 2336 * @chip: nand chip info structure 2337 * @buf: data buffer 2338 * @oob_required: must write chip->oob_poi to OOB 2339 * @page: page number to write 2340 * 2341 * The hw generator calculates the error syndrome automatically. Therefore we 2342 * need a special oob layout and handling. 2343 */ nand_write_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2344 static int nand_write_page_syndrome(struct mtd_info *mtd, 2345 struct nand_chip *chip, 2346 const uint8_t *buf, int oob_required, 2347 int page) 2348 { 2349 int i, eccsize = chip->ecc.size; 2350 int eccbytes = chip->ecc.bytes; 2351 int eccsteps = chip->ecc.steps; 2352 const uint8_t *p = buf; 2353 uint8_t *oob = chip->oob_poi; 2354 2355 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2356 2357 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2358 chip->write_buf(mtd, p, eccsize); 2359 2360 if (chip->ecc.prepad) { 2361 chip->write_buf(mtd, oob, chip->ecc.prepad); 2362 oob += chip->ecc.prepad; 2363 } 2364 2365 chip->ecc.calculate(mtd, p, oob); 2366 chip->write_buf(mtd, oob, eccbytes); 2367 oob += eccbytes; 2368 2369 if (chip->ecc.postpad) { 2370 chip->write_buf(mtd, oob, chip->ecc.postpad); 2371 oob += chip->ecc.postpad; 2372 } 2373 } 2374 2375 /* Calculate remaining oob bytes */ 2376 i = mtd->oobsize - (oob - chip->oob_poi); 2377 if (i) 2378 chip->write_buf(mtd, oob, i); 2379 2380 return 0; 2381 } 2382 2383 /** 2384 * nand_write_page - [REPLACEABLE] write one page 2385 * @mtd: MTD device structure 2386 * @chip: NAND chip descriptor 2387 * @offset: address offset within the page 2388 * @data_len: length of actual data to be written 2389 * @buf: the data to write 2390 * @oob_required: must write chip->oob_poi to OOB 2391 * @page: page number to write 2392 * @raw: use _raw version of write_page 2393 */ nand_write_page(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int raw)2394 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, 2395 uint32_t offset, int data_len, const uint8_t *buf, 2396 int oob_required, int page, int raw) 2397 { 2398 int status, subpage; 2399 2400 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 2401 chip->ecc.write_subpage) 2402 subpage = offset || (data_len < mtd->writesize); 2403 else 2404 subpage = 0; 2405 2406 if (nand_standard_page_accessors(&chip->ecc)) 2407 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); 2408 2409 if (unlikely(raw)) 2410 status = chip->ecc.write_page_raw(mtd, chip, buf, 2411 oob_required, page); 2412 else if (subpage) 2413 status = chip->ecc.write_subpage(mtd, chip, offset, data_len, 2414 buf, oob_required, page); 2415 else 2416 status = chip->ecc.write_page(mtd, chip, buf, oob_required, 2417 page); 2418 2419 if (status < 0) 2420 return status; 2421 2422 if (nand_standard_page_accessors(&chip->ecc)) { 2423 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 2424 2425 status = chip->waitfunc(mtd, chip); 2426 if (status & NAND_STATUS_FAIL) 2427 return -EIO; 2428 } 2429 2430 return 0; 2431 } 2432 2433 /** 2434 * nand_fill_oob - [INTERN] Transfer client buffer to oob 2435 * @mtd: MTD device structure 2436 * @oob: oob data buffer 2437 * @len: oob data write length 2438 * @ops: oob ops structure 2439 */ nand_fill_oob(struct mtd_info * mtd,uint8_t * oob,size_t len,struct mtd_oob_ops * ops)2440 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, 2441 struct mtd_oob_ops *ops) 2442 { 2443 struct nand_chip *chip = mtd_to_nand(mtd); 2444 2445 /* 2446 * Initialise to all 0xFF, to avoid the possibility of left over OOB 2447 * data from a previous OOB read. 2448 */ 2449 memset(chip->oob_poi, 0xff, mtd->oobsize); 2450 2451 switch (ops->mode) { 2452 2453 case MTD_OPS_PLACE_OOB: 2454 case MTD_OPS_RAW: 2455 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 2456 return oob + len; 2457 2458 case MTD_OPS_AUTO_OOB: { 2459 struct nand_oobfree *free = chip->ecc.layout->oobfree; 2460 uint32_t boffs = 0, woffs = ops->ooboffs; 2461 size_t bytes = 0; 2462 2463 for (; free->length && len; free++, len -= bytes) { 2464 /* Write request not from offset 0? */ 2465 if (unlikely(woffs)) { 2466 if (woffs >= free->length) { 2467 woffs -= free->length; 2468 continue; 2469 } 2470 boffs = free->offset + woffs; 2471 bytes = min_t(size_t, len, 2472 (free->length - woffs)); 2473 woffs = 0; 2474 } else { 2475 bytes = min_t(size_t, len, free->length); 2476 boffs = free->offset; 2477 } 2478 memcpy(chip->oob_poi + boffs, oob, bytes); 2479 oob += bytes; 2480 } 2481 return oob; 2482 } 2483 default: 2484 BUG(); 2485 } 2486 return NULL; 2487 } 2488 2489 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) 2490 2491 /** 2492 * nand_do_write_ops - [INTERN] NAND write with ECC 2493 * @mtd: MTD device structure 2494 * @to: offset to write to 2495 * @ops: oob operations description structure 2496 * 2497 * NAND write with ECC. 2498 */ nand_do_write_ops(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2499 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, 2500 struct mtd_oob_ops *ops) 2501 { 2502 int chipnr, realpage, page, column; 2503 struct nand_chip *chip = mtd_to_nand(mtd); 2504 uint32_t writelen = ops->len; 2505 2506 uint32_t oobwritelen = ops->ooblen; 2507 uint32_t oobmaxlen = mtd_oobavail(mtd, ops); 2508 2509 uint8_t *oob = ops->oobbuf; 2510 uint8_t *buf = ops->datbuf; 2511 int ret; 2512 int oob_required = oob ? 1 : 0; 2513 2514 ops->retlen = 0; 2515 if (!writelen) 2516 return 0; 2517 2518 /* Reject writes, which are not page aligned */ 2519 if (NOTALIGNED(to)) { 2520 pr_notice("%s: attempt to write non page aligned data\n", 2521 __func__); 2522 return -EINVAL; 2523 } 2524 2525 column = to & (mtd->writesize - 1); 2526 2527 chipnr = (int)(to >> chip->chip_shift); 2528 chip->select_chip(mtd, chipnr); 2529 2530 /* Check, if it is write protected */ 2531 if (nand_check_wp(mtd)) { 2532 ret = -EIO; 2533 goto err_out; 2534 } 2535 2536 realpage = (int)(to >> chip->page_shift); 2537 page = realpage & chip->pagemask; 2538 2539 /* Invalidate the page cache, when we write to the cached page */ 2540 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && 2541 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) 2542 chip->pagebuf = -1; 2543 2544 /* Don't allow multipage oob writes with offset */ 2545 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { 2546 ret = -EINVAL; 2547 goto err_out; 2548 } 2549 2550 while (1) { 2551 int bytes = mtd->writesize; 2552 uint8_t *wbuf = buf; 2553 int use_bufpoi; 2554 int part_pagewr = (column || writelen < mtd->writesize); 2555 2556 if (part_pagewr) 2557 use_bufpoi = 1; 2558 else if (chip->options & NAND_USE_BOUNCE_BUFFER) 2559 use_bufpoi = !IS_ALIGNED((unsigned long)buf, 2560 chip->buf_align); 2561 else 2562 use_bufpoi = 0; 2563 2564 WATCHDOG_RESET(); 2565 /* Partial page write?, or need to use bounce buffer */ 2566 if (use_bufpoi) { 2567 pr_debug("%s: using write bounce buffer for buf@%p\n", 2568 __func__, buf); 2569 if (part_pagewr) 2570 bytes = min_t(int, bytes - column, writelen); 2571 chip->pagebuf = -1; 2572 memset(chip->buffers->databuf, 0xff, mtd->writesize); 2573 memcpy(&chip->buffers->databuf[column], buf, bytes); 2574 wbuf = chip->buffers->databuf; 2575 } 2576 2577 if (unlikely(oob)) { 2578 size_t len = min(oobwritelen, oobmaxlen); 2579 oob = nand_fill_oob(mtd, oob, len, ops); 2580 oobwritelen -= len; 2581 } else { 2582 /* We still need to erase leftover OOB data */ 2583 memset(chip->oob_poi, 0xff, mtd->oobsize); 2584 } 2585 ret = chip->write_page(mtd, chip, column, bytes, wbuf, 2586 oob_required, page, 2587 (ops->mode == MTD_OPS_RAW)); 2588 if (ret) 2589 break; 2590 2591 writelen -= bytes; 2592 if (!writelen) 2593 break; 2594 2595 column = 0; 2596 buf += bytes; 2597 realpage++; 2598 2599 page = realpage & chip->pagemask; 2600 /* Check, if we cross a chip boundary */ 2601 if (!page) { 2602 chipnr++; 2603 chip->select_chip(mtd, -1); 2604 chip->select_chip(mtd, chipnr); 2605 } 2606 } 2607 2608 ops->retlen = ops->len - writelen; 2609 if (unlikely(oob)) 2610 ops->oobretlen = ops->ooblen; 2611 2612 err_out: 2613 chip->select_chip(mtd, -1); 2614 return ret; 2615 } 2616 2617 /** 2618 * panic_nand_write - [MTD Interface] NAND write with ECC 2619 * @mtd: MTD device structure 2620 * @to: offset to write to 2621 * @len: number of bytes to write 2622 * @retlen: pointer to variable to store the number of written bytes 2623 * @buf: the data to write 2624 * 2625 * NAND write with ECC. Used when performing writes in interrupt context, this 2626 * may for example be called by mtdoops when writing an oops while in panic. 2627 */ panic_nand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const uint8_t * buf)2628 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, 2629 size_t *retlen, const uint8_t *buf) 2630 { 2631 struct nand_chip *chip = mtd_to_nand(mtd); 2632 struct mtd_oob_ops ops; 2633 int ret; 2634 2635 /* Wait for the device to get ready */ 2636 panic_nand_wait(mtd, chip, 400); 2637 2638 /* Grab the device */ 2639 panic_nand_get_device(chip, mtd, FL_WRITING); 2640 2641 memset(&ops, 0, sizeof(ops)); 2642 ops.len = len; 2643 ops.datbuf = (uint8_t *)buf; 2644 ops.mode = MTD_OPS_PLACE_OOB; 2645 2646 ret = nand_do_write_ops(mtd, to, &ops); 2647 2648 *retlen = ops.retlen; 2649 return ret; 2650 } 2651 2652 /** 2653 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 2654 * @mtd: MTD device structure 2655 * @to: offset to write to 2656 * @ops: oob operation description structure 2657 * 2658 * NAND write out-of-band. 2659 */ nand_do_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2660 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 2661 struct mtd_oob_ops *ops) 2662 { 2663 int chipnr, page, status, len; 2664 struct nand_chip *chip = mtd_to_nand(mtd); 2665 2666 pr_debug("%s: to = 0x%08x, len = %i\n", 2667 __func__, (unsigned int)to, (int)ops->ooblen); 2668 2669 len = mtd_oobavail(mtd, ops); 2670 2671 /* Do not allow write past end of page */ 2672 if ((ops->ooboffs + ops->ooblen) > len) { 2673 pr_debug("%s: attempt to write past end of page\n", 2674 __func__); 2675 return -EINVAL; 2676 } 2677 2678 if (unlikely(ops->ooboffs >= len)) { 2679 pr_debug("%s: attempt to start write outside oob\n", 2680 __func__); 2681 return -EINVAL; 2682 } 2683 2684 /* Do not allow write past end of device */ 2685 if (unlikely(to >= mtd->size || 2686 ops->ooboffs + ops->ooblen > 2687 ((mtd->size >> chip->page_shift) - 2688 (to >> chip->page_shift)) * len)) { 2689 pr_debug("%s: attempt to write beyond end of device\n", 2690 __func__); 2691 return -EINVAL; 2692 } 2693 2694 chipnr = (int)(to >> chip->chip_shift); 2695 2696 /* 2697 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 2698 * of my DiskOnChip 2000 test units) will clear the whole data page too 2699 * if we don't do this. I have no clue why, but I seem to have 'fixed' 2700 * it in the doc2000 driver in August 1999. dwmw2. 2701 */ 2702 nand_reset(chip, chipnr); 2703 2704 chip->select_chip(mtd, chipnr); 2705 2706 /* Shift to get page */ 2707 page = (int)(to >> chip->page_shift); 2708 2709 /* Check, if it is write protected */ 2710 if (nand_check_wp(mtd)) { 2711 chip->select_chip(mtd, -1); 2712 return -EROFS; 2713 } 2714 2715 /* Invalidate the page cache, if we write to the cached page */ 2716 if (page == chip->pagebuf) 2717 chip->pagebuf = -1; 2718 2719 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); 2720 2721 if (ops->mode == MTD_OPS_RAW) 2722 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); 2723 else 2724 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); 2725 2726 chip->select_chip(mtd, -1); 2727 2728 if (status) 2729 return status; 2730 2731 ops->oobretlen = ops->ooblen; 2732 2733 return 0; 2734 } 2735 2736 /** 2737 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 2738 * @mtd: MTD device structure 2739 * @to: offset to write to 2740 * @ops: oob operation description structure 2741 */ nand_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2742 static int nand_write_oob(struct mtd_info *mtd, loff_t to, 2743 struct mtd_oob_ops *ops) 2744 { 2745 int ret = -ENOTSUPP; 2746 2747 ops->retlen = 0; 2748 2749 /* Do not allow writes past end of device */ 2750 if (ops->datbuf && (to + ops->len) > mtd->size) { 2751 pr_debug("%s: attempt to write beyond end of device\n", 2752 __func__); 2753 return -EINVAL; 2754 } 2755 2756 nand_get_device(mtd, FL_WRITING); 2757 2758 switch (ops->mode) { 2759 case MTD_OPS_PLACE_OOB: 2760 case MTD_OPS_AUTO_OOB: 2761 case MTD_OPS_RAW: 2762 break; 2763 2764 default: 2765 goto out; 2766 } 2767 2768 if (!ops->datbuf) 2769 ret = nand_do_write_oob(mtd, to, ops); 2770 else 2771 ret = nand_do_write_ops(mtd, to, ops); 2772 2773 out: 2774 nand_release_device(mtd); 2775 return ret; 2776 } 2777 2778 /** 2779 * single_erase - [GENERIC] NAND standard block erase command function 2780 * @mtd: MTD device structure 2781 * @page: the page address of the block which will be erased 2782 * 2783 * Standard erase command for NAND chips. Returns NAND status. 2784 */ single_erase(struct mtd_info * mtd,int page)2785 static int single_erase(struct mtd_info *mtd, int page) 2786 { 2787 struct nand_chip *chip = mtd_to_nand(mtd); 2788 /* Send commands to erase a block */ 2789 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); 2790 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); 2791 2792 return chip->waitfunc(mtd, chip); 2793 } 2794 2795 /** 2796 * nand_erase - [MTD Interface] erase block(s) 2797 * @mtd: MTD device structure 2798 * @instr: erase instruction 2799 * 2800 * Erase one ore more blocks. 2801 */ nand_erase(struct mtd_info * mtd,struct erase_info * instr)2802 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 2803 { 2804 return nand_erase_nand(mtd, instr, 0); 2805 } 2806 2807 /** 2808 * nand_erase_nand - [INTERN] erase block(s) 2809 * @mtd: MTD device structure 2810 * @instr: erase instruction 2811 * @allowbbt: allow erasing the bbt area 2812 * 2813 * Erase one ore more blocks. 2814 */ nand_erase_nand(struct mtd_info * mtd,struct erase_info * instr,int allowbbt)2815 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 2816 int allowbbt) 2817 { 2818 int page, status, pages_per_block, ret, chipnr; 2819 struct nand_chip *chip = mtd_to_nand(mtd); 2820 loff_t len; 2821 2822 pr_debug("%s: start = 0x%012llx, len = %llu\n", 2823 __func__, (unsigned long long)instr->addr, 2824 (unsigned long long)instr->len); 2825 2826 if (check_offs_len(mtd, instr->addr, instr->len)) 2827 return -EINVAL; 2828 2829 /* Grab the lock and see if the device is available */ 2830 nand_get_device(mtd, FL_ERASING); 2831 2832 /* Shift to get first page */ 2833 page = (int)(instr->addr >> chip->page_shift); 2834 chipnr = (int)(instr->addr >> chip->chip_shift); 2835 2836 /* Calculate pages in each block */ 2837 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 2838 2839 /* Select the NAND device */ 2840 chip->select_chip(mtd, chipnr); 2841 2842 /* Check, if it is write protected */ 2843 if (nand_check_wp(mtd)) { 2844 pr_debug("%s: device is write protected!\n", 2845 __func__); 2846 instr->state = MTD_ERASE_FAILED; 2847 goto erase_exit; 2848 } 2849 2850 /* Loop through the pages */ 2851 len = instr->len; 2852 2853 instr->state = MTD_ERASING; 2854 2855 while (len) { 2856 WATCHDOG_RESET(); 2857 2858 /* Check if we have a bad block, we do not erase bad blocks! */ 2859 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) << 2860 chip->page_shift, allowbbt)) { 2861 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", 2862 __func__, page); 2863 instr->state = MTD_ERASE_FAILED; 2864 goto erase_exit; 2865 } 2866 2867 /* 2868 * Invalidate the page cache, if we erase the block which 2869 * contains the current cached page. 2870 */ 2871 if (page <= chip->pagebuf && chip->pagebuf < 2872 (page + pages_per_block)) 2873 chip->pagebuf = -1; 2874 2875 status = chip->erase(mtd, page & chip->pagemask); 2876 2877 /* See if block erase succeeded */ 2878 if (status & NAND_STATUS_FAIL) { 2879 pr_debug("%s: failed erase, page 0x%08x\n", 2880 __func__, page); 2881 instr->state = MTD_ERASE_FAILED; 2882 instr->fail_addr = 2883 ((loff_t)page << chip->page_shift); 2884 goto erase_exit; 2885 } 2886 2887 /* Increment page address and decrement length */ 2888 len -= (1ULL << chip->phys_erase_shift); 2889 page += pages_per_block; 2890 2891 /* Check, if we cross a chip boundary */ 2892 if (len && !(page & chip->pagemask)) { 2893 chipnr++; 2894 chip->select_chip(mtd, -1); 2895 chip->select_chip(mtd, chipnr); 2896 } 2897 } 2898 instr->state = MTD_ERASE_DONE; 2899 2900 erase_exit: 2901 2902 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; 2903 2904 /* Deselect and wake up anyone waiting on the device */ 2905 chip->select_chip(mtd, -1); 2906 nand_release_device(mtd); 2907 2908 /* Do call back function */ 2909 if (!ret) 2910 mtd_erase_callback(instr); 2911 2912 /* Return more or less happy */ 2913 return ret; 2914 } 2915 2916 /** 2917 * nand_sync - [MTD Interface] sync 2918 * @mtd: MTD device structure 2919 * 2920 * Sync is actually a wait for chip ready function. 2921 */ nand_sync(struct mtd_info * mtd)2922 static void nand_sync(struct mtd_info *mtd) 2923 { 2924 pr_debug("%s: called\n", __func__); 2925 2926 /* Grab the lock and see if the device is available */ 2927 nand_get_device(mtd, FL_SYNCING); 2928 /* Release it and go back */ 2929 nand_release_device(mtd); 2930 } 2931 2932 /** 2933 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 2934 * @mtd: MTD device structure 2935 * @offs: offset relative to mtd start 2936 */ nand_block_isbad(struct mtd_info * mtd,loff_t offs)2937 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 2938 { 2939 struct nand_chip *chip = mtd_to_nand(mtd); 2940 int chipnr = (int)(offs >> chip->chip_shift); 2941 int ret; 2942 2943 /* Select the NAND device */ 2944 nand_get_device(mtd, FL_READING); 2945 chip->select_chip(mtd, chipnr); 2946 2947 ret = nand_block_checkbad(mtd, offs, 0); 2948 2949 chip->select_chip(mtd, -1); 2950 nand_release_device(mtd); 2951 2952 return ret; 2953 } 2954 2955 /** 2956 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 2957 * @mtd: MTD device structure 2958 * @ofs: offset relative to mtd start 2959 */ nand_block_markbad(struct mtd_info * mtd,loff_t ofs)2960 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 2961 { 2962 int ret; 2963 2964 ret = nand_block_isbad(mtd, ofs); 2965 if (ret) { 2966 /* If it was bad already, return success and do nothing */ 2967 if (ret > 0) 2968 return 0; 2969 return ret; 2970 } 2971 2972 return nand_block_markbad_lowlevel(mtd, ofs); 2973 } 2974 2975 /** 2976 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand 2977 * @mtd: MTD device structure 2978 * @chip: nand chip info structure 2979 * @addr: feature address. 2980 * @subfeature_param: the subfeature parameters, a four bytes array. 2981 */ nand_onfi_set_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)2982 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, 2983 int addr, uint8_t *subfeature_param) 2984 { 2985 int status; 2986 int i; 2987 2988 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 2989 if (!chip->onfi_version || 2990 !(le16_to_cpu(chip->onfi_params.opt_cmd) 2991 & ONFI_OPT_CMD_SET_GET_FEATURES)) 2992 return -ENOTSUPP; 2993 #endif 2994 2995 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); 2996 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 2997 chip->write_byte(mtd, subfeature_param[i]); 2998 2999 status = chip->waitfunc(mtd, chip); 3000 if (status & NAND_STATUS_FAIL) 3001 return -EIO; 3002 return 0; 3003 } 3004 3005 /** 3006 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand 3007 * @mtd: MTD device structure 3008 * @chip: nand chip info structure 3009 * @addr: feature address. 3010 * @subfeature_param: the subfeature parameters, a four bytes array. 3011 */ nand_onfi_get_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)3012 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, 3013 int addr, uint8_t *subfeature_param) 3014 { 3015 int i; 3016 3017 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 3018 if (!chip->onfi_version || 3019 !(le16_to_cpu(chip->onfi_params.opt_cmd) 3020 & ONFI_OPT_CMD_SET_GET_FEATURES)) 3021 return -ENOTSUPP; 3022 #endif 3023 3024 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); 3025 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 3026 *subfeature_param++ = chip->read_byte(mtd); 3027 return 0; 3028 } 3029 3030 /* Set default functions */ nand_set_defaults(struct nand_chip * chip,int busw)3031 static void nand_set_defaults(struct nand_chip *chip, int busw) 3032 { 3033 /* check for proper chip_delay setup, set 20us if not */ 3034 if (!chip->chip_delay) 3035 chip->chip_delay = 20; 3036 3037 /* check, if a user supplied command function given */ 3038 if (chip->cmdfunc == NULL) 3039 chip->cmdfunc = nand_command; 3040 3041 /* check, if a user supplied wait function given */ 3042 if (chip->waitfunc == NULL) 3043 chip->waitfunc = nand_wait; 3044 3045 if (!chip->select_chip) 3046 chip->select_chip = nand_select_chip; 3047 3048 /* set for ONFI nand */ 3049 if (!chip->onfi_set_features) 3050 chip->onfi_set_features = nand_onfi_set_features; 3051 if (!chip->onfi_get_features) 3052 chip->onfi_get_features = nand_onfi_get_features; 3053 3054 /* If called twice, pointers that depend on busw may need to be reset */ 3055 if (!chip->read_byte || chip->read_byte == nand_read_byte) 3056 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; 3057 if (!chip->read_word) 3058 chip->read_word = nand_read_word; 3059 if (!chip->block_bad) 3060 chip->block_bad = nand_block_bad; 3061 if (!chip->block_markbad) 3062 chip->block_markbad = nand_default_block_markbad; 3063 if (!chip->write_buf || chip->write_buf == nand_write_buf) 3064 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; 3065 if (!chip->write_byte || chip->write_byte == nand_write_byte) 3066 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; 3067 if (!chip->read_buf || chip->read_buf == nand_read_buf) 3068 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; 3069 if (!chip->scan_bbt) 3070 chip->scan_bbt = nand_default_bbt; 3071 3072 if (!chip->controller) { 3073 chip->controller = &chip->hwcontrol; 3074 spin_lock_init(&chip->controller->lock); 3075 init_waitqueue_head(&chip->controller->wq); 3076 } 3077 3078 if (!chip->buf_align) 3079 chip->buf_align = 1; 3080 } 3081 3082 /* Sanitize ONFI strings so we can safely print them */ sanitize_string(char * s,size_t len)3083 static void sanitize_string(char *s, size_t len) 3084 { 3085 ssize_t i; 3086 3087 /* Null terminate */ 3088 s[len - 1] = 0; 3089 3090 /* Remove non printable chars */ 3091 for (i = 0; i < len - 1; i++) { 3092 if (s[i] < ' ' || s[i] > 127) 3093 s[i] = '?'; 3094 } 3095 3096 /* Remove trailing spaces */ 3097 strim(s); 3098 } 3099 onfi_crc16(u16 crc,u8 const * p,size_t len)3100 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) 3101 { 3102 int i; 3103 while (len--) { 3104 crc ^= *p++ << 8; 3105 for (i = 0; i < 8; i++) 3106 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); 3107 } 3108 3109 return crc; 3110 } 3111 3112 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 3113 /* Parse the Extended Parameter Page. */ nand_flash_detect_ext_param_page(struct mtd_info * mtd,struct nand_chip * chip,struct nand_onfi_params * p)3114 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, 3115 struct nand_chip *chip, struct nand_onfi_params *p) 3116 { 3117 struct onfi_ext_param_page *ep; 3118 struct onfi_ext_section *s; 3119 struct onfi_ext_ecc_info *ecc; 3120 uint8_t *cursor; 3121 int ret = -EINVAL; 3122 int len; 3123 int i; 3124 3125 len = le16_to_cpu(p->ext_param_page_length) * 16; 3126 ep = kmalloc(len, GFP_KERNEL); 3127 if (!ep) 3128 return -ENOMEM; 3129 3130 /* Send our own NAND_CMD_PARAM. */ 3131 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); 3132 3133 /* Use the Change Read Column command to skip the ONFI param pages. */ 3134 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 3135 sizeof(*p) * p->num_of_param_pages , -1); 3136 3137 /* Read out the Extended Parameter Page. */ 3138 chip->read_buf(mtd, (uint8_t *)ep, len); 3139 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) 3140 != le16_to_cpu(ep->crc))) { 3141 pr_debug("fail in the CRC.\n"); 3142 goto ext_out; 3143 } 3144 3145 /* 3146 * Check the signature. 3147 * Do not strictly follow the ONFI spec, maybe changed in future. 3148 */ 3149 if (strncmp((char *)ep->sig, "EPPS", 4)) { 3150 pr_debug("The signature is invalid.\n"); 3151 goto ext_out; 3152 } 3153 3154 /* find the ECC section. */ 3155 cursor = (uint8_t *)(ep + 1); 3156 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { 3157 s = ep->sections + i; 3158 if (s->type == ONFI_SECTION_TYPE_2) 3159 break; 3160 cursor += s->length * 16; 3161 } 3162 if (i == ONFI_EXT_SECTION_MAX) { 3163 pr_debug("We can not find the ECC section.\n"); 3164 goto ext_out; 3165 } 3166 3167 /* get the info we want. */ 3168 ecc = (struct onfi_ext_ecc_info *)cursor; 3169 3170 if (!ecc->codeword_size) { 3171 pr_debug("Invalid codeword size\n"); 3172 goto ext_out; 3173 } 3174 3175 chip->ecc_strength_ds = ecc->ecc_bits; 3176 chip->ecc_step_ds = 1 << ecc->codeword_size; 3177 ret = 0; 3178 3179 ext_out: 3180 kfree(ep); 3181 return ret; 3182 } 3183 nand_setup_read_retry_micron(struct mtd_info * mtd,int retry_mode)3184 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) 3185 { 3186 struct nand_chip *chip = mtd_to_nand(mtd); 3187 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; 3188 3189 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, 3190 feature); 3191 } 3192 3193 /* 3194 * Configure chip properties from Micron vendor-specific ONFI table 3195 */ nand_onfi_detect_micron(struct nand_chip * chip,struct nand_onfi_params * p)3196 static void nand_onfi_detect_micron(struct nand_chip *chip, 3197 struct nand_onfi_params *p) 3198 { 3199 struct nand_onfi_vendor_micron *micron = (void *)p->vendor; 3200 3201 if (le16_to_cpu(p->vendor_revision) < 1) 3202 return; 3203 3204 chip->read_retries = micron->read_retry_options; 3205 chip->setup_read_retry = nand_setup_read_retry_micron; 3206 } 3207 3208 /* 3209 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. 3210 */ nand_flash_detect_onfi(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3211 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, 3212 int *busw) 3213 { 3214 struct nand_onfi_params *p = &chip->onfi_params; 3215 int i, j; 3216 int val; 3217 3218 /* Try ONFI for unknown chip or LP */ 3219 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); 3220 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || 3221 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') 3222 return 0; 3223 3224 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); 3225 for (i = 0; i < 3; i++) { 3226 for (j = 0; j < sizeof(*p); j++) 3227 ((uint8_t *)p)[j] = chip->read_byte(mtd); 3228 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == 3229 le16_to_cpu(p->crc)) { 3230 break; 3231 } 3232 } 3233 3234 if (i == 3) { 3235 pr_err("Could not find valid ONFI parameter page; aborting\n"); 3236 return 0; 3237 } 3238 3239 /* Check version */ 3240 val = le16_to_cpu(p->revision); 3241 if (val & (1 << 5)) 3242 chip->onfi_version = 23; 3243 else if (val & (1 << 4)) 3244 chip->onfi_version = 22; 3245 else if (val & (1 << 3)) 3246 chip->onfi_version = 21; 3247 else if (val & (1 << 2)) 3248 chip->onfi_version = 20; 3249 else if (val & (1 << 1)) 3250 chip->onfi_version = 10; 3251 3252 if (!chip->onfi_version) { 3253 pr_info("unsupported ONFI version: %d\n", val); 3254 return 0; 3255 } 3256 3257 sanitize_string(p->manufacturer, sizeof(p->manufacturer)); 3258 sanitize_string(p->model, sizeof(p->model)); 3259 if (!mtd->name) 3260 mtd->name = p->model; 3261 3262 mtd->writesize = le32_to_cpu(p->byte_per_page); 3263 3264 /* 3265 * pages_per_block and blocks_per_lun may not be a power-of-2 size 3266 * (don't ask me who thought of this...). MTD assumes that these 3267 * dimensions will be power-of-2, so just truncate the remaining area. 3268 */ 3269 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); 3270 mtd->erasesize *= mtd->writesize; 3271 3272 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); 3273 3274 /* See erasesize comment */ 3275 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); 3276 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; 3277 chip->bits_per_cell = p->bits_per_cell; 3278 3279 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) 3280 *busw = NAND_BUSWIDTH_16; 3281 else 3282 *busw = 0; 3283 3284 if (p->ecc_bits != 0xff) { 3285 chip->ecc_strength_ds = p->ecc_bits; 3286 chip->ecc_step_ds = 512; 3287 } else if (chip->onfi_version >= 21 && 3288 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { 3289 3290 /* 3291 * The nand_flash_detect_ext_param_page() uses the 3292 * Change Read Column command which maybe not supported 3293 * by the chip->cmdfunc. So try to update the chip->cmdfunc 3294 * now. We do not replace user supplied command function. 3295 */ 3296 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 3297 chip->cmdfunc = nand_command_lp; 3298 3299 /* The Extended Parameter Page is supported since ONFI 2.1. */ 3300 if (nand_flash_detect_ext_param_page(mtd, chip, p)) 3301 pr_warn("Failed to detect ONFI extended param page\n"); 3302 } else { 3303 pr_warn("Could not retrieve ONFI ECC requirements\n"); 3304 } 3305 3306 if (p->jedec_id == NAND_MFR_MICRON) 3307 nand_onfi_detect_micron(chip, p); 3308 3309 return 1; 3310 } 3311 #else nand_flash_detect_onfi(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3312 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, 3313 int *busw) 3314 { 3315 return 0; 3316 } 3317 #endif 3318 3319 /* 3320 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. 3321 */ nand_flash_detect_jedec(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3322 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, 3323 int *busw) 3324 { 3325 struct nand_jedec_params *p = &chip->jedec_params; 3326 struct jedec_ecc_info *ecc; 3327 int val; 3328 int i, j; 3329 3330 /* Try JEDEC for unknown chip or LP */ 3331 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); 3332 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || 3333 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || 3334 chip->read_byte(mtd) != 'C') 3335 return 0; 3336 3337 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); 3338 for (i = 0; i < 3; i++) { 3339 for (j = 0; j < sizeof(*p); j++) 3340 ((uint8_t *)p)[j] = chip->read_byte(mtd); 3341 3342 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == 3343 le16_to_cpu(p->crc)) 3344 break; 3345 } 3346 3347 if (i == 3) { 3348 pr_err("Could not find valid JEDEC parameter page; aborting\n"); 3349 return 0; 3350 } 3351 3352 /* Check version */ 3353 val = le16_to_cpu(p->revision); 3354 if (val & (1 << 2)) 3355 chip->jedec_version = 10; 3356 else if (val & (1 << 1)) 3357 chip->jedec_version = 1; /* vendor specific version */ 3358 3359 if (!chip->jedec_version) { 3360 pr_info("unsupported JEDEC version: %d\n", val); 3361 return 0; 3362 } 3363 3364 sanitize_string(p->manufacturer, sizeof(p->manufacturer)); 3365 sanitize_string(p->model, sizeof(p->model)); 3366 if (!mtd->name) 3367 mtd->name = p->model; 3368 3369 mtd->writesize = le32_to_cpu(p->byte_per_page); 3370 3371 /* Please reference to the comment for nand_flash_detect_onfi. */ 3372 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); 3373 mtd->erasesize *= mtd->writesize; 3374 3375 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); 3376 3377 /* Please reference to the comment for nand_flash_detect_onfi. */ 3378 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); 3379 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; 3380 chip->bits_per_cell = p->bits_per_cell; 3381 3382 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) 3383 *busw = NAND_BUSWIDTH_16; 3384 else 3385 *busw = 0; 3386 3387 /* ECC info */ 3388 ecc = &p->ecc_info[0]; 3389 3390 if (ecc->codeword_size >= 9) { 3391 chip->ecc_strength_ds = ecc->ecc_bits; 3392 chip->ecc_step_ds = 1 << ecc->codeword_size; 3393 } else { 3394 pr_warn("Invalid codeword size\n"); 3395 } 3396 3397 return 1; 3398 } 3399 3400 /* 3401 * nand_id_has_period - Check if an ID string has a given wraparound period 3402 * @id_data: the ID string 3403 * @arrlen: the length of the @id_data array 3404 * @period: the period of repitition 3405 * 3406 * Check if an ID string is repeated within a given sequence of bytes at 3407 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a 3408 * period of 3). This is a helper function for nand_id_len(). Returns non-zero 3409 * if the repetition has a period of @period; otherwise, returns zero. 3410 */ nand_id_has_period(u8 * id_data,int arrlen,int period)3411 static int nand_id_has_period(u8 *id_data, int arrlen, int period) 3412 { 3413 int i, j; 3414 for (i = 0; i < period; i++) 3415 for (j = i + period; j < arrlen; j += period) 3416 if (id_data[i] != id_data[j]) 3417 return 0; 3418 return 1; 3419 } 3420 3421 /* 3422 * nand_id_len - Get the length of an ID string returned by CMD_READID 3423 * @id_data: the ID string 3424 * @arrlen: the length of the @id_data array 3425 3426 * Returns the length of the ID string, according to known wraparound/trailing 3427 * zero patterns. If no pattern exists, returns the length of the array. 3428 */ nand_id_len(u8 * id_data,int arrlen)3429 static int nand_id_len(u8 *id_data, int arrlen) 3430 { 3431 int last_nonzero, period; 3432 3433 /* Find last non-zero byte */ 3434 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) 3435 if (id_data[last_nonzero]) 3436 break; 3437 3438 /* All zeros */ 3439 if (last_nonzero < 0) 3440 return 0; 3441 3442 /* Calculate wraparound period */ 3443 for (period = 1; period < arrlen; period++) 3444 if (nand_id_has_period(id_data, arrlen, period)) 3445 break; 3446 3447 /* There's a repeated pattern */ 3448 if (period < arrlen) 3449 return period; 3450 3451 /* There are trailing zeros */ 3452 if (last_nonzero < arrlen - 1) 3453 return last_nonzero + 1; 3454 3455 /* No pattern detected */ 3456 return arrlen; 3457 } 3458 3459 /* Extract the bits of per cell from the 3rd byte of the extended ID */ nand_get_bits_per_cell(u8 cellinfo)3460 static int nand_get_bits_per_cell(u8 cellinfo) 3461 { 3462 int bits; 3463 3464 bits = cellinfo & NAND_CI_CELLTYPE_MSK; 3465 bits >>= NAND_CI_CELLTYPE_SHIFT; 3466 return bits + 1; 3467 } 3468 3469 /* 3470 * Many new NAND share similar device ID codes, which represent the size of the 3471 * chip. The rest of the parameters must be decoded according to generic or 3472 * manufacturer-specific "extended ID" decoding patterns. 3473 */ nand_decode_ext_id(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8],int * busw)3474 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, 3475 u8 id_data[8], int *busw) 3476 { 3477 int extid, id_len; 3478 /* The 3rd id byte holds MLC / multichip data */ 3479 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 3480 /* The 4th id byte is the important one */ 3481 extid = id_data[3]; 3482 3483 id_len = nand_id_len(id_data, 8); 3484 3485 /* 3486 * Field definitions are in the following datasheets: 3487 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) 3488 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) 3489 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) 3490 * 3491 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung 3492 * ID to decide what to do. 3493 */ 3494 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && 3495 !nand_is_slc(chip) && id_data[5] != 0x00) { 3496 /* Calc pagesize */ 3497 mtd->writesize = 2048 << (extid & 0x03); 3498 extid >>= 2; 3499 /* Calc oobsize */ 3500 switch (((extid >> 2) & 0x04) | (extid & 0x03)) { 3501 case 1: 3502 mtd->oobsize = 128; 3503 break; 3504 case 2: 3505 mtd->oobsize = 218; 3506 break; 3507 case 3: 3508 mtd->oobsize = 400; 3509 break; 3510 case 4: 3511 mtd->oobsize = 436; 3512 break; 3513 case 5: 3514 mtd->oobsize = 512; 3515 break; 3516 case 6: 3517 mtd->oobsize = 640; 3518 break; 3519 case 7: 3520 default: /* Other cases are "reserved" (unknown) */ 3521 mtd->oobsize = 1024; 3522 break; 3523 } 3524 extid >>= 2; 3525 /* Calc blocksize */ 3526 mtd->erasesize = (128 * 1024) << 3527 (((extid >> 1) & 0x04) | (extid & 0x03)); 3528 *busw = 0; 3529 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && 3530 !nand_is_slc(chip)) { 3531 unsigned int tmp; 3532 3533 /* Calc pagesize */ 3534 mtd->writesize = 2048 << (extid & 0x03); 3535 extid >>= 2; 3536 /* Calc oobsize */ 3537 switch (((extid >> 2) & 0x04) | (extid & 0x03)) { 3538 case 0: 3539 mtd->oobsize = 128; 3540 break; 3541 case 1: 3542 mtd->oobsize = 224; 3543 break; 3544 case 2: 3545 mtd->oobsize = 448; 3546 break; 3547 case 3: 3548 mtd->oobsize = 64; 3549 break; 3550 case 4: 3551 mtd->oobsize = 32; 3552 break; 3553 case 5: 3554 mtd->oobsize = 16; 3555 break; 3556 default: 3557 mtd->oobsize = 640; 3558 break; 3559 } 3560 extid >>= 2; 3561 /* Calc blocksize */ 3562 tmp = ((extid >> 1) & 0x04) | (extid & 0x03); 3563 if (tmp < 0x03) 3564 mtd->erasesize = (128 * 1024) << tmp; 3565 else if (tmp == 0x03) 3566 mtd->erasesize = 768 * 1024; 3567 else 3568 mtd->erasesize = (64 * 1024) << tmp; 3569 *busw = 0; 3570 } else { 3571 /* Calc pagesize */ 3572 mtd->writesize = 1024 << (extid & 0x03); 3573 extid >>= 2; 3574 /* Calc oobsize */ 3575 mtd->oobsize = (8 << (extid & 0x01)) * 3576 (mtd->writesize >> 9); 3577 extid >>= 2; 3578 /* Calc blocksize. Blocksize is multiples of 64KiB */ 3579 mtd->erasesize = (64 * 1024) << (extid & 0x03); 3580 extid >>= 2; 3581 /* Get buswidth information */ 3582 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; 3583 3584 /* 3585 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per 3586 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as 3587 * follows: 3588 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, 3589 * 110b -> 24nm 3590 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC 3591 */ 3592 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && 3593 nand_is_slc(chip) && 3594 (id_data[5] & 0x7) == 0x6 /* 24nm */ && 3595 !(id_data[4] & 0x80) /* !BENAND */) { 3596 mtd->oobsize = 32 * mtd->writesize >> 9; 3597 } 3598 3599 } 3600 } 3601 3602 /* 3603 * Old devices have chip data hardcoded in the device ID table. nand_decode_id 3604 * decodes a matching ID table entry and assigns the MTD size parameters for 3605 * the chip. 3606 */ nand_decode_id(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 id_data[8],int * busw)3607 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, 3608 struct nand_flash_dev *type, u8 id_data[8], 3609 int *busw) 3610 { 3611 int maf_id = id_data[0]; 3612 3613 mtd->erasesize = type->erasesize; 3614 mtd->writesize = type->pagesize; 3615 mtd->oobsize = mtd->writesize / 32; 3616 *busw = type->options & NAND_BUSWIDTH_16; 3617 3618 /* All legacy ID NAND are small-page, SLC */ 3619 chip->bits_per_cell = 1; 3620 3621 /* 3622 * Check for Spansion/AMD ID + repeating 5th, 6th byte since 3623 * some Spansion chips have erasesize that conflicts with size 3624 * listed in nand_ids table. 3625 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) 3626 */ 3627 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 3628 && id_data[6] == 0x00 && id_data[7] == 0x00 3629 && mtd->writesize == 512) { 3630 mtd->erasesize = 128 * 1024; 3631 mtd->erasesize <<= ((id_data[3] & 0x03) << 1); 3632 } 3633 } 3634 3635 /* 3636 * Set the bad block marker/indicator (BBM/BBI) patterns according to some 3637 * heuristic patterns using various detected parameters (e.g., manufacturer, 3638 * page size, cell-type information). 3639 */ nand_decode_bbm_options(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8])3640 static void nand_decode_bbm_options(struct mtd_info *mtd, 3641 struct nand_chip *chip, u8 id_data[8]) 3642 { 3643 int maf_id = id_data[0]; 3644 3645 /* Set the bad block position */ 3646 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) 3647 chip->badblockpos = NAND_LARGE_BADBLOCK_POS; 3648 else 3649 chip->badblockpos = NAND_SMALL_BADBLOCK_POS; 3650 3651 /* 3652 * Bad block marker is stored in the last page of each block on Samsung 3653 * and Hynix MLC devices; stored in first two pages of each block on 3654 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, 3655 * AMD/Spansion, and Macronix. All others scan only the first page. 3656 */ 3657 if (!nand_is_slc(chip) && 3658 (maf_id == NAND_MFR_SAMSUNG || 3659 maf_id == NAND_MFR_HYNIX)) 3660 chip->bbt_options |= NAND_BBT_SCANLASTPAGE; 3661 else if ((nand_is_slc(chip) && 3662 (maf_id == NAND_MFR_SAMSUNG || 3663 maf_id == NAND_MFR_HYNIX || 3664 maf_id == NAND_MFR_TOSHIBA || 3665 maf_id == NAND_MFR_AMD || 3666 maf_id == NAND_MFR_MACRONIX)) || 3667 (mtd->writesize == 2048 && 3668 maf_id == NAND_MFR_MICRON)) 3669 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; 3670 } 3671 is_full_id_nand(struct nand_flash_dev * type)3672 static inline bool is_full_id_nand(struct nand_flash_dev *type) 3673 { 3674 return type->id_len; 3675 } 3676 find_full_id_nand(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 * id_data,int * busw)3677 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, 3678 struct nand_flash_dev *type, u8 *id_data, int *busw) 3679 { 3680 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { 3681 mtd->writesize = type->pagesize; 3682 mtd->erasesize = type->erasesize; 3683 mtd->oobsize = type->oobsize; 3684 3685 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 3686 chip->chipsize = (uint64_t)type->chipsize << 20; 3687 chip->options |= type->options; 3688 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); 3689 chip->ecc_step_ds = NAND_ECC_STEP(type); 3690 chip->onfi_timing_mode_default = 3691 type->onfi_timing_mode_default; 3692 3693 *busw = type->options & NAND_BUSWIDTH_16; 3694 3695 if (!mtd->name) 3696 mtd->name = type->name; 3697 3698 return true; 3699 } 3700 return false; 3701 } 3702 3703 /* 3704 * Get the flash and manufacturer id and lookup if the type is supported. 3705 */ nand_get_flash_type(struct mtd_info * mtd,struct nand_chip * chip,int * maf_id,int * dev_id,struct nand_flash_dev * type)3706 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, 3707 struct nand_chip *chip, 3708 int *maf_id, int *dev_id, 3709 struct nand_flash_dev *type) 3710 { 3711 int busw; 3712 int i, maf_idx; 3713 u8 id_data[8]; 3714 3715 /* 3716 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 3717 * after power-up. 3718 */ 3719 nand_reset(chip, 0); 3720 3721 /* Select the device */ 3722 chip->select_chip(mtd, 0); 3723 3724 /* Send the command for reading device ID */ 3725 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 3726 3727 /* Read manufacturer and device IDs */ 3728 *maf_id = chip->read_byte(mtd); 3729 *dev_id = chip->read_byte(mtd); 3730 3731 /* 3732 * Try again to make sure, as some systems the bus-hold or other 3733 * interface concerns can cause random data which looks like a 3734 * possibly credible NAND flash to appear. If the two results do 3735 * not match, ignore the device completely. 3736 */ 3737 3738 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 3739 3740 /* Read entire ID string */ 3741 for (i = 0; i < 8; i++) 3742 id_data[i] = chip->read_byte(mtd); 3743 3744 if (id_data[0] != *maf_id || id_data[1] != *dev_id) { 3745 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", 3746 *maf_id, *dev_id, id_data[0], id_data[1]); 3747 return ERR_PTR(-ENODEV); 3748 } 3749 3750 if (!type) 3751 type = nand_flash_ids; 3752 3753 for (; type->name != NULL; type++) { 3754 if (is_full_id_nand(type)) { 3755 if (find_full_id_nand(mtd, chip, type, id_data, &busw)) 3756 goto ident_done; 3757 } else if (*dev_id == type->dev_id) { 3758 break; 3759 } 3760 } 3761 3762 chip->onfi_version = 0; 3763 if (!type->name || !type->pagesize) { 3764 /* Check if the chip is ONFI compliant */ 3765 if (nand_flash_detect_onfi(mtd, chip, &busw)) 3766 goto ident_done; 3767 3768 /* Check if the chip is JEDEC compliant */ 3769 if (nand_flash_detect_jedec(mtd, chip, &busw)) 3770 goto ident_done; 3771 } 3772 3773 if (!type->name) 3774 return ERR_PTR(-ENODEV); 3775 3776 if (!mtd->name) 3777 mtd->name = type->name; 3778 3779 chip->chipsize = (uint64_t)type->chipsize << 20; 3780 3781 if (!type->pagesize) { 3782 /* Decode parameters from extended ID */ 3783 nand_decode_ext_id(mtd, chip, id_data, &busw); 3784 } else { 3785 nand_decode_id(mtd, chip, type, id_data, &busw); 3786 } 3787 /* Get chip options */ 3788 chip->options |= type->options; 3789 3790 /* 3791 * Check if chip is not a Samsung device. Do not clear the 3792 * options for chips which do not have an extended id. 3793 */ 3794 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) 3795 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; 3796 ident_done: 3797 3798 /* Try to identify manufacturer */ 3799 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { 3800 if (nand_manuf_ids[maf_idx].id == *maf_id) 3801 break; 3802 } 3803 3804 if (chip->options & NAND_BUSWIDTH_AUTO) { 3805 WARN_ON(chip->options & NAND_BUSWIDTH_16); 3806 chip->options |= busw; 3807 nand_set_defaults(chip, busw); 3808 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { 3809 /* 3810 * Check, if buswidth is correct. Hardware drivers should set 3811 * chip correct! 3812 */ 3813 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 3814 *maf_id, *dev_id); 3815 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); 3816 pr_warn("bus width %d instead %d bit\n", 3817 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, 3818 busw ? 16 : 8); 3819 return ERR_PTR(-EINVAL); 3820 } 3821 3822 nand_decode_bbm_options(mtd, chip, id_data); 3823 3824 /* Calculate the address shift from the page size */ 3825 chip->page_shift = ffs(mtd->writesize) - 1; 3826 /* Convert chipsize to number of pages per chip -1 */ 3827 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; 3828 3829 chip->bbt_erase_shift = chip->phys_erase_shift = 3830 ffs(mtd->erasesize) - 1; 3831 if (chip->chipsize & 0xffffffff) 3832 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; 3833 else { 3834 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); 3835 chip->chip_shift += 32 - 1; 3836 } 3837 3838 if (chip->chip_shift - chip->page_shift > 16) 3839 chip->options |= NAND_ROW_ADDR_3; 3840 3841 chip->badblockbits = 8; 3842 chip->erase = single_erase; 3843 3844 /* Do not replace user supplied command function! */ 3845 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 3846 chip->cmdfunc = nand_command_lp; 3847 3848 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 3849 *maf_id, *dev_id); 3850 3851 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 3852 if (chip->onfi_version) 3853 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3854 chip->onfi_params.model); 3855 else if (chip->jedec_version) 3856 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3857 chip->jedec_params.model); 3858 else 3859 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3860 type->name); 3861 #else 3862 if (chip->jedec_version) 3863 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3864 chip->jedec_params.model); 3865 else 3866 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3867 type->name); 3868 3869 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3870 type->name); 3871 #endif 3872 3873 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", 3874 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", 3875 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); 3876 return type; 3877 } 3878 EXPORT_SYMBOL(nand_get_flash_type); 3879 3880 #if CONFIG_IS_ENABLED(OF_CONTROL) 3881 DECLARE_GLOBAL_DATA_PTR; 3882 nand_dt_init(struct mtd_info * mtd,struct nand_chip * chip,int node)3883 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) 3884 { 3885 int ret, ecc_mode = -1, ecc_strength, ecc_step; 3886 const void *blob = gd->fdt_blob; 3887 const char *str; 3888 3889 ret = fdtdec_get_int(blob, node, "nand-bus-width", -1); 3890 if (ret == 16) 3891 chip->options |= NAND_BUSWIDTH_16; 3892 3893 if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt")) 3894 chip->bbt_options |= NAND_BBT_USE_FLASH; 3895 3896 str = fdt_getprop(blob, node, "nand-ecc-mode", NULL); 3897 if (str) { 3898 if (!strcmp(str, "none")) 3899 ecc_mode = NAND_ECC_NONE; 3900 else if (!strcmp(str, "soft")) 3901 ecc_mode = NAND_ECC_SOFT; 3902 else if (!strcmp(str, "hw")) 3903 ecc_mode = NAND_ECC_HW; 3904 else if (!strcmp(str, "hw_syndrome")) 3905 ecc_mode = NAND_ECC_HW_SYNDROME; 3906 else if (!strcmp(str, "hw_oob_first")) 3907 ecc_mode = NAND_ECC_HW_OOB_FIRST; 3908 else if (!strcmp(str, "soft_bch")) 3909 ecc_mode = NAND_ECC_SOFT_BCH; 3910 } 3911 3912 3913 ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1); 3914 ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1); 3915 3916 if ((ecc_step >= 0 && !(ecc_strength >= 0)) || 3917 (!(ecc_step >= 0) && ecc_strength >= 0)) { 3918 pr_err("must set both strength and step size in DT\n"); 3919 return -EINVAL; 3920 } 3921 3922 if (ecc_mode >= 0) 3923 chip->ecc.mode = ecc_mode; 3924 3925 if (ecc_strength >= 0) 3926 chip->ecc.strength = ecc_strength; 3927 3928 if (ecc_step > 0) 3929 chip->ecc.size = ecc_step; 3930 3931 if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL)) 3932 chip->ecc.options |= NAND_ECC_MAXIMIZE; 3933 3934 return 0; 3935 } 3936 #else nand_dt_init(struct mtd_info * mtd,struct nand_chip * chip,int node)3937 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) 3938 { 3939 return 0; 3940 } 3941 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 3942 3943 /** 3944 * nand_scan_ident - [NAND Interface] Scan for the NAND device 3945 * @mtd: MTD device structure 3946 * @maxchips: number of chips to scan for 3947 * @table: alternative NAND ID table 3948 * 3949 * This is the first phase of the normal nand_scan() function. It reads the 3950 * flash ID and sets up MTD fields accordingly. 3951 * 3952 */ nand_scan_ident(struct mtd_info * mtd,int maxchips,struct nand_flash_dev * table)3953 int nand_scan_ident(struct mtd_info *mtd, int maxchips, 3954 struct nand_flash_dev *table) 3955 { 3956 int i, nand_maf_id, nand_dev_id; 3957 struct nand_chip *chip = mtd_to_nand(mtd); 3958 struct nand_flash_dev *type; 3959 int ret; 3960 3961 if (chip->flash_node) { 3962 ret = nand_dt_init(mtd, chip, chip->flash_node); 3963 if (ret) 3964 return ret; 3965 } 3966 3967 /* Set the default functions */ 3968 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); 3969 3970 /* Read the flash type */ 3971 type = nand_get_flash_type(mtd, chip, &nand_maf_id, 3972 &nand_dev_id, table); 3973 3974 if (IS_ERR(type)) { 3975 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) 3976 pr_warn("No NAND device found\n"); 3977 chip->select_chip(mtd, -1); 3978 return PTR_ERR(type); 3979 } 3980 3981 /* Initialize the ->data_interface field. */ 3982 ret = nand_init_data_interface(chip); 3983 if (ret) 3984 return ret; 3985 3986 /* 3987 * Setup the data interface correctly on the chip and controller side. 3988 * This explicit call to nand_setup_data_interface() is only required 3989 * for the first die, because nand_reset() has been called before 3990 * ->data_interface and ->default_onfi_timing_mode were set. 3991 * For the other dies, nand_reset() will automatically switch to the 3992 * best mode for us. 3993 */ 3994 ret = nand_setup_data_interface(chip, 0); 3995 if (ret) 3996 return ret; 3997 3998 chip->select_chip(mtd, -1); 3999 4000 /* Check for a chip array */ 4001 for (i = 1; i < maxchips; i++) { 4002 /* See comment in nand_get_flash_type for reset */ 4003 nand_reset(chip, i); 4004 4005 chip->select_chip(mtd, i); 4006 /* Send the command for reading device ID */ 4007 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 4008 /* Read manufacturer and device IDs */ 4009 if (nand_maf_id != chip->read_byte(mtd) || 4010 nand_dev_id != chip->read_byte(mtd)) { 4011 chip->select_chip(mtd, -1); 4012 break; 4013 } 4014 chip->select_chip(mtd, -1); 4015 } 4016 4017 #ifdef DEBUG 4018 if (i > 1) 4019 pr_info("%d chips detected\n", i); 4020 #endif 4021 4022 /* Store the number of chips and calc total size for mtd */ 4023 chip->numchips = i; 4024 mtd->size = i * chip->chipsize; 4025 4026 return 0; 4027 } 4028 EXPORT_SYMBOL(nand_scan_ident); 4029 4030 /** 4031 * nand_check_ecc_caps - check the sanity of preset ECC settings 4032 * @chip: nand chip info structure 4033 * @caps: ECC caps info structure 4034 * @oobavail: OOB size that the ECC engine can use 4035 * 4036 * When ECC step size and strength are already set, check if they are supported 4037 * by the controller and the calculated ECC bytes fit within the chip's OOB. 4038 * On success, the calculated ECC bytes is set. 4039 */ nand_check_ecc_caps(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4040 int nand_check_ecc_caps(struct nand_chip *chip, 4041 const struct nand_ecc_caps *caps, int oobavail) 4042 { 4043 struct mtd_info *mtd = nand_to_mtd(chip); 4044 const struct nand_ecc_step_info *stepinfo; 4045 int preset_step = chip->ecc.size; 4046 int preset_strength = chip->ecc.strength; 4047 int nsteps, ecc_bytes; 4048 int i, j; 4049 4050 if (WARN_ON(oobavail < 0)) 4051 return -EINVAL; 4052 4053 if (!preset_step || !preset_strength) 4054 return -ENODATA; 4055 4056 nsteps = mtd->writesize / preset_step; 4057 4058 for (i = 0; i < caps->nstepinfos; i++) { 4059 stepinfo = &caps->stepinfos[i]; 4060 4061 if (stepinfo->stepsize != preset_step) 4062 continue; 4063 4064 for (j = 0; j < stepinfo->nstrengths; j++) { 4065 if (stepinfo->strengths[j] != preset_strength) 4066 continue; 4067 4068 ecc_bytes = caps->calc_ecc_bytes(preset_step, 4069 preset_strength); 4070 if (WARN_ON_ONCE(ecc_bytes < 0)) 4071 return ecc_bytes; 4072 4073 if (ecc_bytes * nsteps > oobavail) { 4074 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", 4075 preset_step, preset_strength); 4076 return -ENOSPC; 4077 } 4078 4079 chip->ecc.bytes = ecc_bytes; 4080 4081 return 0; 4082 } 4083 } 4084 4085 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", 4086 preset_step, preset_strength); 4087 4088 return -ENOTSUPP; 4089 } 4090 EXPORT_SYMBOL_GPL(nand_check_ecc_caps); 4091 4092 /** 4093 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes 4094 * @chip: nand chip info structure 4095 * @caps: ECC engine caps info structure 4096 * @oobavail: OOB size that the ECC engine can use 4097 * 4098 * If a chip's ECC requirement is provided, try to meet it with the least 4099 * number of ECC bytes (i.e. with the largest number of OOB-free bytes). 4100 * On success, the chosen ECC settings are set. 4101 */ nand_match_ecc_req(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4102 int nand_match_ecc_req(struct nand_chip *chip, 4103 const struct nand_ecc_caps *caps, int oobavail) 4104 { 4105 struct mtd_info *mtd = nand_to_mtd(chip); 4106 const struct nand_ecc_step_info *stepinfo; 4107 int req_step = chip->ecc_step_ds; 4108 int req_strength = chip->ecc_strength_ds; 4109 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; 4110 int best_step, best_strength, best_ecc_bytes; 4111 int best_ecc_bytes_total = INT_MAX; 4112 int i, j; 4113 4114 if (WARN_ON(oobavail < 0)) 4115 return -EINVAL; 4116 4117 /* No information provided by the NAND chip */ 4118 if (!req_step || !req_strength) 4119 return -ENOTSUPP; 4120 4121 /* number of correctable bits the chip requires in a page */ 4122 req_corr = mtd->writesize / req_step * req_strength; 4123 4124 for (i = 0; i < caps->nstepinfos; i++) { 4125 stepinfo = &caps->stepinfos[i]; 4126 step_size = stepinfo->stepsize; 4127 4128 for (j = 0; j < stepinfo->nstrengths; j++) { 4129 strength = stepinfo->strengths[j]; 4130 4131 /* 4132 * If both step size and strength are smaller than the 4133 * chip's requirement, it is not easy to compare the 4134 * resulted reliability. 4135 */ 4136 if (step_size < req_step && strength < req_strength) 4137 continue; 4138 4139 if (mtd->writesize % step_size) 4140 continue; 4141 4142 nsteps = mtd->writesize / step_size; 4143 4144 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 4145 if (WARN_ON_ONCE(ecc_bytes < 0)) 4146 continue; 4147 ecc_bytes_total = ecc_bytes * nsteps; 4148 4149 if (ecc_bytes_total > oobavail || 4150 strength * nsteps < req_corr) 4151 continue; 4152 4153 /* 4154 * We assume the best is to meet the chip's requrement 4155 * with the least number of ECC bytes. 4156 */ 4157 if (ecc_bytes_total < best_ecc_bytes_total) { 4158 best_ecc_bytes_total = ecc_bytes_total; 4159 best_step = step_size; 4160 best_strength = strength; 4161 best_ecc_bytes = ecc_bytes; 4162 } 4163 } 4164 } 4165 4166 if (best_ecc_bytes_total == INT_MAX) 4167 return -ENOTSUPP; 4168 4169 chip->ecc.size = best_step; 4170 chip->ecc.strength = best_strength; 4171 chip->ecc.bytes = best_ecc_bytes; 4172 4173 return 0; 4174 } 4175 EXPORT_SYMBOL_GPL(nand_match_ecc_req); 4176 4177 /** 4178 * nand_maximize_ecc - choose the max ECC strength available 4179 * @chip: nand chip info structure 4180 * @caps: ECC engine caps info structure 4181 * @oobavail: OOB size that the ECC engine can use 4182 * 4183 * Choose the max ECC strength that is supported on the controller, and can fit 4184 * within the chip's OOB. On success, the chosen ECC settings are set. 4185 */ nand_maximize_ecc(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4186 int nand_maximize_ecc(struct nand_chip *chip, 4187 const struct nand_ecc_caps *caps, int oobavail) 4188 { 4189 struct mtd_info *mtd = nand_to_mtd(chip); 4190 const struct nand_ecc_step_info *stepinfo; 4191 int step_size, strength, nsteps, ecc_bytes, corr; 4192 int best_corr = 0; 4193 int best_step = 0; 4194 int best_strength, best_ecc_bytes; 4195 int i, j; 4196 4197 if (WARN_ON(oobavail < 0)) 4198 return -EINVAL; 4199 4200 for (i = 0; i < caps->nstepinfos; i++) { 4201 stepinfo = &caps->stepinfos[i]; 4202 step_size = stepinfo->stepsize; 4203 4204 /* If chip->ecc.size is already set, respect it */ 4205 if (chip->ecc.size && step_size != chip->ecc.size) 4206 continue; 4207 4208 for (j = 0; j < stepinfo->nstrengths; j++) { 4209 strength = stepinfo->strengths[j]; 4210 4211 if (mtd->writesize % step_size) 4212 continue; 4213 4214 nsteps = mtd->writesize / step_size; 4215 4216 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 4217 if (WARN_ON_ONCE(ecc_bytes < 0)) 4218 continue; 4219 4220 if (ecc_bytes * nsteps > oobavail) 4221 continue; 4222 4223 corr = strength * nsteps; 4224 4225 /* 4226 * If the number of correctable bits is the same, 4227 * bigger step_size has more reliability. 4228 */ 4229 if (corr > best_corr || 4230 (corr == best_corr && step_size > best_step)) { 4231 best_corr = corr; 4232 best_step = step_size; 4233 best_strength = strength; 4234 best_ecc_bytes = ecc_bytes; 4235 } 4236 } 4237 } 4238 4239 if (!best_corr) 4240 return -ENOTSUPP; 4241 4242 chip->ecc.size = best_step; 4243 chip->ecc.strength = best_strength; 4244 chip->ecc.bytes = best_ecc_bytes; 4245 4246 return 0; 4247 } 4248 EXPORT_SYMBOL_GPL(nand_maximize_ecc); 4249 4250 /* 4251 * Check if the chip configuration meet the datasheet requirements. 4252 4253 * If our configuration corrects A bits per B bytes and the minimum 4254 * required correction level is X bits per Y bytes, then we must ensure 4255 * both of the following are true: 4256 * 4257 * (1) A / B >= X / Y 4258 * (2) A >= X 4259 * 4260 * Requirement (1) ensures we can correct for the required bitflip density. 4261 * Requirement (2) ensures we can correct even when all bitflips are clumped 4262 * in the same sector. 4263 */ nand_ecc_strength_good(struct mtd_info * mtd)4264 static bool nand_ecc_strength_good(struct mtd_info *mtd) 4265 { 4266 struct nand_chip *chip = mtd_to_nand(mtd); 4267 struct nand_ecc_ctrl *ecc = &chip->ecc; 4268 int corr, ds_corr; 4269 4270 if (ecc->size == 0 || chip->ecc_step_ds == 0) 4271 /* Not enough information */ 4272 return true; 4273 4274 /* 4275 * We get the number of corrected bits per page to compare 4276 * the correction density. 4277 */ 4278 corr = (mtd->writesize * ecc->strength) / ecc->size; 4279 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; 4280 4281 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; 4282 } 4283 invalid_ecc_page_accessors(struct nand_chip * chip)4284 static bool invalid_ecc_page_accessors(struct nand_chip *chip) 4285 { 4286 struct nand_ecc_ctrl *ecc = &chip->ecc; 4287 4288 if (nand_standard_page_accessors(ecc)) 4289 return false; 4290 4291 /* 4292 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND 4293 * controller driver implements all the page accessors because 4294 * default helpers are not suitable when the core does not 4295 * send the READ0/PAGEPROG commands. 4296 */ 4297 return (!ecc->read_page || !ecc->write_page || 4298 !ecc->read_page_raw || !ecc->write_page_raw || 4299 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) || 4300 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage && 4301 ecc->hwctl && ecc->calculate)); 4302 } 4303 4304 /** 4305 * nand_scan_tail - [NAND Interface] Scan for the NAND device 4306 * @mtd: MTD device structure 4307 * 4308 * This is the second phase of the normal nand_scan() function. It fills out 4309 * all the uninitialized function pointers with the defaults and scans for a 4310 * bad block table if appropriate. 4311 */ nand_scan_tail(struct mtd_info * mtd)4312 int nand_scan_tail(struct mtd_info *mtd) 4313 { 4314 int i; 4315 struct nand_chip *chip = mtd_to_nand(mtd); 4316 struct nand_ecc_ctrl *ecc = &chip->ecc; 4317 struct nand_buffers *nbuf; 4318 4319 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ 4320 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && 4321 !(chip->bbt_options & NAND_BBT_USE_FLASH)); 4322 4323 if (invalid_ecc_page_accessors(chip)) { 4324 pr_err("Invalid ECC page accessors setup\n"); 4325 return -EINVAL; 4326 } 4327 4328 if (!(chip->options & NAND_OWN_BUFFERS)) { 4329 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL); 4330 chip->buffers = nbuf; 4331 } else { 4332 if (!chip->buffers) 4333 return -ENOMEM; 4334 } 4335 4336 /* Set the internal oob buffer location, just after the page data */ 4337 chip->oob_poi = chip->buffers->databuf + mtd->writesize; 4338 4339 /* 4340 * If no default placement scheme is given, select an appropriate one. 4341 */ 4342 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { 4343 switch (mtd->oobsize) { 4344 #ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT 4345 case 8: 4346 ecc->layout = &nand_oob_8; 4347 break; 4348 case 16: 4349 ecc->layout = &nand_oob_16; 4350 break; 4351 case 64: 4352 ecc->layout = &nand_oob_64; 4353 break; 4354 case 128: 4355 ecc->layout = &nand_oob_128; 4356 break; 4357 #endif 4358 default: 4359 pr_warn("No oob scheme defined for oobsize %d\n", 4360 mtd->oobsize); 4361 BUG(); 4362 } 4363 } 4364 4365 if (!chip->write_page) 4366 chip->write_page = nand_write_page; 4367 4368 /* 4369 * Check ECC mode, default to software if 3byte/512byte hardware ECC is 4370 * selected and we have 256 byte pagesize fallback to software ECC 4371 */ 4372 4373 switch (ecc->mode) { 4374 case NAND_ECC_HW_OOB_FIRST: 4375 /* Similar to NAND_ECC_HW, but a separate read_page handle */ 4376 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { 4377 pr_warn("No ECC functions supplied; hardware ECC not possible\n"); 4378 BUG(); 4379 } 4380 if (!ecc->read_page) 4381 ecc->read_page = nand_read_page_hwecc_oob_first; 4382 4383 case NAND_ECC_HW: 4384 /* Use standard hwecc read page function? */ 4385 if (!ecc->read_page) 4386 ecc->read_page = nand_read_page_hwecc; 4387 if (!ecc->write_page) 4388 ecc->write_page = nand_write_page_hwecc; 4389 if (!ecc->read_page_raw) 4390 ecc->read_page_raw = nand_read_page_raw; 4391 if (!ecc->write_page_raw) 4392 ecc->write_page_raw = nand_write_page_raw; 4393 if (!ecc->read_oob) 4394 ecc->read_oob = nand_read_oob_std; 4395 if (!ecc->write_oob) 4396 ecc->write_oob = nand_write_oob_std; 4397 if (!ecc->read_subpage) 4398 ecc->read_subpage = nand_read_subpage; 4399 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 4400 ecc->write_subpage = nand_write_subpage_hwecc; 4401 4402 case NAND_ECC_HW_SYNDROME: 4403 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 4404 (!ecc->read_page || 4405 ecc->read_page == nand_read_page_hwecc || 4406 !ecc->write_page || 4407 ecc->write_page == nand_write_page_hwecc)) { 4408 pr_warn("No ECC functions supplied; hardware ECC not possible\n"); 4409 BUG(); 4410 } 4411 /* Use standard syndrome read/write page function? */ 4412 if (!ecc->read_page) 4413 ecc->read_page = nand_read_page_syndrome; 4414 if (!ecc->write_page) 4415 ecc->write_page = nand_write_page_syndrome; 4416 if (!ecc->read_page_raw) 4417 ecc->read_page_raw = nand_read_page_raw_syndrome; 4418 if (!ecc->write_page_raw) 4419 ecc->write_page_raw = nand_write_page_raw_syndrome; 4420 if (!ecc->read_oob) 4421 ecc->read_oob = nand_read_oob_syndrome; 4422 if (!ecc->write_oob) 4423 ecc->write_oob = nand_write_oob_syndrome; 4424 4425 if (mtd->writesize >= ecc->size) { 4426 if (!ecc->strength) { 4427 pr_warn("Driver must set ecc.strength when using hardware ECC\n"); 4428 BUG(); 4429 } 4430 break; 4431 } 4432 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", 4433 ecc->size, mtd->writesize); 4434 ecc->mode = NAND_ECC_SOFT; 4435 4436 case NAND_ECC_SOFT: 4437 ecc->calculate = nand_calculate_ecc; 4438 ecc->correct = nand_correct_data; 4439 ecc->read_page = nand_read_page_swecc; 4440 ecc->read_subpage = nand_read_subpage; 4441 ecc->write_page = nand_write_page_swecc; 4442 ecc->read_page_raw = nand_read_page_raw; 4443 ecc->write_page_raw = nand_write_page_raw; 4444 ecc->read_oob = nand_read_oob_std; 4445 ecc->write_oob = nand_write_oob_std; 4446 if (!ecc->size) 4447 ecc->size = 256; 4448 ecc->bytes = 3; 4449 ecc->strength = 1; 4450 break; 4451 4452 case NAND_ECC_SOFT_BCH: 4453 if (!mtd_nand_has_bch()) { 4454 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); 4455 BUG(); 4456 } 4457 ecc->calculate = nand_bch_calculate_ecc; 4458 ecc->correct = nand_bch_correct_data; 4459 ecc->read_page = nand_read_page_swecc; 4460 ecc->read_subpage = nand_read_subpage; 4461 ecc->write_page = nand_write_page_swecc; 4462 ecc->read_page_raw = nand_read_page_raw; 4463 ecc->write_page_raw = nand_write_page_raw; 4464 ecc->read_oob = nand_read_oob_std; 4465 ecc->write_oob = nand_write_oob_std; 4466 /* 4467 * Board driver should supply ecc.size and ecc.strength values 4468 * to select how many bits are correctable. Otherwise, default 4469 * to 4 bits for large page devices. 4470 */ 4471 if (!ecc->size && (mtd->oobsize >= 64)) { 4472 ecc->size = 512; 4473 ecc->strength = 4; 4474 } 4475 4476 /* See nand_bch_init() for details. */ 4477 ecc->bytes = 0; 4478 ecc->priv = nand_bch_init(mtd); 4479 if (!ecc->priv) { 4480 pr_warn("BCH ECC initialization failed!\n"); 4481 BUG(); 4482 } 4483 break; 4484 4485 case NAND_ECC_NONE: 4486 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); 4487 ecc->read_page = nand_read_page_raw; 4488 ecc->write_page = nand_write_page_raw; 4489 ecc->read_oob = nand_read_oob_std; 4490 ecc->read_page_raw = nand_read_page_raw; 4491 ecc->write_page_raw = nand_write_page_raw; 4492 ecc->write_oob = nand_write_oob_std; 4493 ecc->size = mtd->writesize; 4494 ecc->bytes = 0; 4495 ecc->strength = 0; 4496 break; 4497 4498 default: 4499 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); 4500 BUG(); 4501 } 4502 4503 /* For many systems, the standard OOB write also works for raw */ 4504 if (!ecc->read_oob_raw) 4505 ecc->read_oob_raw = ecc->read_oob; 4506 if (!ecc->write_oob_raw) 4507 ecc->write_oob_raw = ecc->write_oob; 4508 4509 /* 4510 * The number of bytes available for a client to place data into 4511 * the out of band area. 4512 */ 4513 mtd->oobavail = 0; 4514 if (ecc->layout) { 4515 for (i = 0; ecc->layout->oobfree[i].length; i++) 4516 mtd->oobavail += ecc->layout->oobfree[i].length; 4517 } 4518 4519 /* ECC sanity check: warn if it's too weak */ 4520 if (!nand_ecc_strength_good(mtd)) 4521 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", 4522 mtd->name); 4523 4524 /* 4525 * Set the number of read / write steps for one page depending on ECC 4526 * mode. 4527 */ 4528 ecc->steps = mtd->writesize / ecc->size; 4529 if (ecc->steps * ecc->size != mtd->writesize) { 4530 pr_warn("Invalid ECC parameters\n"); 4531 BUG(); 4532 } 4533 ecc->total = ecc->steps * ecc->bytes; 4534 4535 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 4536 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { 4537 switch (ecc->steps) { 4538 case 2: 4539 mtd->subpage_sft = 1; 4540 break; 4541 case 4: 4542 case 8: 4543 case 16: 4544 mtd->subpage_sft = 2; 4545 break; 4546 } 4547 } 4548 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 4549 4550 /* Initialize state */ 4551 chip->state = FL_READY; 4552 4553 /* Invalidate the pagebuffer reference */ 4554 chip->pagebuf = -1; 4555 4556 /* Large page NAND with SOFT_ECC should support subpage reads */ 4557 switch (ecc->mode) { 4558 case NAND_ECC_SOFT: 4559 case NAND_ECC_SOFT_BCH: 4560 if (chip->page_shift > 9) 4561 chip->options |= NAND_SUBPAGE_READ; 4562 break; 4563 4564 default: 4565 break; 4566 } 4567 4568 /* Fill in remaining MTD driver data */ 4569 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; 4570 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : 4571 MTD_CAP_NANDFLASH; 4572 mtd->_erase = nand_erase; 4573 mtd->_panic_write = panic_nand_write; 4574 mtd->_read_oob = nand_read_oob; 4575 mtd->_write_oob = nand_write_oob; 4576 mtd->_sync = nand_sync; 4577 mtd->_lock = NULL; 4578 mtd->_unlock = NULL; 4579 mtd->_block_isreserved = nand_block_isreserved; 4580 mtd->_block_isbad = nand_block_isbad; 4581 mtd->_block_markbad = nand_block_markbad; 4582 mtd->writebufsize = mtd->writesize; 4583 4584 /* propagate ecc info to mtd_info */ 4585 mtd->ecclayout = ecc->layout; 4586 mtd->ecc_strength = ecc->strength; 4587 mtd->ecc_step_size = ecc->size; 4588 /* 4589 * Initialize bitflip_threshold to its default prior scan_bbt() call. 4590 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be 4591 * properly set. 4592 */ 4593 if (!mtd->bitflip_threshold) 4594 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); 4595 4596 return 0; 4597 } 4598 EXPORT_SYMBOL(nand_scan_tail); 4599 4600 /** 4601 * nand_scan - [NAND Interface] Scan for the NAND device 4602 * @mtd: MTD device structure 4603 * @maxchips: number of chips to scan for 4604 * 4605 * This fills out all the uninitialized function pointers with the defaults. 4606 * The flash ID is read and the mtd/chip structures are filled with the 4607 * appropriate values. 4608 */ nand_scan(struct mtd_info * mtd,int maxchips)4609 int nand_scan(struct mtd_info *mtd, int maxchips) 4610 { 4611 int ret; 4612 4613 ret = nand_scan_ident(mtd, maxchips, NULL); 4614 if (!ret) 4615 ret = nand_scan_tail(mtd); 4616 return ret; 4617 } 4618 EXPORT_SYMBOL(nand_scan); 4619 4620 MODULE_LICENSE("GPL"); 4621 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); 4622 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); 4623 MODULE_DESCRIPTION("Generic NAND flash driver code"); 4624