1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Rockchip USB2.0 PHY with Innosilicon IP block driver
4  *
5  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/power_supply.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/usb/of.h>
30 #include <linux/usb/otg.h>
31 
32 #define BIT_WRITEABLE_SHIFT	16
33 #define SCHEDULE_DELAY		(60 * HZ)
34 #define OTG_SCHEDULE_DELAY	(2 * HZ)
35 
36 struct rockchip_usb2phy;
37 
38 enum rockchip_usb2phy_port_id {
39 	USB2PHY_PORT_OTG,
40 	USB2PHY_PORT_HOST,
41 	USB2PHY_NUM_PORTS,
42 };
43 
44 enum rockchip_usb2phy_host_state {
45 	PHY_STATE_HS_ONLINE	= 0,
46 	PHY_STATE_DISCONNECT	= 1,
47 	PHY_STATE_CONNECT	= 2,
48 	PHY_STATE_FS_LS_ONLINE	= 4,
49 };
50 
51 /**
52  * enum usb_chg_state - Different states involved in USB charger detection.
53  * @USB_CHG_STATE_UNDEFINED:	USB charger is not connected or detection
54  *				process is not yet started.
55  * @USB_CHG_STATE_WAIT_FOR_DCD:	Waiting for Data pins contact.
56  * @USB_CHG_STATE_DCD_DONE:	Data pin contact is detected.
57  * @USB_CHG_STATE_PRIMARY_DONE:	Primary detection is completed (Detects
58  *				between SDP and DCP/CDP).
59  * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
60  *				  between DCP and CDP).
61  * @USB_CHG_STATE_DETECTED:	USB charger type is determined.
62  */
63 enum usb_chg_state {
64 	USB_CHG_STATE_UNDEFINED = 0,
65 	USB_CHG_STATE_WAIT_FOR_DCD,
66 	USB_CHG_STATE_DCD_DONE,
67 	USB_CHG_STATE_PRIMARY_DONE,
68 	USB_CHG_STATE_SECONDARY_DONE,
69 	USB_CHG_STATE_DETECTED,
70 };
71 
72 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
73 	EXTCON_USB,
74 	EXTCON_USB_HOST,
75 	EXTCON_CHG_USB_SDP,
76 	EXTCON_CHG_USB_CDP,
77 	EXTCON_CHG_USB_DCP,
78 	EXTCON_CHG_USB_SLOW,
79 	EXTCON_NONE,
80 };
81 
82 struct usb2phy_reg {
83 	unsigned int	offset;
84 	unsigned int	bitend;
85 	unsigned int	bitstart;
86 	unsigned int	disable;
87 	unsigned int	enable;
88 };
89 
90 /**
91  * struct rockchip_chg_det_reg - usb charger detect registers
92  * @cp_det: charging port detected successfully.
93  * @dcp_det: dedicated charging port detected successfully.
94  * @dp_det: assert data pin connect successfully.
95  * @idm_sink_en: open dm sink curren.
96  * @idp_sink_en: open dp sink current.
97  * @idp_src_en: open dm source current.
98  * @rdm_pdwn_en: open dm pull down resistor.
99  * @vdm_src_en: open dm voltage source.
100  * @vdp_src_en: open dp voltage source.
101  * @opmode: utmi operational mode.
102  */
103 struct rockchip_chg_det_reg {
104 	struct usb2phy_reg	cp_det;
105 	struct usb2phy_reg	dcp_det;
106 	struct usb2phy_reg	dp_det;
107 	struct usb2phy_reg	idm_sink_en;
108 	struct usb2phy_reg	idp_sink_en;
109 	struct usb2phy_reg	idp_src_en;
110 	struct usb2phy_reg	rdm_pdwn_en;
111 	struct usb2phy_reg	vdm_src_en;
112 	struct usb2phy_reg	vdp_src_en;
113 	struct usb2phy_reg	opmode;
114 };
115 
116 /**
117  * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
118  * @phy_sus: phy suspend register.
119  * @bvalid_det_en: vbus valid rise detection enable register.
120  * @bvalid_det_st: vbus valid rise detection status register.
121  * @bvalid_det_clr: vbus valid rise detection clear register.
122  * @disfall_en: host disconnect fall edge detection enable.
123  * @disfall_st: host disconnect fall edge detection state.
124  * @disfall_clr: host disconnect fall edge detection clear.
125  * @disrise_en: host disconnect rise edge detection enable.
126  * @disrise_st: host disconnect rise edge detection state.
127  * @disrise_clr: host disconnect rise edge detection clear.
128  * @id_det_en: id detection enable register.
129  * @id_det_st: id detection state register.
130  * @id_det_clr: id detection clear register.
131  * @ls_det_en: linestate detection enable register.
132  * @ls_det_st: linestate detection state register.
133  * @ls_det_clr: linestate detection clear register.
134  * @utmi_avalid: utmi vbus avalid status register.
135  * @utmi_bvalid: utmi vbus bvalid status register.
136  * @utmi_id: utmi id state register.
137  * @utmi_ls: utmi linestate state register.
138  * @utmi_hstdet: utmi host disconnect register.
139  */
140 struct rockchip_usb2phy_port_cfg {
141 	struct usb2phy_reg	phy_sus;
142 	struct usb2phy_reg	bvalid_det_en;
143 	struct usb2phy_reg	bvalid_det_st;
144 	struct usb2phy_reg	bvalid_det_clr;
145 	struct usb2phy_reg      disfall_en;
146 	struct usb2phy_reg      disfall_st;
147 	struct usb2phy_reg      disfall_clr;
148 	struct usb2phy_reg      disrise_en;
149 	struct usb2phy_reg      disrise_st;
150 	struct usb2phy_reg      disrise_clr;
151 	struct usb2phy_reg	id_det_en;
152 	struct usb2phy_reg	id_det_st;
153 	struct usb2phy_reg	id_det_clr;
154 	struct usb2phy_reg	ls_det_en;
155 	struct usb2phy_reg	ls_det_st;
156 	struct usb2phy_reg	ls_det_clr;
157 	struct usb2phy_reg	utmi_avalid;
158 	struct usb2phy_reg	utmi_bvalid;
159 	struct usb2phy_reg	utmi_id;
160 	struct usb2phy_reg	utmi_ls;
161 	struct usb2phy_reg	utmi_hstdet;
162 };
163 
164 /**
165  * struct rockchip_usb2phy_cfg - usb-phy configuration.
166  * @reg: the address offset of grf for usb-phy config.
167  * @num_ports: specify how many ports that the phy has.
168  * @phy_tuning: phy default parameters tuning.
169  * @clkout_ctl: keep on/turn off output clk of phy.
170  * @port_cfgs: usb-phy port configurations.
171  * @chg_det: charger detection registers.
172  */
173 struct rockchip_usb2phy_cfg {
174 	unsigned int	reg;
175 	unsigned int	num_ports;
176 	int (*phy_tuning)(struct rockchip_usb2phy *rphy);
177 	struct usb2phy_reg	clkout_ctl;
178 	const struct rockchip_usb2phy_port_cfg	port_cfgs[USB2PHY_NUM_PORTS];
179 	const struct rockchip_chg_det_reg	chg_det;
180 };
181 
182 /**
183  * struct rockchip_usb2phy_port - usb-phy port data.
184  * @phy: generic phy.
185  * @port_id: flag for otg port or host port.
186  * @suspended: phy suspended flag.
187  * @vbus_attached: otg device vbus status.
188  * @host_disconnect: usb host disconnect status.
189  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
190  * @id_irq: IRQ number assigned for ID pin detection.
191  * @ls_irq: IRQ number assigned for linestate detection.
192  * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
193  *		 irqs to one irq in otg-port.
194  * @mutex: for register updating in sm_work.
195  * @chg_work: charge detect work.
196  * @otg_sm_work: OTG state machine work.
197  * @sm_work: HOST state machine work.
198  * @port_cfg: port register configuration, assigned by driver data.
199  * @event_nb: hold event notification callback.
200  * @state: define OTG enumeration states before device reset.
201  * @mode: the dr_mode of the controller.
202  */
203 struct rockchip_usb2phy_port {
204 	struct phy	*phy;
205 	unsigned int	port_id;
206 	bool		suspended;
207 	bool		vbus_attached;
208 	bool            host_disconnect;
209 	int		bvalid_irq;
210 	int		id_irq;
211 	int		ls_irq;
212 	int		otg_mux_irq;
213 	struct mutex	mutex;
214 	struct		delayed_work chg_work;
215 	struct		delayed_work otg_sm_work;
216 	struct		delayed_work sm_work;
217 	const struct	rockchip_usb2phy_port_cfg *port_cfg;
218 	struct notifier_block	event_nb;
219 	enum usb_otg_state	state;
220 	enum usb_dr_mode	mode;
221 };
222 
223 /**
224  * struct rockchip_usb2phy - usb2.0 phy driver data.
225  * @dev: pointer to device.
226  * @grf: General Register Files regmap.
227  * @usbgrf: USB General Register Files regmap.
228  * @clk: clock struct of phy input clk.
229  * @clk480m: clock struct of phy output clk.
230  * @clk480m_hw: clock struct of phy output clk management.
231  * @phy_reset: phy reset control.
232  * @chg_state: states involved in USB charger detection.
233  * @chg_type: USB charger types.
234  * @dcd_retries: The retry count used to track Data contact
235  *		 detection process.
236  * @edev: extcon device for notification registration
237  * @irq: muxed interrupt for single irq configuration
238  * @phy_cfg: phy register configuration, assigned by driver data.
239  * @ports: phy port instance.
240  */
241 struct rockchip_usb2phy {
242 	struct device	*dev;
243 	struct regmap	*grf;
244 	struct regmap	*usbgrf;
245 	struct clk	*clk;
246 	struct clk	*clk480m;
247 	struct clk_hw	clk480m_hw;
248 	struct reset_control	*phy_reset;
249 	enum usb_chg_state	chg_state;
250 	enum power_supply_type	chg_type;
251 	u8			dcd_retries;
252 	struct extcon_dev	*edev;
253 	int			irq;
254 	const struct rockchip_usb2phy_cfg	*phy_cfg;
255 	struct rockchip_usb2phy_port	ports[USB2PHY_NUM_PORTS];
256 };
257 
get_reg_base(struct rockchip_usb2phy * rphy)258 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
259 {
260 	return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
261 }
262 
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)263 static inline int property_enable(struct regmap *base,
264 				  const struct usb2phy_reg *reg, bool en)
265 {
266 	unsigned int val, mask, tmp;
267 
268 	tmp = en ? reg->enable : reg->disable;
269 	mask = GENMASK(reg->bitend, reg->bitstart);
270 	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
271 
272 	return regmap_write(base, reg->offset, val);
273 }
274 
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)275 static inline bool property_enabled(struct regmap *base,
276 				    const struct usb2phy_reg *reg)
277 {
278 	int ret;
279 	unsigned int tmp, orig;
280 	unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
281 
282 	ret = regmap_read(base, reg->offset, &orig);
283 	if (ret)
284 		return false;
285 
286 	tmp = (orig & mask) >> reg->bitstart;
287 	return tmp != reg->disable;
288 }
289 
rockchip_usb2phy_reset(struct rockchip_usb2phy * rphy)290 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
291 {
292 	int ret;
293 
294 	ret = reset_control_assert(rphy->phy_reset);
295 	if (ret)
296 		return ret;
297 
298 	udelay(10);
299 
300 	ret = reset_control_deassert(rphy->phy_reset);
301 	if (ret)
302 		return ret;
303 
304 	usleep_range(100, 200);
305 
306 	return 0;
307 }
308 
rockchip_usb2phy_clk480m_prepare(struct clk_hw * hw)309 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
310 {
311 	struct rockchip_usb2phy *rphy =
312 		container_of(hw, struct rockchip_usb2phy, clk480m_hw);
313 	struct regmap *base = get_reg_base(rphy);
314 	int ret;
315 
316 	/* turn on 480m clk output if it is off */
317 	if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
318 		ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
319 		if (ret)
320 			return ret;
321 
322 		/* waiting for the clk become stable */
323 		usleep_range(1200, 1300);
324 	}
325 
326 	return 0;
327 }
328 
rockchip_usb2phy_clk480m_unprepare(struct clk_hw * hw)329 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
330 {
331 	struct rockchip_usb2phy *rphy =
332 		container_of(hw, struct rockchip_usb2phy, clk480m_hw);
333 	struct regmap *base = get_reg_base(rphy);
334 
335 	/* turn off 480m clk output */
336 	property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
337 }
338 
rockchip_usb2phy_clk480m_prepared(struct clk_hw * hw)339 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
340 {
341 	struct rockchip_usb2phy *rphy =
342 		container_of(hw, struct rockchip_usb2phy, clk480m_hw);
343 	struct regmap *base = get_reg_base(rphy);
344 
345 	return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
346 }
347 
348 static unsigned long
rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)349 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
350 				     unsigned long parent_rate)
351 {
352 	return 480000000;
353 }
354 
355 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
356 	.prepare = rockchip_usb2phy_clk480m_prepare,
357 	.unprepare = rockchip_usb2phy_clk480m_unprepare,
358 	.is_prepared = rockchip_usb2phy_clk480m_prepared,
359 	.recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
360 };
361 
rockchip_usb2phy_clk480m_unregister(void * data)362 static void rockchip_usb2phy_clk480m_unregister(void *data)
363 {
364 	struct rockchip_usb2phy *rphy = data;
365 
366 	of_clk_del_provider(rphy->dev->of_node);
367 	clk_unregister(rphy->clk480m);
368 }
369 
370 static int
rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy * rphy)371 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
372 {
373 	struct device_node *node = rphy->dev->of_node;
374 	struct clk_init_data init;
375 	const char *clk_name;
376 	int ret = 0;
377 
378 	init.flags = 0;
379 	init.name = "clk_usbphy_480m";
380 	init.ops = &rockchip_usb2phy_clkout_ops;
381 
382 	/* optional override of the clockname */
383 	of_property_read_string(node, "clock-output-names", &init.name);
384 
385 	if (rphy->clk) {
386 		clk_name = __clk_get_name(rphy->clk);
387 		init.parent_names = &clk_name;
388 		init.num_parents = 1;
389 	} else {
390 		init.parent_names = NULL;
391 		init.num_parents = 0;
392 	}
393 
394 	rphy->clk480m_hw.init = &init;
395 
396 	/* register the clock */
397 	rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
398 	if (IS_ERR(rphy->clk480m)) {
399 		ret = PTR_ERR(rphy->clk480m);
400 		goto err_ret;
401 	}
402 
403 	ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
404 	if (ret < 0)
405 		goto err_clk_provider;
406 
407 	return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy);
408 
409 err_clk_provider:
410 	clk_unregister(rphy->clk480m);
411 err_ret:
412 	return ret;
413 }
414 
rockchip_usb2phy_extcon_register(struct rockchip_usb2phy * rphy)415 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
416 {
417 	int ret;
418 	struct device_node *node = rphy->dev->of_node;
419 	struct extcon_dev *edev;
420 
421 	if (of_property_read_bool(node, "extcon")) {
422 		edev = extcon_get_edev_by_phandle(rphy->dev, 0);
423 		if (IS_ERR(edev)) {
424 			if (PTR_ERR(edev) != -EPROBE_DEFER)
425 				dev_err(rphy->dev, "Invalid or missing extcon\n");
426 			return PTR_ERR(edev);
427 		}
428 	} else {
429 		/* Initialize extcon device */
430 		edev = devm_extcon_dev_allocate(rphy->dev,
431 						rockchip_usb2phy_extcon_cable);
432 
433 		if (IS_ERR(edev))
434 			return -ENOMEM;
435 
436 		ret = devm_extcon_dev_register(rphy->dev, edev);
437 		if (ret) {
438 			dev_err(rphy->dev, "failed to register extcon device\n");
439 			return ret;
440 		}
441 	}
442 
443 	rphy->edev = edev;
444 
445 	return 0;
446 }
447 
rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)448 static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy,
449 						 struct rockchip_usb2phy_port *rport,
450 						 bool en)
451 {
452 	int ret;
453 
454 	ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
455 	if (ret)
456 		return ret;
457 
458 	ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en);
459 	if (ret)
460 		return ret;
461 
462 	ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
463 	if (ret)
464 		return ret;
465 
466 	return property_enable(rphy->grf, &rport->port_cfg->disrise_en, en);
467 }
468 
rockchip_usb2phy_init(struct phy * phy)469 static int rockchip_usb2phy_init(struct phy *phy)
470 {
471 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
472 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
473 	int ret = 0;
474 
475 	mutex_lock(&rport->mutex);
476 
477 	if (rport->port_id == USB2PHY_PORT_OTG) {
478 		if (rport->mode != USB_DR_MODE_HOST &&
479 		    rport->mode != USB_DR_MODE_UNKNOWN) {
480 			/* clear bvalid status and enable bvalid detect irq */
481 			ret = property_enable(rphy->grf,
482 					      &rport->port_cfg->bvalid_det_clr,
483 					      true);
484 			if (ret)
485 				goto out;
486 
487 			ret = property_enable(rphy->grf,
488 					      &rport->port_cfg->bvalid_det_en,
489 					      true);
490 			if (ret)
491 				goto out;
492 
493 			/* clear id status and enable id detect irq */
494 			ret = property_enable(rphy->grf,
495 					      &rport->port_cfg->id_det_clr,
496 					      true);
497 			if (ret)
498 				goto out;
499 
500 			ret = property_enable(rphy->grf,
501 					      &rport->port_cfg->id_det_en,
502 					      true);
503 			if (ret)
504 				goto out;
505 
506 			schedule_delayed_work(&rport->otg_sm_work,
507 					      OTG_SCHEDULE_DELAY * 3);
508 		} else {
509 			/* If OTG works in host only mode, do nothing. */
510 			dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
511 		}
512 	} else if (rport->port_id == USB2PHY_PORT_HOST) {
513 		if (rport->port_cfg->disfall_en.offset) {
514 			rport->host_disconnect = true;
515 			ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true);
516 			if (ret) {
517 				dev_err(rphy->dev, "failed to enable disconnect irq\n");
518 				goto out;
519 			}
520 		}
521 
522 		/* clear linestate and enable linestate detect irq */
523 		ret = property_enable(rphy->grf,
524 				      &rport->port_cfg->ls_det_clr, true);
525 		if (ret)
526 			goto out;
527 
528 		ret = property_enable(rphy->grf,
529 				      &rport->port_cfg->ls_det_en, true);
530 		if (ret)
531 			goto out;
532 
533 		schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
534 	}
535 
536 out:
537 	mutex_unlock(&rport->mutex);
538 	return ret;
539 }
540 
rockchip_usb2phy_power_on(struct phy * phy)541 static int rockchip_usb2phy_power_on(struct phy *phy)
542 {
543 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
544 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
545 	struct regmap *base = get_reg_base(rphy);
546 	int ret;
547 
548 	dev_dbg(&rport->phy->dev, "port power on\n");
549 
550 	if (!rport->suspended)
551 		return 0;
552 
553 	ret = clk_prepare_enable(rphy->clk480m);
554 	if (ret)
555 		return ret;
556 
557 	ret = property_enable(base, &rport->port_cfg->phy_sus, false);
558 	if (ret) {
559 		clk_disable_unprepare(rphy->clk480m);
560 		return ret;
561 	}
562 
563 	/*
564 	 * For rk3588, it needs to reset phy when exit from
565 	 * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC,
566 	 * Bias, and PLL blocks are powered down) for lower
567 	 * power consumption. If you don't want to reset phy,
568 	 * please keep the common_on_n 1'b0 to set these blocks
569 	 * remain powered.
570 	 */
571 	ret = rockchip_usb2phy_reset(rphy);
572 	if (ret)
573 		return ret;
574 
575 	/* waiting for the utmi_clk to become stable */
576 	usleep_range(1500, 2000);
577 
578 	rport->suspended = false;
579 	return 0;
580 }
581 
rockchip_usb2phy_power_off(struct phy * phy)582 static int rockchip_usb2phy_power_off(struct phy *phy)
583 {
584 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
585 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
586 	struct regmap *base = get_reg_base(rphy);
587 	int ret;
588 
589 	dev_dbg(&rport->phy->dev, "port power off\n");
590 
591 	if (rport->suspended)
592 		return 0;
593 
594 	ret = property_enable(base, &rport->port_cfg->phy_sus, true);
595 	if (ret)
596 		return ret;
597 
598 	rport->suspended = true;
599 	clk_disable_unprepare(rphy->clk480m);
600 
601 	return 0;
602 }
603 
rockchip_usb2phy_exit(struct phy * phy)604 static int rockchip_usb2phy_exit(struct phy *phy)
605 {
606 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
607 
608 	if (rport->port_id == USB2PHY_PORT_OTG &&
609 	    rport->mode != USB_DR_MODE_HOST &&
610 	    rport->mode != USB_DR_MODE_UNKNOWN) {
611 		cancel_delayed_work_sync(&rport->otg_sm_work);
612 		cancel_delayed_work_sync(&rport->chg_work);
613 	} else if (rport->port_id == USB2PHY_PORT_HOST)
614 		cancel_delayed_work_sync(&rport->sm_work);
615 
616 	return 0;
617 }
618 
619 static const struct phy_ops rockchip_usb2phy_ops = {
620 	.init		= rockchip_usb2phy_init,
621 	.exit		= rockchip_usb2phy_exit,
622 	.power_on	= rockchip_usb2phy_power_on,
623 	.power_off	= rockchip_usb2phy_power_off,
624 	.owner		= THIS_MODULE,
625 };
626 
rockchip_usb2phy_otg_sm_work(struct work_struct * work)627 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
628 {
629 	struct rockchip_usb2phy_port *rport =
630 		container_of(work, struct rockchip_usb2phy_port,
631 			     otg_sm_work.work);
632 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
633 	static unsigned int cable;
634 	unsigned long delay;
635 	bool vbus_attach, sch_work, notify_charger;
636 
637 	vbus_attach = property_enabled(rphy->grf,
638 				       &rport->port_cfg->utmi_bvalid);
639 
640 	sch_work = false;
641 	notify_charger = false;
642 	delay = OTG_SCHEDULE_DELAY;
643 	dev_dbg(&rport->phy->dev, "%s otg sm work\n",
644 		usb_otg_state_string(rport->state));
645 
646 	switch (rport->state) {
647 	case OTG_STATE_UNDEFINED:
648 		rport->state = OTG_STATE_B_IDLE;
649 		if (!vbus_attach)
650 			rockchip_usb2phy_power_off(rport->phy);
651 		fallthrough;
652 	case OTG_STATE_B_IDLE:
653 		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
654 			dev_dbg(&rport->phy->dev, "usb otg host connect\n");
655 			rport->state = OTG_STATE_A_HOST;
656 			rockchip_usb2phy_power_on(rport->phy);
657 			return;
658 		} else if (vbus_attach) {
659 			dev_dbg(&rport->phy->dev, "vbus_attach\n");
660 			switch (rphy->chg_state) {
661 			case USB_CHG_STATE_UNDEFINED:
662 				schedule_delayed_work(&rport->chg_work, 0);
663 				return;
664 			case USB_CHG_STATE_DETECTED:
665 				switch (rphy->chg_type) {
666 				case POWER_SUPPLY_TYPE_USB:
667 					dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
668 					rockchip_usb2phy_power_on(rport->phy);
669 					rport->state = OTG_STATE_B_PERIPHERAL;
670 					notify_charger = true;
671 					sch_work = true;
672 					cable = EXTCON_CHG_USB_SDP;
673 					break;
674 				case POWER_SUPPLY_TYPE_USB_DCP:
675 					dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
676 					rockchip_usb2phy_power_off(rport->phy);
677 					notify_charger = true;
678 					sch_work = true;
679 					cable = EXTCON_CHG_USB_DCP;
680 					break;
681 				case POWER_SUPPLY_TYPE_USB_CDP:
682 					dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
683 					rockchip_usb2phy_power_on(rport->phy);
684 					rport->state = OTG_STATE_B_PERIPHERAL;
685 					notify_charger = true;
686 					sch_work = true;
687 					cable = EXTCON_CHG_USB_CDP;
688 					break;
689 				default:
690 					break;
691 				}
692 				break;
693 			default:
694 				break;
695 			}
696 		} else {
697 			notify_charger = true;
698 			rphy->chg_state = USB_CHG_STATE_UNDEFINED;
699 			rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
700 		}
701 
702 		if (rport->vbus_attached != vbus_attach) {
703 			rport->vbus_attached = vbus_attach;
704 
705 			if (notify_charger && rphy->edev) {
706 				extcon_set_state_sync(rphy->edev,
707 							cable, vbus_attach);
708 				if (cable == EXTCON_CHG_USB_SDP)
709 					extcon_set_state_sync(rphy->edev,
710 							      EXTCON_USB,
711 							      vbus_attach);
712 			}
713 		}
714 		break;
715 	case OTG_STATE_B_PERIPHERAL:
716 		if (!vbus_attach) {
717 			dev_dbg(&rport->phy->dev, "usb disconnect\n");
718 			rphy->chg_state = USB_CHG_STATE_UNDEFINED;
719 			rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
720 			rport->state = OTG_STATE_B_IDLE;
721 			delay = 0;
722 			rockchip_usb2phy_power_off(rport->phy);
723 		}
724 		sch_work = true;
725 		break;
726 	case OTG_STATE_A_HOST:
727 		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
728 			dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
729 			rport->state = OTG_STATE_B_IDLE;
730 			rockchip_usb2phy_power_off(rport->phy);
731 		}
732 		break;
733 	default:
734 		break;
735 	}
736 
737 	if (sch_work)
738 		schedule_delayed_work(&rport->otg_sm_work, delay);
739 }
740 
chg_to_string(enum power_supply_type chg_type)741 static const char *chg_to_string(enum power_supply_type chg_type)
742 {
743 	switch (chg_type) {
744 	case POWER_SUPPLY_TYPE_USB:
745 		return "USB_SDP_CHARGER";
746 	case POWER_SUPPLY_TYPE_USB_DCP:
747 		return "USB_DCP_CHARGER";
748 	case POWER_SUPPLY_TYPE_USB_CDP:
749 		return "USB_CDP_CHARGER";
750 	default:
751 		return "INVALID_CHARGER";
752 	}
753 }
754 
rockchip_chg_enable_dcd(struct rockchip_usb2phy * rphy,bool en)755 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
756 				    bool en)
757 {
758 	struct regmap *base = get_reg_base(rphy);
759 
760 	property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
761 	property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
762 }
763 
rockchip_chg_enable_primary_det(struct rockchip_usb2phy * rphy,bool en)764 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
765 					    bool en)
766 {
767 	struct regmap *base = get_reg_base(rphy);
768 
769 	property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
770 	property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
771 }
772 
rockchip_chg_enable_secondary_det(struct rockchip_usb2phy * rphy,bool en)773 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
774 					      bool en)
775 {
776 	struct regmap *base = get_reg_base(rphy);
777 
778 	property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
779 	property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
780 }
781 
782 #define CHG_DCD_POLL_TIME	(100 * HZ / 1000)
783 #define CHG_DCD_MAX_RETRIES	6
784 #define CHG_PRIMARY_DET_TIME	(40 * HZ / 1000)
785 #define CHG_SECONDARY_DET_TIME	(40 * HZ / 1000)
rockchip_chg_detect_work(struct work_struct * work)786 static void rockchip_chg_detect_work(struct work_struct *work)
787 {
788 	struct rockchip_usb2phy_port *rport =
789 		container_of(work, struct rockchip_usb2phy_port, chg_work.work);
790 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
791 	struct regmap *base = get_reg_base(rphy);
792 	bool is_dcd, tmout, vout;
793 	unsigned long delay;
794 
795 	dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
796 		rphy->chg_state);
797 	switch (rphy->chg_state) {
798 	case USB_CHG_STATE_UNDEFINED:
799 		if (!rport->suspended)
800 			rockchip_usb2phy_power_off(rport->phy);
801 		/* put the controller in non-driving mode */
802 		property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
803 		/* Start DCD processing stage 1 */
804 		rockchip_chg_enable_dcd(rphy, true);
805 		rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
806 		rphy->dcd_retries = 0;
807 		delay = CHG_DCD_POLL_TIME;
808 		break;
809 	case USB_CHG_STATE_WAIT_FOR_DCD:
810 		/* get data contact detection status */
811 		is_dcd = property_enabled(rphy->grf,
812 					  &rphy->phy_cfg->chg_det.dp_det);
813 		tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
814 		/* stage 2 */
815 		if (is_dcd || tmout) {
816 			/* stage 4 */
817 			/* Turn off DCD circuitry */
818 			rockchip_chg_enable_dcd(rphy, false);
819 			/* Voltage Source on DP, Probe on DM */
820 			rockchip_chg_enable_primary_det(rphy, true);
821 			delay = CHG_PRIMARY_DET_TIME;
822 			rphy->chg_state = USB_CHG_STATE_DCD_DONE;
823 		} else {
824 			/* stage 3 */
825 			delay = CHG_DCD_POLL_TIME;
826 		}
827 		break;
828 	case USB_CHG_STATE_DCD_DONE:
829 		vout = property_enabled(rphy->grf,
830 					&rphy->phy_cfg->chg_det.cp_det);
831 		rockchip_chg_enable_primary_det(rphy, false);
832 		if (vout) {
833 			/* Voltage Source on DM, Probe on DP  */
834 			rockchip_chg_enable_secondary_det(rphy, true);
835 			delay = CHG_SECONDARY_DET_TIME;
836 			rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
837 		} else {
838 			if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
839 				/* floating charger found */
840 				rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
841 				rphy->chg_state = USB_CHG_STATE_DETECTED;
842 				delay = 0;
843 			} else {
844 				rphy->chg_type = POWER_SUPPLY_TYPE_USB;
845 				rphy->chg_state = USB_CHG_STATE_DETECTED;
846 				delay = 0;
847 			}
848 		}
849 		break;
850 	case USB_CHG_STATE_PRIMARY_DONE:
851 		vout = property_enabled(rphy->grf,
852 					&rphy->phy_cfg->chg_det.dcp_det);
853 		/* Turn off voltage source */
854 		rockchip_chg_enable_secondary_det(rphy, false);
855 		if (vout)
856 			rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
857 		else
858 			rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
859 		fallthrough;
860 	case USB_CHG_STATE_SECONDARY_DONE:
861 		rphy->chg_state = USB_CHG_STATE_DETECTED;
862 		fallthrough;
863 	case USB_CHG_STATE_DETECTED:
864 		/* put the controller in normal mode */
865 		property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
866 		rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
867 		dev_dbg(&rport->phy->dev, "charger = %s\n",
868 			 chg_to_string(rphy->chg_type));
869 		return;
870 	default:
871 		return;
872 	}
873 
874 	schedule_delayed_work(&rport->chg_work, delay);
875 }
876 
877 /*
878  * The function manage host-phy port state and suspend/resume phy port
879  * to save power.
880  *
881  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
882  * devices is disconnect or not. Besides, we do not need care it is FS/LS
883  * disconnected or HS disconnected, actually, we just only need get the
884  * device is disconnected at last through rearm the delayed work,
885  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
886  *
887  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
888  * some clk related APIs, so do not invoke it from interrupt context directly.
889  */
rockchip_usb2phy_sm_work(struct work_struct * work)890 static void rockchip_usb2phy_sm_work(struct work_struct *work)
891 {
892 	struct rockchip_usb2phy_port *rport =
893 		container_of(work, struct rockchip_usb2phy_port, sm_work.work);
894 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
895 	unsigned int sh, ul, uhd, state;
896 	unsigned int ul_mask, uhd_mask;
897 	int ret;
898 
899 	mutex_lock(&rport->mutex);
900 
901 	ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
902 	if (ret < 0)
903 		goto next_schedule;
904 
905 	ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
906 			  rport->port_cfg->utmi_ls.bitstart);
907 
908 	if (rport->port_cfg->utmi_hstdet.offset) {
909 		ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
910 		if (ret < 0)
911 			goto next_schedule;
912 
913 		uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
914 				   rport->port_cfg->utmi_hstdet.bitstart);
915 
916 		sh = rport->port_cfg->utmi_hstdet.bitend -
917 		     rport->port_cfg->utmi_hstdet.bitstart + 1;
918 		/* stitch on utmi_ls and utmi_hstdet as phy state */
919 		state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
920 			(((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
921 	} else {
922 		state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 |
923 			rport->host_disconnect;
924 	}
925 
926 	switch (state) {
927 	case PHY_STATE_HS_ONLINE:
928 		dev_dbg(&rport->phy->dev, "HS online\n");
929 		break;
930 	case PHY_STATE_FS_LS_ONLINE:
931 		/*
932 		 * For FS/LS device, the online state share with connect state
933 		 * from utmi_ls and utmi_hstdet register, so we distinguish
934 		 * them via suspended flag.
935 		 *
936 		 * Plus, there are two cases, one is D- Line pull-up, and D+
937 		 * line pull-down, the state is 4; another is D+ line pull-up,
938 		 * and D- line pull-down, the state is 2.
939 		 */
940 		if (!rport->suspended) {
941 			/* D- line pull-up, D+ line pull-down */
942 			dev_dbg(&rport->phy->dev, "FS/LS online\n");
943 			break;
944 		}
945 		fallthrough;
946 	case PHY_STATE_CONNECT:
947 		if (rport->suspended) {
948 			dev_dbg(&rport->phy->dev, "Connected\n");
949 			rockchip_usb2phy_power_on(rport->phy);
950 			rport->suspended = false;
951 		} else {
952 			/* D+ line pull-up, D- line pull-down */
953 			dev_dbg(&rport->phy->dev, "FS/LS online\n");
954 		}
955 		break;
956 	case PHY_STATE_DISCONNECT:
957 		if (!rport->suspended) {
958 			dev_dbg(&rport->phy->dev, "Disconnected\n");
959 			rockchip_usb2phy_power_off(rport->phy);
960 			rport->suspended = true;
961 		}
962 
963 		/*
964 		 * activate the linestate detection to get the next device
965 		 * plug-in irq.
966 		 */
967 		property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
968 		property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
969 
970 		/*
971 		 * we don't need to rearm the delayed work when the phy port
972 		 * is suspended.
973 		 */
974 		mutex_unlock(&rport->mutex);
975 		return;
976 	default:
977 		dev_dbg(&rport->phy->dev, "unknown phy state\n");
978 		break;
979 	}
980 
981 next_schedule:
982 	mutex_unlock(&rport->mutex);
983 	schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
984 }
985 
rockchip_usb2phy_linestate_irq(int irq,void * data)986 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
987 {
988 	struct rockchip_usb2phy_port *rport = data;
989 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
990 
991 	if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
992 		return IRQ_NONE;
993 
994 	mutex_lock(&rport->mutex);
995 
996 	/* disable linestate detect irq and clear its status */
997 	property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
998 	property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
999 
1000 	mutex_unlock(&rport->mutex);
1001 
1002 	/*
1003 	 * In this case for host phy port, a new device is plugged in,
1004 	 * meanwhile, if the phy port is suspended, we need rearm the work to
1005 	 * resume it and mange its states; otherwise, we do nothing about that.
1006 	 */
1007 	if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
1008 		rockchip_usb2phy_sm_work(&rport->sm_work.work);
1009 
1010 	return IRQ_HANDLED;
1011 }
1012 
rockchip_usb2phy_bvalid_irq(int irq,void * data)1013 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
1014 {
1015 	struct rockchip_usb2phy_port *rport = data;
1016 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1017 
1018 	if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
1019 		return IRQ_NONE;
1020 
1021 	/* clear bvalid detect irq pending status */
1022 	property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
1023 
1024 	rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1025 
1026 	return IRQ_HANDLED;
1027 }
1028 
rockchip_usb2phy_id_irq(int irq,void * data)1029 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1030 {
1031 	struct rockchip_usb2phy_port *rport = data;
1032 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1033 	bool id;
1034 
1035 	if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st))
1036 		return IRQ_NONE;
1037 
1038 	/* clear id detect irq pending status */
1039 	property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true);
1040 
1041 	id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1042 	extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
1043 
1044 	return IRQ_HANDLED;
1045 }
1046 
rockchip_usb2phy_otg_mux_irq(int irq,void * data)1047 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
1048 {
1049 	irqreturn_t ret = IRQ_NONE;
1050 
1051 	ret |= rockchip_usb2phy_bvalid_irq(irq, data);
1052 	ret |= rockchip_usb2phy_id_irq(irq, data);
1053 
1054 	return ret;
1055 }
1056 
rockchip_usb2phy_host_disc_irq(int irq,void * data)1057 static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data)
1058 {
1059 	struct rockchip_usb2phy_port *rport = data;
1060 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1061 
1062 	if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) &&
1063 	    !property_enabled(rphy->grf, &rport->port_cfg->disrise_st))
1064 		return IRQ_NONE;
1065 
1066 	mutex_lock(&rport->mutex);
1067 
1068 	/* clear disconnect fall or rise detect irq pending status */
1069 	if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) {
1070 		property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
1071 		rport->host_disconnect = false;
1072 	} else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
1073 		property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
1074 		rport->host_disconnect = true;
1075 	}
1076 
1077 	mutex_unlock(&rport->mutex);
1078 
1079 	return IRQ_HANDLED;
1080 }
1081 
rockchip_usb2phy_irq(int irq,void * data)1082 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
1083 {
1084 	struct rockchip_usb2phy *rphy = data;
1085 	struct rockchip_usb2phy_port *rport;
1086 	irqreturn_t ret = IRQ_NONE;
1087 	unsigned int index;
1088 
1089 	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1090 		rport = &rphy->ports[index];
1091 		if (!rport->phy)
1092 			continue;
1093 
1094 		if (rport->port_id == USB2PHY_PORT_HOST &&
1095 		    rport->port_cfg->disfall_en.offset)
1096 			ret |= rockchip_usb2phy_host_disc_irq(irq, rport);
1097 
1098 		switch (rport->port_id) {
1099 		case USB2PHY_PORT_OTG:
1100 			if (rport->mode != USB_DR_MODE_HOST &&
1101 			    rport->mode != USB_DR_MODE_UNKNOWN)
1102 				ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
1103 			break;
1104 		case USB2PHY_PORT_HOST:
1105 			ret |= rockchip_usb2phy_linestate_irq(irq, rport);
1106 			break;
1107 		}
1108 	}
1109 
1110 	return ret;
1111 }
1112 
rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1113 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
1114 					  struct rockchip_usb2phy_port *rport,
1115 					  struct device_node *child_np)
1116 {
1117 	int ret;
1118 
1119 	/*
1120 	 * If the usb2 phy used combined irq for otg and host port,
1121 	 * don't need to init otg and host port irq separately.
1122 	 */
1123 	if (rphy->irq > 0)
1124 		return 0;
1125 
1126 	switch (rport->port_id) {
1127 	case USB2PHY_PORT_HOST:
1128 		rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1129 		if (rport->ls_irq < 0) {
1130 			dev_err(rphy->dev, "no linestate irq provided\n");
1131 			return rport->ls_irq;
1132 		}
1133 
1134 		ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1135 						rockchip_usb2phy_linestate_irq,
1136 						IRQF_ONESHOT,
1137 						"rockchip_usb2phy", rport);
1138 		if (ret) {
1139 			dev_err(rphy->dev, "failed to request linestate irq handle\n");
1140 			return ret;
1141 		}
1142 		break;
1143 	case USB2PHY_PORT_OTG:
1144 		/*
1145 		 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1146 		 * interrupts muxed together, so probe the otg-mux interrupt first,
1147 		 * if not found, then look for the regular interrupts one by one.
1148 		 */
1149 		rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1150 		if (rport->otg_mux_irq > 0) {
1151 			ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1152 							NULL,
1153 							rockchip_usb2phy_otg_mux_irq,
1154 							IRQF_ONESHOT,
1155 							"rockchip_usb2phy_otg",
1156 							rport);
1157 			if (ret) {
1158 				dev_err(rphy->dev,
1159 					"failed to request otg-mux irq handle\n");
1160 				return ret;
1161 			}
1162 		} else {
1163 			rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1164 			if (rport->bvalid_irq < 0) {
1165 				dev_err(rphy->dev, "no vbus valid irq provided\n");
1166 				ret = rport->bvalid_irq;
1167 				return ret;
1168 			}
1169 
1170 			ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1171 							NULL,
1172 							rockchip_usb2phy_bvalid_irq,
1173 							IRQF_ONESHOT,
1174 							"rockchip_usb2phy_bvalid",
1175 							rport);
1176 			if (ret) {
1177 				dev_err(rphy->dev,
1178 					"failed to request otg-bvalid irq handle\n");
1179 				return ret;
1180 			}
1181 
1182 			rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1183 			if (rport->id_irq < 0) {
1184 				dev_err(rphy->dev, "no otg-id irq provided\n");
1185 				ret = rport->id_irq;
1186 				return ret;
1187 			}
1188 
1189 			ret = devm_request_threaded_irq(rphy->dev, rport->id_irq,
1190 							NULL,
1191 							rockchip_usb2phy_id_irq,
1192 							IRQF_ONESHOT,
1193 							"rockchip_usb2phy_id",
1194 							rport);
1195 			if (ret) {
1196 				dev_err(rphy->dev,
1197 					"failed to request otg-id irq handle\n");
1198 				return ret;
1199 			}
1200 		}
1201 		break;
1202 	default:
1203 		return -EINVAL;
1204 	}
1205 
1206 	return 0;
1207 }
1208 
rockchip_usb2phy_host_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1209 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1210 					   struct rockchip_usb2phy_port *rport,
1211 					   struct device_node *child_np)
1212 {
1213 	int ret;
1214 
1215 	rport->port_id = USB2PHY_PORT_HOST;
1216 	rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1217 	rport->suspended = true;
1218 
1219 	mutex_init(&rport->mutex);
1220 	INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1221 
1222 	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1223 	if (ret) {
1224 		dev_err(rphy->dev, "failed to setup host irq\n");
1225 		return ret;
1226 	}
1227 
1228 	return 0;
1229 }
1230 
rockchip_otg_event(struct notifier_block * nb,unsigned long event,void * ptr)1231 static int rockchip_otg_event(struct notifier_block *nb,
1232 			      unsigned long event, void *ptr)
1233 {
1234 	struct rockchip_usb2phy_port *rport =
1235 		container_of(nb, struct rockchip_usb2phy_port, event_nb);
1236 
1237 	schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1238 
1239 	return NOTIFY_DONE;
1240 }
1241 
rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1242 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1243 					  struct rockchip_usb2phy_port *rport,
1244 					  struct device_node *child_np)
1245 {
1246 	int ret, id;
1247 
1248 	rport->port_id = USB2PHY_PORT_OTG;
1249 	rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1250 	rport->state = OTG_STATE_UNDEFINED;
1251 
1252 	/*
1253 	 * set suspended flag to true, but actually don't
1254 	 * put phy in suspend mode, it aims to enable usb
1255 	 * phy and clock in power_on() called by usb controller
1256 	 * driver during probe.
1257 	 */
1258 	rport->suspended = true;
1259 	rport->vbus_attached = false;
1260 
1261 	mutex_init(&rport->mutex);
1262 
1263 	rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1264 	if (rport->mode == USB_DR_MODE_HOST ||
1265 	    rport->mode == USB_DR_MODE_UNKNOWN) {
1266 		ret = 0;
1267 		goto out;
1268 	}
1269 
1270 	INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1271 	INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1272 
1273 	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1274 	if (ret) {
1275 		dev_err(rphy->dev, "failed to init irq for host port\n");
1276 		goto out;
1277 	}
1278 
1279 	if (!IS_ERR(rphy->edev)) {
1280 		rport->event_nb.notifier_call = rockchip_otg_event;
1281 
1282 		ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1283 					EXTCON_USB_HOST, &rport->event_nb);
1284 		if (ret) {
1285 			dev_err(rphy->dev, "register USB HOST notifier failed\n");
1286 			goto out;
1287 		}
1288 
1289 		if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
1290 			/* do initial sync of usb state */
1291 			id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1292 			extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
1293 		}
1294 	}
1295 
1296 out:
1297 	return ret;
1298 }
1299 
rockchip_usb2phy_probe(struct platform_device * pdev)1300 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1301 {
1302 	struct device *dev = &pdev->dev;
1303 	struct device_node *np = dev->of_node;
1304 	struct device_node *child_np;
1305 	struct phy_provider *provider;
1306 	struct rockchip_usb2phy *rphy;
1307 	const struct rockchip_usb2phy_cfg *phy_cfgs;
1308 	unsigned int reg;
1309 	int index, ret;
1310 
1311 	rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1312 	if (!rphy)
1313 		return -ENOMEM;
1314 
1315 	if (!dev->parent || !dev->parent->of_node) {
1316 		rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
1317 		if (IS_ERR(rphy->grf)) {
1318 			dev_err(dev, "failed to locate usbgrf\n");
1319 			return PTR_ERR(rphy->grf);
1320 		}
1321 	}
1322 
1323 	else {
1324 		rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1325 		if (IS_ERR(rphy->grf))
1326 			return PTR_ERR(rphy->grf);
1327 	}
1328 
1329 	if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1330 		rphy->usbgrf =
1331 			syscon_regmap_lookup_by_phandle(dev->of_node,
1332 							"rockchip,usbgrf");
1333 		if (IS_ERR(rphy->usbgrf))
1334 			return PTR_ERR(rphy->usbgrf);
1335 	} else {
1336 		rphy->usbgrf = NULL;
1337 	}
1338 
1339 	if (of_property_read_u32_index(np, "reg", 0, &reg)) {
1340 		dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1341 			np);
1342 		return -EINVAL;
1343 	}
1344 
1345 	/* support address_cells=2 */
1346 	if (of_property_count_u32_elems(np, "reg") > 2 && reg == 0) {
1347 		if (of_property_read_u32_index(np, "reg", 1, &reg)) {
1348 			dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1349 				np);
1350 			return -EINVAL;
1351 		}
1352 	}
1353 
1354 	rphy->dev = dev;
1355 	phy_cfgs = device_get_match_data(dev);
1356 	rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1357 	rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1358 	rphy->irq = platform_get_irq_optional(pdev, 0);
1359 	platform_set_drvdata(pdev, rphy);
1360 
1361 	if (!phy_cfgs)
1362 		return dev_err_probe(dev, -EINVAL, "phy configs are not assigned!\n");
1363 
1364 	ret = rockchip_usb2phy_extcon_register(rphy);
1365 	if (ret)
1366 		return ret;
1367 
1368 	/* find out a proper config which can be matched with dt. */
1369 	index = 0;
1370 	do {
1371 		if (phy_cfgs[index].reg == reg) {
1372 			rphy->phy_cfg = &phy_cfgs[index];
1373 			break;
1374 		}
1375 
1376 		++index;
1377 	} while (phy_cfgs[index].reg);
1378 
1379 	if (!rphy->phy_cfg) {
1380 		dev_err(dev, "could not find phy config for reg=0x%08x\n", reg);
1381 		return -EINVAL;
1382 	}
1383 
1384 	rphy->phy_reset = devm_reset_control_get_optional(dev, "phy");
1385 	if (IS_ERR(rphy->phy_reset))
1386 		return PTR_ERR(rphy->phy_reset);
1387 
1388 	rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk");
1389 	if (IS_ERR(rphy->clk)) {
1390 		return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk),
1391 				     "failed to get phyclk\n");
1392 	}
1393 
1394 	ret = rockchip_usb2phy_clk480m_register(rphy);
1395 	if (ret) {
1396 		dev_err(dev, "failed to register 480m output clock\n");
1397 		return ret;
1398 	}
1399 
1400 	if (rphy->phy_cfg->phy_tuning) {
1401 		ret = rphy->phy_cfg->phy_tuning(rphy);
1402 		if (ret)
1403 			return ret;
1404 	}
1405 
1406 	index = 0;
1407 	for_each_available_child_of_node(np, child_np) {
1408 		struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1409 		struct phy *phy;
1410 
1411 		/* This driver aims to support both otg-port and host-port */
1412 		if (!of_node_name_eq(child_np, "host-port") &&
1413 		    !of_node_name_eq(child_np, "otg-port"))
1414 			goto next_child;
1415 
1416 		phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1417 		if (IS_ERR(phy)) {
1418 			dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
1419 			ret = PTR_ERR(phy);
1420 			goto put_child;
1421 		}
1422 
1423 		rport->phy = phy;
1424 		phy_set_drvdata(rport->phy, rport);
1425 
1426 		/* initialize otg/host port separately */
1427 		if (of_node_name_eq(child_np, "host-port")) {
1428 			ret = rockchip_usb2phy_host_port_init(rphy, rport,
1429 							      child_np);
1430 			if (ret)
1431 				goto put_child;
1432 		} else {
1433 			ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1434 							     child_np);
1435 			if (ret)
1436 				goto put_child;
1437 		}
1438 
1439 next_child:
1440 		/* to prevent out of boundary */
1441 		if (++index >= rphy->phy_cfg->num_ports) {
1442 			of_node_put(child_np);
1443 			break;
1444 		}
1445 	}
1446 
1447 	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1448 
1449 	if (rphy->irq > 0) {
1450 		ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
1451 						rockchip_usb2phy_irq,
1452 						IRQF_ONESHOT,
1453 						"rockchip_usb2phy",
1454 						rphy);
1455 		if (ret) {
1456 			dev_err(rphy->dev,
1457 				"failed to request usb2phy irq handle\n");
1458 			goto put_child;
1459 		}
1460 	}
1461 
1462 	return PTR_ERR_OR_ZERO(provider);
1463 
1464 put_child:
1465 	of_node_put(child_np);
1466 	return ret;
1467 }
1468 
rk3588_usb2phy_tuning(struct rockchip_usb2phy * rphy)1469 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1470 {
1471 	int ret;
1472 	bool usb3otg = false;
1473 	/*
1474 	 * utmi_termselect = 1'b1 (en FS terminations)
1475 	 * utmi_xcvrselect = 2'b01 (FS transceiver)
1476 	 */
1477 	int suspend_cfg = 0x14;
1478 
1479 	if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) {
1480 		/* USB2 config for USB3_0 and USB3_1 */
1481 		suspend_cfg |= 0x01; /* utmi_opmode = 2'b01 (no-driving) */
1482 		usb3otg = true;
1483 	} else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) {
1484 		/* USB2 config for USB2_0 and USB2_1 */
1485 		suspend_cfg |= 0x00; /* utmi_opmode = 2'b00 (normal) */
1486 	} else {
1487 		return -EINVAL;
1488 	}
1489 
1490 	/* Deassert SIDDQ to power on analog block */
1491 	ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000);
1492 	if (ret)
1493 		return ret;
1494 
1495 	/* Do reset after exit IDDQ mode */
1496 	ret = rockchip_usb2phy_reset(rphy);
1497 	if (ret)
1498 		return ret;
1499 
1500 	/* suspend configuration */
1501 	ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg);
1502 
1503 	/* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
1504 	ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900);
1505 
1506 	/* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
1507 	ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010);
1508 
1509 	if (!usb3otg)
1510 		return ret;
1511 
1512 	/* Pullup iddig pin for USB3_0 OTG mode */
1513 	ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003);
1514 
1515 	return ret;
1516 }
1517 
1518 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1519 	{
1520 		.reg = 0x760,
1521 		.num_ports	= 2,
1522 		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
1523 		.port_cfgs	= {
1524 			[USB2PHY_PORT_OTG] = {
1525 				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
1526 				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
1527 				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
1528 				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
1529 				.id_det_en	= { 0x0680, 6, 5, 0, 3 },
1530 				.id_det_st	= { 0x0690, 6, 5, 0, 3 },
1531 				.id_det_clr	= { 0x06a0, 6, 5, 0, 3 },
1532 				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
1533 				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
1534 				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
1535 				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
1536 				.utmi_id	= { 0x0480, 1, 1, 0, 1 },
1537 				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
1538 			},
1539 			[USB2PHY_PORT_HOST] = {
1540 				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
1541 				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
1542 				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
1543 				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
1544 			}
1545 		},
1546 		.chg_det = {
1547 			.opmode		= { 0x0760, 3, 0, 5, 1 },
1548 			.cp_det		= { 0x0884, 4, 4, 0, 1 },
1549 			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
1550 			.dp_det		= { 0x0884, 5, 5, 0, 1 },
1551 			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
1552 			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
1553 			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
1554 			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
1555 			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
1556 			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
1557 		},
1558 	},
1559 	{
1560 		.reg = 0x800,
1561 		.num_ports	= 2,
1562 		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
1563 		.port_cfgs	= {
1564 			[USB2PHY_PORT_OTG] = {
1565 				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
1566 				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
1567 				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
1568 				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
1569 			},
1570 			[USB2PHY_PORT_HOST] = {
1571 				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
1572 				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
1573 				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
1574 				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
1575 			}
1576 		},
1577 	},
1578 	{ /* sentinel */ }
1579 };
1580 
1581 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1582 	{
1583 		.reg = 0x100,
1584 		.num_ports	= 2,
1585 		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
1586 		.port_cfgs	= {
1587 			[USB2PHY_PORT_OTG] = {
1588 				.phy_sus	= { 0x0100, 8, 0, 0, 0x1d1 },
1589 				.bvalid_det_en	= { 0x3020, 3, 2, 0, 3 },
1590 				.bvalid_det_st	= { 0x3024, 3, 2, 0, 3 },
1591 				.bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
1592 				.id_det_en	= { 0x3020, 5, 4, 0, 3 },
1593 				.id_det_st	= { 0x3024, 5, 4, 0, 3 },
1594 				.id_det_clr	= { 0x3028, 5, 4, 0, 3 },
1595 				.ls_det_en	= { 0x3020, 0, 0, 0, 1 },
1596 				.ls_det_st	= { 0x3024, 0, 0, 0, 1 },
1597 				.ls_det_clr	= { 0x3028, 0, 0, 0, 1 },
1598 				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
1599 				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
1600 				.utmi_id	= { 0x0120, 6, 6, 0, 1 },
1601 				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
1602 			},
1603 			[USB2PHY_PORT_HOST] = {
1604 				.phy_sus	= { 0x0104, 8, 0, 0, 0x1d1 },
1605 				.ls_det_en	= { 0x3020, 1, 1, 0, 1 },
1606 				.ls_det_st	= { 0x3024, 1, 1, 0, 1 },
1607 				.ls_det_clr	= { 0x3028, 1, 1, 0, 1 },
1608 				.utmi_ls	= { 0x0120, 17, 16, 0, 1 },
1609 				.utmi_hstdet	= { 0x0120, 19, 19, 0, 1 }
1610 			}
1611 		},
1612 		.chg_det = {
1613 			.opmode		= { 0x0100, 3, 0, 5, 1 },
1614 			.cp_det		= { 0x0120, 24, 24, 0, 1 },
1615 			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
1616 			.dp_det		= { 0x0120, 25, 25, 0, 1 },
1617 			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
1618 			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
1619 			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
1620 			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
1621 			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
1622 			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
1623 		},
1624 	},
1625 	{ /* sentinel */ }
1626 };
1627 
1628 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1629 	{
1630 		.reg = 0x100,
1631 		.num_ports	= 2,
1632 		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
1633 		.port_cfgs	= {
1634 			[USB2PHY_PORT_OTG] = {
1635 				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
1636 				.bvalid_det_en	= { 0x0110, 3, 2, 0, 3 },
1637 				.bvalid_det_st	= { 0x0114, 3, 2, 0, 3 },
1638 				.bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
1639 				.id_det_en	= { 0x0110, 5, 4, 0, 3 },
1640 				.id_det_st	= { 0x0114, 5, 4, 0, 3 },
1641 				.id_det_clr	= { 0x0118, 5, 4, 0, 3 },
1642 				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
1643 				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
1644 				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
1645 				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
1646 				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
1647 				.utmi_id	= { 0x0120, 6, 6, 0, 1 },
1648 				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
1649 			},
1650 			[USB2PHY_PORT_HOST] = {
1651 				.phy_sus	= { 0x104, 15, 0, 0, 0x1d1 },
1652 				.ls_det_en	= { 0x110, 1, 1, 0, 1 },
1653 				.ls_det_st	= { 0x114, 1, 1, 0, 1 },
1654 				.ls_det_clr	= { 0x118, 1, 1, 0, 1 },
1655 				.utmi_ls	= { 0x120, 17, 16, 0, 1 },
1656 				.utmi_hstdet	= { 0x120, 19, 19, 0, 1 }
1657 			}
1658 		},
1659 		.chg_det = {
1660 			.opmode		= { 0x0100, 3, 0, 5, 1 },
1661 			.cp_det		= { 0x0120, 24, 24, 0, 1 },
1662 			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
1663 			.dp_det		= { 0x0120, 25, 25, 0, 1 },
1664 			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
1665 			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
1666 			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
1667 			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
1668 			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
1669 			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
1670 		},
1671 	},
1672 	{ /* sentinel */ }
1673 };
1674 
1675 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1676 	{
1677 		.reg = 0x700,
1678 		.num_ports	= 2,
1679 		.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
1680 		.port_cfgs	= {
1681 			[USB2PHY_PORT_HOST] = {
1682 				.phy_sus	= { 0x0728, 15, 0, 0, 0x1d1 },
1683 				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
1684 				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
1685 				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 },
1686 				.utmi_ls	= { 0x049c, 14, 13, 0, 1 },
1687 				.utmi_hstdet	= { 0x049c, 12, 12, 0, 1 }
1688 			}
1689 		},
1690 	},
1691 	{ /* sentinel */ }
1692 };
1693 
1694 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1695 	{
1696 		.reg		= 0xe450,
1697 		.num_ports	= 2,
1698 		.clkout_ctl	= { 0xe450, 4, 4, 1, 0 },
1699 		.port_cfgs	= {
1700 			[USB2PHY_PORT_OTG] = {
1701 				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
1702 				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
1703 				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
1704 				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
1705 				.id_det_en	= { 0xe3c0, 5, 4, 0, 3 },
1706 				.id_det_st	= { 0xe3e0, 5, 4, 0, 3 },
1707 				.id_det_clr	= { 0xe3d0, 5, 4, 0, 3 },
1708 				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
1709 				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
1710 				.utmi_id	= { 0xe2ac, 8, 8, 0, 1 },
1711 			},
1712 			[USB2PHY_PORT_HOST] = {
1713 				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
1714 				.ls_det_en	= { 0xe3c0, 6, 6, 0, 1 },
1715 				.ls_det_st	= { 0xe3e0, 6, 6, 0, 1 },
1716 				.ls_det_clr	= { 0xe3d0, 6, 6, 0, 1 },
1717 				.utmi_ls	= { 0xe2ac, 22, 21, 0, 1 },
1718 				.utmi_hstdet	= { 0xe2ac, 23, 23, 0, 1 }
1719 			}
1720 		},
1721 		.chg_det = {
1722 			.opmode		= { 0xe454, 3, 0, 5, 1 },
1723 			.cp_det		= { 0xe2ac, 2, 2, 0, 1 },
1724 			.dcp_det	= { 0xe2ac, 1, 1, 0, 1 },
1725 			.dp_det		= { 0xe2ac, 0, 0, 0, 1 },
1726 			.idm_sink_en	= { 0xe450, 8, 8, 0, 1 },
1727 			.idp_sink_en	= { 0xe450, 7, 7, 0, 1 },
1728 			.idp_src_en	= { 0xe450, 9, 9, 0, 1 },
1729 			.rdm_pdwn_en	= { 0xe450, 10, 10, 0, 1 },
1730 			.vdm_src_en	= { 0xe450, 12, 12, 0, 1 },
1731 			.vdp_src_en	= { 0xe450, 11, 11, 0, 1 },
1732 		},
1733 	},
1734 	{
1735 		.reg		= 0xe460,
1736 		.num_ports	= 2,
1737 		.clkout_ctl	= { 0xe460, 4, 4, 1, 0 },
1738 		.port_cfgs	= {
1739 			[USB2PHY_PORT_OTG] = {
1740 				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
1741 				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1742 				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1743 				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1744 				.id_det_en	= { 0xe3c0, 10, 9, 0, 3 },
1745 				.id_det_st	= { 0xe3e0, 10, 9, 0, 3 },
1746 				.id_det_clr	= { 0xe3d0, 10, 9, 0, 3 },
1747 				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
1748 				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1749 				.utmi_id	= { 0xe2ac, 11, 11, 0, 1 },
1750 			},
1751 			[USB2PHY_PORT_HOST] = {
1752 				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
1753 				.ls_det_en	= { 0xe3c0, 11, 11, 0, 1 },
1754 				.ls_det_st	= { 0xe3e0, 11, 11, 0, 1 },
1755 				.ls_det_clr	= { 0xe3d0, 11, 11, 0, 1 },
1756 				.utmi_ls	= { 0xe2ac, 26, 25, 0, 1 },
1757 				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
1758 			}
1759 		},
1760 	},
1761 	{ /* sentinel */ }
1762 };
1763 
1764 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1765 	{
1766 		.reg = 0xfe8a0000,
1767 		.num_ports	= 2,
1768 		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
1769 		.port_cfgs	= {
1770 			[USB2PHY_PORT_OTG] = {
1771 				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },
1772 				.bvalid_det_en	= { 0x0080, 3, 2, 0, 3 },
1773 				.bvalid_det_st	= { 0x0084, 3, 2, 0, 3 },
1774 				.bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
1775 				.id_det_en	= { 0x0080, 5, 4, 0, 3 },
1776 				.id_det_st	= { 0x0084, 5, 4, 0, 3 },
1777 				.id_det_clr	= { 0x0088, 5, 4, 0, 3 },
1778 				.utmi_avalid	= { 0x00c0, 10, 10, 0, 1 },
1779 				.utmi_bvalid	= { 0x00c0, 9, 9, 0, 1 },
1780 				.utmi_id	= { 0x00c0, 6, 6, 0, 1 },
1781 			},
1782 			[USB2PHY_PORT_HOST] = {
1783 				/* Select suspend control from controller */
1784 				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d2 },
1785 				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
1786 				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
1787 				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
1788 				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
1789 				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
1790 			}
1791 		},
1792 		.chg_det = {
1793 			.opmode		= { 0x0000, 3, 0, 5, 1 },
1794 			.cp_det		= { 0x00c0, 24, 24, 0, 1 },
1795 			.dcp_det	= { 0x00c0, 23, 23, 0, 1 },
1796 			.dp_det		= { 0x00c0, 25, 25, 0, 1 },
1797 			.idm_sink_en	= { 0x0008, 8, 8, 0, 1 },
1798 			.idp_sink_en	= { 0x0008, 7, 7, 0, 1 },
1799 			.idp_src_en	= { 0x0008, 9, 9, 0, 1 },
1800 			.rdm_pdwn_en	= { 0x0008, 10, 10, 0, 1 },
1801 			.vdm_src_en	= { 0x0008, 12, 12, 0, 1 },
1802 			.vdp_src_en	= { 0x0008, 11, 11, 0, 1 },
1803 		},
1804 	},
1805 	{
1806 		.reg = 0xfe8b0000,
1807 		.num_ports	= 2,
1808 		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
1809 		.port_cfgs	= {
1810 			[USB2PHY_PORT_OTG] = {
1811 				.phy_sus	= { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1812 				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
1813 				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
1814 				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
1815 				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
1816 				.utmi_hstdet	= { 0x00c0, 7, 7, 0, 1 }
1817 			},
1818 			[USB2PHY_PORT_HOST] = {
1819 				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1820 				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
1821 				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
1822 				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
1823 				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
1824 				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
1825 			}
1826 		},
1827 	},
1828 	{ /* sentinel */ }
1829 };
1830 
1831 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
1832 	{
1833 		.reg = 0x0000,
1834 		.num_ports	= 1,
1835 		.phy_tuning	= rk3588_usb2phy_tuning,
1836 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
1837 		.port_cfgs	= {
1838 			[USB2PHY_PORT_OTG] = {
1839 				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
1840 				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
1841 				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
1842 				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
1843 				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
1844 				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
1845 				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
1846 				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
1847 				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
1848 				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
1849 				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
1850 				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
1851 				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
1852 				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
1853 				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
1854 				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
1855 			}
1856 		},
1857 		.chg_det = {
1858 			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
1859 			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
1860 			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
1861 			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
1862 			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
1863 			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
1864 			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
1865 			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
1866 			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
1867 		},
1868 	},
1869 	{
1870 		.reg = 0x4000,
1871 		.num_ports	= 1,
1872 		.phy_tuning	= rk3588_usb2phy_tuning,
1873 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
1874 		.port_cfgs	= {
1875 			[USB2PHY_PORT_OTG] = {
1876 				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
1877 				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
1878 				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
1879 				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
1880 				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
1881 				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
1882 				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
1883 				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
1884 				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
1885 				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
1886 				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
1887 				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
1888 				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
1889 				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
1890 				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
1891 				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
1892 			}
1893 		},
1894 		.chg_det = {
1895 			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
1896 			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
1897 			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
1898 			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
1899 			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
1900 			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
1901 			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
1902 			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
1903 			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
1904 		},
1905 	},
1906 	{
1907 		.reg = 0x8000,
1908 		.num_ports	= 1,
1909 		.phy_tuning	= rk3588_usb2phy_tuning,
1910 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
1911 		.port_cfgs	= {
1912 			[USB2PHY_PORT_HOST] = {
1913 				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
1914 				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
1915 				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
1916 				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
1917 				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
1918 				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
1919 				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
1920 				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
1921 				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
1922 				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
1923 				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
1924 			}
1925 		},
1926 	},
1927 	{
1928 		.reg = 0xc000,
1929 		.num_ports	= 1,
1930 		.phy_tuning	= rk3588_usb2phy_tuning,
1931 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
1932 		.port_cfgs	= {
1933 			[USB2PHY_PORT_HOST] = {
1934 				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
1935 				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
1936 				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
1937 				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
1938 				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
1939 				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
1940 				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
1941 				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
1942 				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
1943 				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
1944 				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
1945 			}
1946 		},
1947 	},
1948 	{ /* sentinel */ }
1949 };
1950 
1951 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1952 	{
1953 		.reg = 0x100,
1954 		.num_ports	= 2,
1955 		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
1956 		.port_cfgs	= {
1957 			[USB2PHY_PORT_OTG] = {
1958 				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
1959 				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
1960 				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
1961 				.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1962 				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
1963 				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
1964 				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
1965 				.utmi_bvalid	= { 0x0804, 10, 10, 0, 1 },
1966 				.utmi_ls	= { 0x0804, 13, 12, 0, 1 },
1967 			},
1968 			[USB2PHY_PORT_HOST] = {
1969 				.phy_sus	= { 0x0104, 15, 0, 0, 0x1d1 },
1970 				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
1971 				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
1972 				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 },
1973 				.utmi_ls	= { 0x0804, 9, 8, 0, 1 },
1974 				.utmi_hstdet	= { 0x0804, 7, 7, 0, 1 }
1975 			}
1976 		},
1977 		.chg_det = {
1978 			.opmode		= { 0x0100, 3, 0, 5, 1 },
1979 			.cp_det		= { 0x0804, 1, 1, 0, 1 },
1980 			.dcp_det	= { 0x0804, 0, 0, 0, 1 },
1981 			.dp_det		= { 0x0804, 2, 2, 0, 1 },
1982 			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
1983 			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
1984 			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
1985 			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
1986 			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
1987 			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
1988 		},
1989 	},
1990 	{ /* sentinel */ }
1991 };
1992 
1993 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1994 	{ .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
1995 	{ .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1996 	{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
1997 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1998 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1999 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
2000 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
2001 	{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
2002 	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
2003 	{}
2004 };
2005 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
2006 
2007 static struct platform_driver rockchip_usb2phy_driver = {
2008 	.probe		= rockchip_usb2phy_probe,
2009 	.driver		= {
2010 		.name	= "rockchip-usb2phy",
2011 		.of_match_table = rockchip_usb2phy_dt_match,
2012 	},
2013 };
2014 module_platform_driver(rockchip_usb2phy_driver);
2015 
2016 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
2017 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
2018 MODULE_LICENSE("GPL v2");
2019