1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * spi driver for rockchip
4 *
5 * (C) Copyright 2015 Google, Inc
6 *
7 * (C) Copyright 2008-2013 Rockchip Electronics
8 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <dt-structs.h>
15 #include <errno.h>
16 #include <spi.h>
17 #include <linux/errno.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/periph.h>
21 #include <dm/pinctrl.h>
22 #include "rk_spi.h"
23
24 /* Change to 1 to output registers at the start of each transaction */
25 #define DEBUG_RK_SPI 0
26
27 struct rockchip_spi_platdata {
28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
29 struct dtd_rockchip_rk3288_spi of_plat;
30 #endif
31 s32 frequency; /* Default clock frequency, -1 for none */
32 fdt_addr_t base;
33 uint deactivate_delay_us; /* Delay to wait after deactivate */
34 uint activate_delay_us; /* Delay to wait after activate */
35 };
36
37 struct rockchip_spi_priv {
38 struct rockchip_spi *regs;
39 struct clk clk;
40 unsigned int max_freq;
41 unsigned int mode;
42 ulong last_transaction_us; /* Time of last transaction end */
43 u8 bits_per_word; /* max 16 bits per word */
44 u8 n_bytes;
45 unsigned int speed_hz;
46 unsigned int last_speed_hz;
47 unsigned int tmode;
48 uint input_rate;
49 };
50
51 #define SPI_FIFO_DEPTH 32
52
rkspi_dump_regs(struct rockchip_spi * regs)53 static void rkspi_dump_regs(struct rockchip_spi *regs)
54 {
55 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
56 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
57 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
58 debug("ser: \t\t0x%08x\n", readl(®s->ser));
59 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
60 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
61 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
62 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
63 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
64 debug("sr: \t\t0x%08x\n", readl(®s->sr));
65 debug("imr: \t\t0x%08x\n", readl(®s->imr));
66 debug("isr: \t\t0x%08x\n", readl(®s->isr));
67 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
68 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
69 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
70 }
71
rkspi_enable_chip(struct rockchip_spi * regs,bool enable)72 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
73 {
74 writel(enable ? 1 : 0, ®s->enr);
75 }
76
rkspi_set_clk(struct rockchip_spi_priv * priv,uint speed)77 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
78 {
79 /*
80 * We should try not to exceed the speed requested by the caller:
81 * when selecting a divider, we need to make sure we round up.
82 */
83 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
84
85 /* The baudrate register (BAUDR) is defined as a 32bit register where
86 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
87 * 16bits with 'Fsclk_out' defined as follows:
88 *
89 * Fsclk_out = Fspi_clk/ SCKDV
90 * Where SCKDV is any even value between 2 and 65534.
91 */
92 if (clk_div > 0xfffe) {
93 clk_div = 0xfffe;
94 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
95 __func__, speed, priv->input_rate / clk_div);
96 }
97
98 /* Round up to the next even 16bit number */
99 clk_div = (clk_div + 1) & 0xfffe;
100
101 debug("spi speed %u, div %u\n", speed, clk_div);
102
103 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
104 priv->last_speed_hz = speed;
105 }
106
rkspi_wait_till_not_busy(struct rockchip_spi * regs)107 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
108 {
109 unsigned long start;
110
111 start = get_timer(0);
112 while (readl(®s->sr) & SR_BUSY) {
113 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
114 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
115 return -ETIMEDOUT;
116 }
117 }
118
119 return 0;
120 }
121
spi_cs_activate(struct udevice * dev,uint cs)122 static void spi_cs_activate(struct udevice *dev, uint cs)
123 {
124 struct udevice *bus = dev->parent;
125 struct rockchip_spi_platdata *plat = bus->platdata;
126 struct rockchip_spi_priv *priv = dev_get_priv(bus);
127 struct rockchip_spi *regs = priv->regs;
128
129 /* If it's too soon to do another transaction, wait */
130 if (plat->deactivate_delay_us && priv->last_transaction_us) {
131 ulong delay_us; /* The delay completed so far */
132 delay_us = timer_get_us() - priv->last_transaction_us;
133 if (delay_us < plat->deactivate_delay_us)
134 udelay(plat->deactivate_delay_us - delay_us);
135 }
136
137 debug("activate cs%u\n", cs);
138 writel(1 << cs, ®s->ser);
139 if (plat->activate_delay_us)
140 udelay(plat->activate_delay_us);
141 }
142
spi_cs_deactivate(struct udevice * dev,uint cs)143 static void spi_cs_deactivate(struct udevice *dev, uint cs)
144 {
145 struct udevice *bus = dev->parent;
146 struct rockchip_spi_platdata *plat = bus->platdata;
147 struct rockchip_spi_priv *priv = dev_get_priv(bus);
148 struct rockchip_spi *regs = priv->regs;
149
150 debug("deactivate cs%u\n", cs);
151 writel(0, ®s->ser);
152
153 /* Remember time of this transaction so we can honour the bus delay */
154 if (plat->deactivate_delay_us)
155 priv->last_transaction_us = timer_get_us();
156 }
157
158 #if CONFIG_IS_ENABLED(OF_PLATDATA)
conv_of_platdata(struct udevice * dev)159 static int conv_of_platdata(struct udevice *dev)
160 {
161 struct rockchip_spi_platdata *plat = dev->platdata;
162 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
163 struct rockchip_spi_priv *priv = dev_get_priv(dev);
164 int ret;
165
166 plat->base = dtplat->reg[0];
167 plat->frequency = 20000000;
168 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
169 if (ret < 0)
170 return ret;
171 dev->req_seq = 0;
172
173 return 0;
174 }
175 #endif
176
rockchip_spi_ofdata_to_platdata(struct udevice * bus)177 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
178 {
179 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
180 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
181 struct rockchip_spi_priv *priv = dev_get_priv(bus);
182 int ret;
183
184 plat->base = dev_read_addr(bus);
185
186 ret = clk_get_by_index(bus, 0, &priv->clk);
187 if (ret < 0) {
188 debug("%s: Could not get clock for %s: %d\n", __func__,
189 bus->name, ret);
190 return ret;
191 }
192
193 plat->frequency =
194 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
195 plat->deactivate_delay_us =
196 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
197 plat->activate_delay_us =
198 dev_read_u32_default(bus, "spi-activate-delay", 0);
199
200 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
201 __func__, (uint)plat->base, plat->frequency,
202 plat->deactivate_delay_us);
203 #endif
204
205 return 0;
206 }
207
rockchip_spi_calc_modclk(ulong max_freq)208 static int rockchip_spi_calc_modclk(ulong max_freq)
209 {
210 /*
211 * While this is not strictly correct for the RK3368, as the
212 * GPLL will be 576MHz, things will still work, as the
213 * clk_set_rate(...) implementation in our clock-driver will
214 * chose the next closest rate not exceeding what we request
215 * based on the output of this function.
216 */
217
218 unsigned div;
219 const unsigned long gpll_hz = 594000000UL;
220
221 /*
222 * We need to find an input clock that provides at least twice
223 * the maximum frequency and can be generated from the assumed
224 * speed of GPLL (594MHz) using an integer divider.
225 *
226 * To give us more achievable bitrates at higher speeds (these
227 * are generated by dividing by an even 16-bit integer from
228 * this frequency), we try to have an input frequency of at
229 * least 4x our max_freq.
230 */
231
232 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
233 return gpll_hz / div;
234 }
235
rockchip_spi_probe(struct udevice * bus)236 static int rockchip_spi_probe(struct udevice *bus)
237 {
238 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
239 struct rockchip_spi_priv *priv = dev_get_priv(bus);
240 int ret;
241
242 debug("%s: probe\n", __func__);
243 #if CONFIG_IS_ENABLED(OF_PLATDATA)
244 ret = conv_of_platdata(bus);
245 if (ret)
246 return ret;
247 #endif
248 priv->regs = (struct rockchip_spi *)plat->base;
249
250 priv->last_transaction_us = timer_get_us();
251 priv->max_freq = plat->frequency;
252
253 /* Clamp the value from the DTS against any hardware limits */
254 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
255 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
256
257 /* Find a module-input clock that fits with the max_freq setting */
258 ret = clk_set_rate(&priv->clk,
259 rockchip_spi_calc_modclk(priv->max_freq));
260 if (ret < 0) {
261 debug("%s: Failed to set clock: %d\n", __func__, ret);
262 return ret;
263 }
264 priv->input_rate = ret;
265 debug("%s: rate = %u\n", __func__, priv->input_rate);
266 priv->bits_per_word = 8;
267 priv->tmode = TMOD_TR; /* Tx & Rx */
268
269 return 0;
270 }
271
rockchip_spi_claim_bus(struct udevice * dev)272 static int rockchip_spi_claim_bus(struct udevice *dev)
273 {
274 struct udevice *bus = dev->parent;
275 struct rockchip_spi_priv *priv = dev_get_priv(bus);
276 struct rockchip_spi *regs = priv->regs;
277 u8 spi_dfs, spi_tf;
278 uint ctrlr0;
279
280 /* Disable the SPI hardware */
281 rkspi_enable_chip(regs, 0);
282
283 switch (priv->bits_per_word) {
284 case 8:
285 priv->n_bytes = 1;
286 spi_dfs = DFS_8BIT;
287 spi_tf = HALF_WORD_OFF;
288 break;
289 case 16:
290 priv->n_bytes = 2;
291 spi_dfs = DFS_16BIT;
292 spi_tf = HALF_WORD_ON;
293 break;
294 default:
295 debug("%s: unsupported bits: %dbits\n", __func__,
296 priv->bits_per_word);
297 return -EPROTONOSUPPORT;
298 }
299
300 if (priv->speed_hz != priv->last_speed_hz)
301 rkspi_set_clk(priv, priv->speed_hz);
302
303 /* Operation Mode */
304 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
305
306 /* Data Frame Size */
307 ctrlr0 |= spi_dfs << DFS_SHIFT;
308
309 /* set SPI mode 0..3 */
310 if (priv->mode & SPI_CPOL)
311 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
312 if (priv->mode & SPI_CPHA)
313 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
314
315 /* Chip Select Mode */
316 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
317
318 /* SSN to Sclk_out delay */
319 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
320
321 /* Serial Endian Mode */
322 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
323
324 /* First Bit Mode */
325 ctrlr0 |= FBM_MSB << FBM_SHIFT;
326
327 /* Byte and Halfword Transform */
328 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
329
330 /* Rxd Sample Delay */
331 ctrlr0 |= 0 << RXDSD_SHIFT;
332
333 /* Frame Format */
334 ctrlr0 |= FRF_SPI << FRF_SHIFT;
335
336 /* Tx and Rx mode */
337 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
338
339 writel(ctrlr0, ®s->ctrlr0);
340
341 return 0;
342 }
343
rockchip_spi_release_bus(struct udevice * dev)344 static int rockchip_spi_release_bus(struct udevice *dev)
345 {
346 struct udevice *bus = dev->parent;
347 struct rockchip_spi_priv *priv = dev_get_priv(bus);
348
349 rkspi_enable_chip(priv->regs, false);
350
351 return 0;
352 }
353
rockchip_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)354 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
355 const void *dout, void *din, unsigned long flags)
356 {
357 struct udevice *bus = dev->parent;
358 struct rockchip_spi_priv *priv = dev_get_priv(bus);
359 struct rockchip_spi *regs = priv->regs;
360 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
361 int len = bitlen >> 3;
362 const u8 *out = dout;
363 u8 *in = din;
364 int toread, towrite;
365 int ret;
366
367 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
368 len, flags);
369 if (DEBUG_RK_SPI)
370 rkspi_dump_regs(regs);
371
372 /* Assert CS before transfer */
373 if (flags & SPI_XFER_BEGIN)
374 spi_cs_activate(dev, slave_plat->cs);
375
376 while (len > 0) {
377 int todo = min(len, 0xffff);
378
379 rkspi_enable_chip(regs, false);
380 writel(todo - 1, ®s->ctrlr1);
381 rkspi_enable_chip(regs, true);
382
383 toread = todo;
384 towrite = todo;
385 while (toread || towrite) {
386 u32 status = readl(®s->sr);
387
388 if (towrite && !(status & SR_TF_FULL)) {
389 writel(out ? *out++ : 0, regs->txdr);
390 towrite--;
391 }
392 if (toread && !(status & SR_RF_EMPT)) {
393 u32 byte = readl(regs->rxdr);
394
395 if (in)
396 *in++ = byte;
397 toread--;
398 }
399 }
400 ret = rkspi_wait_till_not_busy(regs);
401 if (ret)
402 break;
403 len -= todo;
404 }
405
406 /* Deassert CS after transfer */
407 if (flags & SPI_XFER_END)
408 spi_cs_deactivate(dev, slave_plat->cs);
409
410 rkspi_enable_chip(regs, false);
411
412 return ret;
413 }
414
rockchip_spi_set_speed(struct udevice * bus,uint speed)415 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
416 {
417 struct rockchip_spi_priv *priv = dev_get_priv(bus);
418
419 /* Clamp to the maximum frequency specified in the DTS */
420 if (speed > priv->max_freq)
421 speed = priv->max_freq;
422
423 priv->speed_hz = speed;
424
425 return 0;
426 }
427
rockchip_spi_set_mode(struct udevice * bus,uint mode)428 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
429 {
430 struct rockchip_spi_priv *priv = dev_get_priv(bus);
431
432 priv->mode = mode;
433
434 return 0;
435 }
436
437 static const struct dm_spi_ops rockchip_spi_ops = {
438 .claim_bus = rockchip_spi_claim_bus,
439 .release_bus = rockchip_spi_release_bus,
440 .xfer = rockchip_spi_xfer,
441 .set_speed = rockchip_spi_set_speed,
442 .set_mode = rockchip_spi_set_mode,
443 /*
444 * cs_info is not needed, since we require all chip selects to be
445 * in the device tree explicitly
446 */
447 };
448
449 static const struct udevice_id rockchip_spi_ids[] = {
450 { .compatible = "rockchip,rk3288-spi" },
451 { .compatible = "rockchip,rk3368-spi" },
452 { .compatible = "rockchip,rk3399-spi" },
453 { }
454 };
455
456 U_BOOT_DRIVER(rockchip_spi) = {
457 #if CONFIG_IS_ENABLED(OF_PLATDATA)
458 .name = "rockchip_rk3288_spi",
459 #else
460 .name = "rockchip_spi",
461 #endif
462 .id = UCLASS_SPI,
463 .of_match = rockchip_spi_ids,
464 .ops = &rockchip_spi_ops,
465 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
466 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
467 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
468 .probe = rockchip_spi_probe,
469 };
470