1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/pinctrl.h>
9 #include <regmap.h>
10 #include <syscon.h>
11 #include <fdtdec.h>
12
13 #include "pinctrl-rockchip.h"
14
15 #define MAX_ROCKCHIP_PINS_ENTRIES 30
16 #define MAX_ROCKCHIP_GPIO_PER_BANK 32
17 #define RK_FUNC_GPIO 0
18
rockchip_verify_config(struct udevice * dev,u32 bank,u32 pin)19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
20 {
21 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
23
24 if (bank >= ctrl->nr_banks) {
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
26 return -EINVAL;
27 }
28
29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
30 debug("pin conf pin %d >= %d\n", pin,
31 MAX_ROCKCHIP_GPIO_PER_BANK);
32 return -EINVAL;
33 }
34
35 return 0;
36 }
37
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)38 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
39 int *reg, u8 *bit, int *mask)
40 {
41 struct rockchip_pinctrl_priv *priv = bank->priv;
42 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
43 struct rockchip_mux_recalced_data *data;
44 int i;
45
46 for (i = 0; i < ctrl->niomux_recalced; i++) {
47 data = &ctrl->iomux_recalced[i];
48 if (data->num == bank->bank_num &&
49 data->pin == pin)
50 break;
51 }
52
53 if (i >= ctrl->niomux_recalced)
54 return;
55
56 *reg = data->reg;
57 *mask = data->mask;
58 *bit = data->bit;
59 }
60
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * reg,u32 * value)61 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
62 int mux, u32 *reg, u32 *value)
63 {
64 struct rockchip_pinctrl_priv *priv = bank->priv;
65 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
66 struct rockchip_mux_route_data *data;
67 int i;
68
69 for (i = 0; i < ctrl->niomux_routes; i++) {
70 data = &ctrl->iomux_routes[i];
71 if (data->bank_num == bank->bank_num &&
72 data->pin == pin && data->func == mux)
73 break;
74 }
75
76 if (i >= ctrl->niomux_routes)
77 return false;
78
79 *reg = data->route_offset;
80 *value = data->route_val;
81
82 return true;
83 }
84
rockchip_get_mux_data(int mux_type,int pin,u8 * bit,int * mask)85 static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
86 {
87 int offset = 0;
88
89 if (mux_type & IOMUX_WIDTH_4BIT) {
90 if ((pin % 8) >= 4)
91 offset = 0x4;
92 *bit = (pin % 4) * 4;
93 *mask = 0xf;
94 } else if (mux_type & IOMUX_WIDTH_3BIT) {
95 /*
96 * pin0 ~ pin4 are at first register, and
97 * pin5 ~ pin7 are at second register.
98 */
99 if ((pin % 8) >= 5)
100 offset = 0x4;
101 *bit = (pin % 8 % 5) * 3;
102 *mask = 0x7;
103 } else {
104 *bit = (pin % 8) * 2;
105 *mask = 0x3;
106 }
107
108 return offset;
109 }
110
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)111 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
112 {
113 struct rockchip_pinctrl_priv *priv = bank->priv;
114 int iomux_num = (pin / 8);
115 struct regmap *regmap;
116 unsigned int val;
117 int reg, ret, mask, mux_type;
118 u8 bit;
119
120 if (iomux_num > 3)
121 return -EINVAL;
122
123 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
124 debug("pin %d is unrouted\n", pin);
125 return -EINVAL;
126 }
127
128 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
129 return RK_FUNC_GPIO;
130
131 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
132 ? priv->regmap_pmu : priv->regmap_base;
133
134 /* get basic quadrupel of mux registers and the correct reg inside */
135 mux_type = bank->iomux[iomux_num].type;
136 reg = bank->iomux[iomux_num].offset;
137 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
138
139 if (bank->recalced_mask & BIT(pin))
140 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
141
142 ret = regmap_read(regmap, reg, &val);
143 if (ret)
144 return ret;
145
146 return ((val >> bit) & mask);
147 }
148
rockchip_pinctrl_get_gpio_mux(struct udevice * dev,int banknum,int index)149 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
150 int index)
151 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
152 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
153
154 return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
155 }
156
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)157 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
158 int pin, int mux)
159 {
160 int iomux_num = (pin / 8);
161
162 if (iomux_num > 3)
163 return -EINVAL;
164
165 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
166 debug("pin %d is unrouted\n", pin);
167 return -EINVAL;
168 }
169
170 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
171 if (mux != IOMUX_GPIO_ONLY) {
172 debug("pin %d only supports a gpio mux\n", pin);
173 return -ENOTSUPP;
174 }
175 }
176
177 return 0;
178 }
179
180 /*
181 * Set a new mux function for a pin.
182 *
183 * The register is divided into the upper and lower 16 bit. When changing
184 * a value, the previous register value is not read and changed. Instead
185 * it seems the changed bits are marked in the upper 16 bit, while the
186 * changed value gets set in the same offset in the lower 16 bit.
187 * All pin settings seem to be 2 bit wide in both the upper and lower
188 * parts.
189 * @bank: pin bank to change
190 * @pin: pin to change
191 * @mux: new mux function to set
192 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)193 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
194 {
195 struct rockchip_pinctrl_priv *priv = bank->priv;
196 int iomux_num = (pin / 8);
197 struct regmap *regmap;
198 int reg, ret, mask, mux_type;
199 u8 bit;
200 u32 data, route_reg, route_val;
201
202 ret = rockchip_verify_mux(bank, pin, mux);
203 if (ret < 0)
204 return ret;
205
206 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
207 return 0;
208
209 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
210
211 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
212 ? priv->regmap_pmu : priv->regmap_base;
213
214 /* get basic quadrupel of mux registers and the correct reg inside */
215 mux_type = bank->iomux[iomux_num].type;
216 reg = bank->iomux[iomux_num].offset;
217 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
218
219 if (bank->recalced_mask & BIT(pin))
220 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
221
222 if (bank->route_mask & BIT(pin)) {
223 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
224 &route_val)) {
225 ret = regmap_write(regmap, route_reg, route_val);
226 if (ret)
227 return ret;
228 }
229 }
230
231 if (mux_type & IOMUX_WRITABLE_32BIT) {
232 regmap_read(regmap, reg, &data);
233 data &= ~(mask << bit);
234 } else {
235 data = (mask << (bit + 16));
236 }
237
238 data |= (mux & mask) << bit;
239 ret = regmap_write(regmap, reg, data);
240
241 return ret;
242 }
243
244 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
245 { 2, 4, 8, 12, -1, -1, -1, -1 },
246 { 3, 6, 9, 12, -1, -1, -1, -1 },
247 { 5, 10, 15, 20, -1, -1, -1, -1 },
248 { 4, 6, 8, 10, 12, 14, 16, 18 },
249 { 4, 7, 10, 13, 16, 19, 22, 26 }
250 };
251
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)252 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
253 int pin_num, int strength)
254 {
255 struct rockchip_pinctrl_priv *priv = bank->priv;
256 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
257 struct regmap *regmap;
258 int reg, ret, i;
259 u32 data, rmask_bits, temp;
260 u8 bit;
261 /* Where need to clean the special mask for rockchip_perpin_drv_list */
262 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
263
264 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
265 pin_num, strength);
266
267 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
268
269 ret = -EINVAL;
270 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
271 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
272 ret = i;
273 break;
274 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
275 ret = rockchip_perpin_drv_list[drv_type][i];
276 break;
277 }
278 }
279
280 if (ret < 0) {
281 debug("unsupported driver strength %d\n", strength);
282 return ret;
283 }
284
285 switch (drv_type) {
286 case DRV_TYPE_IO_1V8_3V0_AUTO:
287 case DRV_TYPE_IO_3V3_ONLY:
288 rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
289 switch (bit) {
290 case 0 ... 12:
291 /* regular case, nothing to do */
292 break;
293 case 15:
294 /*
295 * drive-strength offset is special, as it is spread
296 * over 2 registers, the bit data[15] contains bit 0
297 * of the value while temp[1:0] contains bits 2 and 1
298 */
299 data = (ret & 0x1) << 15;
300 temp = (ret >> 0x1) & 0x3;
301
302 data |= BIT(31);
303 ret = regmap_write(regmap, reg, data);
304 if (ret)
305 return ret;
306
307 temp |= (0x3 << 16);
308 reg += 0x4;
309 ret = regmap_write(regmap, reg, temp);
310
311 return ret;
312 case 18 ... 21:
313 /* setting fully enclosed in the second register */
314 reg += 4;
315 bit -= 16;
316 break;
317 default:
318 debug("unsupported bit: %d for pinctrl drive type: %d\n",
319 bit, drv_type);
320 return -EINVAL;
321 }
322 break;
323 case DRV_TYPE_IO_DEFAULT:
324 case DRV_TYPE_IO_1V8_OR_3V0:
325 case DRV_TYPE_IO_1V8_ONLY:
326 rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
327 break;
328 default:
329 debug("unsupported pinctrl drive type: %d\n",
330 drv_type);
331 return -EINVAL;
332 }
333
334 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
335 regmap_read(regmap, reg, &data);
336 data &= ~(((1 << rmask_bits) - 1) << bit);
337 } else {
338 /* enable the write to the equivalent lower bits */
339 data = ((1 << rmask_bits) - 1) << (bit + 16);
340 }
341
342 data |= (ret << bit);
343 ret = regmap_write(regmap, reg, data);
344 return ret;
345 }
346
347 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
348 {
349 PIN_CONFIG_BIAS_DISABLE,
350 PIN_CONFIG_BIAS_PULL_UP,
351 PIN_CONFIG_BIAS_PULL_DOWN,
352 PIN_CONFIG_BIAS_BUS_HOLD
353 },
354 {
355 PIN_CONFIG_BIAS_DISABLE,
356 PIN_CONFIG_BIAS_PULL_DOWN,
357 PIN_CONFIG_BIAS_DISABLE,
358 PIN_CONFIG_BIAS_PULL_UP
359 },
360 };
361
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)362 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
363 int pin_num, int pull)
364 {
365 struct rockchip_pinctrl_priv *priv = bank->priv;
366 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
367 struct regmap *regmap;
368 int reg, ret, i, pull_type;
369 u8 bit;
370 u32 data;
371
372 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
373 pin_num, pull);
374
375 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
376
377 switch (ctrl->type) {
378 case RK3036:
379 case RK3128:
380 data = BIT(bit + 16);
381 if (pull == PIN_CONFIG_BIAS_DISABLE)
382 data |= BIT(bit);
383 ret = regmap_write(regmap, reg, data);
384 break;
385 case RV1108:
386 case RK3188:
387 case RK3288:
388 case RK3368:
389 case RK3399:
390 /*
391 * Where need to clean the special mask for
392 * rockchip_pull_list.
393 */
394 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
395 ret = -EINVAL;
396 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
397 i++) {
398 if (rockchip_pull_list[pull_type][i] == pull) {
399 ret = i;
400 break;
401 }
402 }
403
404 if (ret < 0) {
405 debug("unsupported pull setting %d\n", pull);
406 return ret;
407 }
408
409 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
410 regmap_read(regmap, reg, &data);
411 data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
412 } else {
413 /* enable the write to the equivalent lower bits */
414 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
415 }
416
417 data |= (ret << bit);
418 ret = regmap_write(regmap, reg, data);
419 break;
420 default:
421 debug("unsupported pinctrl type\n");
422 return -EINVAL;
423 }
424
425 return ret;
426 }
427
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)428 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
429 int pin_num, int enable)
430 {
431 struct rockchip_pinctrl_priv *priv = bank->priv;
432 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
433 struct regmap *regmap;
434 int reg, ret;
435 u8 bit;
436 u32 data;
437
438 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
439 pin_num, enable);
440
441 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
442 if (ret)
443 return ret;
444
445 /* enable the write to the equivalent lower bits */
446 data = BIT(bit + 16) | (enable << bit);
447
448 return regmap_write(regmap, reg, data);
449 }
450
451 /*
452 * Pinconf_ops handling
453 */
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,unsigned int pull)454 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
455 unsigned int pull)
456 {
457 switch (ctrl->type) {
458 case RK3036:
459 case RK3128:
460 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
461 pull == PIN_CONFIG_BIAS_DISABLE);
462 case RV1108:
463 case RK3188:
464 case RK3288:
465 case RK3368:
466 case RK3399:
467 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
468 }
469
470 return false;
471 }
472
473 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct rockchip_pin_bank * bank,u32 pin,u32 param,u32 arg)474 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
475 u32 pin, u32 param, u32 arg)
476 {
477 struct rockchip_pinctrl_priv *priv = bank->priv;
478 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
479 int rc;
480
481 switch (param) {
482 case PIN_CONFIG_BIAS_DISABLE:
483 rc = rockchip_set_pull(bank, pin, param);
484 if (rc)
485 return rc;
486 break;
487
488 case PIN_CONFIG_BIAS_PULL_UP:
489 case PIN_CONFIG_BIAS_PULL_DOWN:
490 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
491 case PIN_CONFIG_BIAS_BUS_HOLD:
492 if (!rockchip_pinconf_pull_valid(ctrl, param))
493 return -ENOTSUPP;
494
495 if (!arg)
496 return -EINVAL;
497
498 rc = rockchip_set_pull(bank, pin, param);
499 if (rc)
500 return rc;
501 break;
502
503 case PIN_CONFIG_DRIVE_STRENGTH:
504 if (!ctrl->drv_calc_reg)
505 return -ENOTSUPP;
506
507 rc = rockchip_set_drive_perpin(bank, pin, arg);
508 if (rc < 0)
509 return rc;
510 break;
511
512 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
513 if (!ctrl->schmitt_calc_reg)
514 return -ENOTSUPP;
515
516 rc = rockchip_set_schmitt(bank, pin, arg);
517 if (rc < 0)
518 return rc;
519 break;
520
521 default:
522 break;
523 }
524
525 return 0;
526 }
527
528 static const struct pinconf_param rockchip_conf_params[] = {
529 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
530 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
531 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
532 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
533 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
534 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
535 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
536 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
537 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
538 };
539
rockchip_pinconf_prop_name_to_param(const char * property,u32 * default_value)540 static int rockchip_pinconf_prop_name_to_param(const char *property,
541 u32 *default_value)
542 {
543 const struct pinconf_param *p, *end;
544
545 p = rockchip_conf_params;
546 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
547
548 /* See if this pctldev supports this parameter */
549 for (; p < end; p++) {
550 if (!strcmp(property, p->property)) {
551 *default_value = p->default_value;
552 return p->param;
553 }
554 }
555
556 *default_value = 0;
557 return -EPERM;
558 }
559
rockchip_pinctrl_set_state(struct udevice * dev,struct udevice * config)560 static int rockchip_pinctrl_set_state(struct udevice *dev,
561 struct udevice *config)
562 {
563 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
564 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
565 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
566 u32 bank, pin, mux, conf, arg, default_val;
567 int ret, count, i;
568 const char *prop_name;
569 const void *value;
570 int prop_len, param;
571 const u32 *data;
572 ofnode node;
573 #ifdef CONFIG_OF_LIVE
574 const struct device_node *np;
575 struct property *pp;
576 #else
577 int property_offset, pcfg_node;
578 const void *blob = gd->fdt_blob;
579 #endif
580 data = dev_read_prop(config, "rockchip,pins", &count);
581 if (count < 0) {
582 debug("%s: bad array size %d\n", __func__, count);
583 return -EINVAL;
584 }
585
586 count /= sizeof(u32);
587 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
588 debug("%s: unsupported pins array count %d\n",
589 __func__, count);
590 return -EINVAL;
591 }
592
593 for (i = 0; i < count; i++)
594 cells[i] = fdt32_to_cpu(data[i]);
595
596 for (i = 0; i < (count >> 2); i++) {
597 bank = cells[4 * i + 0];
598 pin = cells[4 * i + 1];
599 mux = cells[4 * i + 2];
600 conf = cells[4 * i + 3];
601
602 ret = rockchip_verify_config(dev, bank, pin);
603 if (ret)
604 return ret;
605
606 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
607 if (ret)
608 return ret;
609
610 node = ofnode_get_by_phandle(conf);
611 if (!ofnode_valid(node))
612 return -ENODEV;
613 #ifdef CONFIG_OF_LIVE
614 np = ofnode_to_np(node);
615 for (pp = np->properties; pp; pp = pp->next) {
616 prop_name = pp->name;
617 prop_len = pp->length;
618 value = pp->value;
619 #else
620 pcfg_node = ofnode_to_offset(node);
621 fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
622 value = fdt_getprop_by_offset(blob, property_offset,
623 &prop_name, &prop_len);
624 if (!value)
625 return -ENOENT;
626 #endif
627 param = rockchip_pinconf_prop_name_to_param(prop_name,
628 &default_val);
629 if (param < 0)
630 break;
631
632 if (prop_len >= sizeof(fdt32_t))
633 arg = fdt32_to_cpu(*(fdt32_t *)value);
634 else
635 arg = default_val;
636
637 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
638 param, arg);
639 if (ret) {
640 debug("%s: rockchip_pinconf_set fail: %d\n",
641 __func__, ret);
642 return ret;
643 }
644 }
645 }
646
647 return 0;
648 }
649
650 const struct pinctrl_ops rockchip_pinctrl_ops = {
651 .set_state = rockchip_pinctrl_set_state,
652 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
653 };
654
655 /* retrieve the soc specific data */
656 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
657 {
658 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
659 struct rockchip_pin_ctrl *ctrl =
660 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
661 struct rockchip_pin_bank *bank;
662 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
663
664 grf_offs = ctrl->grf_mux_offset;
665 pmu_offs = ctrl->pmu_mux_offset;
666 drv_pmu_offs = ctrl->pmu_drv_offset;
667 drv_grf_offs = ctrl->grf_drv_offset;
668 bank = ctrl->pin_banks;
669
670 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
671 int bank_pins = 0;
672
673 bank->priv = priv;
674 bank->pin_base = ctrl->nr_pins;
675 ctrl->nr_pins += bank->nr_pins;
676
677 /* calculate iomux and drv offsets */
678 for (j = 0; j < 4; j++) {
679 struct rockchip_iomux *iom = &bank->iomux[j];
680 struct rockchip_drv *drv = &bank->drv[j];
681 int inc;
682
683 if (bank_pins >= bank->nr_pins)
684 break;
685
686 /* preset iomux offset value, set new start value */
687 if (iom->offset >= 0) {
688 if (iom->type & IOMUX_SOURCE_PMU)
689 pmu_offs = iom->offset;
690 else
691 grf_offs = iom->offset;
692 } else { /* set current iomux offset */
693 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
694 pmu_offs : grf_offs;
695 }
696
697 /* preset drv offset value, set new start value */
698 if (drv->offset >= 0) {
699 if (iom->type & IOMUX_SOURCE_PMU)
700 drv_pmu_offs = drv->offset;
701 else
702 drv_grf_offs = drv->offset;
703 } else { /* set current drv offset */
704 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
705 drv_pmu_offs : drv_grf_offs;
706 }
707
708 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
709 i, j, iom->offset, drv->offset);
710
711 /*
712 * Increase offset according to iomux width.
713 * 4bit iomux'es are spread over two registers.
714 */
715 inc = (iom->type & (IOMUX_WIDTH_4BIT |
716 IOMUX_WIDTH_3BIT)) ? 8 : 4;
717 if (iom->type & IOMUX_SOURCE_PMU)
718 pmu_offs += inc;
719 else
720 grf_offs += inc;
721
722 /*
723 * Increase offset according to drv width.
724 * 3bit drive-strenth'es are spread over two registers.
725 */
726 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
727 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
728 inc = 8;
729 else
730 inc = 4;
731
732 if (iom->type & IOMUX_SOURCE_PMU)
733 drv_pmu_offs += inc;
734 else
735 drv_grf_offs += inc;
736
737 bank_pins += 8;
738 }
739
740 /* calculate the per-bank recalced_mask */
741 for (j = 0; j < ctrl->niomux_recalced; j++) {
742 int pin = 0;
743
744 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
745 pin = ctrl->iomux_recalced[j].pin;
746 bank->recalced_mask |= BIT(pin);
747 }
748 }
749
750 /* calculate the per-bank route_mask */
751 for (j = 0; j < ctrl->niomux_routes; j++) {
752 int pin = 0;
753
754 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
755 pin = ctrl->iomux_routes[j].pin;
756 bank->route_mask |= BIT(pin);
757 }
758 }
759 }
760
761 return ctrl;
762 }
763
764 int rockchip_pinctrl_probe(struct udevice *dev)
765 {
766 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
767 struct rockchip_pin_ctrl *ctrl;
768 struct udevice *syscon;
769 struct regmap *regmap;
770 int ret = 0;
771
772 /* get rockchip grf syscon phandle */
773 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
774 &syscon);
775 if (ret) {
776 debug("unable to find rockchip,grf syscon device (%d)\n", ret);
777 return ret;
778 }
779
780 /* get grf-reg base address */
781 regmap = syscon_get_regmap(syscon);
782 if (!regmap) {
783 debug("unable to find rockchip grf regmap\n");
784 return -ENODEV;
785 }
786 priv->regmap_base = regmap;
787
788 /* option: get pmu-reg base address */
789 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
790 &syscon);
791 if (!ret) {
792 /* get pmugrf-reg base address */
793 regmap = syscon_get_regmap(syscon);
794 if (!regmap) {
795 debug("unable to find rockchip pmu regmap\n");
796 return -ENODEV;
797 }
798 priv->regmap_pmu = regmap;
799 }
800
801 ctrl = rockchip_pinctrl_get_soc_data(dev);
802 if (!ctrl) {
803 debug("driver data not available\n");
804 return -EINVAL;
805 }
806
807 priv->ctrl = ctrl;
808 return 0;
809 }
810