1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * RNG driver for Freescale RNGC
4 *
5 * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
7 */
8
9 #include <linux/module.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/clk.h>
14 #include <linux/err.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/hw_random.h>
18 #include <linux/completion.h>
19 #include <linux/io.h>
20 #include <linux/bitfield.h>
21
22 #define RNGC_VER_ID 0x0000
23 #define RNGC_COMMAND 0x0004
24 #define RNGC_CONTROL 0x0008
25 #define RNGC_STATUS 0x000C
26 #define RNGC_ERROR 0x0010
27 #define RNGC_FIFO 0x0014
28
29 /* the fields in the ver id register */
30 #define RNG_TYPE GENMASK(31, 28)
31 #define RNGC_VER_MAJ_SHIFT 8
32
33 /* the rng_type field */
34 #define RNGC_TYPE_RNGB 0x1
35 #define RNGC_TYPE_RNGC 0x2
36
37
38 #define RNGC_CMD_CLR_ERR BIT(5)
39 #define RNGC_CMD_CLR_INT BIT(4)
40 #define RNGC_CMD_SEED BIT(1)
41 #define RNGC_CMD_SELF_TEST BIT(0)
42
43 #define RNGC_CTRL_MASK_ERROR BIT(6)
44 #define RNGC_CTRL_MASK_DONE BIT(5)
45 #define RNGC_CTRL_AUTO_SEED BIT(4)
46
47 #define RNGC_STATUS_ERROR BIT(16)
48 #define RNGC_STATUS_FIFO_LEVEL_MASK GENMASK(11, 8)
49 #define RNGC_STATUS_SEED_DONE BIT(5)
50 #define RNGC_STATUS_ST_DONE BIT(4)
51
52 #define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
53
54 #define RNGC_TIMEOUT 3000 /* 3 sec */
55
56
57 static bool self_test = true;
58 module_param(self_test, bool, 0);
59
60 struct imx_rngc {
61 struct device *dev;
62 struct clk *clk;
63 void __iomem *base;
64 struct hwrng rng;
65 struct completion rng_op_done;
66 /*
67 * err_reg is written only by the irq handler and read only
68 * when interrupts are masked, we need no spinlock
69 */
70 u32 err_reg;
71 };
72
73
imx_rngc_irq_mask_clear(struct imx_rngc * rngc)74 static inline void imx_rngc_irq_mask_clear(struct imx_rngc *rngc)
75 {
76 u32 ctrl, cmd;
77
78 /* mask interrupts */
79 ctrl = readl(rngc->base + RNGC_CONTROL);
80 ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR;
81 writel(ctrl, rngc->base + RNGC_CONTROL);
82
83 /*
84 * CLR_INT clears the interrupt only if there's no error
85 * CLR_ERR clear the interrupt and the error register if there
86 * is an error
87 */
88 cmd = readl(rngc->base + RNGC_COMMAND);
89 cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR;
90 writel(cmd, rngc->base + RNGC_COMMAND);
91 }
92
imx_rngc_irq_unmask(struct imx_rngc * rngc)93 static inline void imx_rngc_irq_unmask(struct imx_rngc *rngc)
94 {
95 u32 ctrl;
96
97 ctrl = readl(rngc->base + RNGC_CONTROL);
98 ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR);
99 writel(ctrl, rngc->base + RNGC_CONTROL);
100 }
101
imx_rngc_self_test(struct imx_rngc * rngc)102 static int imx_rngc_self_test(struct imx_rngc *rngc)
103 {
104 u32 cmd;
105 int ret;
106
107 imx_rngc_irq_unmask(rngc);
108
109 /* run self test */
110 cmd = readl(rngc->base + RNGC_COMMAND);
111 writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
112
113 ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT));
114 imx_rngc_irq_mask_clear(rngc);
115 if (!ret)
116 return -ETIMEDOUT;
117
118 return rngc->err_reg ? -EIO : 0;
119 }
120
imx_rngc_read(struct hwrng * rng,void * data,size_t max,bool wait)121 static int imx_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
122 {
123 struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
124 unsigned int status;
125 int retval = 0;
126
127 while (max >= sizeof(u32)) {
128 status = readl(rngc->base + RNGC_STATUS);
129
130 /* is there some error while reading this random number? */
131 if (status & RNGC_STATUS_ERROR)
132 break;
133
134 if (status & RNGC_STATUS_FIFO_LEVEL_MASK) {
135 /* retrieve a random number from FIFO */
136 *(u32 *)data = readl(rngc->base + RNGC_FIFO);
137
138 retval += sizeof(u32);
139 data += sizeof(u32);
140 max -= sizeof(u32);
141 }
142 }
143
144 return retval ? retval : -EIO;
145 }
146
imx_rngc_irq(int irq,void * priv)147 static irqreturn_t imx_rngc_irq(int irq, void *priv)
148 {
149 struct imx_rngc *rngc = (struct imx_rngc *)priv;
150 u32 status;
151
152 /*
153 * clearing the interrupt will also clear the error register
154 * read error and status before clearing
155 */
156 status = readl(rngc->base + RNGC_STATUS);
157 rngc->err_reg = readl(rngc->base + RNGC_ERROR);
158
159 imx_rngc_irq_mask_clear(rngc);
160
161 if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
162 complete(&rngc->rng_op_done);
163
164 return IRQ_HANDLED;
165 }
166
imx_rngc_init(struct hwrng * rng)167 static int imx_rngc_init(struct hwrng *rng)
168 {
169 struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
170 u32 cmd, ctrl;
171 int ret;
172
173 /* clear error */
174 cmd = readl(rngc->base + RNGC_COMMAND);
175 writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
176
177 imx_rngc_irq_unmask(rngc);
178
179 /* create seed, repeat while there is some statistical error */
180 do {
181 /* seed creation */
182 cmd = readl(rngc->base + RNGC_COMMAND);
183 writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
184
185 ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT));
186 if (!ret) {
187 ret = -ETIMEDOUT;
188 goto err;
189 }
190
191 } while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR);
192
193 if (rngc->err_reg) {
194 ret = -EIO;
195 goto err;
196 }
197
198 /*
199 * enable automatic seeding, the rngc creates a new seed automatically
200 * after serving 2^20 random 160-bit words
201 */
202 ctrl = readl(rngc->base + RNGC_CONTROL);
203 ctrl |= RNGC_CTRL_AUTO_SEED;
204 writel(ctrl, rngc->base + RNGC_CONTROL);
205
206 /*
207 * if initialisation was successful, we keep the interrupt
208 * unmasked until imx_rngc_cleanup is called
209 * we mask the interrupt ourselves if we return an error
210 */
211 return 0;
212
213 err:
214 imx_rngc_irq_mask_clear(rngc);
215 return ret;
216 }
217
imx_rngc_cleanup(struct hwrng * rng)218 static void imx_rngc_cleanup(struct hwrng *rng)
219 {
220 struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
221
222 imx_rngc_irq_mask_clear(rngc);
223 }
224
imx_rngc_probe(struct platform_device * pdev)225 static int __init imx_rngc_probe(struct platform_device *pdev)
226 {
227 struct imx_rngc *rngc;
228 int ret;
229 int irq;
230 u32 ver_id;
231 u8 rng_type;
232
233 rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
234 if (!rngc)
235 return -ENOMEM;
236
237 rngc->base = devm_platform_ioremap_resource(pdev, 0);
238 if (IS_ERR(rngc->base))
239 return PTR_ERR(rngc->base);
240
241 rngc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
242 if (IS_ERR(rngc->clk))
243 return dev_err_probe(&pdev->dev, PTR_ERR(rngc->clk), "Cannot get rng_clk\n");
244
245 irq = platform_get_irq(pdev, 0);
246 if (irq < 0)
247 return irq;
248
249 ver_id = readl(rngc->base + RNGC_VER_ID);
250 rng_type = FIELD_GET(RNG_TYPE, ver_id);
251 /*
252 * This driver supports only RNGC and RNGB. (There's a different
253 * driver for RNGA.)
254 */
255 if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB)
256 return -ENODEV;
257
258 init_completion(&rngc->rng_op_done);
259
260 rngc->rng.name = pdev->name;
261 rngc->rng.init = imx_rngc_init;
262 rngc->rng.read = imx_rngc_read;
263 rngc->rng.cleanup = imx_rngc_cleanup;
264 rngc->rng.quality = 19;
265
266 rngc->dev = &pdev->dev;
267 platform_set_drvdata(pdev, rngc);
268
269 imx_rngc_irq_mask_clear(rngc);
270
271 ret = devm_request_irq(&pdev->dev,
272 irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
273 if (ret)
274 return dev_err_probe(&pdev->dev, ret, "Can't get interrupt working.\n");
275
276 if (self_test) {
277 ret = imx_rngc_self_test(rngc);
278 if (ret)
279 return dev_err_probe(&pdev->dev, ret, "self test failed\n");
280 }
281
282 ret = devm_hwrng_register(&pdev->dev, &rngc->rng);
283 if (ret)
284 return dev_err_probe(&pdev->dev, ret, "hwrng registration failed\n");
285
286 dev_info(&pdev->dev,
287 "Freescale RNG%c registered (HW revision %d.%02d)\n",
288 rng_type == RNGC_TYPE_RNGB ? 'B' : 'C',
289 (ver_id >> RNGC_VER_MAJ_SHIFT) & 0xff, ver_id & 0xff);
290 return 0;
291 }
292
imx_rngc_suspend(struct device * dev)293 static int imx_rngc_suspend(struct device *dev)
294 {
295 struct imx_rngc *rngc = dev_get_drvdata(dev);
296
297 clk_disable_unprepare(rngc->clk);
298
299 return 0;
300 }
301
imx_rngc_resume(struct device * dev)302 static int imx_rngc_resume(struct device *dev)
303 {
304 struct imx_rngc *rngc = dev_get_drvdata(dev);
305
306 clk_prepare_enable(rngc->clk);
307
308 return 0;
309 }
310
311 static DEFINE_SIMPLE_DEV_PM_OPS(imx_rngc_pm_ops, imx_rngc_suspend, imx_rngc_resume);
312
313 static const struct of_device_id imx_rngc_dt_ids[] = {
314 { .compatible = "fsl,imx25-rngb" },
315 { /* sentinel */ }
316 };
317 MODULE_DEVICE_TABLE(of, imx_rngc_dt_ids);
318
319 static struct platform_driver imx_rngc_driver = {
320 .driver = {
321 .name = KBUILD_MODNAME,
322 .pm = pm_sleep_ptr(&imx_rngc_pm_ops),
323 .of_match_table = imx_rngc_dt_ids,
324 },
325 };
326
327 module_platform_driver_probe(imx_rngc_driver, imx_rngc_probe);
328
329 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
330 MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
331 MODULE_LICENSE("GPL");
332