1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <asm/armv8/mmu.h>
8 #include <asm/io.h>
9 #include <asm/arch/hardware.h>
10
11 DECLARE_GLOBAL_DATA_PTR;
12
13 #define GRF_EMMCCORE_CON11 0xff77f02c
14
15 static struct mm_region rk3399_mem_map[] = {
16 {
17 .virt = 0x0UL,
18 .phys = 0x0UL,
19 .size = 0xf8000000UL,
20 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
21 PTE_BLOCK_INNER_SHARE
22 }, {
23 .virt = 0xf8000000UL,
24 .phys = 0xf8000000UL,
25 .size = 0x08000000UL,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 PTE_BLOCK_NON_SHARE |
28 PTE_BLOCK_PXN | PTE_BLOCK_UXN
29 }, {
30 /* List terminator */
31 0,
32 }
33 };
34
35 struct mm_region *mem_map = rk3399_mem_map;
36
dram_init_banksize(void)37 int dram_init_banksize(void)
38 {
39 size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
40
41 /* Reserve 0x200000 for ATF bl31 */
42 gd->bd->bi_dram[0].start = 0x200000;
43 gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
44
45 return 0;
46 }
47
arch_cpu_init(void)48 int arch_cpu_init(void)
49 {
50 /* We do some SoC one time setting here. */
51
52 /* Emmc clock generator: disable the clock multipilier */
53 rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
54
55 return 0;
56 }
57