1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #include <linux/component.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12
13 #include <drm/drm_fourcc.h>
14 #include <drm/drm_plane.h>
15 #include <drm/drm_print.h>
16
17 #include "rockchip_drm_vop.h"
18 #include "rockchip_vop_reg.h"
19 #include "rockchip_drm_drv.h"
20
21 #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \
22 { \
23 .offset = off, \
24 .mask = _mask, \
25 .shift = _shift, \
26 .write_mask = _write_mask, \
27 .relaxed = _relaxed, \
28 }
29
30 #define VOP_REG(off, _mask, _shift) \
31 _VOP_REG(off, _mask, _shift, false, true)
32
33 #define VOP_REG_SYNC(off, _mask, _shift) \
34 _VOP_REG(off, _mask, _shift, false, false)
35
36 #define VOP_REG_MASK_SYNC(off, _mask, _shift) \
37 _VOP_REG(off, _mask, _shift, true, false)
38
39 static const uint32_t formats_win_full[] = {
40 DRM_FORMAT_XRGB8888,
41 DRM_FORMAT_ARGB8888,
42 DRM_FORMAT_XBGR8888,
43 DRM_FORMAT_ABGR8888,
44 DRM_FORMAT_RGB888,
45 DRM_FORMAT_BGR888,
46 DRM_FORMAT_RGB565,
47 DRM_FORMAT_BGR565,
48 DRM_FORMAT_NV12,
49 DRM_FORMAT_NV21,
50 DRM_FORMAT_NV16,
51 DRM_FORMAT_NV61,
52 DRM_FORMAT_NV24,
53 DRM_FORMAT_NV42,
54 };
55
56 static const uint64_t format_modifiers_win_full[] = {
57 DRM_FORMAT_MOD_LINEAR,
58 DRM_FORMAT_MOD_INVALID,
59 };
60
61 static const uint64_t format_modifiers_win_full_afbc[] = {
62 ROCKCHIP_AFBC_MOD,
63 DRM_FORMAT_MOD_LINEAR,
64 DRM_FORMAT_MOD_INVALID,
65 };
66
67 static const uint32_t formats_win_lite[] = {
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_ARGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ABGR8888,
72 DRM_FORMAT_RGB888,
73 DRM_FORMAT_BGR888,
74 DRM_FORMAT_RGB565,
75 DRM_FORMAT_BGR565,
76 };
77
78 static const uint64_t format_modifiers_win_lite[] = {
79 DRM_FORMAT_MOD_LINEAR,
80 DRM_FORMAT_MOD_INVALID,
81 };
82
83 static const struct vop_scl_regs rk3036_win0_scl = {
84 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
85 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
86 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
87 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
88 };
89
90 static const struct vop_scl_regs rk3036_win1_scl = {
91 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0),
92 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16),
93 };
94
95 static const struct vop_win_phy rk3036_win0_data = {
96 .scl = &rk3036_win0_scl,
97 .data_formats = formats_win_full,
98 .nformats = ARRAY_SIZE(formats_win_full),
99 .format_modifiers = format_modifiers_win_full,
100 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
101 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
102 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
103 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
104 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
105 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
106 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
107 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
108 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
109 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
110 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
111 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
112 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
113 };
114
115 static const struct vop_win_phy rk3036_win1_data = {
116 .scl = &rk3036_win1_scl,
117 .data_formats = formats_win_lite,
118 .nformats = ARRAY_SIZE(formats_win_lite),
119 .format_modifiers = format_modifiers_win_lite,
120 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
121 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
122 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
123 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
124 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
125 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
126 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
127 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
128 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
129 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
130 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
131 };
132
133 static const struct vop_win_data rk3036_vop_win_data[] = {
134 { .base = 0x00, .phy = &rk3036_win0_data,
135 .type = DRM_PLANE_TYPE_PRIMARY },
136 { .base = 0x00, .phy = &rk3036_win1_data,
137 .type = DRM_PLANE_TYPE_CURSOR },
138 };
139
140 static const int rk3036_vop_intrs[] = {
141 DSP_HOLD_VALID_INTR,
142 FS_INTR,
143 LINE_FLAG_INTR,
144 BUS_ERROR_INTR,
145 };
146
147 static const struct vop_intr rk3036_intr = {
148 .intrs = rk3036_vop_intrs,
149 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
150 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
151 .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0),
152 .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4),
153 .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8),
154 };
155
156 static const struct vop_modeset rk3036_modeset = {
157 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
158 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
159 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
160 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
161 };
162
163 static const struct vop_output rk3036_output = {
164 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
165 };
166
167 static const struct vop_common rk3036_common = {
168 .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
169 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
170 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
171 .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
172 .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
173 .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
174 .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
175 };
176
177 static const struct vop_data rk3036_vop = {
178 .intr = &rk3036_intr,
179 .common = &rk3036_common,
180 .modeset = &rk3036_modeset,
181 .output = &rk3036_output,
182 .win = rk3036_vop_win_data,
183 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
184 .max_output = { 1920, 1080 },
185 };
186
187 static const struct vop_win_phy rk3126_win1_data = {
188 .data_formats = formats_win_lite,
189 .nformats = ARRAY_SIZE(formats_win_lite),
190 .format_modifiers = format_modifiers_win_lite,
191 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
192 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
193 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
194 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
195 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
196 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
197 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
198 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
199 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
200 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
201 };
202
203 static const struct vop_win_data rk3126_vop_win_data[] = {
204 { .base = 0x00, .phy = &rk3036_win0_data,
205 .type = DRM_PLANE_TYPE_PRIMARY },
206 { .base = 0x00, .phy = &rk3126_win1_data,
207 .type = DRM_PLANE_TYPE_CURSOR },
208 };
209
210 static const struct vop_data rk3126_vop = {
211 .intr = &rk3036_intr,
212 .common = &rk3036_common,
213 .modeset = &rk3036_modeset,
214 .output = &rk3036_output,
215 .win = rk3126_vop_win_data,
216 .win_size = ARRAY_SIZE(rk3126_vop_win_data),
217 .max_output = { 1920, 1080 },
218 };
219
220 static const int px30_vop_intrs[] = {
221 FS_INTR,
222 0, 0,
223 LINE_FLAG_INTR,
224 0,
225 BUS_ERROR_INTR,
226 0, 0,
227 DSP_HOLD_VALID_INTR,
228 };
229
230 static const struct vop_intr px30_intr = {
231 .intrs = px30_vop_intrs,
232 .nintrs = ARRAY_SIZE(px30_vop_intrs),
233 .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 0),
234 .status = VOP_REG_MASK_SYNC(PX30_INTR_STATUS, 0xffff, 0),
235 .enable = VOP_REG_MASK_SYNC(PX30_INTR_EN, 0xffff, 0),
236 .clear = VOP_REG_MASK_SYNC(PX30_INTR_CLEAR, 0xffff, 0),
237 };
238
239 static const struct vop_common px30_common = {
240 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1),
241 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16),
242 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14),
243 .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8),
244 .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7),
245 .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6),
246 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0),
247 };
248
249 static const struct vop_modeset px30_modeset = {
250 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
251 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0),
252 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
253 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0),
254 };
255
256 static const struct vop_output px30_output = {
257 .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1),
258 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2),
259 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0),
260 .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25),
261 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26),
262 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24),
263 };
264
265 static const struct vop_scl_regs px30_win_scl = {
266 .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
267 .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
268 .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
269 .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
270 };
271
272 static const struct vop_win_phy px30_win0_data = {
273 .scl = &px30_win_scl,
274 .data_formats = formats_win_full,
275 .nformats = ARRAY_SIZE(formats_win_full),
276 .format_modifiers = format_modifiers_win_full,
277 .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0),
278 .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1),
279 .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12),
280 .uv_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 15),
281 .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0),
282 .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0),
283 .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0),
284 .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0),
285 .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0),
286 .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0),
287 .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16),
288 .alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2),
289 .alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1),
290 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
291 };
292
293 static const struct vop_win_phy px30_win1_data = {
294 .data_formats = formats_win_lite,
295 .nformats = ARRAY_SIZE(formats_win_lite),
296 .format_modifiers = format_modifiers_win_lite,
297 .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0),
298 .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4),
299 .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12),
300 .uv_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 15),
301 .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0),
302 .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0),
303 .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0),
304 .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0),
305 .alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2),
306 .alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1),
307 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
308 };
309
310 static const struct vop_win_phy px30_win2_data = {
311 .data_formats = formats_win_lite,
312 .nformats = ARRAY_SIZE(formats_win_lite),
313 .format_modifiers = format_modifiers_win_lite,
314 .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4),
315 .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0),
316 .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5),
317 .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20),
318 .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0),
319 .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0),
320 .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0),
321 .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0),
322 .alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2),
323 .alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1),
324 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
325 };
326
327 static const struct vop_win_data px30_vop_big_win_data[] = {
328 { .base = 0x00, .phy = &px30_win0_data,
329 .type = DRM_PLANE_TYPE_PRIMARY },
330 { .base = 0x00, .phy = &px30_win1_data,
331 .type = DRM_PLANE_TYPE_OVERLAY },
332 { .base = 0x00, .phy = &px30_win2_data,
333 .type = DRM_PLANE_TYPE_CURSOR },
334 };
335
336 static const struct vop_data px30_vop_big = {
337 .version = VOP_VERSION(2, 6),
338 .intr = &px30_intr,
339 .feature = VOP_FEATURE_INTERNAL_RGB,
340 .common = &px30_common,
341 .modeset = &px30_modeset,
342 .output = &px30_output,
343 .win = px30_vop_big_win_data,
344 .win_size = ARRAY_SIZE(px30_vop_big_win_data),
345 .max_output = { 1920, 1080 },
346 };
347
348 static const struct vop_win_data px30_vop_lit_win_data[] = {
349 { .base = 0x00, .phy = &px30_win1_data,
350 .type = DRM_PLANE_TYPE_PRIMARY },
351 };
352
353 static const struct vop_data px30_vop_lit = {
354 .version = VOP_VERSION(2, 5),
355 .intr = &px30_intr,
356 .feature = VOP_FEATURE_INTERNAL_RGB,
357 .common = &px30_common,
358 .modeset = &px30_modeset,
359 .output = &px30_output,
360 .win = px30_vop_lit_win_data,
361 .win_size = ARRAY_SIZE(px30_vop_lit_win_data),
362 .max_output = { 1920, 1080 },
363 };
364
365 static const struct vop_scl_regs rk3066_win_scl = {
366 .scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
367 .scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
368 .scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
369 .scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
370 };
371
372 static const struct vop_win_phy rk3066_win0_data = {
373 .scl = &rk3066_win_scl,
374 .data_formats = formats_win_full,
375 .nformats = ARRAY_SIZE(formats_win_full),
376 .format_modifiers = format_modifiers_win_full,
377 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
378 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 4),
379 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 19),
380 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 22),
381 .act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
382 .dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
383 .dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
384 .yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
385 .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
386 .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
387 .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
388 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21),
389 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0),
390 };
391
392 static const struct vop_win_phy rk3066_win1_data = {
393 .data_formats = formats_win_full,
394 .nformats = ARRAY_SIZE(formats_win_full),
395 .format_modifiers = format_modifiers_win_full,
396 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
397 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 7),
398 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 23),
399 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 26),
400 .act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
401 .dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
402 .dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
403 .yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
404 .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
405 .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
406 .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
407 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22),
408 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1),
409 };
410
411 static const struct vop_win_phy rk3066_win2_data = {
412 .data_formats = formats_win_lite,
413 .nformats = ARRAY_SIZE(formats_win_lite),
414 .format_modifiers = format_modifiers_win_lite,
415 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
416 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 10),
417 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 27),
418 .dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
419 .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
420 .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
421 .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
422 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23),
423 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2),
424 };
425
426 static const struct vop_modeset rk3066_modeset = {
427 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
428 .hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
429 .vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
430 .vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
431 };
432
433 static const struct vop_output rk3066_output = {
434 .pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
435 };
436
437 static const struct vop_common rk3066_common = {
438 .dma_stop = VOP_REG(RK3066_SYS_CTRL0, 0x1, 0),
439 .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
440 .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
441 .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
442 .dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11),
443 .dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10),
444 .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
445 .dither_up = VOP_REG(RK3066_DSP_CTRL0, 0x1, 9),
446 .dsp_lut_en = VOP_REG(RK3066_SYS_CTRL1, 0x1, 31),
447 .data_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 25),
448 };
449
450 static const struct vop_win_data rk3066_vop_win_data[] = {
451 { .base = 0x00, .phy = &rk3066_win0_data,
452 .type = DRM_PLANE_TYPE_PRIMARY },
453 { .base = 0x00, .phy = &rk3066_win1_data,
454 .type = DRM_PLANE_TYPE_OVERLAY },
455 { .base = 0x00, .phy = &rk3066_win2_data,
456 .type = DRM_PLANE_TYPE_CURSOR },
457 };
458
459 static const int rk3066_vop_intrs[] = {
460 /*
461 * hs_start interrupt fires at frame-start, so serves
462 * the same purpose as dsp_hold in the driver.
463 */
464 DSP_HOLD_VALID_INTR,
465 FS_INTR,
466 LINE_FLAG_INTR,
467 BUS_ERROR_INTR,
468 };
469
470 static const struct vop_intr rk3066_intr = {
471 .intrs = rk3066_vop_intrs,
472 .nintrs = ARRAY_SIZE(rk3066_vop_intrs),
473 .line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
474 .status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
475 .enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
476 .clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
477 };
478
479 static const struct vop_data rk3066_vop = {
480 .version = VOP_VERSION(2, 1),
481 .intr = &rk3066_intr,
482 .common = &rk3066_common,
483 .modeset = &rk3066_modeset,
484 .output = &rk3066_output,
485 .win = rk3066_vop_win_data,
486 .win_size = ARRAY_SIZE(rk3066_vop_win_data),
487 .feature = VOP_FEATURE_INTERNAL_RGB,
488 .max_output = { 1920, 1080 },
489 };
490
491 static const struct vop_scl_regs rk3188_win_scl = {
492 .scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
493 .scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
494 .scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
495 .scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
496 };
497
498 static const struct vop_win_phy rk3188_win0_data = {
499 .scl = &rk3188_win_scl,
500 .data_formats = formats_win_full,
501 .nformats = ARRAY_SIZE(formats_win_full),
502 .format_modifiers = format_modifiers_win_full,
503 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0),
504 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3),
505 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15),
506 .uv_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 18),
507 .act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0),
508 .dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0),
509 .dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0),
510 .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0),
511 .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0),
512 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0),
513 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 18),
514 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0),
515 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29),
516 };
517
518 static const struct vop_win_phy rk3188_win1_data = {
519 .data_formats = formats_win_lite,
520 .nformats = ARRAY_SIZE(formats_win_lite),
521 .format_modifiers = format_modifiers_win_lite,
522 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1),
523 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6),
524 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19),
525 /* no act_info on window1 */
526 .dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0),
527 .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0),
528 .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0),
529 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16),
530 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 19),
531 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 1),
532 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29),
533 };
534
535 static const struct vop_modeset rk3188_modeset = {
536 .htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
537 .hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0),
538 .vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
539 .vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0),
540 };
541
542 static const struct vop_output rk3188_output = {
543 .pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4),
544 };
545
546 static const struct vop_common rk3188_common = {
547 .gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31),
548 .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30),
549 .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0),
550 .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0),
551 .dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27),
552 .dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11),
553 .dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10),
554 .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 24),
555 .dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9),
556 .dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28),
557 .data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25),
558 };
559
560 static const struct vop_win_data rk3188_vop_win_data[] = {
561 { .base = 0x00, .phy = &rk3188_win0_data,
562 .type = DRM_PLANE_TYPE_PRIMARY },
563 { .base = 0x00, .phy = &rk3188_win1_data,
564 .type = DRM_PLANE_TYPE_CURSOR },
565 };
566
567 static const int rk3188_vop_intrs[] = {
568 /*
569 * hs_start interrupt fires at frame-start, so serves
570 * the same purpose as dsp_hold in the driver.
571 */
572 DSP_HOLD_VALID_INTR,
573 FS_INTR,
574 LINE_FLAG_INTR,
575 BUS_ERROR_INTR,
576 };
577
578 static const struct vop_intr rk3188_vop_intr = {
579 .intrs = rk3188_vop_intrs,
580 .nintrs = ARRAY_SIZE(rk3188_vop_intrs),
581 .line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12),
582 .status = VOP_REG(RK3188_INT_STATUS, 0xf, 0),
583 .enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4),
584 .clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8),
585 };
586
587 static const struct vop_data rk3188_vop = {
588 .intr = &rk3188_vop_intr,
589 .common = &rk3188_common,
590 .modeset = &rk3188_modeset,
591 .output = &rk3188_output,
592 .win = rk3188_vop_win_data,
593 .win_size = ARRAY_SIZE(rk3188_vop_win_data),
594 .feature = VOP_FEATURE_INTERNAL_RGB,
595 .max_output = { 2048, 1536 },
596 };
597
598 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
599 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
600 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
601 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
602 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
603 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
604 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
605 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
606 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
607 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
608 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
609 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
610 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
611 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
612 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
613 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
614 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
615 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
616 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
617 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
618 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
619 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
620 };
621
622 static const struct vop_scl_regs rk3288_win_full_scl = {
623 .ext = &rk3288_win_full_scl_ext,
624 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
625 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
626 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
627 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
628 };
629
630 static const struct vop_win_phy rk3288_win01_data = {
631 .scl = &rk3288_win_full_scl,
632 .data_formats = formats_win_full,
633 .nformats = ARRAY_SIZE(formats_win_full),
634 .format_modifiers = format_modifiers_win_full,
635 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
636 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
637 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
638 .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
639 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
640 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
641 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
642 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
643 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
644 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
645 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
646 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
647 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
648 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
649 };
650
651 static const struct vop_win_phy rk3288_win23_data = {
652 .data_formats = formats_win_lite,
653 .nformats = ARRAY_SIZE(formats_win_lite),
654 .format_modifiers = format_modifiers_win_lite,
655 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
656 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
657 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
658 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
659 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
660 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
661 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
662 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
663 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
664 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
665 };
666
667 static const struct vop_modeset rk3288_modeset = {
668 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
669 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
670 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
671 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
672 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
673 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
674 };
675
676 static const struct vop_output rk3288_output = {
677 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
678 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
679 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
680 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
681 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
682 };
683
684 static const struct vop_common rk3288_common = {
685 .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
686 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
687 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
688 .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
689 .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
690 .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
691 .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
692 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
693 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
694 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
695 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
696 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
697 .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
698 };
699
700 /*
701 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
702 * special support to get alpha blending working. For now, just use overlay
703 * window 3 for the drm cursor.
704 *
705 */
706 static const struct vop_win_data rk3288_vop_win_data[] = {
707 { .base = 0x00, .phy = &rk3288_win01_data,
708 .type = DRM_PLANE_TYPE_PRIMARY },
709 { .base = 0x40, .phy = &rk3288_win01_data,
710 .type = DRM_PLANE_TYPE_OVERLAY },
711 { .base = 0x00, .phy = &rk3288_win23_data,
712 .type = DRM_PLANE_TYPE_OVERLAY },
713 { .base = 0x50, .phy = &rk3288_win23_data,
714 .type = DRM_PLANE_TYPE_CURSOR },
715 };
716
717 static const int rk3288_vop_intrs[] = {
718 DSP_HOLD_VALID_INTR,
719 FS_INTR,
720 LINE_FLAG_INTR,
721 BUS_ERROR_INTR,
722 };
723
724 static const struct vop_intr rk3288_vop_intr = {
725 .intrs = rk3288_vop_intrs,
726 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
727 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
728 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
729 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
730 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
731 };
732
733 static const struct vop_data rk3288_vop = {
734 .version = VOP_VERSION(3, 1),
735 .feature = VOP_FEATURE_OUTPUT_RGB10,
736 .intr = &rk3288_vop_intr,
737 .common = &rk3288_common,
738 .modeset = &rk3288_modeset,
739 .output = &rk3288_output,
740 .win = rk3288_vop_win_data,
741 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
742 .lut_size = 1024,
743 /*
744 * This is the maximum resolution for the VOPB, the VOPL can only do
745 * 2560x1600, but we can't distinguish them as they have the same
746 * compatible.
747 */
748 .max_output = { 3840, 2160 },
749 };
750
751 static const int rk3368_vop_intrs[] = {
752 FS_INTR,
753 0, 0,
754 LINE_FLAG_INTR,
755 0,
756 BUS_ERROR_INTR,
757 0, 0, 0, 0, 0, 0, 0,
758 DSP_HOLD_VALID_INTR,
759 };
760
761 static const struct vop_intr rk3368_vop_intr = {
762 .intrs = rk3368_vop_intrs,
763 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
764 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
765 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
766 .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
767 .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
768 .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
769 };
770
771 static const struct vop_win_phy rk3368_win01_data = {
772 .scl = &rk3288_win_full_scl,
773 .data_formats = formats_win_full,
774 .nformats = ARRAY_SIZE(formats_win_full),
775 .format_modifiers = format_modifiers_win_full,
776 .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
777 .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
778 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
779 .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15),
780 .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
781 .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
782 .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0),
783 .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0),
784 .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0),
785 .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0),
786 .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0),
787 .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0),
788 .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16),
789 .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
790 .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0),
791 .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0),
792 };
793
794 static const struct vop_win_phy rk3368_win23_data = {
795 .data_formats = formats_win_lite,
796 .nformats = ARRAY_SIZE(formats_win_lite),
797 .format_modifiers = format_modifiers_win_lite,
798 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
799 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
800 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
801 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
802 .y_mir_en = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
803 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
804 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
805 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
806 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
807 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
808 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
809 };
810
811 static const struct vop_win_data rk3368_vop_win_data[] = {
812 { .base = 0x00, .phy = &rk3368_win01_data,
813 .type = DRM_PLANE_TYPE_PRIMARY },
814 { .base = 0x40, .phy = &rk3368_win01_data,
815 .type = DRM_PLANE_TYPE_OVERLAY },
816 { .base = 0x00, .phy = &rk3368_win23_data,
817 .type = DRM_PLANE_TYPE_OVERLAY },
818 { .base = 0x50, .phy = &rk3368_win23_data,
819 .type = DRM_PLANE_TYPE_CURSOR },
820 };
821
822 static const struct vop_output rk3368_output = {
823 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
824 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
825 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
826 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
827 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
828 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
829 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
830 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
831 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
832 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
833 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
834 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
835 };
836
837 static const struct vop_misc rk3368_misc = {
838 .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11),
839 };
840
841 static const struct vop_data rk3368_vop = {
842 .version = VOP_VERSION(3, 2),
843 .intr = &rk3368_vop_intr,
844 .common = &rk3288_common,
845 .modeset = &rk3288_modeset,
846 .output = &rk3368_output,
847 .misc = &rk3368_misc,
848 .win = rk3368_vop_win_data,
849 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
850 .max_output = { 4096, 2160 },
851 };
852
853 static const struct vop_intr rk3366_vop_intr = {
854 .intrs = rk3368_vop_intrs,
855 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
856 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
857 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
858 .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0),
859 .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0),
860 .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0),
861 };
862
863 static const struct vop_data rk3366_vop = {
864 .version = VOP_VERSION(3, 4),
865 .intr = &rk3366_vop_intr,
866 .common = &rk3288_common,
867 .modeset = &rk3288_modeset,
868 .output = &rk3368_output,
869 .misc = &rk3368_misc,
870 .win = rk3368_vop_win_data,
871 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
872 .max_output = { 4096, 2160 },
873 };
874
875 static const struct vop_output rk3399_output = {
876 .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19),
877 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
878 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
879 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
880 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
881 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16),
882 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
883 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
884 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
885 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
886 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
887 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
888 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
889 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
890 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
891 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
892 };
893
894 static const struct vop_common rk3399_common = {
895 .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
896 .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
897 .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20),
898 .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4),
899 .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3),
900 .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2),
901 .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1),
902 .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
903 .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0),
904 .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7),
905 .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1),
906 .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
907 .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
908 .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
909 .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
910 };
911
912 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
913 .y2r_coefficients = {
914 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
915 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 16),
916 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 0),
917 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 16),
918 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 0),
919 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 16),
920 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 0),
921 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 16),
922 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 16, 0xffff, 0),
923 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 20, 0xffffffff, 0),
924 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 24, 0xffffffff, 0),
925 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 28, 0xffffffff, 0),
926 },
927 };
928
929 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win23_data = { };
930
931 static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
932 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
933 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1) },
934 { .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data,
935 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9) },
936 { .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data },
937 { .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data },
938
939 };
940
941 static const struct vop_win_phy rk3399_win01_data = {
942 .scl = &rk3288_win_full_scl,
943 .data_formats = formats_win_full,
944 .nformats = ARRAY_SIZE(formats_win_full),
945 .format_modifiers = format_modifiers_win_full_afbc,
946 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
947 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
948 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
949 .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
950 .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
951 .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
952 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
953 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
954 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
955 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
956 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
957 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
958 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
959 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
960 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
961 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
962 };
963
964 /*
965 * rk3399 vop big windows register layout is same as rk3288, but we
966 * have a separate rk3399 win data array here so that we can advertise
967 * AFBC on the primary plane.
968 */
969 static const struct vop_win_data rk3399_vop_win_data[] = {
970 { .base = 0x00, .phy = &rk3399_win01_data,
971 .type = DRM_PLANE_TYPE_PRIMARY },
972 { .base = 0x40, .phy = &rk3368_win01_data,
973 .type = DRM_PLANE_TYPE_OVERLAY },
974 { .base = 0x00, .phy = &rk3368_win23_data,
975 .type = DRM_PLANE_TYPE_OVERLAY },
976 { .base = 0x50, .phy = &rk3368_win23_data,
977 .type = DRM_PLANE_TYPE_CURSOR },
978 };
979
980 static const struct vop_afbc rk3399_vop_afbc = {
981 .rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
982 .enable = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
983 .win_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
984 .format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
985 .hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
986 .hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
987 .pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
988 };
989
990 static const struct vop_data rk3399_vop_big = {
991 .version = VOP_VERSION(3, 5),
992 .feature = VOP_FEATURE_OUTPUT_RGB10,
993 .intr = &rk3366_vop_intr,
994 .common = &rk3399_common,
995 .modeset = &rk3288_modeset,
996 .output = &rk3399_output,
997 .afbc = &rk3399_vop_afbc,
998 .misc = &rk3368_misc,
999 .win = rk3399_vop_win_data,
1000 .win_size = ARRAY_SIZE(rk3399_vop_win_data),
1001 .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data,
1002 .lut_size = 1024,
1003 .max_output = { 4096, 2160 },
1004 };
1005
1006 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
1007 { .base = 0x00, .phy = &rk3368_win01_data,
1008 .type = DRM_PLANE_TYPE_PRIMARY },
1009 { .base = 0x00, .phy = &rk3368_win23_data,
1010 .type = DRM_PLANE_TYPE_CURSOR},
1011 };
1012
1013 static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
1014 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
1015 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1)},
1016 { .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data },
1017 };
1018
1019 static const struct vop_data rk3399_vop_lit = {
1020 .version = VOP_VERSION(3, 6),
1021 .intr = &rk3366_vop_intr,
1022 .common = &rk3399_common,
1023 .modeset = &rk3288_modeset,
1024 .output = &rk3399_output,
1025 .misc = &rk3368_misc,
1026 .win = rk3399_vop_lit_win_data,
1027 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
1028 .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data,
1029 .lut_size = 256,
1030 .max_output = { 2560, 1600 },
1031 };
1032
1033 static const struct vop_win_data rk3228_vop_win_data[] = {
1034 { .base = 0x00, .phy = &rk3288_win01_data,
1035 .type = DRM_PLANE_TYPE_PRIMARY },
1036 { .base = 0x40, .phy = &rk3288_win01_data,
1037 .type = DRM_PLANE_TYPE_CURSOR },
1038 };
1039
1040 static const struct vop_data rk3228_vop = {
1041 .version = VOP_VERSION(3, 7),
1042 .feature = VOP_FEATURE_OUTPUT_RGB10,
1043 .intr = &rk3366_vop_intr,
1044 .common = &rk3288_common,
1045 .modeset = &rk3288_modeset,
1046 .output = &rk3399_output,
1047 .misc = &rk3368_misc,
1048 .win = rk3228_vop_win_data,
1049 .win_size = ARRAY_SIZE(rk3228_vop_win_data),
1050 .max_output = { 4096, 2160 },
1051 };
1052
1053 static const struct vop_modeset rk3328_modeset = {
1054 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1055 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
1056 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1057 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
1058 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1059 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1060 };
1061
1062 static const struct vop_output rk3328_output = {
1063 .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
1064 .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
1065 .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
1066 .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
1067 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
1068 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
1069 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
1070 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
1071 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
1072 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
1073 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
1074 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
1075 };
1076
1077 static const struct vop_misc rk3328_misc = {
1078 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
1079 };
1080
1081 static const struct vop_common rk3328_common = {
1082 .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22),
1083 .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
1084 .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
1085 .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
1086 .pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
1087 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
1088 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
1089 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
1090 .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
1091 };
1092
1093 static const struct vop_intr rk3328_vop_intr = {
1094 .intrs = rk3368_vop_intrs,
1095 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
1096 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
1097 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
1098 .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0),
1099 .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0),
1100 .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0),
1101 };
1102
1103 static const struct vop_win_data rk3328_vop_win_data[] = {
1104 { .base = 0xd0, .phy = &rk3368_win01_data,
1105 .type = DRM_PLANE_TYPE_PRIMARY },
1106 { .base = 0x1d0, .phy = &rk3368_win01_data,
1107 .type = DRM_PLANE_TYPE_OVERLAY },
1108 { .base = 0x2d0, .phy = &rk3368_win01_data,
1109 .type = DRM_PLANE_TYPE_CURSOR },
1110 };
1111
1112 static const struct vop_data rk3328_vop = {
1113 .version = VOP_VERSION(3, 8),
1114 .feature = VOP_FEATURE_OUTPUT_RGB10,
1115 .intr = &rk3328_vop_intr,
1116 .common = &rk3328_common,
1117 .modeset = &rk3328_modeset,
1118 .output = &rk3328_output,
1119 .misc = &rk3328_misc,
1120 .win = rk3328_vop_win_data,
1121 .win_size = ARRAY_SIZE(rk3328_vop_win_data),
1122 .max_output = { 4096, 2160 },
1123 };
1124
1125 static const struct of_device_id vop_driver_dt_match[] = {
1126 { .compatible = "rockchip,rk3036-vop",
1127 .data = &rk3036_vop },
1128 { .compatible = "rockchip,rk3126-vop",
1129 .data = &rk3126_vop },
1130 { .compatible = "rockchip,px30-vop-big",
1131 .data = &px30_vop_big },
1132 { .compatible = "rockchip,px30-vop-lit",
1133 .data = &px30_vop_lit },
1134 { .compatible = "rockchip,rk3066-vop",
1135 .data = &rk3066_vop },
1136 { .compatible = "rockchip,rk3188-vop",
1137 .data = &rk3188_vop },
1138 { .compatible = "rockchip,rk3288-vop",
1139 .data = &rk3288_vop },
1140 { .compatible = "rockchip,rk3368-vop",
1141 .data = &rk3368_vop },
1142 { .compatible = "rockchip,rk3366-vop",
1143 .data = &rk3366_vop },
1144 { .compatible = "rockchip,rk3399-vop-big",
1145 .data = &rk3399_vop_big },
1146 { .compatible = "rockchip,rk3399-vop-lit",
1147 .data = &rk3399_vop_lit },
1148 { .compatible = "rockchip,rk3228-vop",
1149 .data = &rk3228_vop },
1150 { .compatible = "rockchip,rk3328-vop",
1151 .data = &rk3328_vop },
1152 {},
1153 };
1154 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
1155
vop_probe(struct platform_device * pdev)1156 static int vop_probe(struct platform_device *pdev)
1157 {
1158 struct device *dev = &pdev->dev;
1159
1160 if (!dev->of_node) {
1161 DRM_DEV_ERROR(dev, "can't find vop devices\n");
1162 return -ENODEV;
1163 }
1164
1165 return component_add(dev, &vop_component_ops);
1166 }
1167
vop_remove(struct platform_device * pdev)1168 static void vop_remove(struct platform_device *pdev)
1169 {
1170 component_del(&pdev->dev, &vop_component_ops);
1171 }
1172
1173 struct platform_driver vop_platform_driver = {
1174 .probe = vop_probe,
1175 .remove_new = vop_remove,
1176 .driver = {
1177 .name = "rockchip-vop",
1178 .of_match_table = vop_driver_dt_match,
1179 },
1180 };
1181