1 /*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
32 #include <linux/aperture.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
37 #include <linux/mm.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/fb.h>
41 #include <linux/init.h>
42 #include <linux/pci.h>
43 #include <linux/backlight.h>
44 #include <linux/bitrev.h>
45 #ifdef CONFIG_PMAC_BACKLIGHT
46 #include <asm/machdep.h>
47 #include <asm/backlight.h>
48 #endif
49
50 #include "rivafb.h"
51 #include "nvreg.h"
52
53 /* version number of this driver */
54 #define RIVAFB_VERSION "0.9.5b"
55
56 /* ------------------------------------------------------------------------- *
57 *
58 * various helpful macros and constants
59 *
60 * ------------------------------------------------------------------------- */
61 #ifdef CONFIG_FB_RIVA_DEBUG
62 #define NVTRACE printk
63 #else
64 #define NVTRACE if(0) printk
65 #endif
66
67 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
68 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
69
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define assert(expr) \
72 if(!(expr)) { \
73 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
74 #expr,__FILE__,__func__,__LINE__); \
75 BUG(); \
76 }
77 #else
78 #define assert(expr)
79 #endif
80
81 #define PFX "rivafb: "
82
83 /* macro that allows you to set overflow bits */
84 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
85 #define SetBit(n) (1<<(n))
86 #define Set8Bits(value) ((value)&0xff)
87
88 /* HW cursor parameters */
89 #define MAX_CURS 32
90
91 /* ------------------------------------------------------------------------- *
92 *
93 * prototypes
94 *
95 * ------------------------------------------------------------------------- */
96
97 static int rivafb_blank(int blank, struct fb_info *info);
98
99 /* ------------------------------------------------------------------------- *
100 *
101 * card identification
102 *
103 * ------------------------------------------------------------------------- */
104
105 static const struct pci_device_id rivafb_pci_tbl[] = {
106 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
108 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
110 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
112 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 // NF2/IGP version, GeForce 4 MX, NV18
147 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { 0, } /* terminate list */
192 };
193 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
194
195 /* ------------------------------------------------------------------------- *
196 *
197 * global variables
198 *
199 * ------------------------------------------------------------------------- */
200
201 /* command line data, set in rivafb_setup() */
202 static int flatpanel = -1; /* Autodetect later */
203 static int forceCRTC = -1;
204 static bool noaccel = 0;
205 static bool nomtrr = 0;
206 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
207
208 static char *mode_option = NULL;
209 static bool strictmode = 0;
210
211 static struct fb_fix_screeninfo rivafb_fix = {
212 .type = FB_TYPE_PACKED_PIXELS,
213 .xpanstep = 1,
214 .ypanstep = 1,
215 };
216
217 static struct fb_var_screeninfo rivafb_default_var = {
218 .xres = 640,
219 .yres = 480,
220 .xres_virtual = 640,
221 .yres_virtual = 480,
222 .bits_per_pixel = 8,
223 .red = {0, 8, 0},
224 .green = {0, 8, 0},
225 .blue = {0, 8, 0},
226 .transp = {0, 0, 0},
227 .activate = FB_ACTIVATE_NOW,
228 .height = -1,
229 .width = -1,
230 .pixclock = 39721,
231 .left_margin = 40,
232 .right_margin = 24,
233 .upper_margin = 32,
234 .lower_margin = 11,
235 .hsync_len = 96,
236 .vsync_len = 2,
237 .vmode = FB_VMODE_NONINTERLACED
238 };
239
240 /* from GGI */
241 static const struct riva_regs reg_template = {
242 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
243 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
244 0x41, 0x01, 0x0F, 0x00, 0x00},
245 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
246 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
247 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
248 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
249 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
250 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
251 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
252 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
253 0x00, /* 0x40 */
254 },
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
256 0xFF},
257 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
258 0xEB /* MISC */
259 };
260
261 /*
262 * Backlight control
263 */
264 #ifdef CONFIG_FB_RIVA_BACKLIGHT
265 /* We do not have any information about which values are allowed, thus
266 * we used safe values.
267 */
268 #define MIN_LEVEL 0x158
269 #define MAX_LEVEL 0x534
270 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
271
riva_bl_get_level_brightness(struct riva_par * par,int level)272 static int riva_bl_get_level_brightness(struct riva_par *par,
273 int level)
274 {
275 struct fb_info *info = pci_get_drvdata(par->pdev);
276 int nlevel;
277
278 /* Get and convert the value */
279 /* No locking on bl_curve since accessing a single value */
280 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
281
282 if (nlevel < 0)
283 nlevel = 0;
284 else if (nlevel < MIN_LEVEL)
285 nlevel = MIN_LEVEL;
286 else if (nlevel > MAX_LEVEL)
287 nlevel = MAX_LEVEL;
288
289 return nlevel;
290 }
291
riva_bl_update_status(struct backlight_device * bd)292 static int riva_bl_update_status(struct backlight_device *bd)
293 {
294 struct riva_par *par = bl_get_data(bd);
295 U032 tmp_pcrt, tmp_pmc;
296 int level = backlight_get_brightness(bd);
297
298 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
299 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
300 if(level > 0) {
301 tmp_pcrt |= 0x1;
302 tmp_pmc |= (1 << 31); /* backlight bit */
303 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
304 }
305 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
306 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
307
308 return 0;
309 }
310
311 static const struct backlight_ops riva_bl_ops = {
312 .update_status = riva_bl_update_status,
313 };
314
riva_bl_init(struct riva_par * par)315 static void riva_bl_init(struct riva_par *par)
316 {
317 struct backlight_properties props;
318 struct fb_info *info = pci_get_drvdata(par->pdev);
319 struct backlight_device *bd;
320 char name[12];
321
322 if (!par->FlatPanel)
323 return;
324
325 #ifdef CONFIG_PMAC_BACKLIGHT
326 if (!machine_is(powermac) ||
327 !pmac_has_backlight_type("mnca"))
328 return;
329 #endif
330
331 snprintf(name, sizeof(name), "rivabl%d", info->node);
332
333 memset(&props, 0, sizeof(struct backlight_properties));
334 props.type = BACKLIGHT_RAW;
335 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
336 bd = backlight_device_register(name, info->device, par, &riva_bl_ops,
337 &props);
338 if (IS_ERR(bd)) {
339 info->bl_dev = NULL;
340 printk(KERN_WARNING "riva: Backlight registration failed\n");
341 goto error;
342 }
343
344 info->bl_dev = bd;
345 fb_bl_default_curve(info, 0,
346 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
347 FB_BACKLIGHT_MAX);
348
349 bd->props.brightness = bd->props.max_brightness;
350 bd->props.power = FB_BLANK_UNBLANK;
351 backlight_update_status(bd);
352
353 printk("riva: Backlight initialized (%s)\n", name);
354
355 return;
356
357 error:
358 return;
359 }
360
riva_bl_exit(struct fb_info * info)361 static void riva_bl_exit(struct fb_info *info)
362 {
363 struct backlight_device *bd = info->bl_dev;
364
365 backlight_device_unregister(bd);
366 printk("riva: Backlight unloaded\n");
367 }
368 #else
riva_bl_init(struct riva_par * par)369 static inline void riva_bl_init(struct riva_par *par) {}
riva_bl_exit(struct fb_info * info)370 static inline void riva_bl_exit(struct fb_info *info) {}
371 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
372
373 /* ------------------------------------------------------------------------- *
374 *
375 * MMIO access macros
376 *
377 * ------------------------------------------------------------------------- */
378
CRTCout(struct riva_par * par,unsigned char index,unsigned char val)379 static inline void CRTCout(struct riva_par *par, unsigned char index,
380 unsigned char val)
381 {
382 VGA_WR08(par->riva.PCIO, 0x3d4, index);
383 VGA_WR08(par->riva.PCIO, 0x3d5, val);
384 }
385
CRTCin(struct riva_par * par,unsigned char index)386 static inline unsigned char CRTCin(struct riva_par *par,
387 unsigned char index)
388 {
389 VGA_WR08(par->riva.PCIO, 0x3d4, index);
390 return (VGA_RD08(par->riva.PCIO, 0x3d5));
391 }
392
GRAout(struct riva_par * par,unsigned char index,unsigned char val)393 static inline void GRAout(struct riva_par *par, unsigned char index,
394 unsigned char val)
395 {
396 VGA_WR08(par->riva.PVIO, 0x3ce, index);
397 VGA_WR08(par->riva.PVIO, 0x3cf, val);
398 }
399
GRAin(struct riva_par * par,unsigned char index)400 static inline unsigned char GRAin(struct riva_par *par,
401 unsigned char index)
402 {
403 VGA_WR08(par->riva.PVIO, 0x3ce, index);
404 return (VGA_RD08(par->riva.PVIO, 0x3cf));
405 }
406
SEQout(struct riva_par * par,unsigned char index,unsigned char val)407 static inline void SEQout(struct riva_par *par, unsigned char index,
408 unsigned char val)
409 {
410 VGA_WR08(par->riva.PVIO, 0x3c4, index);
411 VGA_WR08(par->riva.PVIO, 0x3c5, val);
412 }
413
SEQin(struct riva_par * par,unsigned char index)414 static inline unsigned char SEQin(struct riva_par *par,
415 unsigned char index)
416 {
417 VGA_WR08(par->riva.PVIO, 0x3c4, index);
418 return (VGA_RD08(par->riva.PVIO, 0x3c5));
419 }
420
ATTRout(struct riva_par * par,unsigned char index,unsigned char val)421 static inline void ATTRout(struct riva_par *par, unsigned char index,
422 unsigned char val)
423 {
424 VGA_WR08(par->riva.PCIO, 0x3c0, index);
425 VGA_WR08(par->riva.PCIO, 0x3c0, val);
426 }
427
ATTRin(struct riva_par * par,unsigned char index)428 static inline unsigned char ATTRin(struct riva_par *par,
429 unsigned char index)
430 {
431 VGA_WR08(par->riva.PCIO, 0x3c0, index);
432 return (VGA_RD08(par->riva.PCIO, 0x3c1));
433 }
434
MISCout(struct riva_par * par,unsigned char val)435 static inline void MISCout(struct riva_par *par, unsigned char val)
436 {
437 VGA_WR08(par->riva.PVIO, 0x3c2, val);
438 }
439
MISCin(struct riva_par * par)440 static inline unsigned char MISCin(struct riva_par *par)
441 {
442 return (VGA_RD08(par->riva.PVIO, 0x3cc));
443 }
444
reverse_order(u32 * l)445 static inline void reverse_order(u32 *l)
446 {
447 u8 *a = (u8 *)l;
448 a[0] = bitrev8(a[0]);
449 a[1] = bitrev8(a[1]);
450 a[2] = bitrev8(a[2]);
451 a[3] = bitrev8(a[3]);
452 }
453
454 /* ------------------------------------------------------------------------- *
455 *
456 * cursor stuff
457 *
458 * ------------------------------------------------------------------------- */
459
460 /**
461 * rivafb_load_cursor_image - load cursor image to hardware
462 * @data8: address to monochrome bitmap (1 = foreground color, 0 = background)
463 * @par: pointer to private data
464 * @w: width of cursor image in pixels
465 * @h: height of cursor image in scanlines
466 * @bg: background color (ARGB1555) - alpha bit determines opacity
467 * @fg: foreground color (ARGB1555)
468 *
469 * DESCRIPTiON:
470 * Loads cursor image based on a monochrome source and mask bitmap. The
471 * image bits determines the color of the pixel, 0 for background, 1 for
472 * foreground. Only the affected region (as determined by @w and @h
473 * parameters) will be updated.
474 *
475 * CALLED FROM:
476 * rivafb_cursor()
477 */
rivafb_load_cursor_image(struct riva_par * par,u8 * data8,u16 bg,u16 fg,u32 w,u32 h)478 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
479 u16 bg, u16 fg, u32 w, u32 h)
480 {
481 int i, j, k = 0;
482 u32 b, tmp;
483 u32 *data = (u32 *)data8;
484 bg = le16_to_cpu(bg);
485 fg = le16_to_cpu(fg);
486
487 w = (w + 1) & ~1;
488
489 for (i = 0; i < h; i++) {
490 b = *data++;
491 reverse_order(&b);
492
493 for (j = 0; j < w/2; j++) {
494 tmp = 0;
495 #if defined (__BIG_ENDIAN)
496 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
497 b <<= 1;
498 tmp |= (b & (1 << 31)) ? fg : bg;
499 b <<= 1;
500 #else
501 tmp = (b & 1) ? fg : bg;
502 b >>= 1;
503 tmp |= (b & 1) ? fg << 16 : bg << 16;
504 b >>= 1;
505 #endif
506 writel(tmp, &par->riva.CURSOR[k++]);
507 }
508 k += (MAX_CURS - w)/2;
509 }
510 }
511
512 /* ------------------------------------------------------------------------- *
513 *
514 * general utility functions
515 *
516 * ------------------------------------------------------------------------- */
517
518 /**
519 * riva_wclut - set CLUT entry
520 * @chip: pointer to RIVA_HW_INST object
521 * @regnum: register number
522 * @red: red component
523 * @green: green component
524 * @blue: blue component
525 *
526 * DESCRIPTION:
527 * Sets color register @regnum.
528 *
529 * CALLED FROM:
530 * rivafb_setcolreg()
531 */
riva_wclut(RIVA_HW_INST * chip,unsigned char regnum,unsigned char red,unsigned char green,unsigned char blue)532 static void riva_wclut(RIVA_HW_INST *chip,
533 unsigned char regnum, unsigned char red,
534 unsigned char green, unsigned char blue)
535 {
536 VGA_WR08(chip->PDIO, 0x3c8, regnum);
537 VGA_WR08(chip->PDIO, 0x3c9, red);
538 VGA_WR08(chip->PDIO, 0x3c9, green);
539 VGA_WR08(chip->PDIO, 0x3c9, blue);
540 }
541
542 /**
543 * riva_rclut - read fromCLUT register
544 * @chip: pointer to RIVA_HW_INST object
545 * @regnum: register number
546 * @red: red component
547 * @green: green component
548 * @blue: blue component
549 *
550 * DESCRIPTION:
551 * Reads red, green, and blue from color register @regnum.
552 *
553 * CALLED FROM:
554 * rivafb_setcolreg()
555 */
riva_rclut(RIVA_HW_INST * chip,unsigned char regnum,unsigned char * red,unsigned char * green,unsigned char * blue)556 static void riva_rclut(RIVA_HW_INST *chip,
557 unsigned char regnum, unsigned char *red,
558 unsigned char *green, unsigned char *blue)
559 {
560
561 VGA_WR08(chip->PDIO, 0x3c7, regnum);
562 *red = VGA_RD08(chip->PDIO, 0x3c9);
563 *green = VGA_RD08(chip->PDIO, 0x3c9);
564 *blue = VGA_RD08(chip->PDIO, 0x3c9);
565 }
566
567 /**
568 * riva_save_state - saves current chip state
569 * @par: pointer to riva_par object containing info for current riva board
570 * @regs: pointer to riva_regs object
571 *
572 * DESCRIPTION:
573 * Saves current chip state to @regs.
574 *
575 * CALLED FROM:
576 * rivafb_probe()
577 */
578 /* from GGI */
riva_save_state(struct riva_par * par,struct riva_regs * regs)579 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
580 {
581 int i;
582
583 NVTRACE_ENTER();
584 par->riva.LockUnlock(&par->riva, 0);
585
586 par->riva.UnloadStateExt(&par->riva, ®s->ext);
587
588 regs->misc_output = MISCin(par);
589
590 for (i = 0; i < NUM_CRT_REGS; i++)
591 regs->crtc[i] = CRTCin(par, i);
592
593 for (i = 0; i < NUM_ATC_REGS; i++)
594 regs->attr[i] = ATTRin(par, i);
595
596 for (i = 0; i < NUM_GRC_REGS; i++)
597 regs->gra[i] = GRAin(par, i);
598
599 for (i = 0; i < NUM_SEQ_REGS; i++)
600 regs->seq[i] = SEQin(par, i);
601 NVTRACE_LEAVE();
602 }
603
604 /**
605 * riva_load_state - loads current chip state
606 * @par: pointer to riva_par object containing info for current riva board
607 * @regs: pointer to riva_regs object
608 *
609 * DESCRIPTION:
610 * Loads chip state from @regs.
611 *
612 * CALLED FROM:
613 * riva_load_video_mode()
614 * rivafb_probe()
615 * rivafb_remove()
616 */
617 /* from GGI */
riva_load_state(struct riva_par * par,struct riva_regs * regs)618 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
619 {
620 RIVA_HW_STATE *state = ®s->ext;
621 int i;
622
623 NVTRACE_ENTER();
624 CRTCout(par, 0x11, 0x00);
625
626 par->riva.LockUnlock(&par->riva, 0);
627
628 par->riva.LoadStateExt(&par->riva, state);
629
630 MISCout(par, regs->misc_output);
631
632 for (i = 0; i < NUM_CRT_REGS; i++) {
633 switch (i) {
634 case 0x19:
635 case 0x20 ... 0x40:
636 break;
637 default:
638 CRTCout(par, i, regs->crtc[i]);
639 }
640 }
641
642 for (i = 0; i < NUM_ATC_REGS; i++)
643 ATTRout(par, i, regs->attr[i]);
644
645 for (i = 0; i < NUM_GRC_REGS; i++)
646 GRAout(par, i, regs->gra[i]);
647
648 for (i = 0; i < NUM_SEQ_REGS; i++)
649 SEQout(par, i, regs->seq[i]);
650 NVTRACE_LEAVE();
651 }
652
653 /**
654 * riva_load_video_mode - calculate timings
655 * @info: pointer to fb_info object containing info for current riva board
656 *
657 * DESCRIPTION:
658 * Calculate some timings and then send em off to riva_load_state().
659 *
660 * CALLED FROM:
661 * rivafb_set_par()
662 */
riva_load_video_mode(struct fb_info * info)663 static int riva_load_video_mode(struct fb_info *info)
664 {
665 int bpp, width, hDisplaySize, hDisplay, hStart,
666 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
667 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
668 int rc;
669 struct riva_par *par = info->par;
670 struct riva_regs newmode;
671
672 NVTRACE_ENTER();
673 /* time to calculate */
674 rivafb_blank(FB_BLANK_NORMAL, info);
675
676 bpp = info->var.bits_per_pixel;
677 if (bpp == 16 && info->var.green.length == 5)
678 bpp = 15;
679 width = info->var.xres_virtual;
680 hDisplaySize = info->var.xres;
681 hDisplay = (hDisplaySize / 8) - 1;
682 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
683 hEnd = (hDisplaySize + info->var.right_margin +
684 info->var.hsync_len) / 8 - 1;
685 hTotal = (hDisplaySize + info->var.right_margin +
686 info->var.hsync_len + info->var.left_margin) / 8 - 5;
687 hBlankStart = hDisplay;
688 hBlankEnd = hTotal + 4;
689
690 height = info->var.yres_virtual;
691 vDisplay = info->var.yres - 1;
692 vStart = info->var.yres + info->var.lower_margin - 1;
693 vEnd = info->var.yres + info->var.lower_margin +
694 info->var.vsync_len - 1;
695 vTotal = info->var.yres + info->var.lower_margin +
696 info->var.vsync_len + info->var.upper_margin + 2;
697 vBlankStart = vDisplay;
698 vBlankEnd = vTotal + 1;
699 dotClock = 1000000000 / info->var.pixclock;
700
701 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
702
703 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
704 vTotal |= 1;
705
706 if (par->FlatPanel) {
707 vStart = vTotal - 3;
708 vEnd = vTotal - 2;
709 vBlankStart = vStart;
710 hStart = hTotal - 3;
711 hEnd = hTotal - 2;
712 hBlankEnd = hTotal + 4;
713 }
714
715 newmode.crtc[0x0] = Set8Bits (hTotal);
716 newmode.crtc[0x1] = Set8Bits (hDisplay);
717 newmode.crtc[0x2] = Set8Bits (hBlankStart);
718 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
719 newmode.crtc[0x4] = Set8Bits (hStart);
720 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
721 | SetBitField (hEnd, 4: 0, 4:0);
722 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
723 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
724 | SetBitField (vDisplay, 8: 8, 1:1)
725 | SetBitField (vStart, 8: 8, 2:2)
726 | SetBitField (vBlankStart, 8: 8, 3:3)
727 | SetBit (4)
728 | SetBitField (vTotal, 9: 9, 5:5)
729 | SetBitField (vDisplay, 9: 9, 6:6)
730 | SetBitField (vStart, 9: 9, 7:7);
731 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
732 | SetBit (6);
733 newmode.crtc[0x10] = Set8Bits (vStart);
734 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
735 | SetBit (5);
736 newmode.crtc[0x12] = Set8Bits (vDisplay);
737 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
738 newmode.crtc[0x15] = Set8Bits (vBlankStart);
739 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
740
741 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
742 | SetBitField(vBlankStart,10:10,3:3)
743 | SetBitField(vStart,10:10,2:2)
744 | SetBitField(vDisplay,10:10,1:1)
745 | SetBitField(vTotal,10:10,0:0);
746 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
747 | SetBitField(hDisplay,8:8,1:1)
748 | SetBitField(hBlankStart,8:8,2:2)
749 | SetBitField(hStart,8:8,3:3);
750 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
751 | SetBitField(vDisplay,11:11,2:2)
752 | SetBitField(vStart,11:11,4:4)
753 | SetBitField(vBlankStart,11:11,6:6);
754
755 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
756 int tmp = (hTotal >> 1) & ~1;
757 newmode.ext.interlace = Set8Bits(tmp);
758 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
759 } else
760 newmode.ext.interlace = 0xff; /* interlace off */
761
762 if (par->riva.Architecture >= NV_ARCH_10)
763 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
764
765 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
766 newmode.misc_output &= ~0x40;
767 else
768 newmode.misc_output |= 0x40;
769 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
770 newmode.misc_output &= ~0x80;
771 else
772 newmode.misc_output |= 0x80;
773
774 rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
775 hDisplaySize, height, dotClock);
776 if (rc)
777 goto out;
778
779 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
780 0xfff000ff;
781 if (par->FlatPanel == 1) {
782 newmode.ext.pixel |= (1 << 7);
783 newmode.ext.scale |= (1 << 8);
784 }
785 if (par->SecondCRTC) {
786 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
787 ~0x00001000;
788 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
789 0x00001000;
790 newmode.ext.crtcOwner = 3;
791 newmode.ext.pllsel |= 0x20000800;
792 newmode.ext.vpll2 = newmode.ext.vpll;
793 } else if (par->riva.twoHeads) {
794 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
795 0x00001000;
796 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
797 ~0x00001000;
798 newmode.ext.crtcOwner = 0;
799 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
800 }
801 if (par->FlatPanel == 1) {
802 newmode.ext.pixel |= (1 << 7);
803 newmode.ext.scale |= (1 << 8);
804 }
805 newmode.ext.cursorConfig = 0x02000100;
806 par->current_state = newmode;
807 riva_load_state(par, &par->current_state);
808 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
809
810 out:
811 rivafb_blank(FB_BLANK_UNBLANK, info);
812 NVTRACE_LEAVE();
813
814 return rc;
815 }
816
riva_update_var(struct fb_var_screeninfo * var,const struct fb_videomode * modedb)817 static void riva_update_var(struct fb_var_screeninfo *var,
818 const struct fb_videomode *modedb)
819 {
820 NVTRACE_ENTER();
821 var->xres = var->xres_virtual = modedb->xres;
822 var->yres = modedb->yres;
823 if (var->yres_virtual < var->yres)
824 var->yres_virtual = var->yres;
825 var->xoffset = var->yoffset = 0;
826 var->pixclock = modedb->pixclock;
827 var->left_margin = modedb->left_margin;
828 var->right_margin = modedb->right_margin;
829 var->upper_margin = modedb->upper_margin;
830 var->lower_margin = modedb->lower_margin;
831 var->hsync_len = modedb->hsync_len;
832 var->vsync_len = modedb->vsync_len;
833 var->sync = modedb->sync;
834 var->vmode = modedb->vmode;
835 NVTRACE_LEAVE();
836 }
837
838 /**
839 * rivafb_do_maximize -
840 * @info: pointer to fb_info object containing info for current riva board
841 * @var: standard kernel fb changeable data
842 * @nom: nom
843 * @den: den
844 *
845 * DESCRIPTION:
846 * .
847 *
848 * RETURNS:
849 * -EINVAL on failure, 0 on success
850 *
851 *
852 * CALLED FROM:
853 * rivafb_check_var()
854 */
rivafb_do_maximize(struct fb_info * info,struct fb_var_screeninfo * var,int nom,int den)855 static int rivafb_do_maximize(struct fb_info *info,
856 struct fb_var_screeninfo *var,
857 int nom, int den)
858 {
859 static struct {
860 int xres, yres;
861 } modes[] = {
862 {1600, 1280},
863 {1280, 1024},
864 {1024, 768},
865 {800, 600},
866 {640, 480},
867 {-1, -1}
868 };
869 int i;
870
871 NVTRACE_ENTER();
872 /* use highest possible virtual resolution */
873 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
874 printk(KERN_WARNING PFX
875 "using maximum available virtual resolution\n");
876 for (i = 0; modes[i].xres != -1; i++) {
877 if (modes[i].xres * nom / den * modes[i].yres <
878 info->fix.smem_len)
879 break;
880 }
881 if (modes[i].xres == -1) {
882 printk(KERN_ERR PFX
883 "could not find a virtual resolution that fits into video memory!!\n");
884 NVTRACE("EXIT - EINVAL error\n");
885 return -EINVAL;
886 }
887 var->xres_virtual = modes[i].xres;
888 var->yres_virtual = modes[i].yres;
889
890 printk(KERN_INFO PFX
891 "virtual resolution set to maximum of %dx%d\n",
892 var->xres_virtual, var->yres_virtual);
893 } else if (var->xres_virtual == -1) {
894 var->xres_virtual = (info->fix.smem_len * den /
895 (nom * var->yres_virtual)) & ~15;
896 printk(KERN_WARNING PFX
897 "setting virtual X resolution to %d\n", var->xres_virtual);
898 } else if (var->yres_virtual == -1) {
899 var->xres_virtual = (var->xres_virtual + 15) & ~15;
900 var->yres_virtual = info->fix.smem_len * den /
901 (nom * var->xres_virtual);
902 printk(KERN_WARNING PFX
903 "setting virtual Y resolution to %d\n", var->yres_virtual);
904 } else {
905 var->xres_virtual = (var->xres_virtual + 15) & ~15;
906 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
907 printk(KERN_ERR PFX
908 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
909 var->xres, var->yres, var->bits_per_pixel);
910 NVTRACE("EXIT - EINVAL error\n");
911 return -EINVAL;
912 }
913 }
914
915 if (var->xres_virtual * nom / den >= 8192) {
916 printk(KERN_WARNING PFX
917 "virtual X resolution (%d) is too high, lowering to %d\n",
918 var->xres_virtual, 8192 * den / nom - 16);
919 var->xres_virtual = 8192 * den / nom - 16;
920 }
921
922 if (var->xres_virtual < var->xres) {
923 printk(KERN_ERR PFX
924 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
925 return -EINVAL;
926 }
927
928 if (var->yres_virtual < var->yres) {
929 printk(KERN_ERR PFX
930 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
931 return -EINVAL;
932 }
933 if (var->yres_virtual > 0x7fff/nom)
934 var->yres_virtual = 0x7fff/nom;
935 if (var->xres_virtual > 0x7fff/nom)
936 var->xres_virtual = 0x7fff/nom;
937 NVTRACE_LEAVE();
938 return 0;
939 }
940
941 static void
riva_set_pattern(struct riva_par * par,int clr0,int clr1,int pat0,int pat1)942 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
943 {
944 RIVA_FIFO_FREE(par->riva, Patt, 4);
945 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
946 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
947 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
948 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
949 }
950
951 /* acceleration routines */
wait_for_idle(struct riva_par * par)952 static inline void wait_for_idle(struct riva_par *par)
953 {
954 while (par->riva.Busy(&par->riva));
955 }
956
957 /*
958 * Set ROP. Translate X rop into ROP3. Internal routine.
959 */
960 static void
riva_set_rop_solid(struct riva_par * par,int rop)961 riva_set_rop_solid(struct riva_par *par, int rop)
962 {
963 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
964 RIVA_FIFO_FREE(par->riva, Rop, 1);
965 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
966
967 }
968
riva_setup_accel(struct fb_info * info)969 static void riva_setup_accel(struct fb_info *info)
970 {
971 struct riva_par *par = info->par;
972
973 RIVA_FIFO_FREE(par->riva, Clip, 2);
974 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
975 NV_WR32(&par->riva.Clip->WidthHeight, 0,
976 (info->var.xres_virtual & 0xffff) |
977 (info->var.yres_virtual << 16));
978 riva_set_rop_solid(par, 0xcc);
979 wait_for_idle(par);
980 }
981
982 /**
983 * riva_get_cmap_len - query current color map length
984 * @var: standard kernel fb changeable data
985 *
986 * DESCRIPTION:
987 * Get current color map length.
988 *
989 * RETURNS:
990 * Length of color map
991 *
992 * CALLED FROM:
993 * rivafb_setcolreg()
994 */
riva_get_cmap_len(const struct fb_var_screeninfo * var)995 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
996 {
997 int rc = 256; /* reasonable default */
998
999 switch (var->green.length) {
1000 case 8:
1001 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1002 break;
1003 case 5:
1004 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1005 break;
1006 case 6:
1007 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1008 break;
1009 default:
1010 /* should not occur */
1011 break;
1012 }
1013 return rc;
1014 }
1015
1016 /* ------------------------------------------------------------------------- *
1017 *
1018 * framebuffer operations
1019 *
1020 * ------------------------------------------------------------------------- */
1021
rivafb_open(struct fb_info * info,int user)1022 static int rivafb_open(struct fb_info *info, int user)
1023 {
1024 struct riva_par *par = info->par;
1025
1026 NVTRACE_ENTER();
1027 mutex_lock(&par->open_lock);
1028 if (!par->ref_count) {
1029 #ifdef CONFIG_X86
1030 memset(&par->state, 0, sizeof(struct vgastate));
1031 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1032 /* save the DAC for Riva128 */
1033 if (par->riva.Architecture == NV_ARCH_03)
1034 par->state.flags |= VGA_SAVE_CMAP;
1035 save_vga(&par->state);
1036 #endif
1037 /* vgaHWunlock() + riva unlock (0x7F) */
1038 CRTCout(par, 0x11, 0xFF);
1039 par->riva.LockUnlock(&par->riva, 0);
1040
1041 riva_save_state(par, &par->initial_state);
1042 }
1043 par->ref_count++;
1044 mutex_unlock(&par->open_lock);
1045 NVTRACE_LEAVE();
1046 return 0;
1047 }
1048
rivafb_release(struct fb_info * info,int user)1049 static int rivafb_release(struct fb_info *info, int user)
1050 {
1051 struct riva_par *par = info->par;
1052
1053 NVTRACE_ENTER();
1054 mutex_lock(&par->open_lock);
1055 if (!par->ref_count) {
1056 mutex_unlock(&par->open_lock);
1057 return -EINVAL;
1058 }
1059 if (par->ref_count == 1) {
1060 par->riva.LockUnlock(&par->riva, 0);
1061 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1062 riva_load_state(par, &par->initial_state);
1063 #ifdef CONFIG_X86
1064 restore_vga(&par->state);
1065 #endif
1066 par->riva.LockUnlock(&par->riva, 1);
1067 }
1068 par->ref_count--;
1069 mutex_unlock(&par->open_lock);
1070 NVTRACE_LEAVE();
1071 return 0;
1072 }
1073
rivafb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)1074 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1075 {
1076 const struct fb_videomode *mode;
1077 struct riva_par *par = info->par;
1078 int nom, den; /* translating from pixels->bytes */
1079 int mode_valid = 0;
1080
1081 NVTRACE_ENTER();
1082 if (!var->pixclock)
1083 return -EINVAL;
1084
1085 switch (var->bits_per_pixel) {
1086 case 1 ... 8:
1087 var->red.offset = var->green.offset = var->blue.offset = 0;
1088 var->red.length = var->green.length = var->blue.length = 8;
1089 var->bits_per_pixel = 8;
1090 nom = den = 1;
1091 break;
1092 case 9 ... 15:
1093 var->green.length = 5;
1094 fallthrough;
1095 case 16:
1096 var->bits_per_pixel = 16;
1097 /* The Riva128 supports RGB555 only */
1098 if (par->riva.Architecture == NV_ARCH_03)
1099 var->green.length = 5;
1100 if (var->green.length == 5) {
1101 /* 0rrrrrgg gggbbbbb */
1102 var->red.offset = 10;
1103 var->green.offset = 5;
1104 var->blue.offset = 0;
1105 var->red.length = 5;
1106 var->green.length = 5;
1107 var->blue.length = 5;
1108 } else {
1109 /* rrrrrggg gggbbbbb */
1110 var->red.offset = 11;
1111 var->green.offset = 5;
1112 var->blue.offset = 0;
1113 var->red.length = 5;
1114 var->green.length = 6;
1115 var->blue.length = 5;
1116 }
1117 nom = 2;
1118 den = 1;
1119 break;
1120 case 17 ... 32:
1121 var->red.length = var->green.length = var->blue.length = 8;
1122 var->bits_per_pixel = 32;
1123 var->red.offset = 16;
1124 var->green.offset = 8;
1125 var->blue.offset = 0;
1126 nom = 4;
1127 den = 1;
1128 break;
1129 default:
1130 printk(KERN_ERR PFX
1131 "mode %dx%dx%d rejected...color depth not supported.\n",
1132 var->xres, var->yres, var->bits_per_pixel);
1133 NVTRACE("EXIT, returning -EINVAL\n");
1134 return -EINVAL;
1135 }
1136
1137 if (!strictmode) {
1138 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1139 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1140 mode_valid = 1;
1141 }
1142
1143 /* calculate modeline if supported by monitor */
1144 if (!mode_valid && info->monspecs.gtf) {
1145 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1146 mode_valid = 1;
1147 }
1148
1149 if (!mode_valid) {
1150 mode = fb_find_best_mode(var, &info->modelist);
1151 if (mode) {
1152 riva_update_var(var, mode);
1153 mode_valid = 1;
1154 }
1155 }
1156
1157 if (!mode_valid && info->monspecs.modedb_len)
1158 return -EINVAL;
1159
1160 if (var->xres_virtual < var->xres)
1161 var->xres_virtual = var->xres;
1162 if (var->yres_virtual <= var->yres)
1163 var->yres_virtual = -1;
1164 if (rivafb_do_maximize(info, var, nom, den) < 0)
1165 return -EINVAL;
1166
1167 /* truncate xoffset and yoffset to maximum if too high */
1168 if (var->xoffset > var->xres_virtual - var->xres)
1169 var->xoffset = var->xres_virtual - var->xres - 1;
1170
1171 if (var->yoffset > var->yres_virtual - var->yres)
1172 var->yoffset = var->yres_virtual - var->yres - 1;
1173
1174 var->red.msb_right =
1175 var->green.msb_right =
1176 var->blue.msb_right =
1177 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1178 NVTRACE_LEAVE();
1179 return 0;
1180 }
1181
rivafb_set_par(struct fb_info * info)1182 static int rivafb_set_par(struct fb_info *info)
1183 {
1184 struct riva_par *par = info->par;
1185 int rc = 0;
1186
1187 NVTRACE_ENTER();
1188 /* vgaHWunlock() + riva unlock (0x7F) */
1189 CRTCout(par, 0x11, 0xFF);
1190 par->riva.LockUnlock(&par->riva, 0);
1191 rc = riva_load_video_mode(info);
1192 if (rc)
1193 goto out;
1194 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1195 riva_setup_accel(info);
1196
1197 par->cursor_reset = 1;
1198 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1199 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1200 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1201
1202 if (info->flags & FBINFO_HWACCEL_DISABLED)
1203 info->pixmap.scan_align = 1;
1204 else
1205 info->pixmap.scan_align = 4;
1206
1207 out:
1208 NVTRACE_LEAVE();
1209 return rc;
1210 }
1211
1212 /**
1213 * rivafb_pan_display
1214 * @var: standard kernel fb changeable data
1215 * @info: pointer to fb_info object containing info for current riva board
1216 *
1217 * DESCRIPTION:
1218 * Pan (or wrap, depending on the `vmode' field) the display using the
1219 * `xoffset' and `yoffset' fields of the `var' structure.
1220 * If the values don't fit, return -EINVAL.
1221 *
1222 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1223 */
rivafb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1224 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1225 struct fb_info *info)
1226 {
1227 struct riva_par *par = info->par;
1228 unsigned int base;
1229
1230 NVTRACE_ENTER();
1231 base = var->yoffset * info->fix.line_length + var->xoffset;
1232 par->riva.SetStartAddress(&par->riva, base);
1233 NVTRACE_LEAVE();
1234 return 0;
1235 }
1236
rivafb_blank(int blank,struct fb_info * info)1237 static int rivafb_blank(int blank, struct fb_info *info)
1238 {
1239 struct riva_par *par= info->par;
1240 unsigned char tmp, vesa;
1241
1242 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1243 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1244
1245 NVTRACE_ENTER();
1246
1247 if (blank)
1248 tmp |= 0x20;
1249
1250 switch (blank) {
1251 case FB_BLANK_UNBLANK:
1252 case FB_BLANK_NORMAL:
1253 break;
1254 case FB_BLANK_VSYNC_SUSPEND:
1255 vesa |= 0x80;
1256 break;
1257 case FB_BLANK_HSYNC_SUSPEND:
1258 vesa |= 0x40;
1259 break;
1260 case FB_BLANK_POWERDOWN:
1261 vesa |= 0xc0;
1262 break;
1263 }
1264
1265 SEQout(par, 0x01, tmp);
1266 CRTCout(par, 0x1a, vesa);
1267
1268 NVTRACE_LEAVE();
1269
1270 return 0;
1271 }
1272
1273 /**
1274 * rivafb_setcolreg
1275 * @regno: register index
1276 * @red: red component
1277 * @green: green component
1278 * @blue: blue component
1279 * @transp: transparency
1280 * @info: pointer to fb_info object containing info for current riva board
1281 *
1282 * DESCRIPTION:
1283 * Set a single color register. The values supplied have a 16 bit
1284 * magnitude.
1285 *
1286 * RETURNS:
1287 * Return != 0 for invalid regno.
1288 *
1289 * CALLED FROM:
1290 * fbcmap.c:fb_set_cmap()
1291 */
rivafb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1292 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1293 unsigned blue, unsigned transp,
1294 struct fb_info *info)
1295 {
1296 struct riva_par *par = info->par;
1297 RIVA_HW_INST *chip = &par->riva;
1298 int i;
1299
1300 if (regno >= riva_get_cmap_len(&info->var))
1301 return -EINVAL;
1302
1303 if (info->var.grayscale) {
1304 /* gray = 0.30*R + 0.59*G + 0.11*B */
1305 red = green = blue =
1306 (red * 77 + green * 151 + blue * 28) >> 8;
1307 }
1308
1309 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1310 ((u32 *) info->pseudo_palette)[regno] =
1311 (regno << info->var.red.offset) |
1312 (regno << info->var.green.offset) |
1313 (regno << info->var.blue.offset);
1314 /*
1315 * The Riva128 2D engine requires color information in
1316 * TrueColor format even if framebuffer is in DirectColor
1317 */
1318 if (par->riva.Architecture == NV_ARCH_03) {
1319 switch (info->var.bits_per_pixel) {
1320 case 16:
1321 par->palette[regno] = ((red & 0xf800) >> 1) |
1322 ((green & 0xf800) >> 6) |
1323 ((blue & 0xf800) >> 11);
1324 break;
1325 case 32:
1326 par->palette[regno] = ((red & 0xff00) << 8) |
1327 ((green & 0xff00)) |
1328 ((blue & 0xff00) >> 8);
1329 break;
1330 }
1331 }
1332 }
1333
1334 switch (info->var.bits_per_pixel) {
1335 case 8:
1336 /* "transparent" stuff is completely ignored. */
1337 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1338 break;
1339 case 16:
1340 if (info->var.green.length == 5) {
1341 for (i = 0; i < 8; i++) {
1342 riva_wclut(chip, regno*8+i, red >> 8,
1343 green >> 8, blue >> 8);
1344 }
1345 } else {
1346 u8 r, g, b;
1347
1348 if (regno < 32) {
1349 for (i = 0; i < 8; i++) {
1350 riva_wclut(chip, regno*8+i,
1351 red >> 8, green >> 8,
1352 blue >> 8);
1353 }
1354 }
1355 riva_rclut(chip, regno*4, &r, &g, &b);
1356 for (i = 0; i < 4; i++)
1357 riva_wclut(chip, regno*4+i, r,
1358 green >> 8, b);
1359 }
1360 break;
1361 case 32:
1362 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1363 break;
1364 default:
1365 /* do nothing */
1366 break;
1367 }
1368 return 0;
1369 }
1370
1371 /**
1372 * rivafb_fillrect - hardware accelerated color fill function
1373 * @info: pointer to fb_info structure
1374 * @rect: pointer to fb_fillrect structure
1375 *
1376 * DESCRIPTION:
1377 * This function fills up a region of framebuffer memory with a solid
1378 * color with a choice of two different ROP's, copy or invert.
1379 *
1380 * CALLED FROM:
1381 * framebuffer hook
1382 */
rivafb_fillrect(struct fb_info * info,const struct fb_fillrect * rect)1383 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1384 {
1385 struct riva_par *par = info->par;
1386 u_int color, rop = 0;
1387
1388 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1389 cfb_fillrect(info, rect);
1390 return;
1391 }
1392
1393 if (info->var.bits_per_pixel == 8)
1394 color = rect->color;
1395 else {
1396 if (par->riva.Architecture != NV_ARCH_03)
1397 color = ((u32 *)info->pseudo_palette)[rect->color];
1398 else
1399 color = par->palette[rect->color];
1400 }
1401
1402 switch (rect->rop) {
1403 case ROP_XOR:
1404 rop = 0x66;
1405 break;
1406 case ROP_COPY:
1407 default:
1408 rop = 0xCC;
1409 break;
1410 }
1411
1412 riva_set_rop_solid(par, rop);
1413
1414 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1415 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1416
1417 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1418 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1419 (rect->dx << 16) | rect->dy);
1420 mb();
1421 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1422 (rect->width << 16) | rect->height);
1423 mb();
1424 riva_set_rop_solid(par, 0xcc);
1425
1426 }
1427
1428 /**
1429 * rivafb_copyarea - hardware accelerated blit function
1430 * @info: pointer to fb_info structure
1431 * @region: pointer to fb_copyarea structure
1432 *
1433 * DESCRIPTION:
1434 * This copies an area of pixels from one location to another
1435 *
1436 * CALLED FROM:
1437 * framebuffer hook
1438 */
rivafb_copyarea(struct fb_info * info,const struct fb_copyarea * region)1439 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1440 {
1441 struct riva_par *par = info->par;
1442
1443 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1444 cfb_copyarea(info, region);
1445 return;
1446 }
1447
1448 RIVA_FIFO_FREE(par->riva, Blt, 3);
1449 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1450 (region->sy << 16) | region->sx);
1451 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1452 (region->dy << 16) | region->dx);
1453 mb();
1454 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1455 (region->height << 16) | region->width);
1456 mb();
1457 }
1458
convert_bgcolor_16(u32 * col)1459 static inline void convert_bgcolor_16(u32 *col)
1460 {
1461 *col = ((*col & 0x0000F800) << 8)
1462 | ((*col & 0x00007E0) << 5)
1463 | ((*col & 0x0000001F) << 3)
1464 | 0xFF000000;
1465 mb();
1466 }
1467
1468 /**
1469 * rivafb_imageblit: hardware accelerated color expand function
1470 * @info: pointer to fb_info structure
1471 * @image: pointer to fb_image structure
1472 *
1473 * DESCRIPTION:
1474 * If the source is a monochrome bitmap, the function fills up a a region
1475 * of framebuffer memory with pixels whose color is determined by the bit
1476 * setting of the bitmap, 1 - foreground, 0 - background.
1477 *
1478 * If the source is not a monochrome bitmap, color expansion is not done.
1479 * In this case, it is channeled to a software function.
1480 *
1481 * CALLED FROM:
1482 * framebuffer hook
1483 */
rivafb_imageblit(struct fb_info * info,const struct fb_image * image)1484 static void rivafb_imageblit(struct fb_info *info,
1485 const struct fb_image *image)
1486 {
1487 struct riva_par *par = info->par;
1488 u32 fgx = 0, bgx = 0, width, tmp;
1489 u8 *cdat = (u8 *) image->data;
1490 volatile u32 __iomem *d;
1491 int i, size;
1492
1493 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1494 cfb_imageblit(info, image);
1495 return;
1496 }
1497
1498 switch (info->var.bits_per_pixel) {
1499 case 8:
1500 fgx = image->fg_color;
1501 bgx = image->bg_color;
1502 break;
1503 case 16:
1504 case 32:
1505 if (par->riva.Architecture != NV_ARCH_03) {
1506 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1507 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1508 } else {
1509 fgx = par->palette[image->fg_color];
1510 bgx = par->palette[image->bg_color];
1511 }
1512 if (info->var.green.length == 6)
1513 convert_bgcolor_16(&bgx);
1514 break;
1515 }
1516
1517 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1518 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1519 (image->dy << 16) | (image->dx & 0xFFFF));
1520 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1521 (((image->dy + image->height) << 16) |
1522 ((image->dx + image->width) & 0xffff)));
1523 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1524 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1525 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1526 (image->height << 16) | ((image->width + 31) & ~31));
1527 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1528 (image->height << 16) | ((image->width + 31) & ~31));
1529 NV_WR32(&par->riva.Bitmap->PointE, 0,
1530 (image->dy << 16) | (image->dx & 0xFFFF));
1531
1532 d = &par->riva.Bitmap->MonochromeData01E;
1533
1534 width = (image->width + 31)/32;
1535 size = width * image->height;
1536 while (size >= 16) {
1537 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1538 for (i = 0; i < 16; i++) {
1539 tmp = *((u32 *)cdat);
1540 cdat = (u8 *)((u32 *)cdat + 1);
1541 reverse_order(&tmp);
1542 NV_WR32(d, i*4, tmp);
1543 }
1544 size -= 16;
1545 }
1546 if (size) {
1547 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1548 for (i = 0; i < size; i++) {
1549 tmp = *((u32 *) cdat);
1550 cdat = (u8 *)((u32 *)cdat + 1);
1551 reverse_order(&tmp);
1552 NV_WR32(d, i*4, tmp);
1553 }
1554 }
1555 }
1556
1557 /**
1558 * rivafb_cursor - hardware cursor function
1559 * @info: pointer to info structure
1560 * @cursor: pointer to fbcursor structure
1561 *
1562 * DESCRIPTION:
1563 * A cursor function that supports displaying a cursor image via hardware.
1564 * Within the kernel, copy and invert rops are supported. If exported
1565 * to user space, only the copy rop will be supported.
1566 *
1567 * CALLED FROM
1568 * framebuffer hook
1569 */
rivafb_cursor(struct fb_info * info,struct fb_cursor * cursor)1570 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1571 {
1572 struct riva_par *par = info->par;
1573 u8 data[MAX_CURS * MAX_CURS/8];
1574 int i, set = cursor->set;
1575 u16 fg, bg;
1576
1577 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1578 return -ENXIO;
1579
1580 par->riva.ShowHideCursor(&par->riva, 0);
1581
1582 if (par->cursor_reset) {
1583 set = FB_CUR_SETALL;
1584 par->cursor_reset = 0;
1585 }
1586
1587 if (set & FB_CUR_SETSIZE)
1588 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1589
1590 if (set & FB_CUR_SETPOS) {
1591 u32 xx, yy, temp;
1592
1593 yy = cursor->image.dy - info->var.yoffset;
1594 xx = cursor->image.dx - info->var.xoffset;
1595 temp = xx & 0xFFFF;
1596 temp |= yy << 16;
1597
1598 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1599 }
1600
1601
1602 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1603 u32 bg_idx = cursor->image.bg_color;
1604 u32 fg_idx = cursor->image.fg_color;
1605 u32 s_pitch = (cursor->image.width+7) >> 3;
1606 u32 d_pitch = MAX_CURS/8;
1607 u8 *dat = (u8 *) cursor->image.data;
1608 u8 *msk = (u8 *) cursor->mask;
1609 u8 *src;
1610
1611 src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
1612
1613 if (src) {
1614 switch (cursor->rop) {
1615 case ROP_XOR:
1616 for (i = 0; i < s_pitch * cursor->image.height; i++)
1617 src[i] = dat[i] ^ msk[i];
1618 break;
1619 case ROP_COPY:
1620 default:
1621 for (i = 0; i < s_pitch * cursor->image.height; i++)
1622 src[i] = dat[i] & msk[i];
1623 break;
1624 }
1625
1626 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1627 cursor->image.height);
1628
1629 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1630 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1631 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1632 1 << 15;
1633
1634 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1635 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1636 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1637 1 << 15;
1638
1639 par->riva.LockUnlock(&par->riva, 0);
1640
1641 rivafb_load_cursor_image(par, data, bg, fg,
1642 cursor->image.width,
1643 cursor->image.height);
1644 kfree(src);
1645 }
1646 }
1647
1648 if (cursor->enable)
1649 par->riva.ShowHideCursor(&par->riva, 1);
1650
1651 return 0;
1652 }
1653
rivafb_sync(struct fb_info * info)1654 static int rivafb_sync(struct fb_info *info)
1655 {
1656 struct riva_par *par = info->par;
1657
1658 wait_for_idle(par);
1659 return 0;
1660 }
1661
1662 /* ------------------------------------------------------------------------- *
1663 *
1664 * initialization helper functions
1665 *
1666 * ------------------------------------------------------------------------- */
1667
1668 /* kernel interface */
1669 static const struct fb_ops riva_fb_ops = {
1670 .owner = THIS_MODULE,
1671 .fb_open = rivafb_open,
1672 .fb_release = rivafb_release,
1673 .fb_check_var = rivafb_check_var,
1674 .fb_set_par = rivafb_set_par,
1675 .fb_setcolreg = rivafb_setcolreg,
1676 .fb_pan_display = rivafb_pan_display,
1677 .fb_blank = rivafb_blank,
1678 .fb_fillrect = rivafb_fillrect,
1679 .fb_copyarea = rivafb_copyarea,
1680 .fb_imageblit = rivafb_imageblit,
1681 .fb_cursor = rivafb_cursor,
1682 .fb_sync = rivafb_sync,
1683 };
1684
riva_set_fbinfo(struct fb_info * info)1685 static int riva_set_fbinfo(struct fb_info *info)
1686 {
1687 unsigned int cmap_len;
1688 struct riva_par *par = info->par;
1689
1690 NVTRACE_ENTER();
1691 info->flags = FBINFO_HWACCEL_XPAN
1692 | FBINFO_HWACCEL_YPAN
1693 | FBINFO_HWACCEL_COPYAREA
1694 | FBINFO_HWACCEL_FILLRECT
1695 | FBINFO_HWACCEL_IMAGEBLIT;
1696
1697 /* Accel seems to not work properly on NV30 yet...*/
1698 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1699 printk(KERN_DEBUG PFX "disabling acceleration\n");
1700 info->flags |= FBINFO_HWACCEL_DISABLED;
1701 }
1702
1703 info->var = rivafb_default_var;
1704 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1705 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1706
1707 info->pseudo_palette = par->pseudo_palette;
1708
1709 cmap_len = riva_get_cmap_len(&info->var);
1710 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1711
1712 info->pixmap.size = 8 * 1024;
1713 info->pixmap.buf_align = 4;
1714 info->pixmap.access_align = 32;
1715 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1716 info->var.yres_virtual = -1;
1717 NVTRACE_LEAVE();
1718 return (rivafb_check_var(&info->var, info));
1719 }
1720
riva_get_EDID_OF(struct fb_info * info,struct pci_dev * pd)1721 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1722 {
1723 struct riva_par *par = info->par;
1724 struct device_node *dp;
1725 const unsigned char *pedid = NULL;
1726 const unsigned char *disptype = NULL;
1727 static char *propnames[] = {
1728 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1729 int i;
1730
1731 NVTRACE_ENTER();
1732 dp = pci_device_to_OF_node(pd);
1733 for (; dp != NULL; dp = dp->child) {
1734 disptype = of_get_property(dp, "display-type", NULL);
1735 if (disptype == NULL)
1736 continue;
1737 if (strncmp(disptype, "LCD", 3) != 0)
1738 continue;
1739 for (i = 0; propnames[i] != NULL; ++i) {
1740 pedid = of_get_property(dp, propnames[i], NULL);
1741 if (pedid != NULL) {
1742 par->EDID = (unsigned char *)pedid;
1743 NVTRACE("LCD found.\n");
1744 return 1;
1745 }
1746 }
1747 }
1748 NVTRACE_LEAVE();
1749 return 0;
1750 }
1751
1752 #if defined(CONFIG_FB_RIVA_I2C)
riva_get_EDID_i2c(struct fb_info * info)1753 static int riva_get_EDID_i2c(struct fb_info *info)
1754 {
1755 struct riva_par *par = info->par;
1756 struct fb_var_screeninfo var;
1757 int i;
1758
1759 NVTRACE_ENTER();
1760 par->riva.LockUnlock(&par->riva, 0);
1761 riva_create_i2c_busses(par);
1762 for (i = 0; i < 3; i++) {
1763 if (!par->chan[i].par)
1764 continue;
1765 riva_probe_i2c_connector(par, i, &par->EDID);
1766 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1767 printk(PFX "Found EDID Block from BUS %i\n", i);
1768 break;
1769 }
1770 }
1771
1772 NVTRACE_LEAVE();
1773 return (par->EDID) ? 1 : 0;
1774 }
1775 #endif /* CONFIG_FB_RIVA_I2C */
1776
riva_update_default_var(struct fb_var_screeninfo * var,struct fb_info * info)1777 static void riva_update_default_var(struct fb_var_screeninfo *var,
1778 struct fb_info *info)
1779 {
1780 struct fb_monspecs *specs = &info->monspecs;
1781 struct fb_videomode modedb;
1782
1783 NVTRACE_ENTER();
1784 /* respect mode options */
1785 if (mode_option) {
1786 fb_find_mode(var, info, mode_option,
1787 specs->modedb, specs->modedb_len,
1788 NULL, 8);
1789 } else if (specs->modedb != NULL) {
1790 /* get first mode in database as fallback */
1791 modedb = specs->modedb[0];
1792 /* get preferred timing */
1793 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1794 int i;
1795
1796 for (i = 0; i < specs->modedb_len; i++) {
1797 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1798 modedb = specs->modedb[i];
1799 break;
1800 }
1801 }
1802 }
1803 var->bits_per_pixel = 8;
1804 riva_update_var(var, &modedb);
1805 }
1806 NVTRACE_LEAVE();
1807 }
1808
1809
riva_get_EDID(struct fb_info * info,struct pci_dev * pdev)1810 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1811 {
1812 NVTRACE_ENTER();
1813 if (riva_get_EDID_OF(info, pdev)) {
1814 NVTRACE_LEAVE();
1815 return;
1816 }
1817 if (IS_ENABLED(CONFIG_OF))
1818 printk(PFX "could not retrieve EDID from OF\n");
1819 #if defined(CONFIG_FB_RIVA_I2C)
1820 if (!riva_get_EDID_i2c(info))
1821 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1822 #endif
1823 NVTRACE_LEAVE();
1824 }
1825
1826
riva_get_edidinfo(struct fb_info * info)1827 static void riva_get_edidinfo(struct fb_info *info)
1828 {
1829 struct fb_var_screeninfo *var = &rivafb_default_var;
1830 struct riva_par *par = info->par;
1831
1832 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1833 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1834 &info->modelist);
1835 riva_update_default_var(var, info);
1836
1837 /* if user specified flatpanel, we respect that */
1838 if (info->monspecs.input & FB_DISP_DDI)
1839 par->FlatPanel = 1;
1840 }
1841
1842 /* ------------------------------------------------------------------------- *
1843 *
1844 * PCI bus
1845 *
1846 * ------------------------------------------------------------------------- */
1847
riva_get_arch(struct pci_dev * pd)1848 static u32 riva_get_arch(struct pci_dev *pd)
1849 {
1850 u32 arch = 0;
1851
1852 switch (pd->device & 0x0ff0) {
1853 case 0x0100: /* GeForce 256 */
1854 case 0x0110: /* GeForce2 MX */
1855 case 0x0150: /* GeForce2 */
1856 case 0x0170: /* GeForce4 MX */
1857 case 0x0180: /* GeForce4 MX (8x AGP) */
1858 case 0x01A0: /* nForce */
1859 case 0x01F0: /* nForce2 */
1860 arch = NV_ARCH_10;
1861 break;
1862 case 0x0200: /* GeForce3 */
1863 case 0x0250: /* GeForce4 Ti */
1864 case 0x0280: /* GeForce4 Ti (8x AGP) */
1865 arch = NV_ARCH_20;
1866 break;
1867 case 0x0300: /* GeForceFX 5800 */
1868 case 0x0310: /* GeForceFX 5600 */
1869 case 0x0320: /* GeForceFX 5200 */
1870 case 0x0330: /* GeForceFX 5900 */
1871 case 0x0340: /* GeForceFX 5700 */
1872 arch = NV_ARCH_30;
1873 break;
1874 case 0x0020: /* TNT, TNT2 */
1875 arch = NV_ARCH_04;
1876 break;
1877 case 0x0010: /* Riva128 */
1878 arch = NV_ARCH_03;
1879 break;
1880 default: /* unknown architecture */
1881 break;
1882 }
1883 return arch;
1884 }
1885
rivafb_probe(struct pci_dev * pd,const struct pci_device_id * ent)1886 static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1887 {
1888 struct riva_par *default_par;
1889 struct fb_info *info;
1890 int ret;
1891
1892 NVTRACE_ENTER();
1893 assert(pd != NULL);
1894
1895 ret = aperture_remove_conflicting_pci_devices(pd, "rivafb");
1896 if (ret)
1897 return ret;
1898
1899 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1900 if (!info) {
1901 ret = -ENOMEM;
1902 goto err_ret;
1903 }
1904 default_par = info->par;
1905 default_par->pdev = pd;
1906
1907 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1908 if (info->pixmap.addr == NULL) {
1909 ret = -ENOMEM;
1910 goto err_framebuffer_release;
1911 }
1912
1913 ret = pci_enable_device(pd);
1914 if (ret < 0) {
1915 printk(KERN_ERR PFX "cannot enable PCI device\n");
1916 goto err_free_pixmap;
1917 }
1918
1919 ret = pci_request_regions(pd, "rivafb");
1920 if (ret < 0) {
1921 printk(KERN_ERR PFX "cannot request PCI regions\n");
1922 goto err_disable_device;
1923 }
1924
1925 mutex_init(&default_par->open_lock);
1926 default_par->riva.Architecture = riva_get_arch(pd);
1927
1928 default_par->Chipset = (pd->vendor << 16) | pd->device;
1929 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1930
1931 if(default_par->riva.Architecture == 0) {
1932 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1933 ret=-ENODEV;
1934 goto err_release_region;
1935 }
1936 if(default_par->riva.Architecture == NV_ARCH_10 ||
1937 default_par->riva.Architecture == NV_ARCH_20 ||
1938 default_par->riva.Architecture == NV_ARCH_30) {
1939 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1940 } else {
1941 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1942 }
1943
1944 default_par->FlatPanel = flatpanel;
1945 if (flatpanel == 1)
1946 printk(KERN_INFO PFX "flatpanel support enabled\n");
1947 default_par->forceCRTC = forceCRTC;
1948
1949 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1950 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1951
1952 {
1953 /* enable IO and mem if not already done */
1954 unsigned short cmd;
1955
1956 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1957 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1958 pci_write_config_word(pd, PCI_COMMAND, cmd);
1959 }
1960
1961 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1962 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1963
1964 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1965 rivafb_fix.mmio_len);
1966 if (!default_par->ctrl_base) {
1967 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1968 ret = -EIO;
1969 goto err_release_region;
1970 }
1971
1972 switch (default_par->riva.Architecture) {
1973 case NV_ARCH_03:
1974 /* Riva128's PRAMIN is in the "framebuffer" space
1975 * Since these cards were never made with more than 8 megabytes
1976 * we can safely allocate this separately.
1977 */
1978 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1979 if (!default_par->riva.PRAMIN) {
1980 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1981 ret = -EIO;
1982 goto err_iounmap_ctrl_base;
1983 }
1984 break;
1985 case NV_ARCH_04:
1986 case NV_ARCH_10:
1987 case NV_ARCH_20:
1988 case NV_ARCH_30:
1989 default_par->riva.PCRTC0 =
1990 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
1991 default_par->riva.PRAMIN =
1992 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
1993 break;
1994 }
1995 riva_common_setup(default_par);
1996
1997 if (default_par->riva.Architecture == NV_ARCH_03) {
1998 default_par->riva.PCRTC = default_par->riva.PCRTC0
1999 = default_par->riva.PGRAPH;
2000 }
2001
2002 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2003 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2004 info->screen_base = ioremap_wc(rivafb_fix.smem_start,
2005 rivafb_fix.smem_len);
2006 if (!info->screen_base) {
2007 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2008 ret = -EIO;
2009 goto err_iounmap_pramin;
2010 }
2011
2012 if (!nomtrr)
2013 default_par->wc_cookie =
2014 arch_phys_wc_add(rivafb_fix.smem_start,
2015 rivafb_fix.smem_len);
2016
2017 info->fbops = &riva_fb_ops;
2018 info->fix = rivafb_fix;
2019 riva_get_EDID(info, pd);
2020 riva_get_edidinfo(info);
2021
2022 ret=riva_set_fbinfo(info);
2023 if (ret < 0) {
2024 printk(KERN_ERR PFX "error setting initial video mode\n");
2025 goto err_iounmap_screen_base;
2026 }
2027
2028 fb_destroy_modedb(info->monspecs.modedb);
2029 info->monspecs.modedb = NULL;
2030
2031 pci_set_drvdata(pd, info);
2032
2033 ret = register_framebuffer(info);
2034 if (ret < 0) {
2035 printk(KERN_ERR PFX
2036 "error registering riva framebuffer\n");
2037 goto err_iounmap_screen_base;
2038 }
2039
2040 if (backlight)
2041 riva_bl_init(info->par);
2042
2043 printk(KERN_INFO PFX
2044 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2045 info->fix.id,
2046 RIVAFB_VERSION,
2047 info->fix.smem_len / (1024 * 1024),
2048 info->fix.smem_start);
2049
2050 NVTRACE_LEAVE();
2051 return 0;
2052
2053 err_iounmap_screen_base:
2054 #ifdef CONFIG_FB_RIVA_I2C
2055 riva_delete_i2c_busses(info->par);
2056 #endif
2057 iounmap(info->screen_base);
2058 err_iounmap_pramin:
2059 if (default_par->riva.Architecture == NV_ARCH_03)
2060 iounmap(default_par->riva.PRAMIN);
2061 err_iounmap_ctrl_base:
2062 iounmap(default_par->ctrl_base);
2063 err_release_region:
2064 pci_release_regions(pd);
2065 err_disable_device:
2066 err_free_pixmap:
2067 kfree(info->pixmap.addr);
2068 err_framebuffer_release:
2069 framebuffer_release(info);
2070 err_ret:
2071 return ret;
2072 }
2073
rivafb_remove(struct pci_dev * pd)2074 static void rivafb_remove(struct pci_dev *pd)
2075 {
2076 struct fb_info *info = pci_get_drvdata(pd);
2077 struct riva_par *par = info->par;
2078
2079 NVTRACE_ENTER();
2080
2081 #ifdef CONFIG_FB_RIVA_I2C
2082 riva_delete_i2c_busses(par);
2083 kfree(par->EDID);
2084 #endif
2085
2086 riva_bl_exit(info);
2087 unregister_framebuffer(info);
2088
2089 arch_phys_wc_del(par->wc_cookie);
2090 iounmap(par->ctrl_base);
2091 iounmap(info->screen_base);
2092 if (par->riva.Architecture == NV_ARCH_03)
2093 iounmap(par->riva.PRAMIN);
2094 pci_release_regions(pd);
2095 kfree(info->pixmap.addr);
2096 framebuffer_release(info);
2097 NVTRACE_LEAVE();
2098 }
2099
2100 /* ------------------------------------------------------------------------- *
2101 *
2102 * initialization
2103 *
2104 * ------------------------------------------------------------------------- */
2105
2106 #ifndef MODULE
rivafb_setup(char * options)2107 static int rivafb_setup(char *options)
2108 {
2109 char *this_opt;
2110
2111 NVTRACE_ENTER();
2112 if (!options || !*options)
2113 return 0;
2114
2115 while ((this_opt = strsep(&options, ",")) != NULL) {
2116 if (!strncmp(this_opt, "forceCRTC", 9)) {
2117 char *p;
2118
2119 p = this_opt + 9;
2120 if (!*p || !*(++p)) continue;
2121 forceCRTC = *p - '0';
2122 if (forceCRTC < 0 || forceCRTC > 1)
2123 forceCRTC = -1;
2124 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2125 flatpanel = 1;
2126 } else if (!strncmp(this_opt, "backlight:", 10)) {
2127 backlight = simple_strtoul(this_opt+10, NULL, 0);
2128 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2129 nomtrr = 1;
2130 } else if (!strncmp(this_opt, "strictmode", 10)) {
2131 strictmode = 1;
2132 } else if (!strncmp(this_opt, "noaccel", 7)) {
2133 noaccel = 1;
2134 } else
2135 mode_option = this_opt;
2136 }
2137 NVTRACE_LEAVE();
2138 return 0;
2139 }
2140 #endif /* !MODULE */
2141
2142 static struct pci_driver rivafb_driver = {
2143 .name = "rivafb",
2144 .id_table = rivafb_pci_tbl,
2145 .probe = rivafb_probe,
2146 .remove = rivafb_remove,
2147 };
2148
2149
2150
2151 /* ------------------------------------------------------------------------- *
2152 *
2153 * modularization
2154 *
2155 * ------------------------------------------------------------------------- */
2156
rivafb_init(void)2157 static int rivafb_init(void)
2158 {
2159 #ifndef MODULE
2160 char *option = NULL;
2161 #endif
2162
2163 if (fb_modesetting_disabled("rivafb"))
2164 return -ENODEV;
2165
2166 #ifndef MODULE
2167 if (fb_get_options("rivafb", &option))
2168 return -ENODEV;
2169 rivafb_setup(option);
2170 #endif
2171 return pci_register_driver(&rivafb_driver);
2172 }
2173
2174
2175 module_init(rivafb_init);
2176
rivafb_exit(void)2177 static void __exit rivafb_exit(void)
2178 {
2179 pci_unregister_driver(&rivafb_driver);
2180 }
2181
2182 module_exit(rivafb_exit);
2183
2184 module_param(noaccel, bool, 0);
2185 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2186 module_param(flatpanel, int, 0);
2187 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2188 module_param(forceCRTC, int, 0);
2189 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2190 module_param(nomtrr, bool, 0);
2191 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2192 module_param(strictmode, bool, 0);
2193 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2194
2195 MODULE_AUTHOR("Ani Joshi, maintainer");
2196 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2197 MODULE_LICENSE("GPL");
2198