1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
3  *
4  * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5  * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
6  */
7 
8 #include <linux/kernel.h>
9 
10 #include "zd_rf.h"
11 #include "zd_usb.h"
12 #include "zd_chip.h"
13 
14 static const u32 rf2959_table[][2] = {
15 	RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
16 	RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
17 	RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
18 	RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
19 	RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
20 	RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
21 	RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
22 	RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
23 	RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
24 	RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
25 	RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
26 	RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
27 	RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
28 	RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
29 };
30 
31 #if 0
32 static int bits(u32 rw, int from, int to)
33 {
34 	rw &= ~(0xffffffffU << (to+1));
35 	rw >>= from;
36 	return rw;
37 }
38 
39 static int bit(u32 rw, int bit)
40 {
41 	return bits(rw, bit, bit);
42 }
43 
44 static void dump_regwrite(u32 rw)
45 {
46 	int reg = bits(rw, 18, 22);
47 	int rw_flag = bits(rw, 23, 23);
48 	PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
49 
50 	switch (reg) {
51 	case 0:
52 		PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d"
53 		       " if_vco_reg_en %d if_vga_en %d",
54 		       bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
55 		       bit(rw, 0));
56 		break;
57 	case 1:
58 		PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
59 		       " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
60 		       " ifloopc %d dac1 %d",
61 		       bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
62 		       bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
63 		       bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
64 		break;
65 	case 2:
66 		PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
67 		       bits(rw, 6, 17), bits(rw, 0, 5));
68 		break;
69 	case 3:
70 		PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
71 		break;
72 	case 4:
73 		PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
74 		       bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
75 		break;
76 	case 5:
77 		PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
78 		       " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
79 		       " dac %d",
80 		       bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
81 		       bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
82 		       bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
83 		break;
84 	case 6:
85 		PDEBUG("reg6 RFPLL2 n %d num %d",
86 		       bits(rw, 6, 17), bits(rw, 0, 5));
87 		break;
88 	case 7:
89 		PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
90 		break;
91 	case 8:
92 		PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
93 		       bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
94 		break;
95 	case 9:
96 		PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
97 		       bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
98 		       bits(rw, 0, 2));
99 		break;
100 	case 10:
101 		PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
102 		       " rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
103 		       " intbiasen %d tybypass %d",
104 		       bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
105 		       bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
106 		       bit(rw, 1), bit(rw, 0));
107 		break;
108 	case 11:
109 		PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
110 			" tx_delay %d",
111 			bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
112 			bits(rw, 0, 2));
113 		break;
114 	case 12:
115 		PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
116 		       bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
117 		break;
118 	case 13:
119 		PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
120 		       " lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
121 		       " rf_biasvco %d",
122 		       bit(rw, 17), bit(rw, 16), bit(rw, 15),
123 		       bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
124 		       bits(rw, 0, 2));
125 		break;
126 	case 14:
127 		PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
128 		       " tx_acal %d tx_pcal %d",
129 		       bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
130 		       bits(rw, 0, 3));
131 		break;
132 	}
133 }
134 #endif /* 0 */
135 
rf2959_init_hw(struct zd_rf * rf)136 static int rf2959_init_hw(struct zd_rf *rf)
137 {
138 	int r;
139 	struct zd_chip *chip = zd_rf_to_chip(rf);
140 
141 	static const struct zd_ioreq16 ioreqs[] = {
142 		{ ZD_CR2,   0x1E }, { ZD_CR9,   0x20 }, { ZD_CR10,  0x89 },
143 		{ ZD_CR11,  0x00 }, { ZD_CR15,  0xD0 }, { ZD_CR17,  0x68 },
144 		{ ZD_CR19,  0x4a }, { ZD_CR20,  0x0c }, { ZD_CR21,  0x0E },
145 		{ ZD_CR23,  0x48 },
146 		/* normal size for cca threshold */
147 		{ ZD_CR24,  0x14 },
148 		/* { ZD_CR24,  0x20 }, */
149 		{ ZD_CR26,  0x90 }, { ZD_CR27,  0x30 }, { ZD_CR29,  0x20 },
150 		{ ZD_CR31,  0xb2 }, { ZD_CR32,  0x43 }, { ZD_CR33,  0x28 },
151 		{ ZD_CR38,  0x30 }, { ZD_CR34,  0x0f }, { ZD_CR35,  0xF0 },
152 		{ ZD_CR41,  0x2a }, { ZD_CR46,  0x7F }, { ZD_CR47,  0x1E },
153 		{ ZD_CR51,  0xc5 }, { ZD_CR52,  0xc5 }, { ZD_CR53,  0xc5 },
154 		{ ZD_CR79,  0x58 }, { ZD_CR80,  0x30 }, { ZD_CR81,  0x30 },
155 		{ ZD_CR82,  0x00 }, { ZD_CR83,  0x24 }, { ZD_CR84,  0x04 },
156 		{ ZD_CR85,  0x00 }, { ZD_CR86,  0x10 }, { ZD_CR87,  0x2A },
157 		{ ZD_CR88,  0x10 }, { ZD_CR89,  0x24 }, { ZD_CR90,  0x18 },
158 		/* { ZD_CR91,  0x18 }, */
159 		/* should solve continuous CTS frame problems */
160 		{ ZD_CR91,  0x00 },
161 		{ ZD_CR92,  0x0a }, { ZD_CR93,  0x00 }, { ZD_CR94,  0x01 },
162 		{ ZD_CR95,  0x00 }, { ZD_CR96,  0x40 }, { ZD_CR97,  0x37 },
163 		{ ZD_CR98,  0x05 }, { ZD_CR99,  0x28 }, { ZD_CR100, 0x00 },
164 		{ ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 },
165 		{ ZD_CR104, 0x18 }, { ZD_CR105, 0x12 },
166 		/* normal size */
167 		{ ZD_CR106, 0x1a },
168 		/* { ZD_CR106, 0x22 }, */
169 		{ ZD_CR107, 0x24 }, { ZD_CR108, 0x0a }, { ZD_CR109, 0x13 },
170 		{ ZD_CR110, 0x2F }, { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 },
171 		{ ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, { ZD_CR115, 0x40 },
172 		{ ZD_CR116, 0x40 }, { ZD_CR117, 0xF0 }, { ZD_CR118, 0xF0 },
173 		{ ZD_CR119, 0x16 },
174 		/* no TX continuation */
175 		{ ZD_CR122, 0x00 },
176 		/* { ZD_CR122, 0xff }, */
177 		{ ZD_CR127, 0x03 }, { ZD_CR131, 0x08 }, { ZD_CR138, 0x28 },
178 		{ ZD_CR148, 0x44 }, { ZD_CR150, 0x10 }, { ZD_CR169, 0xBB },
179 		{ ZD_CR170, 0xBB },
180 	};
181 
182 	static const u32 rv[] = {
183 		0x000007,  /* REG0(CFG1) */
184 		0x07dd43,  /* REG1(IFPLL1) */
185 		0x080959,  /* REG2(IFPLL2) */
186 		0x0e6666,
187 		0x116a57,  /* REG4 */
188 		0x17dd43,  /* REG5 */
189 		0x1819f9,  /* REG6 */
190 		0x1e6666,
191 		0x214554,
192 		0x25e7fa,
193 		0x27fffa,
194 		/* The Zydas driver somehow forgets to set this value. It's
195 		 * only set for Japan. We are using internal power control
196 		 * for now.
197 		 */
198 		0x294128, /* internal power */
199 		/* 0x28252c, */ /* External control TX power */
200 		/* ZD_CR31_CCK, ZD_CR51_6-36M, ZD_CR52_48M, ZD_CR53_54M */
201 		0x2c0000,
202 		0x300000,
203 		0x340000,  /* REG13(0xD) */
204 		0x381e0f,  /* REG14(0xE) */
205 		/* Bogus, RF2959's data sheet doesn't know register 27, which is
206 		 * actually referenced here. The commented 0x11 is 17.
207 		 */
208 		0x6c180f,  /* REG27(0x11) */
209 	};
210 
211 	r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
212 	if (r)
213 		return r;
214 
215 	return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
216 }
217 
rf2959_set_channel(struct zd_rf * rf,u8 channel)218 static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
219 {
220 	int i, r;
221 	const u32 *rv = rf2959_table[channel-1];
222 	struct zd_chip *chip = zd_rf_to_chip(rf);
223 
224 	for (i = 0; i < 2; i++) {
225 		r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
226 		if (r)
227 			return r;
228 	}
229 	return 0;
230 }
231 
rf2959_switch_radio_on(struct zd_rf * rf)232 static int rf2959_switch_radio_on(struct zd_rf *rf)
233 {
234 	static const struct zd_ioreq16 ioreqs[] = {
235 		{ ZD_CR10, 0x89 },
236 		{ ZD_CR11, 0x00 },
237 	};
238 	struct zd_chip *chip = zd_rf_to_chip(rf);
239 
240 	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
241 }
242 
rf2959_switch_radio_off(struct zd_rf * rf)243 static int rf2959_switch_radio_off(struct zd_rf *rf)
244 {
245 	static const struct zd_ioreq16 ioreqs[] = {
246 		{ ZD_CR10, 0x15 },
247 		{ ZD_CR11, 0x81 },
248 	};
249 	struct zd_chip *chip = zd_rf_to_chip(rf);
250 
251 	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
252 }
253 
zd_rf_init_rf2959(struct zd_rf * rf)254 int zd_rf_init_rf2959(struct zd_rf *rf)
255 {
256 	struct zd_chip *chip = zd_rf_to_chip(rf);
257 
258 	if (zd_chip_is_zd1211b(chip)) {
259 		dev_err(zd_chip_dev(chip),
260 		       "RF2959 is currently not supported for ZD1211B"
261 		       " devices\n");
262 		return -ENODEV;
263 	}
264 	rf->init_hw = rf2959_init_hw;
265 	rf->set_channel = rf2959_set_channel;
266 	rf->switch_radio_on = rf2959_switch_radio_on;
267 	rf->switch_radio_off = rf2959_switch_radio_off;
268 	return 0;
269 }
270