1/*
2 *  BSD LICENSE
3 *
4 *  Copyright(c) 2016 Broadcom.  All rights reserved.
5 *
6 *  Redistribution and use in source and binary forms, with or without
7 *  modification, are permitted provided that the following conditions
8 *  are met:
9 *
10 *    * Redistributions of source code must retain the above copyright
11 *      notice, this list of conditions and the following disclaimer.
12 *    * Redistributions in binary form must reproduce the above copyright
13 *      notice, this list of conditions and the following disclaimer in
14 *      the documentation and/or other materials provided with the
15 *      distribution.
16 *    * Neither the name of Broadcom Corporation nor the names of its
17 *      contributors may be used to endorse or promote products derived
18 *      from this software without specific prior written permission.
19 *
20 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/* BCM23550 and BCM21664 have almost identical clocks */
34#include <dt-bindings/clock/bcm21664.h>
35#include <dt-bindings/interrupt-controller/arm-gic.h>
36#include <dt-bindings/interrupt-controller/irq.h>
37
38/ {
39	#address-cells = <1>;
40	#size-cells = <1>;
41	model = "BCM23550 SoC";
42	compatible = "brcm,bcm23550";
43	interrupt-parent = <&gic>;
44
45	cpus {
46		#address-cells = <1>;
47		#size-cells = <0>;
48
49		cpu0: cpu@0 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a7";
52			reg = <0>;
53			clock-frequency = <1000000000>;
54		};
55
56		cpu1: cpu@1 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a7";
59			enable-method = "brcm,bcm23550";
60			secondary-boot-reg = <0x35004178>;
61			reg = <1>;
62			clock-frequency = <1000000000>;
63		};
64
65		cpu2: cpu@2 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a7";
68			enable-method = "brcm,bcm23550";
69			secondary-boot-reg = <0x35004178>;
70			reg = <2>;
71			clock-frequency = <1000000000>;
72		};
73
74		cpu3: cpu@3 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a7";
77			enable-method = "brcm,bcm23550";
78			secondary-boot-reg = <0x35004178>;
79			reg = <3>;
80			clock-frequency = <1000000000>;
81		};
82	};
83
84	/* Hub bus */
85	hub@34000000 {
86		compatible = "simple-bus";
87		ranges = <0 0x34000000 0x102f83ac>;
88		#address-cells = <1>;
89		#size-cells = <1>;
90
91		smc@4e000 {
92			compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
93			reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
94		};
95
96		resetmgr: reset-controller@1001f00 {
97			compatible = "brcm,bcm21664-resetmgr";
98			reg = <0x01001f00 0x24>;
99		};
100
101		gpio: gpio@1003000 {
102			compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
103			reg = <0x01003000 0x524>;
104			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
105				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
106				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
107				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
108			#gpio-cells = <2>;
109			#interrupt-cells = <2>;
110			gpio-controller;
111			interrupt-controller;
112		};
113
114		timer@1006000 {
115			compatible = "brcm,kona-timer";
116			reg = <0x01006000 0x1c>;
117			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
118			clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
119		};
120	};
121
122	/* Slaves bus */
123	slaves@3e000000 {
124		compatible = "simple-bus";
125		ranges = <0 0x3e000000 0x0001c070>;
126		#address-cells = <1>;
127		#size-cells = <1>;
128
129		uartb: serial@0 {
130			compatible = "snps,dw-apb-uart";
131			reg = <0x00000000 0x118>;
132			clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
133			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
134			reg-shift = <2>;
135			reg-io-width = <4>;
136			status = "disabled";
137		};
138
139		uartb2: serial@1000 {
140			compatible = "snps,dw-apb-uart";
141			reg = <0x00001000 0x118>;
142			clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
143			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
144			reg-shift = <2>;
145			reg-io-width = <4>;
146			status = "disabled";
147		};
148
149		uartb3: serial@2000 {
150			compatible = "snps,dw-apb-uart";
151			reg = <0x00002000 0x118>;
152			clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
153			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
154			reg-shift = <2>;
155			reg-io-width = <4>;
156			status = "disabled";
157		};
158
159		bsc1: i2c@16000 {
160			compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
161			reg = <0x00016000 0x70>;
162			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
163			#address-cells = <1>;
164			#size-cells = <0>;
165			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
166			status = "disabled";
167		};
168
169		bsc2: i2c@17000 {
170			compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
171			reg = <0x00017000 0x70>;
172			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
173			#address-cells = <1>;
174			#size-cells = <0>;
175			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
176			status = "disabled";
177		};
178
179		bsc3: i2c@18000 {
180			compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
181			reg = <0x00018000 0x70>;
182			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
183			#address-cells = <1>;
184			#size-cells = <0>;
185			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
186			status = "disabled";
187		};
188
189		bsc4: i2c@1c000 {
190			compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
191			reg = <0x0001c000 0x70>;
192			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
193			#address-cells = <1>;
194			#size-cells = <0>;
195			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
196			status = "disabled";
197		};
198	};
199
200	/* Apps bus */
201	apps@3e300000 {
202		compatible = "simple-bus";
203		ranges = <0 0x3e300000 0x01b77000>;
204		#address-cells = <1>;
205		#size-cells = <1>;
206
207		usbotg: usb@e20000 {
208			compatible = "snps,dwc2";
209			reg = <0x00e20000 0x10000>;
210			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
211			clocks = <&usb_otg_ahb_clk>;
212			clock-names = "otg";
213			phys = <&usbphy>;
214			phy-names = "usb2-phy";
215			status = "disabled";
216		};
217
218		usbphy: usb-phy@e30000 {
219			compatible = "brcm,kona-usb2-phy";
220			reg = <0x00e30000 0x28>;
221			#phy-cells = <0>;
222			status = "disabled";
223		};
224
225		sdio1: mmc@e80000 {
226			compatible = "brcm,kona-sdhci";
227			reg = <0x00e80000 0x801c>;
228			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
229			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
230			status = "disabled";
231		};
232
233		sdio2: mmc@e90000 {
234			compatible = "brcm,kona-sdhci";
235			reg = <0x00e90000 0x801c>;
236			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
237			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
238			status = "disabled";
239		};
240
241		sdio3: mmc@ea0000 {
242			compatible = "brcm,kona-sdhci";
243			reg = <0x00ea0000 0x801c>;
244			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
245			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
246			status = "disabled";
247		};
248
249		sdio4: mmc@eb0000 {
250			compatible = "brcm,kona-sdhci";
251			reg = <0x00eb0000 0x801c>;
252			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
253			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
254			status = "disabled";
255		};
256
257		cdc: cdc@1b0e000 {
258			compatible = "brcm,bcm23550-cdc";
259			reg = <0x01b0e000 0x78>;
260		};
261
262		gic: interrupt-controller@1b21000 {
263			compatible = "arm,cortex-a9-gic";
264			#interrupt-cells = <3>;
265			#address-cells = <0>;
266			interrupt-controller;
267			reg = <0x01b21000 0x1000>,
268			      <0x01b22000 0x1000>;
269		};
270	};
271
272	clocks {
273		#address-cells = <1>;
274		#size-cells = <1>;
275		ranges;
276
277		/*
278		 * Fixed clocks are defined before CCUs whose
279		 * clocks may depend on them.
280		 */
281
282		ref_32k_clk: ref_32k {
283			#clock-cells = <0>;
284			compatible = "fixed-clock";
285			clock-frequency = <32768>;
286		};
287
288		bbl_32k_clk: bbl_32k {
289			#clock-cells = <0>;
290			compatible = "fixed-clock";
291			clock-frequency = <32768>;
292		};
293
294		ref_13m_clk: ref_13m {
295			#clock-cells = <0>;
296			compatible = "fixed-clock";
297			clock-frequency = <13000000>;
298		};
299
300		var_13m_clk: var_13m {
301			#clock-cells = <0>;
302			compatible = "fixed-clock";
303			clock-frequency = <13000000>;
304		};
305
306		dft_19_5m_clk: dft_19_5m {
307			#clock-cells = <0>;
308			compatible = "fixed-clock";
309			clock-frequency = <19500000>;
310		};
311
312		ref_crystal_clk: ref_crystal {
313			#clock-cells = <0>;
314			compatible = "fixed-clock";
315			clock-frequency = <26000000>;
316		};
317
318		ref_52m_clk: ref_52m {
319			#clock-cells = <0>;
320			compatible = "fixed-clock";
321			clock-frequency = <52000000>;
322		};
323
324		var_52m_clk: var_52m {
325			#clock-cells = <0>;
326			compatible = "fixed-clock";
327			clock-frequency = <52000000>;
328		};
329
330		usb_otg_ahb_clk: usb_otg_ahb {
331			#clock-cells = <0>;
332			compatible = "fixed-clock";
333			clock-frequency = <52000000>;
334		};
335
336		ref_96m_clk: ref_96m {
337			#clock-cells = <0>;
338			compatible = "fixed-clock";
339			clock-frequency = <96000000>;
340		};
341
342		var_96m_clk: var_96m {
343			#clock-cells = <0>;
344			compatible = "fixed-clock";
345			clock-frequency = <96000000>;
346		};
347
348		ref_104m_clk: ref_104m {
349			#clock-cells = <0>;
350			compatible = "fixed-clock";
351			clock-frequency = <104000000>;
352		};
353
354		var_104m_clk: var_104m {
355			#clock-cells = <0>;
356			compatible = "fixed-clock";
357			clock-frequency = <104000000>;
358		};
359
360		ref_156m_clk: ref_156m {
361			#clock-cells = <0>;
362			compatible = "fixed-clock";
363			clock-frequency = <156000000>;
364		};
365
366		var_156m_clk: var_156m {
367			#clock-cells = <0>;
368			compatible = "fixed-clock";
369			clock-frequency = <156000000>;
370		};
371
372		root_ccu: root_ccu@35001000 {
373			compatible = "brcm,bcm21664-root-ccu";
374			reg = <0x35001000 0x0f00>;
375			#clock-cells = <1>;
376			clock-output-names = "frac_1m";
377		};
378
379		aon_ccu: aon_ccu@35002000 {
380			compatible = "brcm,bcm21664-aon-ccu";
381			reg = <0x35002000 0x0f00>;
382			#clock-cells = <1>;
383			clock-output-names = "hub_timer";
384		};
385
386		slave_ccu: slave_ccu@3e011000 {
387			compatible = "brcm,bcm21664-slave-ccu";
388			reg = <0x3e011000 0x0f00>;
389			#clock-cells = <1>;
390			clock-output-names = "uartb",
391					     "uartb2",
392					     "uartb3",
393					     "bsc1",
394					     "bsc2",
395					     "bsc3",
396					     "bsc4";
397		};
398
399		master_ccu: master_ccu@3f001000 {
400			compatible = "brcm,bcm21664-master-ccu";
401			reg = <0x3f001000 0x0f00>;
402			#clock-cells = <1>;
403			clock-output-names = "sdio1",
404					     "sdio2",
405					     "sdio3",
406					     "sdio4",
407					     "sdio1_sleep",
408					     "sdio2_sleep",
409					     "sdio3_sleep",
410					     "sdio4_sleep";
411		};
412	};
413};
414