1 /* 2 * Memory transaction attributes 3 * 4 * Copyright (c) 2015 Linaro Limited. 5 * 6 * Authors: 7 * Peter Maydell <peter.maydell@linaro.org> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 */ 13 14 #ifndef MEMATTRS_H 15 #define MEMATTRS_H 16 17 /* Every memory transaction has associated with it a set of 18 * attributes. Some of these are generic (such as the ID of 19 * the bus master); some are specific to a particular kind of 20 * bus (such as the ARM Secure/NonSecure bit). We define them 21 * all as non-overlapping bitfields in a single struct to avoid 22 * confusion if different parts of QEMU used the same bit for 23 * different semantics. 24 */ 25 typedef struct MemTxAttrs { 26 /* 27 * ARM/AMBA: TrustZone Secure access 28 * x86: System Management Mode access 29 */ 30 unsigned int secure:1; 31 /* 32 * ARM: ArmSecuritySpace. This partially overlaps secure, but it is 33 * easier to have both fields to assist code that does not understand 34 * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). 35 */ 36 unsigned int space:2; 37 /* Memory access is usermode (unprivileged) */ 38 unsigned int user:1; 39 /* 40 * Bus interconnect and peripherals can access anything (memories, 41 * devices) by default. By setting the 'memory' bit, bus transaction 42 * are restricted to "normal" memories (per the AMBA documentation) 43 * versus devices. Access to devices will be logged and rejected 44 * (see MEMTX_ACCESS_ERROR). 45 */ 46 unsigned int memory:1; 47 /* Debug access that can even write to ROM. */ 48 unsigned int debug:1; 49 /* Requester ID (for MSI for example) */ 50 unsigned int requester_id:16; 51 52 /* 53 * PID (PCI PASID) support: Limited to 8 bits process identifier. 54 */ 55 unsigned int pid:8; 56 57 /* PCI - IOMMU operations, see PCIAddressType */ 58 unsigned int address_type:1; 59 60 /* 61 * Bus masters which don't specify any attributes will get this 62 * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can 63 * distinguish "all attributes deliberately clear" from 64 * "didn't specify" if necessary. "debug" can be set alongside 65 * "unspecified". 66 */ 67 bool unspecified; 68 69 uint8_t _reserved1; 70 uint16_t _reserved2; 71 } MemTxAttrs; 72 73 QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8); 74 75 /* Bus masters which don't specify any attributes will get this, 76 * which has all attribute bits clear except the topmost one 77 * (so that we can distinguish "all attributes deliberately clear" 78 * from "didn't specify" if necessary). 79 */ 80 #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = true }) 81 82 /* New-style MMIO accessors can indicate that the transaction failed. 83 * A zero (MEMTX_OK) response means success; anything else is a failure 84 * of some kind. The memory subsystem will bitwise-OR together results 85 * if it is synthesizing an operation from multiple smaller accesses. 86 */ 87 #define MEMTX_OK 0 88 #define MEMTX_ERROR (1U << 0) /* device returned an error */ 89 #define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ 90 #define MEMTX_ACCESS_ERROR (1U << 2) /* access denied */ 91 typedef uint32_t MemTxResult; 92 93 #endif 94