1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define MAX_SURFACE_NUM 6 80 #define NUM_PIXEL_FORMATS 10 81 82 enum tiling_mode { 83 TILING_MODE_INVALID, 84 TILING_MODE_LINEAR, 85 TILING_MODE_TILED, 86 TILING_MODE_COUNT 87 }; 88 89 enum view_3d_format { 90 VIEW_3D_FORMAT_NONE = 0, 91 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 92 VIEW_3D_FORMAT_SIDE_BY_SIDE, 93 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 94 VIEW_3D_FORMAT_COUNT, 95 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 96 }; 97 98 enum plane_stereo_format { 99 PLANE_STEREO_FORMAT_NONE = 0, 100 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 101 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 102 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 103 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 104 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 105 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 106 }; 107 108 /* TODO: Find way to calculate number of bits 109 * Please increase if pixel_format enum increases 110 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 111 */ 112 113 enum dc_edid_connector_type { 114 DC_EDID_CONNECTOR_UNKNOWN = 0, 115 DC_EDID_CONNECTOR_ANALOG = 1, 116 DC_EDID_CONNECTOR_DIGITAL = 10, 117 DC_EDID_CONNECTOR_DVI = 11, 118 DC_EDID_CONNECTOR_HDMIA = 12, 119 DC_EDID_CONNECTOR_MDDI = 14, 120 DC_EDID_CONNECTOR_DISPLAYPORT = 15 121 }; 122 123 enum dc_edid_status { 124 EDID_OK, 125 EDID_BAD_INPUT, 126 EDID_NO_RESPONSE, 127 EDID_BAD_CHECKSUM, 128 EDID_THE_SAME, 129 EDID_FALL_BACK, 130 EDID_PARTIAL_VALID, 131 }; 132 133 enum act_return_status { 134 ACT_SUCCESS, 135 ACT_LINK_LOST, 136 ACT_FAILED 137 }; 138 139 /* audio capability from EDID*/ 140 struct dc_cea_audio_mode { 141 uint8_t format_code; /* ucData[0] [6:3]*/ 142 uint8_t channel_count; /* ucData[0] [2:0]*/ 143 uint8_t sample_rate; /* ucData[1]*/ 144 union { 145 uint8_t sample_size; /* for LPCM*/ 146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 147 uint8_t max_bit_rate; 148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 149 }; 150 }; 151 152 struct dc_edid { 153 uint32_t length; 154 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 155 }; 156 157 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 158 * is used. In this case we assume speaker location are: front left, front 159 * right and front center. */ 160 #define DEFAULT_SPEAKER_LOCATION 5 161 162 #define DC_MAX_AUDIO_DESC_COUNT 16 163 164 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 165 166 union display_content_support { 167 unsigned int raw; 168 struct { 169 unsigned int valid_content_type :1; 170 unsigned int game_content :1; 171 unsigned int cinema_content :1; 172 unsigned int photo_content :1; 173 unsigned int graphics_content :1; 174 unsigned int reserved :27; 175 } bits; 176 }; 177 178 struct dc_panel_patch { 179 unsigned int dppowerup_delay; 180 unsigned int extra_t12_ms; 181 unsigned int extra_delay_backlight_off; 182 unsigned int extra_t7_ms; 183 unsigned int skip_scdc_overwrite; 184 unsigned int delay_ignore_msa; 185 unsigned int disable_fec; 186 unsigned int extra_t3_ms; 187 unsigned int max_dsc_target_bpp_limit; 188 unsigned int embedded_tiled_slave; 189 unsigned int disable_fams; 190 unsigned int skip_avmute; 191 unsigned int mst_start_top_delay; 192 unsigned int remove_sink_ext_caps; 193 unsigned int disable_colorimetry; 194 }; 195 196 struct dc_edid_caps { 197 /* sink identification */ 198 uint16_t manufacturer_id; 199 uint16_t product_id; 200 uint32_t serial_number; 201 uint8_t manufacture_week; 202 uint8_t manufacture_year; 203 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 204 205 /* audio caps */ 206 uint8_t speaker_flags; 207 uint32_t audio_mode_count; 208 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 209 uint32_t audio_latency; 210 uint32_t video_latency; 211 212 union display_content_support content_support; 213 214 uint8_t qs_bit; 215 uint8_t qy_bit; 216 217 uint32_t max_tmds_clk_mhz; 218 219 /*HDMI 2.0 caps*/ 220 bool lte_340mcsc_scramble; 221 222 bool edid_hdmi; 223 bool hdr_supported; 224 225 struct dc_panel_patch panel_patch; 226 }; 227 228 struct dc_mode_flags { 229 /* note: part of refresh rate flag*/ 230 uint32_t INTERLACE :1; 231 /* native display timing*/ 232 uint32_t NATIVE :1; 233 /* preferred is the recommended mode, one per display */ 234 uint32_t PREFERRED :1; 235 /* true if this mode should use reduced blanking timings 236 *_not_ related to the Reduced Blanking adjustment*/ 237 uint32_t REDUCED_BLANKING :1; 238 /* note: part of refreshrate flag*/ 239 uint32_t VIDEO_OPTIMIZED_RATE :1; 240 /* should be reported to upper layers as mode_flags*/ 241 uint32_t PACKED_PIXEL_FORMAT :1; 242 /*< preferred view*/ 243 uint32_t PREFERRED_VIEW :1; 244 /* this timing should be used only in tiled mode*/ 245 uint32_t TILED_MODE :1; 246 uint32_t DSE_MODE :1; 247 /* Refresh rate divider when Miracast sink is using a 248 different rate than the output display device 249 Must be zero for wired displays and non-zero for 250 Miracast displays*/ 251 uint32_t MIRACAST_REFRESH_DIVIDER; 252 }; 253 254 255 enum dc_timing_source { 256 TIMING_SOURCE_UNDEFINED, 257 258 /* explicitly specifed by user, most important*/ 259 TIMING_SOURCE_USER_FORCED, 260 TIMING_SOURCE_USER_OVERRIDE, 261 TIMING_SOURCE_CUSTOM, 262 TIMING_SOURCE_EXPLICIT, 263 264 /* explicitly specified by the display device, more important*/ 265 TIMING_SOURCE_EDID_CEA_SVD_3D, 266 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 267 TIMING_SOURCE_EDID_CEA_SVD_420, 268 TIMING_SOURCE_EDID_DETAILED, 269 TIMING_SOURCE_EDID_ESTABLISHED, 270 TIMING_SOURCE_EDID_STANDARD, 271 TIMING_SOURCE_EDID_CEA_SVD, 272 TIMING_SOURCE_EDID_CVT_3BYTE, 273 TIMING_SOURCE_EDID_4BYTE, 274 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 275 TIMING_SOURCE_EDID_CEA_RID, 276 TIMING_SOURCE_VBIOS, 277 TIMING_SOURCE_CV, 278 TIMING_SOURCE_TV, 279 TIMING_SOURCE_HDMI_VIC, 280 281 /* implicitly specified by display device, still safe but less important*/ 282 TIMING_SOURCE_DEFAULT, 283 284 /* only used for custom base modes */ 285 TIMING_SOURCE_CUSTOM_BASE, 286 287 /* these timing might not work, least important*/ 288 TIMING_SOURCE_RANGELIMIT, 289 TIMING_SOURCE_OS_FORCED, 290 TIMING_SOURCE_IMPLICIT, 291 292 /* only used by default mode list*/ 293 TIMING_SOURCE_BASICMODE, 294 295 TIMING_SOURCE_COUNT 296 }; 297 298 299 struct stereo_3d_features { 300 bool supported ; 301 bool allTimings ; 302 bool cloneMode ; 303 bool scaling ; 304 bool singleFrameSWPacked; 305 }; 306 307 enum dc_timing_support_method { 308 TIMING_SUPPORT_METHOD_UNDEFINED, 309 TIMING_SUPPORT_METHOD_EXPLICIT, 310 TIMING_SUPPORT_METHOD_IMPLICIT, 311 TIMING_SUPPORT_METHOD_NATIVE 312 }; 313 314 struct dc_mode_info { 315 uint32_t pixel_width; 316 uint32_t pixel_height; 317 uint32_t field_rate; 318 /* Vertical refresh rate for progressive modes. 319 * Field rate for interlaced modes.*/ 320 321 enum dc_timing_standard timing_standard; 322 enum dc_timing_source timing_source; 323 struct dc_mode_flags flags; 324 }; 325 326 enum dc_power_state { 327 DC_POWER_STATE_ON = 1, 328 DC_POWER_STATE_STANDBY, 329 DC_POWER_STATE_SUSPEND, 330 DC_POWER_STATE_OFF 331 }; 332 333 /* DC PowerStates */ 334 enum dc_video_power_state { 335 DC_VIDEO_POWER_UNSPECIFIED = 0, 336 DC_VIDEO_POWER_ON = 1, 337 DC_VIDEO_POWER_STANDBY, 338 DC_VIDEO_POWER_SUSPEND, 339 DC_VIDEO_POWER_OFF, 340 DC_VIDEO_POWER_HIBERNATE, 341 DC_VIDEO_POWER_SHUTDOWN, 342 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 343 DC_VIDEO_POWER_AFTER_RESET, 344 DC_VIDEO_POWER_MAXIMUM 345 }; 346 347 enum dc_acpi_cm_power_state { 348 DC_ACPI_CM_POWER_STATE_D0 = 1, 349 DC_ACPI_CM_POWER_STATE_D1 = 2, 350 DC_ACPI_CM_POWER_STATE_D2 = 4, 351 DC_ACPI_CM_POWER_STATE_D3 = 8 352 }; 353 354 enum dc_connection_type { 355 dc_connection_none, 356 dc_connection_single, 357 dc_connection_mst_branch, 358 dc_connection_sst_branch 359 }; 360 361 struct dc_csc_adjustments { 362 struct fixed31_32 contrast; 363 struct fixed31_32 saturation; 364 struct fixed31_32 brightness; 365 struct fixed31_32 hue; 366 }; 367 368 /* Scaling format */ 369 enum scaling_transformation { 370 SCALING_TRANSFORMATION_UNINITIALIZED, 371 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 372 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 373 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 374 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 375 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 376 SCALING_TRANSFORMATION_INVALID = 0x80000000, 377 378 /* Flag the first and last */ 379 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 380 SCALING_TRANSFORMATION_END = 381 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 382 }; 383 384 enum display_content_type { 385 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 386 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 387 DISPLAY_CONTENT_TYPE_PHOTO = 2, 388 DISPLAY_CONTENT_TYPE_CINEMA = 4, 389 DISPLAY_CONTENT_TYPE_GAME = 8 390 }; 391 392 enum cm_gamut_adjust_type { 393 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 394 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 395 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 396 }; 397 398 struct cm_grph_csc_adjustment { 399 struct fixed31_32 temperature_matrix[12]; 400 enum cm_gamut_adjust_type gamut_adjust_type; 401 enum cm_gamut_coef_format gamut_coef_format; 402 }; 403 404 /* writeback */ 405 struct dwb_stereo_params { 406 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 407 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 408 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 409 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 410 }; 411 412 struct dc_dwb_cnv_params { 413 unsigned int src_width; /* input active width */ 414 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 415 unsigned int crop_width; /* cropped window width at cnv output */ 416 bool crop_en; /* window cropping enable in cnv */ 417 unsigned int crop_height; /* cropped window height at cnv output */ 418 unsigned int crop_x; /* cropped window start x value at cnv output */ 419 unsigned int crop_y; /* cropped window start y value at cnv output */ 420 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 421 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 422 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 423 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 424 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 425 }; 426 427 struct dc_dwb_params { 428 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 429 unsigned int hdr_mult; /* must be in FP1.6.12 */ 430 struct cm_grph_csc_adjustment csc_params; 431 struct dwb_stereo_params stereo_params; 432 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 433 unsigned int dest_width; /* Destination width */ 434 unsigned int dest_height; /* Destination height */ 435 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 436 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 437 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 438 struct scaling_taps scaler_taps; /* Scaling taps */ 439 enum dwb_subsample_position subsample_position; 440 struct dc_transfer_func *out_transfer_func; 441 }; 442 443 /* audio*/ 444 445 union audio_sample_rates { 446 struct sample_rates { 447 uint8_t RATE_32:1; 448 uint8_t RATE_44_1:1; 449 uint8_t RATE_48:1; 450 uint8_t RATE_88_2:1; 451 uint8_t RATE_96:1; 452 uint8_t RATE_176_4:1; 453 uint8_t RATE_192:1; 454 } rate; 455 456 uint8_t all; 457 }; 458 459 struct audio_speaker_flags { 460 uint32_t FL_FR:1; 461 uint32_t LFE:1; 462 uint32_t FC:1; 463 uint32_t RL_RR:1; 464 uint32_t RC:1; 465 uint32_t FLC_FRC:1; 466 uint32_t RLC_RRC:1; 467 uint32_t SUPPORT_AI:1; 468 }; 469 470 struct audio_speaker_info { 471 uint32_t ALLSPEAKERS:7; 472 uint32_t SUPPORT_AI:1; 473 }; 474 475 476 struct audio_info_flags { 477 478 union { 479 480 struct audio_speaker_flags speaker_flags; 481 struct audio_speaker_info info; 482 483 uint8_t all; 484 }; 485 }; 486 487 enum audio_format_code { 488 AUDIO_FORMAT_CODE_FIRST = 1, 489 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 490 491 AUDIO_FORMAT_CODE_AC3, 492 /*Layers 1 & 2 */ 493 AUDIO_FORMAT_CODE_MPEG1, 494 /*MPEG1 Layer 3 */ 495 AUDIO_FORMAT_CODE_MP3, 496 /*multichannel */ 497 AUDIO_FORMAT_CODE_MPEG2, 498 AUDIO_FORMAT_CODE_AAC, 499 AUDIO_FORMAT_CODE_DTS, 500 AUDIO_FORMAT_CODE_ATRAC, 501 AUDIO_FORMAT_CODE_1BITAUDIO, 502 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 503 AUDIO_FORMAT_CODE_DTS_HD, 504 AUDIO_FORMAT_CODE_MAT_MLP, 505 AUDIO_FORMAT_CODE_DST, 506 AUDIO_FORMAT_CODE_WMAPRO, 507 AUDIO_FORMAT_CODE_LAST, 508 AUDIO_FORMAT_CODE_COUNT = 509 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 510 }; 511 512 struct audio_mode { 513 /* ucData[0] [6:3] */ 514 enum audio_format_code format_code; 515 /* ucData[0] [2:0] */ 516 uint8_t channel_count; 517 /* ucData[1] */ 518 union audio_sample_rates sample_rates; 519 union { 520 /* for LPCM */ 521 uint8_t sample_size; 522 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 523 uint8_t max_bit_rate; 524 /* for Audio Formats 9-15 */ 525 uint8_t vendor_specific; 526 }; 527 }; 528 529 struct audio_info { 530 struct audio_info_flags flags; 531 uint32_t video_latency; 532 uint32_t audio_latency; 533 uint32_t display_index; 534 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 535 uint32_t manufacture_id; 536 uint32_t product_id; 537 /* PortID used for ContainerID when defined */ 538 uint32_t port_id[2]; 539 uint32_t mode_count; 540 /* this field must be last in this struct */ 541 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 542 }; 543 struct audio_check { 544 unsigned int audio_packet_type; 545 unsigned int max_audiosample_rate; 546 unsigned int acat; 547 }; 548 enum dc_infoframe_type { 549 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 550 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 551 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 552 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 553 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 554 }; 555 556 struct dc_info_packet { 557 bool valid; 558 uint8_t hb0; 559 uint8_t hb1; 560 uint8_t hb2; 561 uint8_t hb3; 562 uint8_t sb[32]; 563 }; 564 565 struct dc_info_packet_128 { 566 bool valid; 567 uint8_t hb0; 568 uint8_t hb1; 569 uint8_t hb2; 570 uint8_t hb3; 571 uint8_t sb[128]; 572 }; 573 574 #define DC_PLANE_UPDATE_TIMES_MAX 10 575 576 struct dc_plane_flip_time { 577 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 578 unsigned int index; 579 unsigned int prev_update_time_in_us; 580 }; 581 582 enum dc_psr_state { 583 PSR_STATE0 = 0x0, 584 PSR_STATE1, 585 PSR_STATE1a, 586 PSR_STATE2, 587 PSR_STATE2a, 588 PSR_STATE2b, 589 PSR_STATE3, 590 PSR_STATE3Init, 591 PSR_STATE4, 592 PSR_STATE4a, 593 PSR_STATE4b, 594 PSR_STATE4c, 595 PSR_STATE4d, 596 PSR_STATE4_FULL_FRAME, 597 PSR_STATE4a_FULL_FRAME, 598 PSR_STATE4b_FULL_FRAME, 599 PSR_STATE4c_FULL_FRAME, 600 PSR_STATE4_FULL_FRAME_POWERUP, 601 PSR_STATE4_FULL_FRAME_HW_LOCK, 602 PSR_STATE5, 603 PSR_STATE5a, 604 PSR_STATE5b, 605 PSR_STATE5c, 606 PSR_STATE_HWLOCK_MGR, 607 PSR_STATE_POLLVUPDATE, 608 PSR_STATE_INVALID = 0xFF 609 }; 610 611 struct psr_config { 612 unsigned char psr_version; 613 unsigned int psr_rfb_setup_time; 614 bool psr_exit_link_training_required; 615 bool psr_frame_capture_indication_req; 616 unsigned int psr_sdp_transmit_line_num_deadline; 617 bool allow_smu_optimizations; 618 bool allow_multi_disp_optimizations; 619 /* Panel self refresh 2 selective update granularity required */ 620 bool su_granularity_required; 621 /* psr2 selective update y granularity capability */ 622 uint8_t su_y_granularity; 623 unsigned int line_time_in_us; 624 uint8_t rate_control_caps; 625 uint16_t dsc_slice_height; 626 }; 627 628 union dmcu_psr_level { 629 struct { 630 unsigned int SKIP_CRC:1; 631 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 632 unsigned int SKIP_PHY_POWER_DOWN:1; 633 unsigned int SKIP_AUX_ACK_CHECK:1; 634 unsigned int SKIP_CRTC_DISABLE:1; 635 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 636 unsigned int SKIP_SMU_NOTIFICATION:1; 637 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 638 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 639 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 640 unsigned int DISABLE_ALPM:1; 641 unsigned int ALPM_DEFAULT_PD_MODE:1; 642 unsigned int RESERVED:20; 643 } bits; 644 unsigned int u32all; 645 }; 646 647 enum physical_phy_id { 648 PHYLD_0, 649 PHYLD_1, 650 PHYLD_2, 651 PHYLD_3, 652 PHYLD_4, 653 PHYLD_5, 654 PHYLD_6, 655 PHYLD_7, 656 PHYLD_8, 657 PHYLD_9, 658 PHYLD_COUNT, 659 PHYLD_UNKNOWN = (-1L) 660 }; 661 662 enum phy_type { 663 PHY_TYPE_UNKNOWN = 1, 664 PHY_TYPE_PCIE_PHY = 2, 665 PHY_TYPE_UNIPHY = 3, 666 }; 667 668 struct psr_context { 669 /* ddc line */ 670 enum channel_id channel; 671 /* Transmitter id */ 672 enum transmitter transmitterId; 673 /* Engine Id is used for Dig Be source select */ 674 enum engine_id engineId; 675 /* Controller Id used for Dig Fe source select */ 676 enum controller_id controllerId; 677 /* Pcie or Uniphy */ 678 enum phy_type phyType; 679 /* Physical PHY Id used by SMU interpretation */ 680 enum physical_phy_id smuPhyId; 681 /* Vertical total pixels from crtc timing. 682 * This is used for static screen detection. 683 * ie. If we want to detect half a frame, 684 * we use this to determine the hyst lines. 685 */ 686 unsigned int crtcTimingVerticalTotal; 687 /* PSR supported from panel capabilities and 688 * current display configuration 689 */ 690 bool psrSupportedDisplayConfig; 691 /* Whether fast link training is supported by the panel */ 692 bool psrExitLinkTrainingRequired; 693 /* If RFB setup time is greater than the total VBLANK time, 694 * it is not possible for the sink to capture the video frame 695 * in the same frame the SDP is sent. In this case, 696 * the frame capture indication bit should be set and an extra 697 * static frame should be transmitted to the sink. 698 */ 699 bool psrFrameCaptureIndicationReq; 700 /* Set the last possible line SDP may be transmitted without violating 701 * the RFB setup time or entering the active video frame. 702 */ 703 unsigned int sdpTransmitLineNumDeadline; 704 /* The VSync rate in Hz used to calculate the 705 * step size for smooth brightness feature 706 */ 707 unsigned int vsync_rate_hz; 708 unsigned int skipPsrWaitForPllLock; 709 unsigned int numberOfControllers; 710 /* Unused, for future use. To indicate that first changed frame from 711 * state3 shouldn't result in psr_inactive, but rather to perform 712 * an automatic single frame rfb_update. 713 */ 714 bool rfb_update_auto_en; 715 /* Number of frame before entering static screen */ 716 unsigned int timehyst_frames; 717 /* Partial frames before entering static screen */ 718 unsigned int hyst_lines; 719 /* # of repeated AUX transaction attempts to make before 720 * indicating failure to the driver 721 */ 722 unsigned int aux_repeats; 723 /* Controls hw blocks to power down during PSR active state */ 724 union dmcu_psr_level psr_level; 725 /* Controls additional delay after remote frame capture before 726 * continuing powerd own 727 */ 728 unsigned int frame_delay; 729 bool allow_smu_optimizations; 730 bool allow_multi_disp_optimizations; 731 /* Panel self refresh 2 selective update granularity required */ 732 bool su_granularity_required; 733 /* psr2 selective update y granularity capability */ 734 uint8_t su_y_granularity; 735 unsigned int line_time_in_us; 736 uint8_t rate_control_caps; 737 uint16_t dsc_slice_height; 738 }; 739 740 struct colorspace_transform { 741 struct fixed31_32 matrix[12]; 742 bool enable_remap; 743 }; 744 745 enum i2c_mot_mode { 746 I2C_MOT_UNDEF, 747 I2C_MOT_TRUE, 748 I2C_MOT_FALSE 749 }; 750 751 struct AsicStateEx { 752 unsigned int memoryClock; 753 unsigned int displayClock; 754 unsigned int engineClock; 755 unsigned int maxSupportedDppClock; 756 unsigned int dppClock; 757 unsigned int socClock; 758 unsigned int dcfClockDeepSleep; 759 unsigned int fClock; 760 unsigned int phyClock; 761 }; 762 763 764 enum dc_clock_type { 765 DC_CLOCK_TYPE_DISPCLK = 0, 766 DC_CLOCK_TYPE_DPPCLK = 1, 767 }; 768 769 struct dc_clock_config { 770 uint32_t max_clock_khz; 771 uint32_t min_clock_khz; 772 uint32_t bw_requirequired_clock_khz; 773 uint32_t current_clock_khz;/*current clock in use*/ 774 }; 775 776 struct hw_asic_id { 777 uint32_t chip_id; 778 uint32_t chip_family; 779 uint32_t pci_revision_id; 780 uint32_t hw_internal_rev; 781 uint32_t vram_type; 782 uint32_t vram_width; 783 uint32_t feature_flags; 784 uint32_t fake_paths_num; 785 void *atombios_base_address; 786 }; 787 788 struct dc_context { 789 struct dc *dc; 790 791 void *driver_context; /* e.g. amdgpu_device */ 792 struct dc_perf_trace *perf_trace; 793 void *cgs_device; 794 795 enum dce_environment dce_environment; 796 struct hw_asic_id asic_id; 797 798 /* todo: below should probably move to dc. to facilitate removal 799 * of AS we will store these here 800 */ 801 enum dce_version dce_version; 802 struct dc_bios *dc_bios; 803 bool created_bios; 804 struct gpio_service *gpio_service; 805 uint32_t dc_sink_id_count; 806 uint32_t dc_stream_id_count; 807 uint32_t dc_edp_id_count; 808 uint64_t fbc_gpu_addr; 809 struct dc_dmub_srv *dmub_srv; 810 struct cp_psp cp_psp; 811 uint32_t *dcn_reg_offsets; 812 uint32_t *nbio_reg_offsets; 813 }; 814 815 /* DSC DPCD capabilities */ 816 union dsc_slice_caps1 { 817 struct { 818 uint8_t NUM_SLICES_1 : 1; 819 uint8_t NUM_SLICES_2 : 1; 820 uint8_t RESERVED : 1; 821 uint8_t NUM_SLICES_4 : 1; 822 uint8_t NUM_SLICES_6 : 1; 823 uint8_t NUM_SLICES_8 : 1; 824 uint8_t NUM_SLICES_10 : 1; 825 uint8_t NUM_SLICES_12 : 1; 826 } bits; 827 uint8_t raw; 828 }; 829 830 union dsc_slice_caps2 { 831 struct { 832 uint8_t NUM_SLICES_16 : 1; 833 uint8_t NUM_SLICES_20 : 1; 834 uint8_t NUM_SLICES_24 : 1; 835 uint8_t RESERVED : 5; 836 } bits; 837 uint8_t raw; 838 }; 839 840 union dsc_color_formats { 841 struct { 842 uint8_t RGB : 1; 843 uint8_t YCBCR_444 : 1; 844 uint8_t YCBCR_SIMPLE_422 : 1; 845 uint8_t YCBCR_NATIVE_422 : 1; 846 uint8_t YCBCR_NATIVE_420 : 1; 847 uint8_t RESERVED : 3; 848 } bits; 849 uint8_t raw; 850 }; 851 852 union dsc_color_depth { 853 struct { 854 uint8_t RESERVED1 : 1; 855 uint8_t COLOR_DEPTH_8_BPC : 1; 856 uint8_t COLOR_DEPTH_10_BPC : 1; 857 uint8_t COLOR_DEPTH_12_BPC : 1; 858 uint8_t RESERVED2 : 3; 859 } bits; 860 uint8_t raw; 861 }; 862 863 struct dsc_dec_dpcd_caps { 864 bool is_dsc_supported; 865 uint8_t dsc_version; 866 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 867 union dsc_slice_caps1 slice_caps1; 868 union dsc_slice_caps2 slice_caps2; 869 int32_t lb_bit_depth; 870 bool is_block_pred_supported; 871 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 872 union dsc_color_formats color_formats; 873 union dsc_color_depth color_depth; 874 int32_t throughput_mode_0_mps; /* In MPs */ 875 int32_t throughput_mode_1_mps; /* In MPs */ 876 int32_t max_slice_width; 877 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 878 879 /* Extended DSC caps */ 880 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 881 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 882 uint32_t branch_max_line_width; 883 bool is_dp; /* Decoded format */ 884 }; 885 886 struct dc_golden_table { 887 uint16_t dc_golden_table_ver; 888 uint32_t aux_dphy_rx_control0_val; 889 uint32_t aux_dphy_tx_control_val; 890 uint32_t aux_dphy_rx_control1_val; 891 uint32_t dc_gpio_aux_ctrl_0_val; 892 uint32_t dc_gpio_aux_ctrl_1_val; 893 uint32_t dc_gpio_aux_ctrl_2_val; 894 uint32_t dc_gpio_aux_ctrl_3_val; 895 uint32_t dc_gpio_aux_ctrl_4_val; 896 uint32_t dc_gpio_aux_ctrl_5_val; 897 }; 898 899 enum dc_gpu_mem_alloc_type { 900 DC_MEM_ALLOC_TYPE_GART, 901 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 902 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 903 DC_MEM_ALLOC_TYPE_AGP 904 }; 905 906 enum dc_link_encoding_format { 907 DC_LINK_ENCODING_UNSPECIFIED = 0, 908 DC_LINK_ENCODING_DP_8b_10b, 909 DC_LINK_ENCODING_DP_128b_132b, 910 DC_LINK_ENCODING_HDMI_TMDS, 911 DC_LINK_ENCODING_HDMI_FRL 912 }; 913 914 enum dc_psr_version { 915 DC_PSR_VERSION_1 = 0, 916 DC_PSR_VERSION_SU_1 = 1, 917 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 918 }; 919 920 /* Possible values of display_endpoint_id.endpoint */ 921 enum display_endpoint_type { 922 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 923 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 924 DISPLAY_ENDPOINT_UNKNOWN = -1 925 }; 926 927 /* Extends graphics_object_id with an additional member 'ep_type' for 928 * distinguishing between physical endpoints (with entries in BIOS connector table) and 929 * logical endpoints. 930 */ 931 struct display_endpoint_id { 932 struct graphics_object_id link_id; 933 enum display_endpoint_type ep_type; 934 }; 935 936 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 937 struct otg_phy_mux { 938 uint8_t phy_output_num; 939 uint8_t otg_output_num; 940 }; 941 #endif 942 943 enum dc_detect_reason { 944 DETECT_REASON_BOOT, 945 DETECT_REASON_RESUMEFROMS3S4, 946 DETECT_REASON_HPD, 947 DETECT_REASON_HPDRX, 948 DETECT_REASON_FALLBACK, 949 DETECT_REASON_RETRAIN, 950 DETECT_REASON_TDR, 951 }; 952 953 struct dc_link_status { 954 bool link_active; 955 struct dpcd_caps *dpcd_caps; 956 }; 957 958 union hdcp_rx_caps { 959 struct { 960 uint8_t version; 961 uint8_t reserved; 962 struct { 963 uint8_t repeater : 1; 964 uint8_t hdcp_capable : 1; 965 uint8_t reserved : 6; 966 } byte0; 967 } fields; 968 uint8_t raw[3]; 969 }; 970 971 union hdcp_bcaps { 972 struct { 973 uint8_t HDCP_CAPABLE:1; 974 uint8_t REPEATER:1; 975 uint8_t RESERVED:6; 976 } bits; 977 uint8_t raw; 978 }; 979 980 struct hdcp_caps { 981 union hdcp_rx_caps rx_caps; 982 union hdcp_bcaps bcaps; 983 }; 984 985 /* DP MST stream allocation (payload bandwidth number) */ 986 struct link_mst_stream_allocation { 987 /* DIG front */ 988 const struct stream_encoder *stream_enc; 989 /* HPO DP Stream Encoder */ 990 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 991 /* associate DRM payload table with DC stream encoder */ 992 uint8_t vcp_id; 993 /* number of slots required for the DP stream in transport packet */ 994 uint8_t slot_count; 995 }; 996 997 #define MAX_CONTROLLER_NUM 6 998 999 /* DP MST stream allocation table */ 1000 struct link_mst_stream_allocation_table { 1001 /* number of DP video streams */ 1002 int stream_count; 1003 /* array of stream allocations */ 1004 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 1005 }; 1006 1007 /* PSR feature flags */ 1008 struct psr_settings { 1009 bool psr_feature_enabled; // PSR is supported by sink 1010 bool psr_allow_active; // PSR is currently active 1011 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1012 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1013 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1014 1015 /* These parameters are calculated in Driver, 1016 * based on display timing and Sink capabilities. 1017 * If VBLANK region is too small and Sink takes a long time 1018 * to set up RFB, it may take an extra frame to enter PSR state. 1019 */ 1020 bool psr_frame_capture_indication_req; 1021 unsigned int psr_sdp_transmit_line_num_deadline; 1022 uint8_t force_ffu_mode; 1023 unsigned int psr_power_opt; 1024 }; 1025 1026 enum replay_coasting_vtotal_type { 1027 PR_COASTING_TYPE_NOM = 0, 1028 PR_COASTING_TYPE_STATIC, 1029 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1030 PR_COASTING_TYPE_TEST_HARNESS, 1031 PR_COASTING_TYPE_NUM, 1032 }; 1033 1034 union replay_error_status { 1035 struct { 1036 unsigned char STATE_TRANSITION_ERROR :1; 1037 unsigned char LINK_CRC_ERROR :1; 1038 unsigned char DESYNC_ERROR :1; 1039 unsigned char RESERVED :5; 1040 } bits; 1041 unsigned char raw; 1042 }; 1043 1044 struct replay_config { 1045 bool replay_supported; // Replay feature is supported 1046 unsigned int replay_power_opt_supported; // Power opt flags that are supported 1047 bool replay_smu_opt_supported; // SMU optimization is supported 1048 unsigned int replay_enable_option; // Replay enablement option 1049 uint32_t debug_flags; // Replay debug flags 1050 bool replay_timing_sync_supported; // Replay desync is supported 1051 union replay_error_status replay_error_status; // Replay error status 1052 }; 1053 1054 /* Replay feature flags */ 1055 struct replay_settings { 1056 struct replay_config config; // Replay configuration 1057 bool replay_feature_enabled; // Replay feature is ready for activating 1058 bool replay_allow_active; // Replay is currently active 1059 unsigned int replay_power_opt_active; // Power opt flags that are activated currently 1060 bool replay_smu_opt_enable; // SMU optimization is enabled 1061 uint16_t coasting_vtotal; // Current Coasting vtotal 1062 uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; // Coasting vtotal table 1063 }; 1064 1065 /* To split out "global" and "per-panel" config settings. 1066 * Add a struct dc_panel_config under dc_link 1067 */ 1068 struct dc_panel_config { 1069 /* extra panel power sequence parameters */ 1070 struct pps { 1071 unsigned int extra_t3_ms; 1072 unsigned int extra_t7_ms; 1073 unsigned int extra_delay_backlight_off; 1074 unsigned int extra_post_t7_ms; 1075 unsigned int extra_pre_t11_ms; 1076 unsigned int extra_t12_ms; 1077 unsigned int extra_post_OUI_ms; 1078 } pps; 1079 /* nit brightness */ 1080 struct nits_brightness { 1081 unsigned int peak; /* nits */ 1082 unsigned int max_avg; /* nits */ 1083 unsigned int min; /* 1/10000 nits */ 1084 unsigned int max_nonboost_brightness_millinits; 1085 unsigned int min_brightness_millinits; 1086 } nits_brightness; 1087 /* PSR */ 1088 struct psr { 1089 bool disable_psr; 1090 bool disallow_psrsu; 1091 bool disallow_replay; 1092 bool rc_disable; 1093 bool rc_allow_static_screen; 1094 bool rc_allow_fullscreen_VPB; 1095 unsigned int replay_enable_option; 1096 } psr; 1097 /* ABM */ 1098 struct varib { 1099 unsigned int varibright_feature_enable; 1100 unsigned int def_varibright_level; 1101 unsigned int abm_config_setting; 1102 } varib; 1103 /* edp DSC */ 1104 struct dsc { 1105 bool disable_dsc_edp; 1106 unsigned int force_dsc_edp_policy; 1107 } dsc; 1108 /* eDP ILR */ 1109 struct ilr { 1110 bool optimize_edp_link_rate; /* eDP ILR */ 1111 } ilr; 1112 }; 1113 1114 #define MAX_SINKS_PER_LINK 4 1115 1116 /* 1117 * USB4 DPIA BW ALLOCATION STRUCTS 1118 */ 1119 struct dc_dpia_bw_alloc { 1120 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1121 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1122 int link_max_bw; // The Max BW that link can require/support 1123 int allocated_bw; // The Actual Allocated BW for this DPIA 1124 int estimated_bw; // The estimated available BW for this DPIA 1125 int bw_granularity; // BW Granularity 1126 int dp_overhead; // DP overhead in dp tunneling 1127 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1128 bool response_ready; // Response ready from the CM side 1129 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1130 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1131 }; 1132 1133 enum dc_hpd_enable_select { 1134 HPD_EN_FOR_ALL_EDP = 0, 1135 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1136 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1137 }; 1138 1139 #endif /* DC_TYPES_H_ */ 1140