1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * EHCI HCD (Host Controller Driver) for USB.
4 *
5 * Copyright (C) 2013,2014 Renesas Electronics Corporation
6 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/ehci-rmobile.h>
12 #include "ehci.h"
13
14 #if defined(CONFIG_R8A7740)
15 static u32 usb_base_address[] = {
16 0xC6700000
17 };
18 #elif defined(CONFIG_R8A7790)
19 static u32 usb_base_address[] = {
20 0xEE080000, /* USB0 (EHCI) */
21 0xEE0A0000, /* USB1 */
22 0xEE0C0000, /* USB2 */
23 };
24 #elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
25 defined(CONFIG_R8A7794)
26 static u32 usb_base_address[] = {
27 0xEE080000, /* USB0 (EHCI) */
28 0xEE0C0000, /* USB1 */
29 };
30 #else
31 #error rmobile EHCI USB driver not supported on this platform
32 #endif
33
ehci_hcd_stop(int index)34 int ehci_hcd_stop(int index)
35 {
36 int i;
37 u32 base;
38 struct ahbcom_pci_bridge *ahbcom_pci;
39
40 base = usb_base_address[index];
41 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
42 writel(0, &ahbcom_pci->ahb_bus_ctr);
43
44 /* reset ehci */
45 setbits_le32(base + EHCI_USBCMD, CMD_RESET);
46 for (i = 100; i > 0; i--) {
47 if (!(readl(base + EHCI_USBCMD) & CMD_RESET))
48 break;
49 udelay(100);
50 }
51
52 if (!i)
53 printf("error : ehci(%d) reset failed.\n", index);
54
55 if (index == (ARRAY_SIZE(usb_base_address) - 1))
56 setbits_le32(SMSTPCR7, SMSTPCR703);
57
58 return 0;
59 }
60
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)61 int ehci_hcd_init(int index, enum usb_init_type init,
62 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
63 {
64 u32 base;
65 u32 phys_base;
66 struct rmobile_ehci_reg *rehci;
67 struct ahbcom_pci_bridge *ahbcom_pci;
68 struct ahbconf_pci_bridge *ahbconf_pci;
69 struct ahb_pciconf *ahb_pciconf_ohci;
70 struct ahb_pciconf *ahb_pciconf_ehci;
71 uint32_t cap_base;
72
73 base = usb_base_address[index];
74 phys_base = base;
75 if (index == 0)
76 clrbits_le32(SMSTPCR7, SMSTPCR703);
77
78 rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET);
79 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
80 ahbconf_pci =
81 (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET);
82 ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET);
83 ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET);
84
85 /* Clock & Reset & Direct Power Down */
86 clrsetbits_le32(&ahbcom_pci->usbctr,
87 (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB);
88 clrbits_le32(&ahbcom_pci->usbctr, PLL_RST);
89
90 /* AHB-PCI Bridge Communication Registers */
91 writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
92 writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
93 &ahbcom_pci->pciahb_win1_ctr);
94 writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
95 &ahbcom_pci->pciahb_win2_ctr);
96 writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr);
97
98 setbits_le32(&ahbcom_pci->pci_arbiter_ctr,
99 PCIBP_MODE | PCIREQ1 | PCIREQ0);
100
101 /* PCI Configuration Registers for AHBPCI */
102 writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
103 &ahbcom_pci->ahbpci_win1_ctr);
104 writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
105 writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
106 writel(0xf0000000, &ahbconf_pci->win2_basead);
107 writel(SERREN | PERREN | MASTEREN | MEMEN,
108 &ahbconf_pci->cmnd_sts);
109
110 /* PCI Configuration Registers for EHCI */
111 writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr);
112 writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead);
113 writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead);
114 writel(SERREN | PERREN | MASTEREN | MEMEN,
115 &ahb_pciconf_ohci->cmnd_sts);
116 writel(SERREN | PERREN | MASTEREN | MEMEN,
117 &ahb_pciconf_ehci->cmnd_sts);
118
119 /* Enable PCI interrupt */
120 setbits_le32(&ahbcom_pci->pci_int_enable,
121 USBH_PMEEN | USBH_INTBEN | USBH_INTAEN);
122
123 *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion);
124 cap_base = ehci_readl(&(*hccr)->cr_capbase);
125 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base));
126
127 return 0;
128 }
129