xref: /openbmc/linux/sound/soc/codecs/cx2072x.c (revision 878b5fee)
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // ALSA SoC CX20721/CX20723 codec driver
4 //
5 // Copyright:	(C) 2017 Conexant Systems, Inc.
6 // Author:	Simon Ho, <Simon.ho@conexant.com>
7 //
8 // TODO: add support for TDM mode.
9 //
10 
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio.h>
15 #include <linux/init.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/initval.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/tlv.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include "cx2072x.h"
32 
33 #define PLL_OUT_HZ_48	(1024 * 3 * 48000)
34 #define BITS_PER_SLOT	8
35 
36 /* codec private data */
37 struct cx2072x_priv {
38 	struct regmap *regmap;
39 	struct clk *mclk;
40 	unsigned int mclk_rate;
41 	struct device *dev;
42 	struct snd_soc_component *codec;
43 	struct snd_soc_jack_gpio jack_gpio;
44 	struct mutex lock;
45 	unsigned int bclk_ratio;
46 	bool pll_changed;
47 	bool i2spcm_changed;
48 	int sample_size;
49 	int frame_size;
50 	int sample_rate;
51 	unsigned int dai_fmt;
52 	bool en_aec_ref;
53 };
54 
55 /*
56  * DAC/ADC Volume
57  *
58  * max : 74 : 0 dB
59  *	 ( in 1 dB  step )
60  * min : 0 : -74 dB
61  */
62 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7400, 100, 0);
63 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7400, 100, 0);
64 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 1200, 0);
65 
66 struct cx2072x_eq_ctrl {
67 	u8 ch;
68 	u8 band;
69 };
70 
71 static const DECLARE_TLV_DB_RANGE(hpf_tlv,
72 	0, 0, TLV_DB_SCALE_ITEM(120, 0, 0),
73 	1, 63, TLV_DB_SCALE_ITEM(30, 30, 0)
74 );
75 
76 /* Lookup table for PRE_DIV */
77 static const struct {
78 	unsigned int mclk;
79 	unsigned int div;
80 } mclk_pre_div[] = {
81 	{ 6144000, 1 },
82 	{ 12288000, 2 },
83 	{ 19200000, 3 },
84 	{ 26000000, 4 },
85 	{ 28224000, 5 },
86 	{ 36864000, 6 },
87 	{ 36864000, 7 },
88 	{ 48000000, 8 },
89 	{ 49152000, 8 },
90 };
91 
92 /*
93  * cx2072x register cache.
94  */
95 static const struct reg_default cx2072x_reg_defaults[] = {
96 	{ CX2072X_AFG_POWER_STATE, 0x00000003 },
97 	{ CX2072X_UM_RESPONSE, 0x00000000 },
98 	{ CX2072X_GPIO_DATA, 0x00000000 },
99 	{ CX2072X_GPIO_ENABLE, 0x00000000 },
100 	{ CX2072X_GPIO_DIRECTION, 0x00000000 },
101 	{ CX2072X_GPIO_WAKE, 0x00000000 },
102 	{ CX2072X_GPIO_UM_ENABLE, 0x00000000 },
103 	{ CX2072X_GPIO_STICKY_MASK, 0x00000000 },
104 	{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
105 	{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
106 	{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
107 	{ CX2072X_DAC1_POWER_STATE, 0x00000433 },
108 	{ CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
109 	{ CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
110 	{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
111 	{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
112 	{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
113 	{ CX2072X_DAC2_POWER_STATE, 0x00000433 },
114 	{ CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
115 	{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
116 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
117 	{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
118 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
119 	{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
120 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
121 	{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
122 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
123 	{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
124 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
125 	{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
126 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
127 	{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
128 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
129 	{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
130 	{ CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
131 	{ CX2072X_ADC1_POWER_STATE, 0x00000433 },
132 	{ CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
133 	{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
134 	{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
135 	{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
136 	{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
137 	{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
138 	{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
139 	{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
140 	{ CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
141 	{ CX2072X_ADC2_POWER_STATE, 0x00000433 },
142 	{ CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
143 	{ CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
144 	{ CX2072X_PORTA_POWER_STATE, 0x00000433 },
145 	{ CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
146 	{ CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
147 	{ CX2072X_PORTA_PIN_SENSE, 0x00000000 },
148 	{ CX2072X_PORTA_EAPD_BTL, 0x00000002 },
149 	{ CX2072X_PORTB_POWER_STATE, 0x00000433 },
150 	{ CX2072X_PORTB_PIN_CTRL, 0x00000000 },
151 	{ CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },
152 	{ CX2072X_PORTB_PIN_SENSE, 0x00000000 },
153 	{ CX2072X_PORTB_EAPD_BTL, 0x00000002 },
154 	{ CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
155 	{ CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
156 	{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
157 	{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
158 	{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
159 	{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
160 	{ CX2072X_PORTD_POWER_STATE, 0x00000433 },
161 	{ CX2072X_PORTD_PIN_CTRL, 0x00000020 },
162 	{ CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
163 	{ CX2072X_PORTD_PIN_SENSE, 0x00000000 },
164 	{ CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
165 	{ CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
166 	{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
167 	{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
168 	{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
169 	{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
170 	{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
171 	{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
172 	{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
173 	{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
174 	{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
175 	{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
176 	{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
177 	{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
178 	{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
179 	{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
180 	{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
181 	{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
182 	{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
183 	{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
184 	{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
185 	{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
186 	{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
187 	{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
188 	{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
189 	{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
190 	{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
191 	{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
192 	{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
193 	{ CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
194 	{ CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
195 	{ CX2072X_SPKR_DRC_TEST, 0x00000000 },
196 	{ CX2072X_DIGITAL_BIOS_TEST0, 0x001f008a },
197 	{ CX2072X_DIGITAL_BIOS_TEST2, 0x00990026 },
198 	{ CX2072X_I2SPCM_CONTROL1, 0x00010001 },
199 	{ CX2072X_I2SPCM_CONTROL2, 0x00000000 },
200 	{ CX2072X_I2SPCM_CONTROL3, 0x00000000 },
201 	{ CX2072X_I2SPCM_CONTROL4, 0x00000000 },
202 	{ CX2072X_I2SPCM_CONTROL5, 0x00000000 },
203 	{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
204 	{ CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
205 	{ CX2072X_CODEC_TEST2, 0x00000000 },
206 	{ CX2072X_CODEC_TEST9, 0x00000004 },
207 	{ CX2072X_CODEC_TEST20, 0x00000600 },
208 	{ CX2072X_CODEC_TEST26, 0x00000208 },
209 	{ CX2072X_ANALOG_TEST4, 0x00000000 },
210 	{ CX2072X_ANALOG_TEST5, 0x00000000 },
211 	{ CX2072X_ANALOG_TEST6, 0x0000059a },
212 	{ CX2072X_ANALOG_TEST7, 0x000000a7 },
213 	{ CX2072X_ANALOG_TEST8, 0x00000017 },
214 	{ CX2072X_ANALOG_TEST9, 0x00000000 },
215 	{ CX2072X_ANALOG_TEST10, 0x00000285 },
216 	{ CX2072X_ANALOG_TEST11, 0x00000000 },
217 	{ CX2072X_ANALOG_TEST12, 0x00000000 },
218 	{ CX2072X_ANALOG_TEST13, 0x00000000 },
219 	{ CX2072X_DIGITAL_TEST1, 0x00000242 },
220 	{ CX2072X_DIGITAL_TEST11, 0x00000000 },
221 	{ CX2072X_DIGITAL_TEST12, 0x00000084 },
222 	{ CX2072X_DIGITAL_TEST15, 0x00000077 },
223 	{ CX2072X_DIGITAL_TEST16, 0x00000021 },
224 	{ CX2072X_DIGITAL_TEST17, 0x00000018 },
225 	{ CX2072X_DIGITAL_TEST18, 0x00000024 },
226 	{ CX2072X_DIGITAL_TEST19, 0x00000001 },
227 	{ CX2072X_DIGITAL_TEST20, 0x00000002 },
228 };
229 
230 /*
231  * register initialization
232  */
233 static const struct reg_sequence cx2072x_reg_init[] = {
234 	{ CX2072X_ANALOG_TEST9,	0x080 },    /* DC offset Calibration */
235 	{ CX2072X_CODEC_TEST26,	0x65f },    /* Disable the PA */
236 	{ CX2072X_ANALOG_TEST10, 0x289 },   /* Set the speaker output gain */
237 	{ CX2072X_CODEC_TEST20,	0xf05 },
238 	{ CX2072X_CODEC_TESTXX,	0x380 },
239 	{ CX2072X_CODEC_TEST26,	0xb90 },
240 	{ CX2072X_CODEC_TEST9,	0x001 },    /* Enable 30 Hz High pass filter */
241 	{ CX2072X_ANALOG_TEST3,	0x300 },    /* Disable PCBEEP pad */
242 	{ CX2072X_CODEC_TEST24,	0x100 },    /* Disable SnM mode */
243 	{ CX2072X_PORTD_PIN_CTRL, 0x020 },  /* Enable PortD input */
244 	{ CX2072X_GPIO_ENABLE,	0x040 },    /* Enable GPIO7 pin for button */
245 	{ CX2072X_GPIO_UM_ENABLE, 0x040 },  /* Enable UM for GPIO7 */
246 	{ CX2072X_UM_RESPONSE,	0x080 },    /* Enable button response */
247 	{ CX2072X_DIGITAL_TEST12, 0x0c4 },  /* Enable headset button */
248 	{ CX2072X_DIGITAL_TEST0, 0x415 },   /* Power down class-D during idle */
249 	{ CX2072X_I2SPCM_CONTROL2, 0x00f }, /* Enable I2S TX */
250 	{ CX2072X_I2SPCM_CONTROL3, 0x00f }, /* Enable I2S RX */
251 };
252 
cx2072x_register_size(unsigned int reg)253 static unsigned int cx2072x_register_size(unsigned int reg)
254 {
255 	switch (reg) {
256 	case CX2072X_VENDOR_ID:
257 	case CX2072X_REVISION_ID:
258 	case CX2072X_PORTA_PIN_SENSE:
259 	case CX2072X_PORTB_PIN_SENSE:
260 	case CX2072X_PORTD_PIN_SENSE:
261 	case CX2072X_PORTE_PIN_SENSE:
262 	case CX2072X_PORTF_PIN_SENSE:
263 	case CX2072X_I2SPCM_CONTROL1:
264 	case CX2072X_I2SPCM_CONTROL2:
265 	case CX2072X_I2SPCM_CONTROL3:
266 	case CX2072X_I2SPCM_CONTROL4:
267 	case CX2072X_I2SPCM_CONTROL5:
268 	case CX2072X_I2SPCM_CONTROL6:
269 	case CX2072X_UM_INTERRUPT_CRTL_E:
270 	case CX2072X_EQ_G_COEFF:
271 	case CX2072X_SPKR_DRC_CONTROL:
272 	case CX2072X_SPKR_DRC_TEST:
273 	case CX2072X_DIGITAL_BIOS_TEST0:
274 	case CX2072X_DIGITAL_BIOS_TEST2:
275 		return 4;
276 	case CX2072X_EQ_ENABLE_BYPASS:
277 	case CX2072X_EQ_B0_COEFF:
278 	case CX2072X_EQ_B1_COEFF:
279 	case CX2072X_EQ_B2_COEFF:
280 	case CX2072X_EQ_A1_COEFF:
281 	case CX2072X_EQ_A2_COEFF:
282 	case CX2072X_DAC1_CONVERTER_FORMAT:
283 	case CX2072X_DAC2_CONVERTER_FORMAT:
284 	case CX2072X_ADC1_CONVERTER_FORMAT:
285 	case CX2072X_ADC2_CONVERTER_FORMAT:
286 	case CX2072X_CODEC_TEST2:
287 	case CX2072X_CODEC_TEST9:
288 	case CX2072X_CODEC_TEST20:
289 	case CX2072X_CODEC_TEST26:
290 	case CX2072X_ANALOG_TEST3:
291 	case CX2072X_ANALOG_TEST4:
292 	case CX2072X_ANALOG_TEST5:
293 	case CX2072X_ANALOG_TEST6:
294 	case CX2072X_ANALOG_TEST7:
295 	case CX2072X_ANALOG_TEST8:
296 	case CX2072X_ANALOG_TEST9:
297 	case CX2072X_ANALOG_TEST10:
298 	case CX2072X_ANALOG_TEST11:
299 	case CX2072X_ANALOG_TEST12:
300 	case CX2072X_ANALOG_TEST13:
301 	case CX2072X_DIGITAL_TEST0:
302 	case CX2072X_DIGITAL_TEST1:
303 	case CX2072X_DIGITAL_TEST11:
304 	case CX2072X_DIGITAL_TEST12:
305 	case CX2072X_DIGITAL_TEST15:
306 	case CX2072X_DIGITAL_TEST16:
307 	case CX2072X_DIGITAL_TEST17:
308 	case CX2072X_DIGITAL_TEST18:
309 	case CX2072X_DIGITAL_TEST19:
310 	case CX2072X_DIGITAL_TEST20:
311 		return 2;
312 	default:
313 		return 1;
314 	}
315 }
316 
cx2072x_readable_register(struct device * dev,unsigned int reg)317 static bool cx2072x_readable_register(struct device *dev, unsigned int reg)
318 {
319 	switch (reg) {
320 	case CX2072X_VENDOR_ID:
321 	case CX2072X_REVISION_ID:
322 	case CX2072X_CURRENT_BCLK_FREQUENCY:
323 	case CX2072X_AFG_POWER_STATE:
324 	case CX2072X_UM_RESPONSE:
325 	case CX2072X_GPIO_DATA:
326 	case CX2072X_GPIO_ENABLE:
327 	case CX2072X_GPIO_DIRECTION:
328 	case CX2072X_GPIO_WAKE:
329 	case CX2072X_GPIO_UM_ENABLE:
330 	case CX2072X_GPIO_STICKY_MASK:
331 	case CX2072X_DAC1_CONVERTER_FORMAT:
332 	case CX2072X_DAC1_AMP_GAIN_RIGHT:
333 	case CX2072X_DAC1_AMP_GAIN_LEFT:
334 	case CX2072X_DAC1_POWER_STATE:
335 	case CX2072X_DAC1_CONVERTER_STREAM_CHANNEL:
336 	case CX2072X_DAC1_EAPD_ENABLE:
337 	case CX2072X_DAC2_CONVERTER_FORMAT:
338 	case CX2072X_DAC2_AMP_GAIN_RIGHT:
339 	case CX2072X_DAC2_AMP_GAIN_LEFT:
340 	case CX2072X_DAC2_POWER_STATE:
341 	case CX2072X_DAC2_CONVERTER_STREAM_CHANNEL:
342 	case CX2072X_ADC1_CONVERTER_FORMAT:
343 	case CX2072X_ADC1_AMP_GAIN_RIGHT_0:
344 	case CX2072X_ADC1_AMP_GAIN_LEFT_0:
345 	case CX2072X_ADC1_AMP_GAIN_RIGHT_1:
346 	case CX2072X_ADC1_AMP_GAIN_LEFT_1:
347 	case CX2072X_ADC1_AMP_GAIN_RIGHT_2:
348 	case CX2072X_ADC1_AMP_GAIN_LEFT_2:
349 	case CX2072X_ADC1_AMP_GAIN_RIGHT_3:
350 	case CX2072X_ADC1_AMP_GAIN_LEFT_3:
351 	case CX2072X_ADC1_AMP_GAIN_RIGHT_4:
352 	case CX2072X_ADC1_AMP_GAIN_LEFT_4:
353 	case CX2072X_ADC1_AMP_GAIN_RIGHT_5:
354 	case CX2072X_ADC1_AMP_GAIN_LEFT_5:
355 	case CX2072X_ADC1_AMP_GAIN_RIGHT_6:
356 	case CX2072X_ADC1_AMP_GAIN_LEFT_6:
357 	case CX2072X_ADC1_CONNECTION_SELECT_CONTROL:
358 	case CX2072X_ADC1_POWER_STATE:
359 	case CX2072X_ADC1_CONVERTER_STREAM_CHANNEL:
360 	case CX2072X_ADC2_CONVERTER_FORMAT:
361 	case CX2072X_ADC2_AMP_GAIN_RIGHT_0:
362 	case CX2072X_ADC2_AMP_GAIN_LEFT_0:
363 	case CX2072X_ADC2_AMP_GAIN_RIGHT_1:
364 	case CX2072X_ADC2_AMP_GAIN_LEFT_1:
365 	case CX2072X_ADC2_AMP_GAIN_RIGHT_2:
366 	case CX2072X_ADC2_AMP_GAIN_LEFT_2:
367 	case CX2072X_ADC2_CONNECTION_SELECT_CONTROL:
368 	case CX2072X_ADC2_POWER_STATE:
369 	case CX2072X_ADC2_CONVERTER_STREAM_CHANNEL:
370 	case CX2072X_PORTA_CONNECTION_SELECT_CTRL:
371 	case CX2072X_PORTA_POWER_STATE:
372 	case CX2072X_PORTA_PIN_CTRL:
373 	case CX2072X_PORTA_UNSOLICITED_RESPONSE:
374 	case CX2072X_PORTA_PIN_SENSE:
375 	case CX2072X_PORTA_EAPD_BTL:
376 	case CX2072X_PORTB_POWER_STATE:
377 	case CX2072X_PORTB_PIN_CTRL:
378 	case CX2072X_PORTB_UNSOLICITED_RESPONSE:
379 	case CX2072X_PORTB_PIN_SENSE:
380 	case CX2072X_PORTB_EAPD_BTL:
381 	case CX2072X_PORTB_GAIN_RIGHT:
382 	case CX2072X_PORTB_GAIN_LEFT:
383 	case CX2072X_PORTC_POWER_STATE:
384 	case CX2072X_PORTC_PIN_CTRL:
385 	case CX2072X_PORTC_GAIN_RIGHT:
386 	case CX2072X_PORTC_GAIN_LEFT:
387 	case CX2072X_PORTD_POWER_STATE:
388 	case CX2072X_PORTD_PIN_CTRL:
389 	case CX2072X_PORTD_UNSOLICITED_RESPONSE:
390 	case CX2072X_PORTD_PIN_SENSE:
391 	case CX2072X_PORTD_GAIN_RIGHT:
392 	case CX2072X_PORTD_GAIN_LEFT:
393 	case CX2072X_PORTE_CONNECTION_SELECT_CTRL:
394 	case CX2072X_PORTE_POWER_STATE:
395 	case CX2072X_PORTE_PIN_CTRL:
396 	case CX2072X_PORTE_UNSOLICITED_RESPONSE:
397 	case CX2072X_PORTE_PIN_SENSE:
398 	case CX2072X_PORTE_EAPD_BTL:
399 	case CX2072X_PORTE_GAIN_RIGHT:
400 	case CX2072X_PORTE_GAIN_LEFT:
401 	case CX2072X_PORTF_POWER_STATE:
402 	case CX2072X_PORTF_PIN_CTRL:
403 	case CX2072X_PORTF_UNSOLICITED_RESPONSE:
404 	case CX2072X_PORTF_PIN_SENSE:
405 	case CX2072X_PORTF_GAIN_RIGHT:
406 	case CX2072X_PORTF_GAIN_LEFT:
407 	case CX2072X_PORTG_POWER_STATE:
408 	case CX2072X_PORTG_PIN_CTRL:
409 	case CX2072X_PORTG_CONNECTION_SELECT_CTRL:
410 	case CX2072X_PORTG_EAPD_BTL:
411 	case CX2072X_PORTM_POWER_STATE:
412 	case CX2072X_PORTM_PIN_CTRL:
413 	case CX2072X_PORTM_CONNECTION_SELECT_CTRL:
414 	case CX2072X_PORTM_EAPD_BTL:
415 	case CX2072X_MIXER_POWER_STATE:
416 	case CX2072X_MIXER_GAIN_RIGHT_0:
417 	case CX2072X_MIXER_GAIN_LEFT_0:
418 	case CX2072X_MIXER_GAIN_RIGHT_1:
419 	case CX2072X_MIXER_GAIN_LEFT_1:
420 	case CX2072X_EQ_ENABLE_BYPASS:
421 	case CX2072X_EQ_B0_COEFF:
422 	case CX2072X_EQ_B1_COEFF:
423 	case CX2072X_EQ_B2_COEFF:
424 	case CX2072X_EQ_A1_COEFF:
425 	case CX2072X_EQ_A2_COEFF:
426 	case CX2072X_EQ_G_COEFF:
427 	case CX2072X_SPKR_DRC_ENABLE_STEP:
428 	case CX2072X_SPKR_DRC_CONTROL:
429 	case CX2072X_SPKR_DRC_TEST:
430 	case CX2072X_DIGITAL_BIOS_TEST0:
431 	case CX2072X_DIGITAL_BIOS_TEST2:
432 	case CX2072X_I2SPCM_CONTROL1:
433 	case CX2072X_I2SPCM_CONTROL2:
434 	case CX2072X_I2SPCM_CONTROL3:
435 	case CX2072X_I2SPCM_CONTROL4:
436 	case CX2072X_I2SPCM_CONTROL5:
437 	case CX2072X_I2SPCM_CONTROL6:
438 	case CX2072X_UM_INTERRUPT_CRTL_E:
439 	case CX2072X_CODEC_TEST2:
440 	case CX2072X_CODEC_TEST9:
441 	case CX2072X_CODEC_TEST20:
442 	case CX2072X_CODEC_TEST26:
443 	case CX2072X_ANALOG_TEST4:
444 	case CX2072X_ANALOG_TEST5:
445 	case CX2072X_ANALOG_TEST6:
446 	case CX2072X_ANALOG_TEST7:
447 	case CX2072X_ANALOG_TEST8:
448 	case CX2072X_ANALOG_TEST9:
449 	case CX2072X_ANALOG_TEST10:
450 	case CX2072X_ANALOG_TEST11:
451 	case CX2072X_ANALOG_TEST12:
452 	case CX2072X_ANALOG_TEST13:
453 	case CX2072X_DIGITAL_TEST0:
454 	case CX2072X_DIGITAL_TEST1:
455 	case CX2072X_DIGITAL_TEST11:
456 	case CX2072X_DIGITAL_TEST12:
457 	case CX2072X_DIGITAL_TEST15:
458 	case CX2072X_DIGITAL_TEST16:
459 	case CX2072X_DIGITAL_TEST17:
460 	case CX2072X_DIGITAL_TEST18:
461 	case CX2072X_DIGITAL_TEST19:
462 	case CX2072X_DIGITAL_TEST20:
463 		return true;
464 	default:
465 		return false;
466 	}
467 }
468 
cx2072x_volatile_register(struct device * dev,unsigned int reg)469 static bool cx2072x_volatile_register(struct device *dev, unsigned int reg)
470 {
471 	switch (reg) {
472 	case CX2072X_VENDOR_ID:
473 	case CX2072X_REVISION_ID:
474 	case CX2072X_UM_INTERRUPT_CRTL_E:
475 	case CX2072X_DIGITAL_TEST11:
476 	case CX2072X_PORTA_PIN_SENSE:
477 	case CX2072X_PORTB_PIN_SENSE:
478 	case CX2072X_PORTD_PIN_SENSE:
479 	case CX2072X_PORTE_PIN_SENSE:
480 	case CX2072X_PORTF_PIN_SENSE:
481 	case CX2072X_EQ_G_COEFF:
482 	case CX2072X_EQ_BAND:
483 		return true;
484 	default:
485 		return false;
486 	}
487 }
488 
cx2072x_reg_raw_write(struct i2c_client * client,unsigned int reg,const void * val,size_t val_count)489 static int cx2072x_reg_raw_write(struct i2c_client *client,
490 				 unsigned int reg,
491 				 const void *val, size_t val_count)
492 {
493 	struct device *dev = &client->dev;
494 	u8 buf[2 + CX2072X_MAX_EQ_COEFF];
495 	int ret;
496 
497 	if (WARN_ON(val_count + 2 > sizeof(buf)))
498 		return -EINVAL;
499 
500 	buf[0] = reg >> 8;
501 	buf[1] = reg & 0xff;
502 
503 	memcpy(buf + 2, val, val_count);
504 
505 	ret = i2c_master_send(client, buf, val_count + 2);
506 	if (ret != val_count + 2) {
507 		dev_err(dev, "I2C write failed, ret = %d\n", ret);
508 		return ret < 0 ? ret : -EIO;
509 	}
510 	return 0;
511 }
512 
cx2072x_reg_write(void * context,unsigned int reg,unsigned int value)513 static int cx2072x_reg_write(void *context, unsigned int reg,
514 			     unsigned int value)
515 {
516 	__le32 raw_value;
517 	unsigned int size;
518 
519 	size = cx2072x_register_size(reg);
520 
521 	if (reg == CX2072X_UM_INTERRUPT_CRTL_E) {
522 		/* Update the MSB byte only */
523 		reg += 3;
524 		size = 1;
525 		value >>= 24;
526 	}
527 
528 	raw_value = cpu_to_le32(value);
529 	return cx2072x_reg_raw_write(context, reg, &raw_value, size);
530 }
531 
cx2072x_reg_read(void * context,unsigned int reg,unsigned int * value)532 static int cx2072x_reg_read(void *context, unsigned int reg,
533 			    unsigned int *value)
534 {
535 	struct i2c_client *client = context;
536 	struct device *dev = &client->dev;
537 	__le32 recv_buf = 0;
538 	struct i2c_msg msgs[2];
539 	unsigned int size;
540 	u8 send_buf[2];
541 	int ret;
542 
543 	size = cx2072x_register_size(reg);
544 
545 	send_buf[0] = reg >> 8;
546 	send_buf[1] = reg & 0xff;
547 
548 	msgs[0].addr = client->addr;
549 	msgs[0].len = sizeof(send_buf);
550 	msgs[0].buf = send_buf;
551 	msgs[0].flags = 0;
552 
553 	msgs[1].addr = client->addr;
554 	msgs[1].len = size;
555 	msgs[1].buf = (u8 *)&recv_buf;
556 	msgs[1].flags = I2C_M_RD;
557 
558 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
559 	if (ret != ARRAY_SIZE(msgs)) {
560 		dev_err(dev, "Failed to read register, ret = %d\n", ret);
561 		return ret < 0 ? ret : -EIO;
562 	}
563 
564 	*value = le32_to_cpu(recv_buf);
565 	return 0;
566 }
567 
568 /* get suggested pre_div valuce from mclk frequency */
get_div_from_mclk(unsigned int mclk)569 static unsigned int get_div_from_mclk(unsigned int mclk)
570 {
571 	unsigned int div = 8;
572 	int i;
573 
574 	for (i = 0; i < ARRAY_SIZE(mclk_pre_div); i++) {
575 		if (mclk <= mclk_pre_div[i].mclk) {
576 			div = mclk_pre_div[i].div;
577 			break;
578 		}
579 	}
580 	return div;
581 }
582 
cx2072x_config_pll(struct cx2072x_priv * cx2072x)583 static int cx2072x_config_pll(struct cx2072x_priv *cx2072x)
584 {
585 	struct device *dev = cx2072x->dev;
586 	unsigned int pre_div;
587 	unsigned int pre_div_val;
588 	unsigned int pll_input;
589 	unsigned int pll_output;
590 	unsigned int int_div;
591 	unsigned int frac_div;
592 	u64 frac_num;
593 	unsigned int frac;
594 	unsigned int sample_rate = cx2072x->sample_rate;
595 	int pt_sample_per_sync = 2;
596 	int pt_clock_per_sample = 96;
597 
598 	switch (sample_rate) {
599 	case 48000:
600 	case 32000:
601 	case 24000:
602 	case 16000:
603 		break;
604 
605 	case 96000:
606 		pt_sample_per_sync = 1;
607 		pt_clock_per_sample = 48;
608 		break;
609 
610 	case 192000:
611 		pt_sample_per_sync = 0;
612 		pt_clock_per_sample = 24;
613 		break;
614 
615 	default:
616 		dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
617 		return -EINVAL;
618 	}
619 
620 	/* Configure PLL settings */
621 	pre_div = get_div_from_mclk(cx2072x->mclk_rate);
622 	pll_input = cx2072x->mclk_rate / pre_div;
623 	pll_output = sample_rate * 3072;
624 	int_div = pll_output / pll_input;
625 	frac_div = pll_output - (int_div * pll_input);
626 
627 	if (frac_div) {
628 		frac_div *= 1000;
629 		frac_div /= pll_input;
630 		frac_num = (u64)(4000 + frac_div) * ((1 << 20) - 4);
631 		do_div(frac_num, 7);
632 		frac = ((u32)frac_num + 499) / 1000;
633 	}
634 	pre_div_val = (pre_div - 1) * 2;
635 
636 	regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST4,
637 		     0x40 | (pre_div_val << 8));
638 	if (frac_div == 0) {
639 		/* Int mode */
640 		regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7, 0x100);
641 	} else {
642 		/* frac mode */
643 		regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST6,
644 			     frac & 0xfff);
645 		regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7,
646 			     (u8)(frac >> 12));
647 	}
648 
649 	int_div--;
650 	regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST8, int_div);
651 
652 	/* configure PLL tracking */
653 	if (frac_div == 0) {
654 		/* disable PLL tracking */
655 		regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16, 0x00);
656 	} else {
657 		/* configure and enable PLL tracking */
658 		regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
659 			     (pt_sample_per_sync << 4) & 0xf0);
660 		regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST17,
661 			     pt_clock_per_sample);
662 		regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST18,
663 			     pt_clock_per_sample * 3 / 2);
664 		regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST19, 0x01);
665 		regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST20, 0x02);
666 		regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
667 				   0x01, 0x01);
668 	}
669 
670 	return 0;
671 }
672 
cx2072x_config_i2spcm(struct cx2072x_priv * cx2072x)673 static int cx2072x_config_i2spcm(struct cx2072x_priv *cx2072x)
674 {
675 	struct device *dev = cx2072x->dev;
676 	unsigned int bclk_rate = 0;
677 	int is_i2s = 0;
678 	int has_one_bit_delay = 0;
679 	int is_frame_inv = 0;
680 	int is_bclk_inv = 0;
681 	int pulse_len;
682 	int frame_len = cx2072x->frame_size;
683 	int sample_size = cx2072x->sample_size;
684 	int i2s_right_slot;
685 	int i2s_right_pause_interval = 0;
686 	int i2s_right_pause_pos;
687 	int is_big_endian = 1;
688 	u64 div;
689 	unsigned int mod;
690 	union cx2072x_reg_i2spcm_ctrl_reg1 reg1;
691 	union cx2072x_reg_i2spcm_ctrl_reg2 reg2;
692 	union cx2072x_reg_i2spcm_ctrl_reg3 reg3;
693 	union cx2072x_reg_i2spcm_ctrl_reg4 reg4;
694 	union cx2072x_reg_i2spcm_ctrl_reg5 reg5;
695 	union cx2072x_reg_i2spcm_ctrl_reg6 reg6;
696 	union cx2072x_reg_digital_bios_test2 regdbt2;
697 	const unsigned int fmt = cx2072x->dai_fmt;
698 
699 	if (frame_len <= 0) {
700 		dev_err(dev, "Incorrect frame len %d\n", frame_len);
701 		return -EINVAL;
702 	}
703 
704 	if (sample_size <= 0) {
705 		dev_err(dev, "Incorrect sample size %d\n", sample_size);
706 		return -EINVAL;
707 	}
708 
709 	dev_dbg(dev, "config_i2spcm set_dai_fmt- %08x\n", fmt);
710 
711 	regdbt2.ulval = 0xac;
712 
713 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
714 	case SND_SOC_DAIFMT_CBP_CFP:
715 		reg2.r.tx_master = 1;
716 		reg3.r.rx_master = 1;
717 		break;
718 
719 	case SND_SOC_DAIFMT_CBC_CFC:
720 		reg2.r.tx_master = 0;
721 		reg3.r.rx_master = 0;
722 		break;
723 
724 	default:
725 		dev_err(dev, "Unsupported DAI clocking mode\n");
726 		return -EINVAL;
727 	}
728 
729 	/* set format */
730 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
731 	case SND_SOC_DAIFMT_I2S:
732 		is_i2s = 1;
733 		has_one_bit_delay = 1;
734 		pulse_len = frame_len / 2;
735 		break;
736 
737 	case SND_SOC_DAIFMT_RIGHT_J:
738 		is_i2s = 1;
739 		pulse_len = frame_len / 2;
740 		break;
741 
742 	case SND_SOC_DAIFMT_LEFT_J:
743 		is_i2s = 1;
744 		pulse_len = frame_len / 2;
745 		break;
746 
747 	default:
748 		dev_err(dev, "Unsupported DAI format\n");
749 		return -EINVAL;
750 	}
751 
752 	/* clock inversion */
753 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
754 	case SND_SOC_DAIFMT_NB_NF:
755 		is_frame_inv = is_i2s;
756 		is_bclk_inv = is_i2s;
757 		break;
758 
759 	case SND_SOC_DAIFMT_IB_IF:
760 		is_frame_inv = !is_i2s;
761 		is_bclk_inv = !is_i2s;
762 		break;
763 
764 	case SND_SOC_DAIFMT_IB_NF:
765 		is_frame_inv = is_i2s;
766 		is_bclk_inv = !is_i2s;
767 		break;
768 
769 	case SND_SOC_DAIFMT_NB_IF:
770 		is_frame_inv = !is_i2s;
771 		is_bclk_inv = is_i2s;
772 		break;
773 
774 	default:
775 		dev_err(dev, "Unsupported DAI clock inversion\n");
776 		return -EINVAL;
777 	}
778 
779 	reg1.r.rx_data_one_line = 1;
780 	reg1.r.tx_data_one_line = 1;
781 
782 	if (is_i2s) {
783 		i2s_right_slot = (frame_len / 2) / BITS_PER_SLOT;
784 		i2s_right_pause_interval = (frame_len / 2) % BITS_PER_SLOT;
785 		i2s_right_pause_pos = i2s_right_slot * BITS_PER_SLOT;
786 	}
787 
788 	reg1.r.rx_ws_pol = is_frame_inv;
789 	reg1.r.rx_ws_wid = pulse_len - 1;
790 
791 	reg1.r.rx_frm_len = frame_len / BITS_PER_SLOT - 1;
792 	reg1.r.rx_sa_size = (sample_size / BITS_PER_SLOT) - 1;
793 
794 	reg1.r.tx_ws_pol = reg1.r.rx_ws_pol;
795 	reg1.r.tx_ws_wid = pulse_len - 1;
796 	reg1.r.tx_frm_len = reg1.r.rx_frm_len;
797 	reg1.r.tx_sa_size = reg1.r.rx_sa_size;
798 
799 	reg2.r.tx_endian_sel = !is_big_endian;
800 	reg2.r.tx_dstart_dly = has_one_bit_delay;
801 	if (cx2072x->en_aec_ref)
802 		reg2.r.tx_dstart_dly = 0;
803 
804 	reg3.r.rx_endian_sel = !is_big_endian;
805 	reg3.r.rx_dstart_dly = has_one_bit_delay;
806 
807 	reg4.ulval = 0;
808 
809 	if (is_i2s) {
810 		reg2.r.tx_slot_1 = 0;
811 		reg2.r.tx_slot_2 = i2s_right_slot;
812 		reg3.r.rx_slot_1 = 0;
813 		if (cx2072x->en_aec_ref)
814 			reg3.r.rx_slot_2 = 0;
815 		else
816 			reg3.r.rx_slot_2 = i2s_right_slot;
817 		reg6.r.rx_pause_start_pos = i2s_right_pause_pos;
818 		reg6.r.rx_pause_cycles = i2s_right_pause_interval;
819 		reg6.r.tx_pause_start_pos = i2s_right_pause_pos;
820 		reg6.r.tx_pause_cycles = i2s_right_pause_interval;
821 	} else {
822 		dev_err(dev, "TDM mode is not implemented yet\n");
823 		return -EINVAL;
824 	}
825 	regdbt2.r.i2s_bclk_invert = is_bclk_inv;
826 
827 	/* Configures the BCLK output */
828 	bclk_rate = cx2072x->sample_rate * frame_len;
829 	reg5.r.i2s_pcm_clk_div_chan_en = 0;
830 
831 	/* Disables bclk output before setting new value */
832 	regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, 0);
833 
834 	if (reg2.r.tx_master) {
835 		/* Configures BCLK rate */
836 		div = PLL_OUT_HZ_48;
837 		mod = do_div(div, bclk_rate);
838 		if (mod) {
839 			dev_err(dev, "Unsupported BCLK %dHz\n", bclk_rate);
840 			return -EINVAL;
841 		}
842 		dev_dbg(dev, "enables BCLK %dHz output\n", bclk_rate);
843 		reg5.r.i2s_pcm_clk_div = (u32)div - 1;
844 		reg5.r.i2s_pcm_clk_div_chan_en = 1;
845 	}
846 
847 	regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL1, reg1.ulval);
848 	regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL2, 0xffffffc0,
849 			   reg2.ulval);
850 	regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL3, 0xffffffc0,
851 			   reg3.ulval);
852 	regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL4, reg4.ulval);
853 	regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL6, reg6.ulval);
854 	regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, reg5.ulval);
855 
856 	regmap_write(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
857 		     regdbt2.ulval);
858 
859 	return 0;
860 }
861 
afg_power_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)862 static int afg_power_ev(struct snd_soc_dapm_widget *w,
863 			struct snd_kcontrol *kcontrol, int event)
864 {
865 	struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
866 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
867 
868 	switch (event) {
869 	case SND_SOC_DAPM_POST_PMU:
870 		regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
871 				   0x00, 0x10);
872 		break;
873 
874 	case SND_SOC_DAPM_PRE_PMD:
875 		regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
876 				   0x10, 0x10);
877 		break;
878 	}
879 
880 	return 0;
881 }
882 
883 static const struct snd_kcontrol_new cx2072x_snd_controls[] = {
884 	SOC_DOUBLE_R_TLV("PortD Boost Volume", CX2072X_PORTD_GAIN_LEFT,
885 			 CX2072X_PORTD_GAIN_RIGHT, 0, 3, 0, boost_tlv),
886 	SOC_DOUBLE_R_TLV("PortC Boost Volume", CX2072X_PORTC_GAIN_LEFT,
887 			 CX2072X_PORTC_GAIN_RIGHT, 0, 3, 0, boost_tlv),
888 	SOC_DOUBLE_R_TLV("PortB Boost Volume", CX2072X_PORTB_GAIN_LEFT,
889 			 CX2072X_PORTB_GAIN_RIGHT, 0, 3, 0, boost_tlv),
890 	SOC_DOUBLE_R_TLV("PortD ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_1,
891 			 CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0, 0x4a, 0, adc_tlv),
892 	SOC_DOUBLE_R_TLV("PortC ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_2,
893 			 CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0, 0x4a, 0, adc_tlv),
894 	SOC_DOUBLE_R_TLV("PortB ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_0,
895 			 CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0, 0x4a, 0, adc_tlv),
896 	SOC_DOUBLE_R_TLV("DAC1 Volume", CX2072X_DAC1_AMP_GAIN_LEFT,
897 			 CX2072X_DAC1_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
898 	SOC_DOUBLE_R("DAC1 Switch", CX2072X_DAC1_AMP_GAIN_LEFT,
899 		     CX2072X_DAC1_AMP_GAIN_RIGHT, 7,  1, 0),
900 	SOC_DOUBLE_R_TLV("DAC2 Volume", CX2072X_DAC2_AMP_GAIN_LEFT,
901 			 CX2072X_DAC2_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
902 	SOC_SINGLE_TLV("HPF Freq", CX2072X_CODEC_TEST9, 0, 0x3f, 0, hpf_tlv),
903 	SOC_DOUBLE("HPF Switch", CX2072X_CODEC_TEST9, 8, 9, 1, 1),
904 	SOC_SINGLE("PortA HP Amp Switch", CX2072X_PORTA_PIN_CTRL, 7, 1, 0),
905 };
906 
cx2072x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)907 static int cx2072x_hw_params(struct snd_pcm_substream *substream,
908 			     struct snd_pcm_hw_params *params,
909 			     struct snd_soc_dai *dai)
910 {
911 	struct snd_soc_component *codec = dai->component;
912 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
913 	struct device *dev = codec->dev;
914 	const unsigned int sample_rate = params_rate(params);
915 	int sample_size, frame_size;
916 
917 	/* Data sizes if not using TDM */
918 	sample_size = params_width(params);
919 
920 	if (sample_size < 0)
921 		return sample_size;
922 
923 	frame_size = snd_soc_params_to_frame_size(params);
924 	if (frame_size < 0)
925 		return frame_size;
926 
927 	if (cx2072x->mclk_rate == 0) {
928 		dev_err(dev, "Master clock rate is not configured\n");
929 		return -EINVAL;
930 	}
931 
932 	if (cx2072x->bclk_ratio)
933 		frame_size = cx2072x->bclk_ratio;
934 
935 	switch (sample_rate) {
936 	case 48000:
937 	case 32000:
938 	case 24000:
939 	case 16000:
940 	case 96000:
941 	case 192000:
942 		break;
943 
944 	default:
945 		dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
946 		return -EINVAL;
947 	}
948 
949 	dev_dbg(dev, "Sample size %d bits, frame = %d bits, rate = %d Hz\n",
950 		sample_size, frame_size, sample_rate);
951 
952 	cx2072x->frame_size = frame_size;
953 	cx2072x->sample_size = sample_size;
954 	cx2072x->sample_rate = sample_rate;
955 
956 	if (dai->id == CX2072X_DAI_DSP) {
957 		cx2072x->en_aec_ref = true;
958 		dev_dbg(cx2072x->dev, "enables aec reference\n");
959 		regmap_write(cx2072x->regmap,
960 			     CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 3);
961 	}
962 
963 	if (cx2072x->pll_changed) {
964 		cx2072x_config_pll(cx2072x);
965 		cx2072x->pll_changed = false;
966 	}
967 
968 	if (cx2072x->i2spcm_changed) {
969 		cx2072x_config_i2spcm(cx2072x);
970 		cx2072x->i2spcm_changed = false;
971 	}
972 
973 	return 0;
974 }
975 
cx2072x_set_dai_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)976 static int cx2072x_set_dai_bclk_ratio(struct snd_soc_dai *dai,
977 				      unsigned int ratio)
978 {
979 	struct snd_soc_component *codec = dai->component;
980 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
981 
982 	cx2072x->bclk_ratio = ratio;
983 	return 0;
984 }
985 
cx2072x_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)986 static int cx2072x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
987 				  unsigned int freq, int dir)
988 {
989 	struct snd_soc_component *codec = dai->component;
990 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
991 
992 	if (clk_set_rate(cx2072x->mclk, freq)) {
993 		dev_err(codec->dev, "set clk rate failed\n");
994 		return -EINVAL;
995 	}
996 
997 	cx2072x->mclk_rate = freq;
998 	return 0;
999 }
1000 
cx2072x_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1001 static int cx2072x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1002 {
1003 	struct snd_soc_component *codec = dai->component;
1004 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1005 	struct device *dev = codec->dev;
1006 
1007 	dev_dbg(dev, "set_dai_fmt- %08x\n", fmt);
1008 	/* set master/slave */
1009 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1010 	case SND_SOC_DAIFMT_CBP_CFP:
1011 	case SND_SOC_DAIFMT_CBC_CFC:
1012 		break;
1013 
1014 	default:
1015 		dev_err(dev, "Unsupported DAI master mode\n");
1016 		return -EINVAL;
1017 	}
1018 
1019 	/* set format */
1020 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1021 	case SND_SOC_DAIFMT_I2S:
1022 	case SND_SOC_DAIFMT_RIGHT_J:
1023 	case SND_SOC_DAIFMT_LEFT_J:
1024 		break;
1025 
1026 	default:
1027 		dev_err(dev, "Unsupported DAI format\n");
1028 		return -EINVAL;
1029 	}
1030 
1031 	/* clock inversion */
1032 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1033 	case SND_SOC_DAIFMT_NB_NF:
1034 	case SND_SOC_DAIFMT_IB_IF:
1035 	case SND_SOC_DAIFMT_IB_NF:
1036 	case SND_SOC_DAIFMT_NB_IF:
1037 		break;
1038 
1039 	default:
1040 		dev_err(dev, "Unsupported DAI clock inversion\n");
1041 		return -EINVAL;
1042 	}
1043 
1044 	cx2072x->dai_fmt = fmt;
1045 	return 0;
1046 }
1047 
1048 static const struct snd_kcontrol_new portaouten_ctl =
1049 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTA_PIN_CTRL, 6, 1, 0);
1050 
1051 static const struct snd_kcontrol_new porteouten_ctl =
1052 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 6, 1, 0);
1053 
1054 static const struct snd_kcontrol_new portgouten_ctl =
1055 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTG_PIN_CTRL, 6, 1, 0);
1056 
1057 static const struct snd_kcontrol_new portmouten_ctl =
1058 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTM_PIN_CTRL, 6, 1, 0);
1059 
1060 static const struct snd_kcontrol_new portbinen_ctl =
1061 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTB_PIN_CTRL, 5, 1, 0);
1062 
1063 static const struct snd_kcontrol_new portcinen_ctl =
1064 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTC_PIN_CTRL, 5, 1, 0);
1065 
1066 static const struct snd_kcontrol_new portdinen_ctl =
1067 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTD_PIN_CTRL, 5, 1, 0);
1068 
1069 static const struct snd_kcontrol_new porteinen_ctl =
1070 	SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 5, 1, 0);
1071 
1072 static const struct snd_kcontrol_new i2sadc1l_ctl =
1073 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 0, 1, 0);
1074 
1075 static const struct snd_kcontrol_new i2sadc1r_ctl =
1076 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 1, 1, 0);
1077 
1078 static const struct snd_kcontrol_new i2sadc2l_ctl =
1079 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 2, 1, 0);
1080 
1081 static const struct snd_kcontrol_new i2sadc2r_ctl =
1082 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 3, 1, 0);
1083 
1084 static const struct snd_kcontrol_new i2sdac1l_ctl =
1085 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 0, 1, 0);
1086 
1087 static const struct snd_kcontrol_new i2sdac1r_ctl =
1088 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 1, 1, 0);
1089 
1090 static const struct snd_kcontrol_new i2sdac2l_ctl =
1091 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 2, 1, 0);
1092 
1093 static const struct snd_kcontrol_new i2sdac2r_ctl =
1094 	SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 3, 1, 0);
1095 
1096 static const char * const dac_enum_text[] = {
1097 	"DAC1 Switch", "DAC2 Switch",
1098 };
1099 
1100 static const struct soc_enum porta_dac_enum =
1101 SOC_ENUM_SINGLE(CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1102 
1103 static const struct snd_kcontrol_new porta_mux =
1104 SOC_DAPM_ENUM("PortA Mux", porta_dac_enum);
1105 
1106 static const struct soc_enum portg_dac_enum =
1107 SOC_ENUM_SINGLE(CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1108 
1109 static const struct snd_kcontrol_new portg_mux =
1110 SOC_DAPM_ENUM("PortG Mux", portg_dac_enum);
1111 
1112 static const struct soc_enum porte_dac_enum =
1113 SOC_ENUM_SINGLE(CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1114 
1115 static const struct snd_kcontrol_new porte_mux =
1116 SOC_DAPM_ENUM("PortE Mux", porte_dac_enum);
1117 
1118 static const struct soc_enum portm_dac_enum =
1119 SOC_ENUM_SINGLE(CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1120 
1121 static const struct snd_kcontrol_new portm_mux =
1122 SOC_DAPM_ENUM("PortM Mux", portm_dac_enum);
1123 
1124 static const char * const adc1in_sel_text[] = {
1125 	"PortB Switch", "PortD Switch", "PortC Switch", "Widget15 Switch",
1126 	"PortE Switch", "PortF Switch", "PortH Switch"
1127 };
1128 
1129 static const struct soc_enum adc1in_sel_enum =
1130 SOC_ENUM_SINGLE(CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0, 7, adc1in_sel_text);
1131 
1132 static const struct snd_kcontrol_new adc1_mux =
1133 SOC_DAPM_ENUM("ADC1 Mux", adc1in_sel_enum);
1134 
1135 static const char * const adc2in_sel_text[] = {
1136 	"PortC Switch", "Widget15 Switch", "PortH Switch"
1137 };
1138 
1139 static const struct soc_enum adc2in_sel_enum =
1140 SOC_ENUM_SINGLE(CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0, 3, adc2in_sel_text);
1141 
1142 static const struct snd_kcontrol_new adc2_mux =
1143 SOC_DAPM_ENUM("ADC2 Mux", adc2in_sel_enum);
1144 
1145 static const struct snd_kcontrol_new wid15_mix[] = {
1146 	SOC_DAPM_SINGLE("DAC1L Switch", CX2072X_MIXER_GAIN_LEFT_0, 7, 1, 1),
1147 	SOC_DAPM_SINGLE("DAC1R Switch", CX2072X_MIXER_GAIN_RIGHT_0, 7, 1, 1),
1148 	SOC_DAPM_SINGLE("DAC2L Switch", CX2072X_MIXER_GAIN_LEFT_1, 7, 1, 1),
1149 	SOC_DAPM_SINGLE("DAC2R Switch", CX2072X_MIXER_GAIN_RIGHT_1, 7, 1, 1),
1150 };
1151 
1152 #define CX2072X_DAPM_SUPPLY_S(wname, wsubseq, wreg, wshift, wmask,  won_val, \
1153 	woff_val, wevent, wflags) \
1154 	{.id = snd_soc_dapm_supply, .name = wname, .kcontrol_news = NULL, \
1155 	.num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1156 	.on_val = won_val, .off_val = woff_val, \
1157 	.subseq = wsubseq, .event = wevent, .event_flags = wflags}
1158 
1159 #define CX2072X_DAPM_SWITCH(wname,  wreg, wshift, wmask,  won_val, woff_val, \
1160 	wevent, wflags) \
1161 	{.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
1162 	.num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1163 	.on_val = won_val, .off_val = woff_val, \
1164 	.event = wevent, .event_flags = wflags}
1165 
1166 #define CX2072X_DAPM_SWITCH(wname,  wreg, wshift, wmask,  won_val, woff_val, \
1167 	wevent, wflags) \
1168 	{.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
1169 	.num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1170 	.on_val = won_val, .off_val = woff_val, \
1171 	.event = wevent, .event_flags = wflags}
1172 
1173 #define CX2072X_DAPM_REG_E(wid, wname, wreg, wshift, wmask, won_val, woff_val, \
1174 				wevent, wflags) \
1175 	{.id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \
1176 	.reg = wreg, .shift = wshift, .mask = wmask, \
1177 	.on_val = won_val, .off_val = woff_val, \
1178 	.event = wevent, .event_flags = wflags}
1179 
1180 static const struct snd_soc_dapm_widget cx2072x_dapm_widgets[] = {
1181 	/*Playback*/
1182 	SND_SOC_DAPM_AIF_IN("In AIF", "Playback", 0, SND_SOC_NOPM, 0, 0),
1183 
1184 	SND_SOC_DAPM_SWITCH("I2S DAC1L", SND_SOC_NOPM, 0, 0, &i2sdac1l_ctl),
1185 	SND_SOC_DAPM_SWITCH("I2S DAC1R", SND_SOC_NOPM, 0, 0, &i2sdac1r_ctl),
1186 	SND_SOC_DAPM_SWITCH("I2S DAC2L", SND_SOC_NOPM, 0, 0, &i2sdac2l_ctl),
1187 	SND_SOC_DAPM_SWITCH("I2S DAC2R", SND_SOC_NOPM, 0, 0, &i2sdac2r_ctl),
1188 
1189 	SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC1", CX2072X_DAC1_POWER_STATE,
1190 			 0, 0xfff, 0x00, 0x03),
1191 
1192 	SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC2", CX2072X_DAC2_POWER_STATE,
1193 			 0, 0xfff, 0x00, 0x03),
1194 
1195 	SND_SOC_DAPM_MUX("PortA Mux", SND_SOC_NOPM, 0, 0, &porta_mux),
1196 	SND_SOC_DAPM_MUX("PortG Mux", SND_SOC_NOPM, 0, 0, &portg_mux),
1197 	SND_SOC_DAPM_MUX("PortE Mux", SND_SOC_NOPM, 0, 0, &porte_mux),
1198 	SND_SOC_DAPM_MUX("PortM Mux", SND_SOC_NOPM, 0, 0, &portm_mux),
1199 
1200 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortA Power",
1201 			 CX2072X_PORTA_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1202 
1203 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortM Power",
1204 			 CX2072X_PORTM_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1205 
1206 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortG Power",
1207 			 CX2072X_PORTG_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1208 
1209 	CX2072X_DAPM_SUPPLY_S("AFG Power", 0, CX2072X_AFG_POWER_STATE,
1210 			      0, 0xfff, 0x00, 0x03, afg_power_ev,
1211 			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1212 
1213 	SND_SOC_DAPM_SWITCH("PortA Out En", SND_SOC_NOPM, 0, 0,
1214 			    &portaouten_ctl),
1215 	SND_SOC_DAPM_SWITCH("PortE Out En", SND_SOC_NOPM, 0, 0,
1216 			    &porteouten_ctl),
1217 	SND_SOC_DAPM_SWITCH("PortG Out En", SND_SOC_NOPM, 0, 0,
1218 			    &portgouten_ctl),
1219 	SND_SOC_DAPM_SWITCH("PortM Out En", SND_SOC_NOPM, 0, 0,
1220 			    &portmouten_ctl),
1221 
1222 	SND_SOC_DAPM_OUTPUT("PORTA"),
1223 	SND_SOC_DAPM_OUTPUT("PORTG"),
1224 	SND_SOC_DAPM_OUTPUT("PORTE"),
1225 	SND_SOC_DAPM_OUTPUT("PORTM"),
1226 	SND_SOC_DAPM_OUTPUT("AEC REF"),
1227 
1228 	/*Capture*/
1229 	SND_SOC_DAPM_AIF_OUT("Out AIF", "Capture", 0, SND_SOC_NOPM, 0, 0),
1230 
1231 	SND_SOC_DAPM_SWITCH("I2S ADC1L", SND_SOC_NOPM, 0, 0, &i2sadc1l_ctl),
1232 	SND_SOC_DAPM_SWITCH("I2S ADC1R", SND_SOC_NOPM, 0, 0, &i2sadc1r_ctl),
1233 	SND_SOC_DAPM_SWITCH("I2S ADC2L", SND_SOC_NOPM, 0, 0, &i2sadc2l_ctl),
1234 	SND_SOC_DAPM_SWITCH("I2S ADC2R", SND_SOC_NOPM, 0, 0, &i2sadc2r_ctl),
1235 
1236 	SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC1", CX2072X_ADC1_POWER_STATE,
1237 			 0, 0xff, 0x00, 0x03),
1238 	SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC2", CX2072X_ADC2_POWER_STATE,
1239 			 0, 0xff, 0x00, 0x03),
1240 
1241 	SND_SOC_DAPM_MUX("ADC1 Mux", SND_SOC_NOPM, 0, 0, &adc1_mux),
1242 	SND_SOC_DAPM_MUX("ADC2 Mux", SND_SOC_NOPM, 0, 0, &adc2_mux),
1243 
1244 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortB Power",
1245 			 CX2072X_PORTB_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1246 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortC Power",
1247 			 CX2072X_PORTC_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1248 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortD Power",
1249 			 CX2072X_PORTD_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1250 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortE Power",
1251 			 CX2072X_PORTE_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1252 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "Widget15 Power",
1253 			 CX2072X_MIXER_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1254 
1255 	SND_SOC_DAPM_MIXER("Widget15 Mixer", SND_SOC_NOPM, 0, 0,
1256 			   wid15_mix, ARRAY_SIZE(wid15_mix)),
1257 	SND_SOC_DAPM_SWITCH("PortB In En", SND_SOC_NOPM, 0, 0, &portbinen_ctl),
1258 	SND_SOC_DAPM_SWITCH("PortC In En", SND_SOC_NOPM, 0, 0, &portcinen_ctl),
1259 	SND_SOC_DAPM_SWITCH("PortD In En", SND_SOC_NOPM, 0, 0, &portdinen_ctl),
1260 	SND_SOC_DAPM_SWITCH("PortE In En", SND_SOC_NOPM, 0, 0, &porteinen_ctl),
1261 
1262 	SND_SOC_DAPM_MICBIAS("Headset Bias", CX2072X_ANALOG_TEST11, 1, 0),
1263 	SND_SOC_DAPM_MICBIAS("PortB Mic Bias", CX2072X_PORTB_PIN_CTRL, 2, 0),
1264 	SND_SOC_DAPM_MICBIAS("PortD Mic Bias", CX2072X_PORTD_PIN_CTRL, 2, 0),
1265 	SND_SOC_DAPM_MICBIAS("PortE Mic Bias", CX2072X_PORTE_PIN_CTRL, 2, 0),
1266 	SND_SOC_DAPM_INPUT("PORTB"),
1267 	SND_SOC_DAPM_INPUT("PORTC"),
1268 	SND_SOC_DAPM_INPUT("PORTD"),
1269 	SND_SOC_DAPM_INPUT("PORTEIN"),
1270 
1271 };
1272 
1273 static const struct snd_soc_dapm_route cx2072x_intercon[] = {
1274 	/* Playback */
1275 	{"In AIF", NULL, "AFG Power"},
1276 	{"I2S DAC1L", "Switch", "In AIF"},
1277 	{"I2S DAC1R", "Switch", "In AIF"},
1278 	{"I2S DAC2L", "Switch", "In AIF"},
1279 	{"I2S DAC2R", "Switch", "In AIF"},
1280 	{"DAC1", NULL, "I2S DAC1L"},
1281 	{"DAC1", NULL, "I2S DAC1R"},
1282 	{"DAC2", NULL, "I2S DAC2L"},
1283 	{"DAC2", NULL, "I2S DAC2R"},
1284 	{"PortA Mux", "DAC1 Switch", "DAC1"},
1285 	{"PortA Mux", "DAC2 Switch", "DAC2"},
1286 	{"PortG Mux", "DAC1 Switch", "DAC1"},
1287 	{"PortG Mux", "DAC2 Switch", "DAC2"},
1288 	{"PortE Mux", "DAC1 Switch", "DAC1"},
1289 	{"PortE Mux", "DAC2 Switch", "DAC2"},
1290 	{"PortM Mux", "DAC1 Switch", "DAC1"},
1291 	{"PortM Mux", "DAC2 Switch", "DAC2"},
1292 	{"Widget15 Mixer", "DAC1L Switch", "DAC1"},
1293 	{"Widget15 Mixer", "DAC1R Switch", "DAC2"},
1294 	{"Widget15 Mixer", "DAC2L Switch", "DAC1"},
1295 	{"Widget15 Mixer", "DAC2R Switch", "DAC2"},
1296 	{"Widget15 Mixer", NULL, "Widget15 Power"},
1297 	{"PortA Out En", "Switch", "PortA Mux"},
1298 	{"PortG Out En", "Switch", "PortG Mux"},
1299 	{"PortE Out En", "Switch", "PortE Mux"},
1300 	{"PortM Out En", "Switch", "PortM Mux"},
1301 	{"PortA Mux", NULL, "PortA Power"},
1302 	{"PortG Mux", NULL, "PortG Power"},
1303 	{"PortE Mux", NULL, "PortE Power"},
1304 	{"PortM Mux", NULL, "PortM Power"},
1305 	{"PortA Out En", NULL, "PortA Power"},
1306 	{"PortG Out En", NULL, "PortG Power"},
1307 	{"PortE Out En", NULL, "PortE Power"},
1308 	{"PortM Out En", NULL, "PortM Power"},
1309 	{"PORTA", NULL, "PortA Out En"},
1310 	{"PORTG", NULL, "PortG Out En"},
1311 	{"PORTE", NULL, "PortE Out En"},
1312 	{"PORTM", NULL, "PortM Out En"},
1313 
1314 	/* Capture */
1315 	{"PORTD", NULL, "Headset Bias"},
1316 	{"PortB In En", "Switch", "PORTB"},
1317 	{"PortC In En", "Switch", "PORTC"},
1318 	{"PortD In En", "Switch", "PORTD"},
1319 	{"PortE In En", "Switch", "PORTEIN"},
1320 	{"ADC1 Mux", "PortB Switch", "PortB In En"},
1321 	{"ADC1 Mux", "PortC Switch", "PortC In En"},
1322 	{"ADC1 Mux", "PortD Switch", "PortD In En"},
1323 	{"ADC1 Mux", "PortE Switch", "PortE In En"},
1324 	{"ADC1 Mux", "Widget15 Switch", "Widget15 Mixer"},
1325 	{"ADC2 Mux", "PortC Switch", "PortC In En"},
1326 	{"ADC2 Mux", "Widget15 Switch", "Widget15 Mixer"},
1327 	{"ADC1", NULL, "ADC1 Mux"},
1328 	{"ADC2", NULL, "ADC2 Mux"},
1329 	{"I2S ADC1L", "Switch", "ADC1"},
1330 	{"I2S ADC1R", "Switch", "ADC1"},
1331 	{"I2S ADC2L", "Switch", "ADC2"},
1332 	{"I2S ADC2R", "Switch", "ADC2"},
1333 	{"Out AIF", NULL, "I2S ADC1L"},
1334 	{"Out AIF", NULL, "I2S ADC1R"},
1335 	{"Out AIF", NULL, "I2S ADC2L"},
1336 	{"Out AIF", NULL, "I2S ADC2R"},
1337 	{"Out AIF", NULL, "AFG Power"},
1338 	{"AEC REF", NULL, "Out AIF"},
1339 	{"PortB In En", NULL, "PortB Power"},
1340 	{"PortC In En", NULL, "PortC Power"},
1341 	{"PortD In En", NULL, "PortD Power"},
1342 	{"PortE In En", NULL, "PortE Power"},
1343 };
1344 
cx2072x_set_bias_level(struct snd_soc_component * codec,enum snd_soc_bias_level level)1345 static int cx2072x_set_bias_level(struct snd_soc_component *codec,
1346 				  enum snd_soc_bias_level level)
1347 {
1348 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1349 	const enum snd_soc_bias_level old_level =
1350 		snd_soc_component_get_bias_level(codec);
1351 
1352 	if (level == SND_SOC_BIAS_STANDBY && old_level == SND_SOC_BIAS_OFF)
1353 		regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0);
1354 	else if (level == SND_SOC_BIAS_OFF && old_level != SND_SOC_BIAS_OFF)
1355 		regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 3);
1356 
1357 	return 0;
1358 }
1359 
1360 /*
1361  * FIXME: the whole jack detection code below is pretty platform-specific;
1362  * it has lots of implicit assumptions about the pins, etc.
1363  * However, since we have no other code and reference, take this hard-coded
1364  * setup for now.  Once when we have different platform implementations,
1365  * this needs to be rewritten in a more generic form, or moving into the
1366  * platform data.
1367  */
cx2072x_enable_jack_detect(struct snd_soc_component * codec)1368 static void cx2072x_enable_jack_detect(struct snd_soc_component *codec)
1369 {
1370 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1371 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec);
1372 
1373 	/* No-sticky input type */
1374 	regmap_write(cx2072x->regmap, CX2072X_GPIO_STICKY_MASK, 0x1f);
1375 
1376 	/* Use GPOI0 as interrupt pin */
1377 	regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
1378 
1379 	/* Enables unsolitited message on PortA */
1380 	regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x80);
1381 
1382 	/* support both nokia and apple headset set. Monitor time = 275 ms */
1383 	regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST15, 0x73);
1384 
1385 	/* Disable TIP detection */
1386 	regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST12, 0x300);
1387 
1388 	/* Switch MusicD3Live pin to GPIO */
1389 	regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST1, 0);
1390 
1391 	snd_soc_dapm_mutex_lock(dapm);
1392 
1393 	snd_soc_dapm_force_enable_pin_unlocked(dapm, "PORTD");
1394 	snd_soc_dapm_force_enable_pin_unlocked(dapm, "Headset Bias");
1395 	snd_soc_dapm_force_enable_pin_unlocked(dapm, "PortD Mic Bias");
1396 
1397 	snd_soc_dapm_mutex_unlock(dapm);
1398 }
1399 
cx2072x_disable_jack_detect(struct snd_soc_component * codec)1400 static void cx2072x_disable_jack_detect(struct snd_soc_component *codec)
1401 {
1402 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1403 
1404 	regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0);
1405 	regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0);
1406 }
1407 
cx2072x_jack_status_check(void * data)1408 static int cx2072x_jack_status_check(void *data)
1409 {
1410 	struct snd_soc_component *codec = data;
1411 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1412 	unsigned int jack;
1413 	unsigned int type = 0;
1414 	int state = 0;
1415 
1416 	mutex_lock(&cx2072x->lock);
1417 
1418 	regmap_read(cx2072x->regmap, CX2072X_PORTA_PIN_SENSE, &jack);
1419 	jack = jack >> 24;
1420 	regmap_read(cx2072x->regmap, CX2072X_DIGITAL_TEST11, &type);
1421 
1422 	if (jack == 0x80) {
1423 		type = type >> 8;
1424 
1425 		if (type & 0x8) {
1426 			/* Apple headset */
1427 			state |= SND_JACK_HEADSET;
1428 			if (type & 0x2)
1429 				state |= SND_JACK_BTN_0;
1430 		} else {
1431 			/*
1432 			 * Nokia headset (type & 0x4) and
1433 			 * regular Headphone
1434 			 */
1435 			state |= SND_JACK_HEADPHONE;
1436 		}
1437 	}
1438 
1439 	/* clear interrupt */
1440 	regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
1441 
1442 	mutex_unlock(&cx2072x->lock);
1443 
1444 	dev_dbg(codec->dev, "CX2072X_HSDETECT type=0x%X,Jack state = %x\n",
1445 		type, state);
1446 	return state;
1447 }
1448 
1449 static const struct snd_soc_jack_gpio cx2072x_jack_gpio = {
1450 	.name = "headset",
1451 	.report = SND_JACK_HEADSET | SND_JACK_BTN_0,
1452 	.debounce_time = 150,
1453 	.wake = true,
1454 	.jack_status_check = cx2072x_jack_status_check,
1455 };
1456 
cx2072x_set_jack(struct snd_soc_component * codec,struct snd_soc_jack * jack,void * data)1457 static int cx2072x_set_jack(struct snd_soc_component *codec,
1458 			    struct snd_soc_jack *jack, void *data)
1459 {
1460 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1461 	int err;
1462 
1463 	if (!jack) {
1464 		cx2072x_disable_jack_detect(codec);
1465 		return 0;
1466 	}
1467 
1468 	if (!cx2072x->jack_gpio.gpiod_dev) {
1469 		cx2072x->jack_gpio = cx2072x_jack_gpio;
1470 		cx2072x->jack_gpio.gpiod_dev = codec->dev;
1471 		cx2072x->jack_gpio.data = codec;
1472 		err = snd_soc_jack_add_gpios(jack, 1, &cx2072x->jack_gpio);
1473 		if (err) {
1474 			cx2072x->jack_gpio.gpiod_dev = NULL;
1475 			return err;
1476 		}
1477 	}
1478 
1479 	cx2072x_enable_jack_detect(codec);
1480 	return 0;
1481 }
1482 
cx2072x_probe(struct snd_soc_component * codec)1483 static int cx2072x_probe(struct snd_soc_component *codec)
1484 {
1485 	struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1486 
1487 	cx2072x->codec = codec;
1488 
1489 	/*
1490 	 * FIXME: below is, again, a very platform-specific init sequence,
1491 	 * but we keep the code here just for simplicity.  It seems that all
1492 	 * existing hardware implementations require this, so there is no very
1493 	 * much reason to move this out of the codec driver to the platform
1494 	 * data.
1495 	 * But of course it's no "right" thing; if you are a good boy, don't
1496 	 * read and follow the code like this!
1497 	 */
1498 	pm_runtime_get_sync(codec->dev);
1499 	regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0);
1500 
1501 	regmap_multi_reg_write(cx2072x->regmap, cx2072x_reg_init,
1502 			       ARRAY_SIZE(cx2072x_reg_init));
1503 
1504 	/* configure PortC as input device */
1505 	regmap_update_bits(cx2072x->regmap, CX2072X_PORTC_PIN_CTRL,
1506 			   0x20, 0x20);
1507 
1508 	regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
1509 			   0x84, 0xff);
1510 
1511 	regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 3);
1512 	pm_runtime_put(codec->dev);
1513 
1514 	return 0;
1515 }
1516 
1517 static const struct snd_soc_component_driver soc_codec_driver_cx2072x = {
1518 	.probe = cx2072x_probe,
1519 	.set_bias_level = cx2072x_set_bias_level,
1520 	.set_jack = cx2072x_set_jack,
1521 	.controls = cx2072x_snd_controls,
1522 	.num_controls = ARRAY_SIZE(cx2072x_snd_controls),
1523 	.dapm_widgets = cx2072x_dapm_widgets,
1524 	.num_dapm_widgets = ARRAY_SIZE(cx2072x_dapm_widgets),
1525 	.dapm_routes = cx2072x_intercon,
1526 	.num_dapm_routes = ARRAY_SIZE(cx2072x_intercon),
1527 	.endianness = 1,
1528 };
1529 
1530 /*
1531  * DAI ops
1532  */
1533 static const struct snd_soc_dai_ops cx2072x_dai_ops = {
1534 	.set_sysclk = cx2072x_set_dai_sysclk,
1535 	.set_fmt = cx2072x_set_dai_fmt,
1536 	.hw_params = cx2072x_hw_params,
1537 	.set_bclk_ratio = cx2072x_set_dai_bclk_ratio,
1538 };
1539 
cx2072x_dsp_dai_probe(struct snd_soc_dai * dai)1540 static int cx2072x_dsp_dai_probe(struct snd_soc_dai *dai)
1541 {
1542 	struct cx2072x_priv *cx2072x =
1543 		snd_soc_component_get_drvdata(dai->component);
1544 
1545 	cx2072x->en_aec_ref = true;
1546 	return 0;
1547 }
1548 
1549 static const struct snd_soc_dai_ops cx2072x_dai_ops2 = {
1550 	.probe		= cx2072x_dsp_dai_probe,
1551 	.set_sysclk	= cx2072x_set_dai_sysclk,
1552 	.set_fmt	= cx2072x_set_dai_fmt,
1553 	.hw_params	= cx2072x_hw_params,
1554 	.set_bclk_ratio	= cx2072x_set_dai_bclk_ratio,
1555 };
1556 
1557 #define CX2072X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1558 
1559 static struct snd_soc_dai_driver soc_codec_cx2072x_dai[] = {
1560 	{ /* playback and capture */
1561 		.name = "cx2072x-hifi",
1562 		.id	= CX2072X_DAI_HIFI,
1563 		.playback = {
1564 			.stream_name = "Playback",
1565 			.channels_min = 1,
1566 			.channels_max = 2,
1567 			.rates = CX2072X_RATES_DSP,
1568 			.formats = CX2072X_FORMATS,
1569 		},
1570 		.capture = {
1571 			.stream_name = "Capture",
1572 			.channels_min = 1,
1573 			.channels_max = 2,
1574 			.rates = CX2072X_RATES_DSP,
1575 			.formats = CX2072X_FORMATS,
1576 		},
1577 		.ops = &cx2072x_dai_ops,
1578 		.symmetric_rate = 1,
1579 	},
1580 	{ /* plabayck only, return echo reference to Conexant DSP chip */
1581 		.name = "cx2072x-dsp",
1582 		.id	= CX2072X_DAI_DSP,
1583 		.playback = {
1584 			.stream_name = "DSP Playback",
1585 			.channels_min = 2,
1586 			.channels_max = 2,
1587 			.rates = CX2072X_RATES_DSP,
1588 			.formats = CX2072X_FORMATS,
1589 		},
1590 		.ops = &cx2072x_dai_ops2,
1591 	},
1592 	{ /* plabayck only, return echo reference through I2S TX */
1593 		.name = "cx2072x-aec",
1594 		.id	= 3,
1595 		.capture = {
1596 			.stream_name = "AEC Capture",
1597 			.channels_min = 2,
1598 			.channels_max = 2,
1599 			.rates = CX2072X_RATES_DSP,
1600 			.formats = CX2072X_FORMATS,
1601 		},
1602 	},
1603 };
1604 
1605 static const struct regmap_config cx2072x_regmap = {
1606 	.reg_bits = 16,
1607 	.val_bits = 32,
1608 	.max_register = CX2072X_REG_MAX,
1609 	.reg_defaults = cx2072x_reg_defaults,
1610 	.num_reg_defaults = ARRAY_SIZE(cx2072x_reg_defaults),
1611 	.cache_type = REGCACHE_RBTREE,
1612 	.readable_reg = cx2072x_readable_register,
1613 	.volatile_reg = cx2072x_volatile_register,
1614 	/* Needs custom read/write functions for various register lengths */
1615 	.reg_read = cx2072x_reg_read,
1616 	.reg_write = cx2072x_reg_write,
1617 };
1618 
cx2072x_runtime_suspend(struct device * dev)1619 static int __maybe_unused cx2072x_runtime_suspend(struct device *dev)
1620 {
1621 	struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
1622 
1623 	clk_disable_unprepare(cx2072x->mclk);
1624 	return 0;
1625 }
1626 
cx2072x_runtime_resume(struct device * dev)1627 static int __maybe_unused cx2072x_runtime_resume(struct device *dev)
1628 {
1629 	struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
1630 
1631 	return clk_prepare_enable(cx2072x->mclk);
1632 }
1633 
cx2072x_i2c_probe(struct i2c_client * i2c)1634 static int cx2072x_i2c_probe(struct i2c_client *i2c)
1635 {
1636 	struct cx2072x_priv *cx2072x;
1637 	unsigned int ven_id, rev_id;
1638 	int ret;
1639 
1640 	cx2072x = devm_kzalloc(&i2c->dev, sizeof(struct cx2072x_priv),
1641 			       GFP_KERNEL);
1642 	if (!cx2072x)
1643 		return -ENOMEM;
1644 
1645 	cx2072x->regmap = devm_regmap_init(&i2c->dev, NULL, i2c,
1646 					   &cx2072x_regmap);
1647 	if (IS_ERR(cx2072x->regmap))
1648 		return PTR_ERR(cx2072x->regmap);
1649 
1650 	mutex_init(&cx2072x->lock);
1651 
1652 	i2c_set_clientdata(i2c, cx2072x);
1653 
1654 	cx2072x->dev = &i2c->dev;
1655 	cx2072x->pll_changed = true;
1656 	cx2072x->i2spcm_changed = true;
1657 	cx2072x->bclk_ratio = 0;
1658 
1659 	cx2072x->mclk = devm_clk_get(cx2072x->dev, "mclk");
1660 	if (IS_ERR(cx2072x->mclk)) {
1661 		dev_err(cx2072x->dev, "Failed to get MCLK\n");
1662 		return PTR_ERR(cx2072x->mclk);
1663 	}
1664 
1665 	regmap_read(cx2072x->regmap, CX2072X_VENDOR_ID, &ven_id);
1666 	regmap_read(cx2072x->regmap, CX2072X_REVISION_ID, &rev_id);
1667 
1668 	dev_info(cx2072x->dev, "codec version: %08x,%08x\n", ven_id, rev_id);
1669 
1670 	ret = devm_snd_soc_register_component(cx2072x->dev,
1671 					      &soc_codec_driver_cx2072x,
1672 					      soc_codec_cx2072x_dai,
1673 					      ARRAY_SIZE(soc_codec_cx2072x_dai));
1674 	if (ret < 0)
1675 		return ret;
1676 
1677 	pm_runtime_use_autosuspend(cx2072x->dev);
1678 	pm_runtime_enable(cx2072x->dev);
1679 
1680 	return 0;
1681 }
1682 
cx2072x_i2c_remove(struct i2c_client * i2c)1683 static void cx2072x_i2c_remove(struct i2c_client *i2c)
1684 {
1685 	pm_runtime_disable(&i2c->dev);
1686 }
1687 
1688 static const struct i2c_device_id cx2072x_i2c_id[] = {
1689 	{ "cx20721", 0 },
1690 	{ "cx20723", 0 },
1691 	{}
1692 };
1693 MODULE_DEVICE_TABLE(i2c, cx2072x_i2c_id);
1694 
1695 #ifdef CONFIG_ACPI
1696 static struct acpi_device_id cx2072x_acpi_match[] = {
1697 	{ "14F10720", 0 },
1698 	{},
1699 };
1700 MODULE_DEVICE_TABLE(acpi, cx2072x_acpi_match);
1701 #endif
1702 
1703 static const struct dev_pm_ops cx2072x_runtime_pm = {
1704 	SET_RUNTIME_PM_OPS(cx2072x_runtime_suspend, cx2072x_runtime_resume,
1705 			   NULL)
1706 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1707 				pm_runtime_force_resume)
1708 };
1709 
1710 static struct i2c_driver cx2072x_i2c_driver = {
1711 	.driver = {
1712 		.name = "cx2072x",
1713 		.acpi_match_table = ACPI_PTR(cx2072x_acpi_match),
1714 		.pm = &cx2072x_runtime_pm,
1715 	},
1716 	.probe = cx2072x_i2c_probe,
1717 	.remove = cx2072x_i2c_remove,
1718 	.id_table = cx2072x_i2c_id,
1719 };
1720 
1721 module_i2c_driver(cx2072x_i2c_driver);
1722 
1723 MODULE_DESCRIPTION("ASoC cx2072x Codec Driver");
1724 MODULE_AUTHOR("Simon Ho <simon.ho@conexant.com>");
1725 MODULE_LICENSE("GPL");
1726