1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #define pr_fmt(fmt) "GICv3: " fmt
8
9 #include <linux/acpi.h>
10 #include <linux/cpu.h>
11 #include <linux/cpu_pm.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kstrtox.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/percpu.h>
20 #include <linux/refcount.h>
21 #include <linux/slab.h>
22
23 #include <linux/irqchip.h>
24 #include <linux/irqchip/arm-gic-common.h>
25 #include <linux/irqchip/arm-gic-v3.h>
26 #include <linux/irqchip/irq-partition-percpu.h>
27 #include <linux/bitfield.h>
28 #include <linux/bits.h>
29 #include <linux/arm-smccc.h>
30
31 #include <asm/cputype.h>
32 #include <asm/exception.h>
33 #include <asm/smp_plat.h>
34 #include <asm/virt.h>
35
36 #include "irq-gic-common.h"
37
38 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
39
40 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
41 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
42 #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2)
43 #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3)
44
45 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
46
47 struct redist_region {
48 void __iomem *redist_base;
49 phys_addr_t phys_base;
50 bool single_redist;
51 };
52
53 struct gic_chip_data {
54 struct fwnode_handle *fwnode;
55 phys_addr_t dist_phys_base;
56 void __iomem *dist_base;
57 struct redist_region *redist_regions;
58 struct rdists rdists;
59 struct irq_domain *domain;
60 u64 redist_stride;
61 u32 nr_redist_regions;
62 u64 flags;
63 bool has_rss;
64 unsigned int ppi_nr;
65 struct partition_desc **ppi_descs;
66 };
67
68 #define T241_CHIPS_MAX 4
69 static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly;
70 static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum);
71
72 static DEFINE_STATIC_KEY_FALSE(gic_arm64_2941627_erratum);
73
74 static struct gic_chip_data gic_data __read_mostly;
75 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
76
77 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
78 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
79 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
80
81 /*
82 * The behaviours of RPR and PMR registers differ depending on the value of
83 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
84 * distributor and redistributors depends on whether security is enabled in the
85 * GIC.
86 *
87 * When security is enabled, non-secure priority values from the (re)distributor
88 * are presented to the GIC CPUIF as follow:
89 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
90 *
91 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
92 * EL1 are subject to a similar operation thus matching the priorities presented
93 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
94 * these values are unchanged by the GIC.
95 *
96 * see GICv3/GICv4 Architecture Specification (IHI0069D):
97 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
98 * priorities.
99 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
100 * interrupt.
101 */
102 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
103
104 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
105 EXPORT_SYMBOL(gic_nonsecure_priorities);
106
107 /*
108 * When the Non-secure world has access to group 0 interrupts (as a
109 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
110 * return the Distributor's view of the interrupt priority.
111 *
112 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
113 * written by software is moved to the Non-secure range by the Distributor.
114 *
115 * If both are true (which is when gic_nonsecure_priorities gets enabled),
116 * we need to shift down the priority programmed by software to match it
117 * against the value returned by ICC_RPR_EL1.
118 */
119 #define GICD_INT_RPR_PRI(priority) \
120 ({ \
121 u32 __priority = (priority); \
122 if (static_branch_unlikely(&gic_nonsecure_priorities)) \
123 __priority = 0x80 | (__priority >> 1); \
124 \
125 __priority; \
126 })
127
128 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
129 static refcount_t *ppi_nmi_refs;
130
131 static struct gic_kvm_info gic_v3_kvm_info __initdata;
132 static DEFINE_PER_CPU(bool, has_rss);
133
134 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
135 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
136 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
137 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
138
139 /* Our default, arbitrary priority value. Linux only uses one anyway. */
140 #define DEFAULT_PMR_VALUE 0xf0
141
142 enum gic_intid_range {
143 SGI_RANGE,
144 PPI_RANGE,
145 SPI_RANGE,
146 EPPI_RANGE,
147 ESPI_RANGE,
148 LPI_RANGE,
149 __INVALID_RANGE__
150 };
151
__get_intid_range(irq_hw_number_t hwirq)152 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
153 {
154 switch (hwirq) {
155 case 0 ... 15:
156 return SGI_RANGE;
157 case 16 ... 31:
158 return PPI_RANGE;
159 case 32 ... 1019:
160 return SPI_RANGE;
161 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
162 return EPPI_RANGE;
163 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
164 return ESPI_RANGE;
165 case 8192 ... GENMASK(23, 0):
166 return LPI_RANGE;
167 default:
168 return __INVALID_RANGE__;
169 }
170 }
171
get_intid_range(struct irq_data * d)172 static enum gic_intid_range get_intid_range(struct irq_data *d)
173 {
174 return __get_intid_range(d->hwirq);
175 }
176
gic_irq(struct irq_data * d)177 static inline unsigned int gic_irq(struct irq_data *d)
178 {
179 return d->hwirq;
180 }
181
gic_irq_in_rdist(struct irq_data * d)182 static inline bool gic_irq_in_rdist(struct irq_data *d)
183 {
184 switch (get_intid_range(d)) {
185 case SGI_RANGE:
186 case PPI_RANGE:
187 case EPPI_RANGE:
188 return true;
189 default:
190 return false;
191 }
192 }
193
gic_dist_base_alias(struct irq_data * d)194 static inline void __iomem *gic_dist_base_alias(struct irq_data *d)
195 {
196 if (static_branch_unlikely(&gic_nvidia_t241_erratum)) {
197 irq_hw_number_t hwirq = irqd_to_hwirq(d);
198 u32 chip;
199
200 /*
201 * For the erratum T241-FABRIC-4, read accesses to GICD_In{E}
202 * registers are directed to the chip that owns the SPI. The
203 * the alias region can also be used for writes to the
204 * GICD_In{E} except GICD_ICENABLERn. Each chip has support
205 * for 320 {E}SPIs. Mappings for all 4 chips:
206 * Chip0 = 32-351
207 * Chip1 = 352-671
208 * Chip2 = 672-991
209 * Chip3 = 4096-4415
210 */
211 switch (__get_intid_range(hwirq)) {
212 case SPI_RANGE:
213 chip = (hwirq - 32) / 320;
214 break;
215 case ESPI_RANGE:
216 chip = 3;
217 break;
218 default:
219 unreachable();
220 }
221 return t241_dist_base_alias[chip];
222 }
223
224 return gic_data.dist_base;
225 }
226
gic_dist_base(struct irq_data * d)227 static inline void __iomem *gic_dist_base(struct irq_data *d)
228 {
229 switch (get_intid_range(d)) {
230 case SGI_RANGE:
231 case PPI_RANGE:
232 case EPPI_RANGE:
233 /* SGI+PPI -> SGI_base for this CPU */
234 return gic_data_rdist_sgi_base();
235
236 case SPI_RANGE:
237 case ESPI_RANGE:
238 /* SPI -> dist_base */
239 return gic_data.dist_base;
240
241 default:
242 return NULL;
243 }
244 }
245
gic_do_wait_for_rwp(void __iomem * base,u32 bit)246 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
247 {
248 u32 count = 1000000; /* 1s! */
249
250 while (readl_relaxed(base + GICD_CTLR) & bit) {
251 count--;
252 if (!count) {
253 pr_err_ratelimited("RWP timeout, gone fishing\n");
254 return;
255 }
256 cpu_relax();
257 udelay(1);
258 }
259 }
260
261 /* Wait for completion of a distributor change */
gic_dist_wait_for_rwp(void)262 static void gic_dist_wait_for_rwp(void)
263 {
264 gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
265 }
266
267 /* Wait for completion of a redistributor change */
gic_redist_wait_for_rwp(void)268 static void gic_redist_wait_for_rwp(void)
269 {
270 gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
271 }
272
273 #ifdef CONFIG_ARM64
274
gic_read_iar(void)275 static u64 __maybe_unused gic_read_iar(void)
276 {
277 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
278 return gic_read_iar_cavium_thunderx();
279 else
280 return gic_read_iar_common();
281 }
282 #endif
283
gic_enable_redist(bool enable)284 static void gic_enable_redist(bool enable)
285 {
286 void __iomem *rbase;
287 u32 count = 1000000; /* 1s! */
288 u32 val;
289
290 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
291 return;
292
293 rbase = gic_data_rdist_rd_base();
294
295 val = readl_relaxed(rbase + GICR_WAKER);
296 if (enable)
297 /* Wake up this CPU redistributor */
298 val &= ~GICR_WAKER_ProcessorSleep;
299 else
300 val |= GICR_WAKER_ProcessorSleep;
301 writel_relaxed(val, rbase + GICR_WAKER);
302
303 if (!enable) { /* Check that GICR_WAKER is writeable */
304 val = readl_relaxed(rbase + GICR_WAKER);
305 if (!(val & GICR_WAKER_ProcessorSleep))
306 return; /* No PM support in this redistributor */
307 }
308
309 while (--count) {
310 val = readl_relaxed(rbase + GICR_WAKER);
311 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
312 break;
313 cpu_relax();
314 udelay(1);
315 }
316 if (!count)
317 pr_err_ratelimited("redistributor failed to %s...\n",
318 enable ? "wakeup" : "sleep");
319 }
320
321 /*
322 * Routines to disable, enable, EOI and route interrupts
323 */
convert_offset_index(struct irq_data * d,u32 offset,u32 * index)324 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
325 {
326 switch (get_intid_range(d)) {
327 case SGI_RANGE:
328 case PPI_RANGE:
329 case SPI_RANGE:
330 *index = d->hwirq;
331 return offset;
332 case EPPI_RANGE:
333 /*
334 * Contrary to the ESPI range, the EPPI range is contiguous
335 * to the PPI range in the registers, so let's adjust the
336 * displacement accordingly. Consistency is overrated.
337 */
338 *index = d->hwirq - EPPI_BASE_INTID + 32;
339 return offset;
340 case ESPI_RANGE:
341 *index = d->hwirq - ESPI_BASE_INTID;
342 switch (offset) {
343 case GICD_ISENABLER:
344 return GICD_ISENABLERnE;
345 case GICD_ICENABLER:
346 return GICD_ICENABLERnE;
347 case GICD_ISPENDR:
348 return GICD_ISPENDRnE;
349 case GICD_ICPENDR:
350 return GICD_ICPENDRnE;
351 case GICD_ISACTIVER:
352 return GICD_ISACTIVERnE;
353 case GICD_ICACTIVER:
354 return GICD_ICACTIVERnE;
355 case GICD_IPRIORITYR:
356 return GICD_IPRIORITYRnE;
357 case GICD_ICFGR:
358 return GICD_ICFGRnE;
359 case GICD_IROUTER:
360 return GICD_IROUTERnE;
361 default:
362 break;
363 }
364 break;
365 default:
366 break;
367 }
368
369 WARN_ON(1);
370 *index = d->hwirq;
371 return offset;
372 }
373
gic_peek_irq(struct irq_data * d,u32 offset)374 static int gic_peek_irq(struct irq_data *d, u32 offset)
375 {
376 void __iomem *base;
377 u32 index, mask;
378
379 offset = convert_offset_index(d, offset, &index);
380 mask = 1 << (index % 32);
381
382 if (gic_irq_in_rdist(d))
383 base = gic_data_rdist_sgi_base();
384 else
385 base = gic_dist_base_alias(d);
386
387 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
388 }
389
gic_poke_irq(struct irq_data * d,u32 offset)390 static void gic_poke_irq(struct irq_data *d, u32 offset)
391 {
392 void __iomem *base;
393 u32 index, mask;
394
395 offset = convert_offset_index(d, offset, &index);
396 mask = 1 << (index % 32);
397
398 if (gic_irq_in_rdist(d))
399 base = gic_data_rdist_sgi_base();
400 else
401 base = gic_data.dist_base;
402
403 writel_relaxed(mask, base + offset + (index / 32) * 4);
404 }
405
gic_mask_irq(struct irq_data * d)406 static void gic_mask_irq(struct irq_data *d)
407 {
408 gic_poke_irq(d, GICD_ICENABLER);
409 if (gic_irq_in_rdist(d))
410 gic_redist_wait_for_rwp();
411 else
412 gic_dist_wait_for_rwp();
413 }
414
gic_eoimode1_mask_irq(struct irq_data * d)415 static void gic_eoimode1_mask_irq(struct irq_data *d)
416 {
417 gic_mask_irq(d);
418 /*
419 * When masking a forwarded interrupt, make sure it is
420 * deactivated as well.
421 *
422 * This ensures that an interrupt that is getting
423 * disabled/masked will not get "stuck", because there is
424 * noone to deactivate it (guest is being terminated).
425 */
426 if (irqd_is_forwarded_to_vcpu(d))
427 gic_poke_irq(d, GICD_ICACTIVER);
428 }
429
gic_unmask_irq(struct irq_data * d)430 static void gic_unmask_irq(struct irq_data *d)
431 {
432 gic_poke_irq(d, GICD_ISENABLER);
433 }
434
gic_supports_nmi(void)435 static inline bool gic_supports_nmi(void)
436 {
437 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
438 static_branch_likely(&supports_pseudo_nmis);
439 }
440
gic_irq_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool val)441 static int gic_irq_set_irqchip_state(struct irq_data *d,
442 enum irqchip_irq_state which, bool val)
443 {
444 u32 reg;
445
446 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
447 return -EINVAL;
448
449 switch (which) {
450 case IRQCHIP_STATE_PENDING:
451 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
452 break;
453
454 case IRQCHIP_STATE_ACTIVE:
455 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
456 break;
457
458 case IRQCHIP_STATE_MASKED:
459 if (val) {
460 gic_mask_irq(d);
461 return 0;
462 }
463 reg = GICD_ISENABLER;
464 break;
465
466 default:
467 return -EINVAL;
468 }
469
470 gic_poke_irq(d, reg);
471
472 /*
473 * Force read-back to guarantee that the active state has taken
474 * effect, and won't race with a guest-driven deactivation.
475 */
476 if (reg == GICD_ISACTIVER)
477 gic_peek_irq(d, reg);
478 return 0;
479 }
480
gic_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * val)481 static int gic_irq_get_irqchip_state(struct irq_data *d,
482 enum irqchip_irq_state which, bool *val)
483 {
484 if (d->hwirq >= 8192) /* PPI/SPI only */
485 return -EINVAL;
486
487 switch (which) {
488 case IRQCHIP_STATE_PENDING:
489 *val = gic_peek_irq(d, GICD_ISPENDR);
490 break;
491
492 case IRQCHIP_STATE_ACTIVE:
493 *val = gic_peek_irq(d, GICD_ISACTIVER);
494 break;
495
496 case IRQCHIP_STATE_MASKED:
497 *val = !gic_peek_irq(d, GICD_ISENABLER);
498 break;
499
500 default:
501 return -EINVAL;
502 }
503
504 return 0;
505 }
506
gic_irq_set_prio(struct irq_data * d,u8 prio)507 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
508 {
509 void __iomem *base = gic_dist_base(d);
510 u32 offset, index;
511
512 offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
513
514 writeb_relaxed(prio, base + offset + index);
515 }
516
__gic_get_ppi_index(irq_hw_number_t hwirq)517 static u32 __gic_get_ppi_index(irq_hw_number_t hwirq)
518 {
519 switch (__get_intid_range(hwirq)) {
520 case PPI_RANGE:
521 return hwirq - 16;
522 case EPPI_RANGE:
523 return hwirq - EPPI_BASE_INTID + 16;
524 default:
525 unreachable();
526 }
527 }
528
gic_get_ppi_index(struct irq_data * d)529 static u32 gic_get_ppi_index(struct irq_data *d)
530 {
531 return __gic_get_ppi_index(d->hwirq);
532 }
533
gic_irq_nmi_setup(struct irq_data * d)534 static int gic_irq_nmi_setup(struct irq_data *d)
535 {
536 struct irq_desc *desc = irq_to_desc(d->irq);
537
538 if (!gic_supports_nmi())
539 return -EINVAL;
540
541 if (gic_peek_irq(d, GICD_ISENABLER)) {
542 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
543 return -EINVAL;
544 }
545
546 /*
547 * A secondary irq_chip should be in charge of LPI request,
548 * it should not be possible to get there
549 */
550 if (WARN_ON(gic_irq(d) >= 8192))
551 return -EINVAL;
552
553 /* desc lock should already be held */
554 if (gic_irq_in_rdist(d)) {
555 u32 idx = gic_get_ppi_index(d);
556
557 /* Setting up PPI as NMI, only switch handler for first NMI */
558 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
559 refcount_set(&ppi_nmi_refs[idx], 1);
560 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
561 }
562 } else {
563 desc->handle_irq = handle_fasteoi_nmi;
564 }
565
566 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
567
568 return 0;
569 }
570
gic_irq_nmi_teardown(struct irq_data * d)571 static void gic_irq_nmi_teardown(struct irq_data *d)
572 {
573 struct irq_desc *desc = irq_to_desc(d->irq);
574
575 if (WARN_ON(!gic_supports_nmi()))
576 return;
577
578 if (gic_peek_irq(d, GICD_ISENABLER)) {
579 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
580 return;
581 }
582
583 /*
584 * A secondary irq_chip should be in charge of LPI request,
585 * it should not be possible to get there
586 */
587 if (WARN_ON(gic_irq(d) >= 8192))
588 return;
589
590 /* desc lock should already be held */
591 if (gic_irq_in_rdist(d)) {
592 u32 idx = gic_get_ppi_index(d);
593
594 /* Tearing down NMI, only switch handler for last NMI */
595 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
596 desc->handle_irq = handle_percpu_devid_irq;
597 } else {
598 desc->handle_irq = handle_fasteoi_irq;
599 }
600
601 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
602 }
603
gic_arm64_erratum_2941627_needed(struct irq_data * d)604 static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)
605 {
606 enum gic_intid_range range;
607
608 if (!static_branch_unlikely(&gic_arm64_2941627_erratum))
609 return false;
610
611 range = get_intid_range(d);
612
613 /*
614 * The workaround is needed if the IRQ is an SPI and
615 * the target cpu is different from the one we are
616 * executing on.
617 */
618 return (range == SPI_RANGE || range == ESPI_RANGE) &&
619 !cpumask_test_cpu(raw_smp_processor_id(),
620 irq_data_get_effective_affinity_mask(d));
621 }
622
gic_eoi_irq(struct irq_data * d)623 static void gic_eoi_irq(struct irq_data *d)
624 {
625 write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
626 isb();
627
628 if (gic_arm64_erratum_2941627_needed(d)) {
629 /*
630 * Make sure the GIC stream deactivate packet
631 * issued by ICC_EOIR1_EL1 has completed before
632 * deactivating through GICD_IACTIVER.
633 */
634 dsb(sy);
635 gic_poke_irq(d, GICD_ICACTIVER);
636 }
637 }
638
gic_eoimode1_eoi_irq(struct irq_data * d)639 static void gic_eoimode1_eoi_irq(struct irq_data *d)
640 {
641 /*
642 * No need to deactivate an LPI, or an interrupt that
643 * is is getting forwarded to a vcpu.
644 */
645 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
646 return;
647
648 if (!gic_arm64_erratum_2941627_needed(d))
649 gic_write_dir(gic_irq(d));
650 else
651 gic_poke_irq(d, GICD_ICACTIVER);
652 }
653
gic_set_type(struct irq_data * d,unsigned int type)654 static int gic_set_type(struct irq_data *d, unsigned int type)
655 {
656 enum gic_intid_range range;
657 unsigned int irq = gic_irq(d);
658 void __iomem *base;
659 u32 offset, index;
660 int ret;
661
662 range = get_intid_range(d);
663
664 /* Interrupt configuration for SGIs can't be changed */
665 if (range == SGI_RANGE)
666 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
667
668 /* SPIs have restrictions on the supported types */
669 if ((range == SPI_RANGE || range == ESPI_RANGE) &&
670 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
671 return -EINVAL;
672
673 if (gic_irq_in_rdist(d))
674 base = gic_data_rdist_sgi_base();
675 else
676 base = gic_dist_base_alias(d);
677
678 offset = convert_offset_index(d, GICD_ICFGR, &index);
679
680 ret = gic_configure_irq(index, type, base + offset, NULL);
681 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
682 /* Misconfigured PPIs are usually not fatal */
683 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
684 ret = 0;
685 }
686
687 return ret;
688 }
689
gic_irq_set_vcpu_affinity(struct irq_data * d,void * vcpu)690 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
691 {
692 if (get_intid_range(d) == SGI_RANGE)
693 return -EINVAL;
694
695 if (vcpu)
696 irqd_set_forwarded_to_vcpu(d);
697 else
698 irqd_clr_forwarded_to_vcpu(d);
699 return 0;
700 }
701
gic_cpu_to_affinity(int cpu)702 static u64 gic_cpu_to_affinity(int cpu)
703 {
704 u64 mpidr = cpu_logical_map(cpu);
705 u64 aff;
706
707 /* ASR8601 needs to have its affinities shifted down... */
708 if (unlikely(gic_data.flags & FLAGS_WORKAROUND_ASR_ERRATUM_8601001))
709 mpidr = (MPIDR_AFFINITY_LEVEL(mpidr, 1) |
710 (MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8));
711
712 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
713 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
714 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
715 MPIDR_AFFINITY_LEVEL(mpidr, 0));
716
717 return aff;
718 }
719
gic_deactivate_unhandled(u32 irqnr)720 static void gic_deactivate_unhandled(u32 irqnr)
721 {
722 if (static_branch_likely(&supports_deactivate_key)) {
723 if (irqnr < 8192)
724 gic_write_dir(irqnr);
725 } else {
726 write_gicreg(irqnr, ICC_EOIR1_EL1);
727 isb();
728 }
729 }
730
731 /*
732 * Follow a read of the IAR with any HW maintenance that needs to happen prior
733 * to invoking the relevant IRQ handler. We must do two things:
734 *
735 * (1) Ensure instruction ordering between a read of IAR and subsequent
736 * instructions in the IRQ handler using an ISB.
737 *
738 * It is possible for the IAR to report an IRQ which was signalled *after*
739 * the CPU took an IRQ exception as multiple interrupts can race to be
740 * recognized by the GIC, earlier interrupts could be withdrawn, and/or
741 * later interrupts could be prioritized by the GIC.
742 *
743 * For devices which are tightly coupled to the CPU, such as PMUs, a
744 * context synchronization event is necessary to ensure that system
745 * register state is not stale, as these may have been indirectly written
746 * *after* exception entry.
747 *
748 * (2) Deactivate the interrupt when EOI mode 1 is in use.
749 */
gic_complete_ack(u32 irqnr)750 static inline void gic_complete_ack(u32 irqnr)
751 {
752 if (static_branch_likely(&supports_deactivate_key))
753 write_gicreg(irqnr, ICC_EOIR1_EL1);
754
755 isb();
756 }
757
gic_rpr_is_nmi_prio(void)758 static bool gic_rpr_is_nmi_prio(void)
759 {
760 if (!gic_supports_nmi())
761 return false;
762
763 return unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI));
764 }
765
gic_irqnr_is_special(u32 irqnr)766 static bool gic_irqnr_is_special(u32 irqnr)
767 {
768 return irqnr >= 1020 && irqnr <= 1023;
769 }
770
__gic_handle_irq(u32 irqnr,struct pt_regs * regs)771 static void __gic_handle_irq(u32 irqnr, struct pt_regs *regs)
772 {
773 if (gic_irqnr_is_special(irqnr))
774 return;
775
776 gic_complete_ack(irqnr);
777
778 if (generic_handle_domain_irq(gic_data.domain, irqnr)) {
779 WARN_ONCE(true, "Unexpected interrupt (irqnr %u)\n", irqnr);
780 gic_deactivate_unhandled(irqnr);
781 }
782 }
783
__gic_handle_nmi(u32 irqnr,struct pt_regs * regs)784 static void __gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
785 {
786 if (gic_irqnr_is_special(irqnr))
787 return;
788
789 gic_complete_ack(irqnr);
790
791 if (generic_handle_domain_nmi(gic_data.domain, irqnr)) {
792 WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr);
793 gic_deactivate_unhandled(irqnr);
794 }
795 }
796
797 /*
798 * An exception has been taken from a context with IRQs enabled, and this could
799 * be an IRQ or an NMI.
800 *
801 * The entry code called us with DAIF.IF set to keep NMIs masked. We must clear
802 * DAIF.IF (and update ICC_PMR_EL1 to mask regular IRQs) prior to returning,
803 * after handling any NMI but before handling any IRQ.
804 *
805 * The entry code has performed IRQ entry, and if an NMI is detected we must
806 * perform NMI entry/exit around invoking the handler.
807 */
__gic_handle_irq_from_irqson(struct pt_regs * regs)808 static void __gic_handle_irq_from_irqson(struct pt_regs *regs)
809 {
810 bool is_nmi;
811 u32 irqnr;
812
813 irqnr = gic_read_iar();
814
815 is_nmi = gic_rpr_is_nmi_prio();
816
817 if (is_nmi) {
818 nmi_enter();
819 __gic_handle_nmi(irqnr, regs);
820 nmi_exit();
821 }
822
823 if (gic_prio_masking_enabled()) {
824 gic_pmr_mask_irqs();
825 gic_arch_enable_irqs();
826 }
827
828 if (!is_nmi)
829 __gic_handle_irq(irqnr, regs);
830 }
831
832 /*
833 * An exception has been taken from a context with IRQs disabled, which can only
834 * be an NMI.
835 *
836 * The entry code called us with DAIF.IF set to keep NMIs masked. We must leave
837 * DAIF.IF (and ICC_PMR_EL1) unchanged.
838 *
839 * The entry code has performed NMI entry.
840 */
__gic_handle_irq_from_irqsoff(struct pt_regs * regs)841 static void __gic_handle_irq_from_irqsoff(struct pt_regs *regs)
842 {
843 u64 pmr;
844 u32 irqnr;
845
846 /*
847 * We were in a context with IRQs disabled. However, the
848 * entry code has set PMR to a value that allows any
849 * interrupt to be acknowledged, and not just NMIs. This can
850 * lead to surprising effects if the NMI has been retired in
851 * the meantime, and that there is an IRQ pending. The IRQ
852 * would then be taken in NMI context, something that nobody
853 * wants to debug twice.
854 *
855 * Until we sort this, drop PMR again to a level that will
856 * actually only allow NMIs before reading IAR, and then
857 * restore it to what it was.
858 */
859 pmr = gic_read_pmr();
860 gic_pmr_mask_irqs();
861 isb();
862 irqnr = gic_read_iar();
863 gic_write_pmr(pmr);
864
865 __gic_handle_nmi(irqnr, regs);
866 }
867
gic_handle_irq(struct pt_regs * regs)868 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
869 {
870 if (unlikely(gic_supports_nmi() && !interrupts_enabled(regs)))
871 __gic_handle_irq_from_irqsoff(regs);
872 else
873 __gic_handle_irq_from_irqson(regs);
874 }
875
gic_get_pribits(void)876 static u32 gic_get_pribits(void)
877 {
878 u32 pribits;
879
880 pribits = gic_read_ctlr();
881 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
882 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
883 pribits++;
884
885 return pribits;
886 }
887
gic_has_group0(void)888 static bool gic_has_group0(void)
889 {
890 u32 val;
891 u32 old_pmr;
892
893 old_pmr = gic_read_pmr();
894
895 /*
896 * Let's find out if Group0 is under control of EL3 or not by
897 * setting the highest possible, non-zero priority in PMR.
898 *
899 * If SCR_EL3.FIQ is set, the priority gets shifted down in
900 * order for the CPU interface to set bit 7, and keep the
901 * actual priority in the non-secure range. In the process, it
902 * looses the least significant bit and the actual priority
903 * becomes 0x80. Reading it back returns 0, indicating that
904 * we're don't have access to Group0.
905 */
906 gic_write_pmr(BIT(8 - gic_get_pribits()));
907 val = gic_read_pmr();
908
909 gic_write_pmr(old_pmr);
910
911 return val != 0;
912 }
913
gic_dist_init(void)914 static void __init gic_dist_init(void)
915 {
916 unsigned int i;
917 u64 affinity;
918 void __iomem *base = gic_data.dist_base;
919 u32 val;
920
921 /* Disable the distributor */
922 writel_relaxed(0, base + GICD_CTLR);
923 gic_dist_wait_for_rwp();
924
925 /*
926 * Configure SPIs as non-secure Group-1. This will only matter
927 * if the GIC only has a single security state. This will not
928 * do the right thing if the kernel is running in secure mode,
929 * but that's not the intended use case anyway.
930 */
931 for (i = 32; i < GIC_LINE_NR; i += 32)
932 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
933
934 /* Extended SPI range, not handled by the GICv2/GICv3 common code */
935 for (i = 0; i < GIC_ESPI_NR; i += 32) {
936 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
937 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
938 }
939
940 for (i = 0; i < GIC_ESPI_NR; i += 32)
941 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
942
943 for (i = 0; i < GIC_ESPI_NR; i += 16)
944 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
945
946 for (i = 0; i < GIC_ESPI_NR; i += 4)
947 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
948
949 /* Now do the common stuff */
950 gic_dist_config(base, GIC_LINE_NR, NULL);
951
952 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
953 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
954 pr_info("Enabling SGIs without active state\n");
955 val |= GICD_CTLR_nASSGIreq;
956 }
957
958 /* Enable distributor with ARE, Group1, and wait for it to drain */
959 writel_relaxed(val, base + GICD_CTLR);
960 gic_dist_wait_for_rwp();
961
962 /*
963 * Set all global interrupts to the boot CPU only. ARE must be
964 * enabled.
965 */
966 affinity = gic_cpu_to_affinity(smp_processor_id());
967 for (i = 32; i < GIC_LINE_NR; i++)
968 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
969
970 for (i = 0; i < GIC_ESPI_NR; i++)
971 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
972 }
973
gic_iterate_rdists(int (* fn)(struct redist_region *,void __iomem *))974 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
975 {
976 int ret = -ENODEV;
977 int i;
978
979 for (i = 0; i < gic_data.nr_redist_regions; i++) {
980 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
981 u64 typer;
982 u32 reg;
983
984 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
985 if (reg != GIC_PIDR2_ARCH_GICv3 &&
986 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
987 pr_warn("No redistributor present @%p\n", ptr);
988 break;
989 }
990
991 do {
992 typer = gic_read_typer(ptr + GICR_TYPER);
993 ret = fn(gic_data.redist_regions + i, ptr);
994 if (!ret)
995 return 0;
996
997 if (gic_data.redist_regions[i].single_redist)
998 break;
999
1000 if (gic_data.redist_stride) {
1001 ptr += gic_data.redist_stride;
1002 } else {
1003 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
1004 if (typer & GICR_TYPER_VLPIS)
1005 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
1006 }
1007 } while (!(typer & GICR_TYPER_LAST));
1008 }
1009
1010 return ret ? -ENODEV : 0;
1011 }
1012
__gic_populate_rdist(struct redist_region * region,void __iomem * ptr)1013 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
1014 {
1015 unsigned long mpidr;
1016 u64 typer;
1017 u32 aff;
1018
1019 /*
1020 * Convert affinity to a 32bit value that can be matched to
1021 * GICR_TYPER bits [63:32].
1022 */
1023 mpidr = gic_cpu_to_affinity(smp_processor_id());
1024
1025 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
1026 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
1027 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
1028 MPIDR_AFFINITY_LEVEL(mpidr, 0));
1029
1030 typer = gic_read_typer(ptr + GICR_TYPER);
1031 if ((typer >> 32) == aff) {
1032 u64 offset = ptr - region->redist_base;
1033 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
1034 gic_data_rdist_rd_base() = ptr;
1035 gic_data_rdist()->phys_base = region->phys_base + offset;
1036
1037 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
1038 smp_processor_id(), mpidr,
1039 (int)(region - gic_data.redist_regions),
1040 &gic_data_rdist()->phys_base);
1041 return 0;
1042 }
1043
1044 /* Try next one */
1045 return 1;
1046 }
1047
gic_populate_rdist(void)1048 static int gic_populate_rdist(void)
1049 {
1050 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
1051 return 0;
1052
1053 /* We couldn't even deal with ourselves... */
1054 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
1055 smp_processor_id(),
1056 (unsigned long)cpu_logical_map(smp_processor_id()));
1057 return -ENODEV;
1058 }
1059
__gic_update_rdist_properties(struct redist_region * region,void __iomem * ptr)1060 static int __gic_update_rdist_properties(struct redist_region *region,
1061 void __iomem *ptr)
1062 {
1063 u64 typer = gic_read_typer(ptr + GICR_TYPER);
1064 u32 ctlr = readl_relaxed(ptr + GICR_CTLR);
1065
1066 /* Boot-time cleanup */
1067 if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
1068 u64 val;
1069
1070 /* Deactivate any present vPE */
1071 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
1072 if (val & GICR_VPENDBASER_Valid)
1073 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
1074 ptr + SZ_128K + GICR_VPENDBASER);
1075
1076 /* Mark the VPE table as invalid */
1077 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
1078 val &= ~GICR_VPROPBASER_4_1_VALID;
1079 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
1080 }
1081
1082 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
1083
1084 /*
1085 * TYPER.RVPEID implies some form of DirectLPI, no matter what the
1086 * doc says... :-/ And CTLR.IR implies another subset of DirectLPI
1087 * that the ITS driver can make use of for LPIs (and not VLPIs).
1088 *
1089 * These are 3 different ways to express the same thing, depending
1090 * on the revision of the architecture and its relaxations over
1091 * time. Just group them under the 'direct_lpi' banner.
1092 */
1093 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
1094 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
1095 !!(ctlr & GICR_CTLR_IR) |
1096 gic_data.rdists.has_rvpeid);
1097 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
1098
1099 /* Detect non-sensical configurations */
1100 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
1101 gic_data.rdists.has_direct_lpi = false;
1102 gic_data.rdists.has_vlpis = false;
1103 gic_data.rdists.has_rvpeid = false;
1104 }
1105
1106 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
1107
1108 return 1;
1109 }
1110
gic_update_rdist_properties(void)1111 static void gic_update_rdist_properties(void)
1112 {
1113 gic_data.ppi_nr = UINT_MAX;
1114 gic_iterate_rdists(__gic_update_rdist_properties);
1115 if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
1116 gic_data.ppi_nr = 0;
1117 pr_info("GICv3 features: %d PPIs%s%s\n",
1118 gic_data.ppi_nr,
1119 gic_data.has_rss ? ", RSS" : "",
1120 gic_data.rdists.has_direct_lpi ? ", DirectLPI" : "");
1121
1122 if (gic_data.rdists.has_vlpis)
1123 pr_info("GICv4 features: %s%s%s\n",
1124 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
1125 gic_data.rdists.has_rvpeid ? "RVPEID " : "",
1126 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
1127 }
1128
1129 /* Check whether it's single security state view */
gic_dist_security_disabled(void)1130 static inline bool gic_dist_security_disabled(void)
1131 {
1132 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
1133 }
1134
gic_cpu_sys_reg_init(void)1135 static void gic_cpu_sys_reg_init(void)
1136 {
1137 int i, cpu = smp_processor_id();
1138 u64 mpidr = gic_cpu_to_affinity(cpu);
1139 u64 need_rss = MPIDR_RS(mpidr);
1140 bool group0;
1141 u32 pribits;
1142
1143 /*
1144 * Need to check that the SRE bit has actually been set. If
1145 * not, it means that SRE is disabled at EL2. We're going to
1146 * die painfully, and there is nothing we can do about it.
1147 *
1148 * Kindly inform the luser.
1149 */
1150 if (!gic_enable_sre())
1151 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
1152
1153 pribits = gic_get_pribits();
1154
1155 group0 = gic_has_group0();
1156
1157 /* Set priority mask register */
1158 if (!gic_prio_masking_enabled()) {
1159 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
1160 } else if (gic_supports_nmi()) {
1161 /*
1162 * Mismatch configuration with boot CPU, the system is likely
1163 * to die as interrupt masking will not work properly on all
1164 * CPUs
1165 *
1166 * The boot CPU calls this function before enabling NMI support,
1167 * and as a result we'll never see this warning in the boot path
1168 * for that CPU.
1169 */
1170 if (static_branch_unlikely(&gic_nonsecure_priorities))
1171 WARN_ON(!group0 || gic_dist_security_disabled());
1172 else
1173 WARN_ON(group0 && !gic_dist_security_disabled());
1174 }
1175
1176 /*
1177 * Some firmwares hand over to the kernel with the BPR changed from
1178 * its reset value (and with a value large enough to prevent
1179 * any pre-emptive interrupts from working at all). Writing a zero
1180 * to BPR restores is reset value.
1181 */
1182 gic_write_bpr1(0);
1183
1184 if (static_branch_likely(&supports_deactivate_key)) {
1185 /* EOI drops priority only (mode 1) */
1186 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
1187 } else {
1188 /* EOI deactivates interrupt too (mode 0) */
1189 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
1190 }
1191
1192 /* Always whack Group0 before Group1 */
1193 if (group0) {
1194 switch(pribits) {
1195 case 8:
1196 case 7:
1197 write_gicreg(0, ICC_AP0R3_EL1);
1198 write_gicreg(0, ICC_AP0R2_EL1);
1199 fallthrough;
1200 case 6:
1201 write_gicreg(0, ICC_AP0R1_EL1);
1202 fallthrough;
1203 case 5:
1204 case 4:
1205 write_gicreg(0, ICC_AP0R0_EL1);
1206 }
1207
1208 isb();
1209 }
1210
1211 switch(pribits) {
1212 case 8:
1213 case 7:
1214 write_gicreg(0, ICC_AP1R3_EL1);
1215 write_gicreg(0, ICC_AP1R2_EL1);
1216 fallthrough;
1217 case 6:
1218 write_gicreg(0, ICC_AP1R1_EL1);
1219 fallthrough;
1220 case 5:
1221 case 4:
1222 write_gicreg(0, ICC_AP1R0_EL1);
1223 }
1224
1225 isb();
1226
1227 /* ... and let's hit the road... */
1228 gic_write_grpen1(1);
1229
1230 /* Keep the RSS capability status in per_cpu variable */
1231 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1232
1233 /* Check all the CPUs have capable of sending SGIs to other CPUs */
1234 for_each_online_cpu(i) {
1235 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1236
1237 need_rss |= MPIDR_RS(gic_cpu_to_affinity(i));
1238 if (need_rss && (!have_rss))
1239 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1240 cpu, (unsigned long)mpidr,
1241 i, (unsigned long)gic_cpu_to_affinity(i));
1242 }
1243
1244 /**
1245 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1246 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1247 * UNPREDICTABLE choice of :
1248 * - The write is ignored.
1249 * - The RS field is treated as 0.
1250 */
1251 if (need_rss && (!gic_data.has_rss))
1252 pr_crit_once("RSS is required but GICD doesn't support it\n");
1253 }
1254
1255 static bool gicv3_nolpi;
1256
gicv3_nolpi_cfg(char * buf)1257 static int __init gicv3_nolpi_cfg(char *buf)
1258 {
1259 return kstrtobool(buf, &gicv3_nolpi);
1260 }
1261 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1262
gic_dist_supports_lpis(void)1263 static int gic_dist_supports_lpis(void)
1264 {
1265 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1266 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1267 !gicv3_nolpi);
1268 }
1269
gic_cpu_init(void)1270 static void gic_cpu_init(void)
1271 {
1272 void __iomem *rbase;
1273 int i;
1274
1275 /* Register ourselves with the rest of the world */
1276 if (gic_populate_rdist())
1277 return;
1278
1279 gic_enable_redist(true);
1280
1281 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1282 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1283 "Distributor has extended ranges, but CPU%d doesn't\n",
1284 smp_processor_id());
1285
1286 rbase = gic_data_rdist_sgi_base();
1287
1288 /* Configure SGIs/PPIs as non-secure Group-1 */
1289 for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1290 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1291
1292 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1293
1294 /* initialise system registers */
1295 gic_cpu_sys_reg_init();
1296 }
1297
1298 #ifdef CONFIG_SMP
1299
1300 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1301 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
1302
gic_starting_cpu(unsigned int cpu)1303 static int gic_starting_cpu(unsigned int cpu)
1304 {
1305 gic_cpu_init();
1306
1307 if (gic_dist_supports_lpis())
1308 its_cpu_init();
1309
1310 return 0;
1311 }
1312
gic_compute_target_list(int * base_cpu,const struct cpumask * mask,unsigned long cluster_id)1313 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1314 unsigned long cluster_id)
1315 {
1316 int next_cpu, cpu = *base_cpu;
1317 unsigned long mpidr;
1318 u16 tlist = 0;
1319
1320 mpidr = gic_cpu_to_affinity(cpu);
1321
1322 while (cpu < nr_cpu_ids) {
1323 tlist |= 1 << (mpidr & 0xf);
1324
1325 next_cpu = cpumask_next(cpu, mask);
1326 if (next_cpu >= nr_cpu_ids)
1327 goto out;
1328 cpu = next_cpu;
1329
1330 mpidr = gic_cpu_to_affinity(cpu);
1331
1332 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1333 cpu--;
1334 goto out;
1335 }
1336 }
1337 out:
1338 *base_cpu = cpu;
1339 return tlist;
1340 }
1341
1342 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1343 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1344 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1345
gic_send_sgi(u64 cluster_id,u16 tlist,unsigned int irq)1346 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1347 {
1348 u64 val;
1349
1350 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1351 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
1352 irq << ICC_SGI1R_SGI_ID_SHIFT |
1353 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
1354 MPIDR_TO_SGI_RS(cluster_id) |
1355 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1356
1357 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1358 gic_write_sgi1r(val);
1359 }
1360
gic_ipi_send_mask(struct irq_data * d,const struct cpumask * mask)1361 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1362 {
1363 int cpu;
1364
1365 if (WARN_ON(d->hwirq >= 16))
1366 return;
1367
1368 /*
1369 * Ensure that stores to Normal memory are visible to the
1370 * other CPUs before issuing the IPI.
1371 */
1372 dsb(ishst);
1373
1374 for_each_cpu(cpu, mask) {
1375 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(gic_cpu_to_affinity(cpu));
1376 u16 tlist;
1377
1378 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1379 gic_send_sgi(cluster_id, tlist, d->hwirq);
1380 }
1381
1382 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1383 isb();
1384 }
1385
gic_smp_init(void)1386 static void __init gic_smp_init(void)
1387 {
1388 struct irq_fwspec sgi_fwspec = {
1389 .fwnode = gic_data.fwnode,
1390 .param_count = 1,
1391 };
1392 int base_sgi;
1393
1394 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1395 "irqchip/arm/gicv3:starting",
1396 gic_starting_cpu, NULL);
1397
1398 /* Register all 8 non-secure SGIs */
1399 base_sgi = irq_domain_alloc_irqs(gic_data.domain, 8, NUMA_NO_NODE, &sgi_fwspec);
1400 if (WARN_ON(base_sgi <= 0))
1401 return;
1402
1403 set_smp_ipi_range(base_sgi, 8);
1404 }
1405
gic_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)1406 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1407 bool force)
1408 {
1409 unsigned int cpu;
1410 u32 offset, index;
1411 void __iomem *reg;
1412 int enabled;
1413 u64 val;
1414
1415 if (force)
1416 cpu = cpumask_first(mask_val);
1417 else
1418 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1419
1420 if (cpu >= nr_cpu_ids)
1421 return -EINVAL;
1422
1423 if (gic_irq_in_rdist(d))
1424 return -EINVAL;
1425
1426 /* If interrupt was enabled, disable it first */
1427 enabled = gic_peek_irq(d, GICD_ISENABLER);
1428 if (enabled)
1429 gic_mask_irq(d);
1430
1431 offset = convert_offset_index(d, GICD_IROUTER, &index);
1432 reg = gic_dist_base(d) + offset + (index * 8);
1433 val = gic_cpu_to_affinity(cpu);
1434
1435 gic_write_irouter(val, reg);
1436
1437 /*
1438 * If the interrupt was enabled, enabled it again. Otherwise,
1439 * just wait for the distributor to have digested our changes.
1440 */
1441 if (enabled)
1442 gic_unmask_irq(d);
1443
1444 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1445
1446 return IRQ_SET_MASK_OK_DONE;
1447 }
1448 #else
1449 #define gic_set_affinity NULL
1450 #define gic_ipi_send_mask NULL
1451 #define gic_smp_init() do { } while(0)
1452 #endif
1453
gic_retrigger(struct irq_data * data)1454 static int gic_retrigger(struct irq_data *data)
1455 {
1456 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
1457 }
1458
1459 #ifdef CONFIG_CPU_PM
gic_cpu_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)1460 static int gic_cpu_pm_notifier(struct notifier_block *self,
1461 unsigned long cmd, void *v)
1462 {
1463 if (cmd == CPU_PM_EXIT) {
1464 if (gic_dist_security_disabled())
1465 gic_enable_redist(true);
1466 gic_cpu_sys_reg_init();
1467 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1468 gic_write_grpen1(0);
1469 gic_enable_redist(false);
1470 }
1471 return NOTIFY_OK;
1472 }
1473
1474 static struct notifier_block gic_cpu_pm_notifier_block = {
1475 .notifier_call = gic_cpu_pm_notifier,
1476 };
1477
gic_cpu_pm_init(void)1478 static void gic_cpu_pm_init(void)
1479 {
1480 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1481 }
1482
1483 #else
gic_cpu_pm_init(void)1484 static inline void gic_cpu_pm_init(void) { }
1485 #endif /* CONFIG_CPU_PM */
1486
1487 static struct irq_chip gic_chip = {
1488 .name = "GICv3",
1489 .irq_mask = gic_mask_irq,
1490 .irq_unmask = gic_unmask_irq,
1491 .irq_eoi = gic_eoi_irq,
1492 .irq_set_type = gic_set_type,
1493 .irq_set_affinity = gic_set_affinity,
1494 .irq_retrigger = gic_retrigger,
1495 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1496 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1497 .irq_nmi_setup = gic_irq_nmi_setup,
1498 .irq_nmi_teardown = gic_irq_nmi_teardown,
1499 .ipi_send_mask = gic_ipi_send_mask,
1500 .flags = IRQCHIP_SET_TYPE_MASKED |
1501 IRQCHIP_SKIP_SET_WAKE |
1502 IRQCHIP_MASK_ON_SUSPEND,
1503 };
1504
1505 static struct irq_chip gic_eoimode1_chip = {
1506 .name = "GICv3",
1507 .irq_mask = gic_eoimode1_mask_irq,
1508 .irq_unmask = gic_unmask_irq,
1509 .irq_eoi = gic_eoimode1_eoi_irq,
1510 .irq_set_type = gic_set_type,
1511 .irq_set_affinity = gic_set_affinity,
1512 .irq_retrigger = gic_retrigger,
1513 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1514 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1515 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
1516 .irq_nmi_setup = gic_irq_nmi_setup,
1517 .irq_nmi_teardown = gic_irq_nmi_teardown,
1518 .ipi_send_mask = gic_ipi_send_mask,
1519 .flags = IRQCHIP_SET_TYPE_MASKED |
1520 IRQCHIP_SKIP_SET_WAKE |
1521 IRQCHIP_MASK_ON_SUSPEND,
1522 };
1523
gic_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)1524 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1525 irq_hw_number_t hw)
1526 {
1527 struct irq_chip *chip = &gic_chip;
1528 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1529
1530 if (static_branch_likely(&supports_deactivate_key))
1531 chip = &gic_eoimode1_chip;
1532
1533 switch (__get_intid_range(hw)) {
1534 case SGI_RANGE:
1535 case PPI_RANGE:
1536 case EPPI_RANGE:
1537 irq_set_percpu_devid(irq);
1538 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1539 handle_percpu_devid_irq, NULL, NULL);
1540 break;
1541
1542 case SPI_RANGE:
1543 case ESPI_RANGE:
1544 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1545 handle_fasteoi_irq, NULL, NULL);
1546 irq_set_probe(irq);
1547 irqd_set_single_target(irqd);
1548 break;
1549
1550 case LPI_RANGE:
1551 if (!gic_dist_supports_lpis())
1552 return -EPERM;
1553 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1554 handle_fasteoi_irq, NULL, NULL);
1555 break;
1556
1557 default:
1558 return -EPERM;
1559 }
1560
1561 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1562 irqd_set_handle_enforce_irqctx(irqd);
1563 return 0;
1564 }
1565
gic_irq_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1566 static int gic_irq_domain_translate(struct irq_domain *d,
1567 struct irq_fwspec *fwspec,
1568 unsigned long *hwirq,
1569 unsigned int *type)
1570 {
1571 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1572 *hwirq = fwspec->param[0];
1573 *type = IRQ_TYPE_EDGE_RISING;
1574 return 0;
1575 }
1576
1577 if (is_of_node(fwspec->fwnode)) {
1578 if (fwspec->param_count < 3)
1579 return -EINVAL;
1580
1581 switch (fwspec->param[0]) {
1582 case 0: /* SPI */
1583 *hwirq = fwspec->param[1] + 32;
1584 break;
1585 case 1: /* PPI */
1586 *hwirq = fwspec->param[1] + 16;
1587 break;
1588 case 2: /* ESPI */
1589 *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1590 break;
1591 case 3: /* EPPI */
1592 *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1593 break;
1594 case GIC_IRQ_TYPE_LPI: /* LPI */
1595 *hwirq = fwspec->param[1];
1596 break;
1597 case GIC_IRQ_TYPE_PARTITION:
1598 *hwirq = fwspec->param[1];
1599 if (fwspec->param[1] >= 16)
1600 *hwirq += EPPI_BASE_INTID - 16;
1601 else
1602 *hwirq += 16;
1603 break;
1604 default:
1605 return -EINVAL;
1606 }
1607
1608 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1609
1610 /*
1611 * Make it clear that broken DTs are... broken.
1612 * Partitioned PPIs are an unfortunate exception.
1613 */
1614 WARN_ON(*type == IRQ_TYPE_NONE &&
1615 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1616 return 0;
1617 }
1618
1619 if (is_fwnode_irqchip(fwspec->fwnode)) {
1620 if(fwspec->param_count != 2)
1621 return -EINVAL;
1622
1623 if (fwspec->param[0] < 16) {
1624 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1625 fwspec->param[0]);
1626 return -EINVAL;
1627 }
1628
1629 *hwirq = fwspec->param[0];
1630 *type = fwspec->param[1];
1631
1632 WARN_ON(*type == IRQ_TYPE_NONE);
1633 return 0;
1634 }
1635
1636 return -EINVAL;
1637 }
1638
gic_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)1639 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1640 unsigned int nr_irqs, void *arg)
1641 {
1642 int i, ret;
1643 irq_hw_number_t hwirq;
1644 unsigned int type = IRQ_TYPE_NONE;
1645 struct irq_fwspec *fwspec = arg;
1646
1647 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1648 if (ret)
1649 return ret;
1650
1651 for (i = 0; i < nr_irqs; i++) {
1652 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1653 if (ret)
1654 return ret;
1655 }
1656
1657 return 0;
1658 }
1659
gic_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)1660 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1661 unsigned int nr_irqs)
1662 {
1663 int i;
1664
1665 for (i = 0; i < nr_irqs; i++) {
1666 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1667 irq_set_handler(virq + i, NULL);
1668 irq_domain_reset_irq_data(d);
1669 }
1670 }
1671
fwspec_is_partitioned_ppi(struct irq_fwspec * fwspec,irq_hw_number_t hwirq)1672 static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec,
1673 irq_hw_number_t hwirq)
1674 {
1675 enum gic_intid_range range;
1676
1677 if (!gic_data.ppi_descs)
1678 return false;
1679
1680 if (!is_of_node(fwspec->fwnode))
1681 return false;
1682
1683 if (fwspec->param_count < 4 || !fwspec->param[3])
1684 return false;
1685
1686 range = __get_intid_range(hwirq);
1687 if (range != PPI_RANGE && range != EPPI_RANGE)
1688 return false;
1689
1690 return true;
1691 }
1692
gic_irq_domain_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)1693 static int gic_irq_domain_select(struct irq_domain *d,
1694 struct irq_fwspec *fwspec,
1695 enum irq_domain_bus_token bus_token)
1696 {
1697 unsigned int type, ret, ppi_idx;
1698 irq_hw_number_t hwirq;
1699
1700 /* Not for us */
1701 if (fwspec->fwnode != d->fwnode)
1702 return 0;
1703
1704 /* If this is not DT, then we have a single domain */
1705 if (!is_of_node(fwspec->fwnode))
1706 return 1;
1707
1708 ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type);
1709 if (WARN_ON_ONCE(ret))
1710 return 0;
1711
1712 if (!fwspec_is_partitioned_ppi(fwspec, hwirq))
1713 return d == gic_data.domain;
1714
1715 /*
1716 * If this is a PPI and we have a 4th (non-null) parameter,
1717 * then we need to match the partition domain.
1718 */
1719 ppi_idx = __gic_get_ppi_index(hwirq);
1720 return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]);
1721 }
1722
1723 static const struct irq_domain_ops gic_irq_domain_ops = {
1724 .translate = gic_irq_domain_translate,
1725 .alloc = gic_irq_domain_alloc,
1726 .free = gic_irq_domain_free,
1727 .select = gic_irq_domain_select,
1728 };
1729
partition_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1730 static int partition_domain_translate(struct irq_domain *d,
1731 struct irq_fwspec *fwspec,
1732 unsigned long *hwirq,
1733 unsigned int *type)
1734 {
1735 unsigned long ppi_intid;
1736 struct device_node *np;
1737 unsigned int ppi_idx;
1738 int ret;
1739
1740 if (!gic_data.ppi_descs)
1741 return -ENOMEM;
1742
1743 np = of_find_node_by_phandle(fwspec->param[3]);
1744 if (WARN_ON(!np))
1745 return -EINVAL;
1746
1747 ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type);
1748 if (WARN_ON_ONCE(ret))
1749 return 0;
1750
1751 ppi_idx = __gic_get_ppi_index(ppi_intid);
1752 ret = partition_translate_id(gic_data.ppi_descs[ppi_idx],
1753 of_node_to_fwnode(np));
1754 if (ret < 0)
1755 return ret;
1756
1757 *hwirq = ret;
1758 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1759
1760 return 0;
1761 }
1762
1763 static const struct irq_domain_ops partition_domain_ops = {
1764 .translate = partition_domain_translate,
1765 .select = gic_irq_domain_select,
1766 };
1767
gic_enable_quirk_msm8996(void * data)1768 static bool gic_enable_quirk_msm8996(void *data)
1769 {
1770 struct gic_chip_data *d = data;
1771
1772 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1773
1774 return true;
1775 }
1776
gic_enable_quirk_mtk_gicr(void * data)1777 static bool gic_enable_quirk_mtk_gicr(void *data)
1778 {
1779 struct gic_chip_data *d = data;
1780
1781 d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE;
1782
1783 return true;
1784 }
1785
gic_enable_quirk_cavium_38539(void * data)1786 static bool gic_enable_quirk_cavium_38539(void *data)
1787 {
1788 struct gic_chip_data *d = data;
1789
1790 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1791
1792 return true;
1793 }
1794
gic_enable_quirk_hip06_07(void * data)1795 static bool gic_enable_quirk_hip06_07(void *data)
1796 {
1797 struct gic_chip_data *d = data;
1798
1799 /*
1800 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1801 * not being an actual ARM implementation). The saving grace is
1802 * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1803 * HIP07 doesn't even have a proper IIDR, and still pretends to
1804 * have ESPI. In both cases, put them right.
1805 */
1806 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1807 /* Zero both ESPI and the RES0 field next to it... */
1808 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1809 return true;
1810 }
1811
1812 return false;
1813 }
1814
1815 #define T241_CHIPN_MASK GENMASK_ULL(45, 44)
1816 #define T241_CHIP_GICDA_OFFSET 0x1580000
1817 #define SMCCC_SOC_ID_T241 0x036b0241
1818
gic_enable_quirk_nvidia_t241(void * data)1819 static bool gic_enable_quirk_nvidia_t241(void *data)
1820 {
1821 s32 soc_id = arm_smccc_get_soc_id_version();
1822 unsigned long chip_bmask = 0;
1823 phys_addr_t phys;
1824 u32 i;
1825
1826 /* Check JEP106 code for NVIDIA T241 chip (036b:0241) */
1827 if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241))
1828 return false;
1829
1830 /* Find the chips based on GICR regions PHYS addr */
1831 for (i = 0; i < gic_data.nr_redist_regions; i++) {
1832 chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK,
1833 (u64)gic_data.redist_regions[i].phys_base));
1834 }
1835
1836 if (hweight32(chip_bmask) < 3)
1837 return false;
1838
1839 /* Setup GICD alias regions */
1840 for (i = 0; i < ARRAY_SIZE(t241_dist_base_alias); i++) {
1841 if (chip_bmask & BIT(i)) {
1842 phys = gic_data.dist_phys_base + T241_CHIP_GICDA_OFFSET;
1843 phys |= FIELD_PREP(T241_CHIPN_MASK, i);
1844 t241_dist_base_alias[i] = ioremap(phys, SZ_64K);
1845 WARN_ON_ONCE(!t241_dist_base_alias[i]);
1846 }
1847 }
1848 static_branch_enable(&gic_nvidia_t241_erratum);
1849 return true;
1850 }
1851
gic_enable_quirk_asr8601(void * data)1852 static bool gic_enable_quirk_asr8601(void *data)
1853 {
1854 struct gic_chip_data *d = data;
1855
1856 d->flags |= FLAGS_WORKAROUND_ASR_ERRATUM_8601001;
1857
1858 return true;
1859 }
1860
gic_enable_quirk_arm64_2941627(void * data)1861 static bool gic_enable_quirk_arm64_2941627(void *data)
1862 {
1863 static_branch_enable(&gic_arm64_2941627_erratum);
1864 return true;
1865 }
1866
rd_set_non_coherent(void * data)1867 static bool rd_set_non_coherent(void *data)
1868 {
1869 struct gic_chip_data *d = data;
1870
1871 d->rdists.flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE;
1872 return true;
1873 }
1874
1875 static const struct gic_quirk gic_quirks[] = {
1876 {
1877 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1878 .compatible = "qcom,msm8996-gic-v3",
1879 .init = gic_enable_quirk_msm8996,
1880 },
1881 {
1882 .desc = "GICv3: ASR erratum 8601001",
1883 .compatible = "asr,asr8601-gic-v3",
1884 .init = gic_enable_quirk_asr8601,
1885 },
1886 {
1887 .desc = "GICv3: Mediatek Chromebook GICR save problem",
1888 .property = "mediatek,broken-save-restore-fw",
1889 .init = gic_enable_quirk_mtk_gicr,
1890 },
1891 {
1892 .desc = "GICv3: HIP06 erratum 161010803",
1893 .iidr = 0x0204043b,
1894 .mask = 0xffffffff,
1895 .init = gic_enable_quirk_hip06_07,
1896 },
1897 {
1898 .desc = "GICv3: HIP07 erratum 161010803",
1899 .iidr = 0x00000000,
1900 .mask = 0xffffffff,
1901 .init = gic_enable_quirk_hip06_07,
1902 },
1903 {
1904 /*
1905 * Reserved register accesses generate a Synchronous
1906 * External Abort. This erratum applies to:
1907 * - ThunderX: CN88xx
1908 * - OCTEON TX: CN83xx, CN81xx
1909 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1910 */
1911 .desc = "GICv3: Cavium erratum 38539",
1912 .iidr = 0xa000034c,
1913 .mask = 0xe8f00fff,
1914 .init = gic_enable_quirk_cavium_38539,
1915 },
1916 {
1917 .desc = "GICv3: NVIDIA erratum T241-FABRIC-4",
1918 .iidr = 0x0402043b,
1919 .mask = 0xffffffff,
1920 .init = gic_enable_quirk_nvidia_t241,
1921 },
1922 {
1923 /*
1924 * GIC-700: 2941627 workaround - IP variant [0,1]
1925 *
1926 */
1927 .desc = "GICv3: ARM64 erratum 2941627",
1928 .iidr = 0x0400043b,
1929 .mask = 0xff0e0fff,
1930 .init = gic_enable_quirk_arm64_2941627,
1931 },
1932 {
1933 /*
1934 * GIC-700: 2941627 workaround - IP variant [2]
1935 */
1936 .desc = "GICv3: ARM64 erratum 2941627",
1937 .iidr = 0x0402043b,
1938 .mask = 0xff0f0fff,
1939 .init = gic_enable_quirk_arm64_2941627,
1940 },
1941 {
1942 .desc = "GICv3: non-coherent attribute",
1943 .property = "dma-noncoherent",
1944 .init = rd_set_non_coherent,
1945 },
1946 {
1947 }
1948 };
1949
gic_enable_nmi_support(void)1950 static void gic_enable_nmi_support(void)
1951 {
1952 int i;
1953
1954 if (!gic_prio_masking_enabled())
1955 return;
1956
1957 if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) {
1958 pr_warn("Skipping NMI enable due to firmware issues\n");
1959 return;
1960 }
1961
1962 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1963 if (!ppi_nmi_refs)
1964 return;
1965
1966 for (i = 0; i < gic_data.ppi_nr; i++)
1967 refcount_set(&ppi_nmi_refs[i], 0);
1968
1969 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
1970 gic_has_relaxed_pmr_sync() ? "relaxed" : "forced");
1971
1972 /*
1973 * How priority values are used by the GIC depends on two things:
1974 * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
1975 * and if Group 0 interrupts can be delivered to Linux in the non-secure
1976 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
1977 * ICC_PMR_EL1 register and the priority that software assigns to
1978 * interrupts:
1979 *
1980 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
1981 * -----------------------------------------------------------
1982 * 1 | - | unchanged | unchanged
1983 * -----------------------------------------------------------
1984 * 0 | 1 | non-secure | non-secure
1985 * -----------------------------------------------------------
1986 * 0 | 0 | unchanged | non-secure
1987 *
1988 * where non-secure means that the value is right-shifted by one and the
1989 * MSB bit set, to make it fit in the non-secure priority range.
1990 *
1991 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
1992 * are both either modified or unchanged, we can use the same set of
1993 * priorities.
1994 *
1995 * In the last case, where only the interrupt priorities are modified to
1996 * be in the non-secure range, we use a different PMR value to mask IRQs
1997 * and the rest of the values that we use remain unchanged.
1998 */
1999 if (gic_has_group0() && !gic_dist_security_disabled())
2000 static_branch_enable(&gic_nonsecure_priorities);
2001
2002 static_branch_enable(&supports_pseudo_nmis);
2003
2004 if (static_branch_likely(&supports_deactivate_key))
2005 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
2006 else
2007 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
2008 }
2009
gic_init_bases(phys_addr_t dist_phys_base,void __iomem * dist_base,struct redist_region * rdist_regs,u32 nr_redist_regions,u64 redist_stride,struct fwnode_handle * handle)2010 static int __init gic_init_bases(phys_addr_t dist_phys_base,
2011 void __iomem *dist_base,
2012 struct redist_region *rdist_regs,
2013 u32 nr_redist_regions,
2014 u64 redist_stride,
2015 struct fwnode_handle *handle)
2016 {
2017 u32 typer;
2018 int err;
2019
2020 if (!is_hyp_mode_available())
2021 static_branch_disable(&supports_deactivate_key);
2022
2023 if (static_branch_likely(&supports_deactivate_key))
2024 pr_info("GIC: Using split EOI/Deactivate mode\n");
2025
2026 gic_data.fwnode = handle;
2027 gic_data.dist_phys_base = dist_phys_base;
2028 gic_data.dist_base = dist_base;
2029 gic_data.redist_regions = rdist_regs;
2030 gic_data.nr_redist_regions = nr_redist_regions;
2031 gic_data.redist_stride = redist_stride;
2032
2033 /*
2034 * Find out how many interrupts are supported.
2035 */
2036 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
2037 gic_data.rdists.gicd_typer = typer;
2038
2039 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
2040 gic_quirks, &gic_data);
2041
2042 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
2043 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
2044
2045 /*
2046 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
2047 * architecture spec (which says that reserved registers are RES0).
2048 */
2049 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
2050 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
2051
2052 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
2053 &gic_data);
2054 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
2055 if (!static_branch_unlikely(&gic_nvidia_t241_erratum)) {
2056 /* Disable GICv4.x features for the erratum T241-FABRIC-4 */
2057 gic_data.rdists.has_rvpeid = true;
2058 gic_data.rdists.has_vlpis = true;
2059 gic_data.rdists.has_direct_lpi = true;
2060 gic_data.rdists.has_vpend_valid_dirty = true;
2061 }
2062
2063 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
2064 err = -ENOMEM;
2065 goto out_free;
2066 }
2067
2068 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
2069
2070 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
2071
2072 if (typer & GICD_TYPER_MBIS) {
2073 err = mbi_init(handle, gic_data.domain);
2074 if (err)
2075 pr_err("Failed to initialize MBIs\n");
2076 }
2077
2078 set_handle_irq(gic_handle_irq);
2079
2080 gic_update_rdist_properties();
2081
2082 gic_dist_init();
2083 gic_cpu_init();
2084 gic_smp_init();
2085 gic_cpu_pm_init();
2086
2087 if (gic_dist_supports_lpis()) {
2088 its_init(handle, &gic_data.rdists, gic_data.domain);
2089 its_cpu_init();
2090 its_lpi_memreserve_init();
2091 } else {
2092 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
2093 gicv2m_init(handle, gic_data.domain);
2094 }
2095
2096 gic_enable_nmi_support();
2097
2098 return 0;
2099
2100 out_free:
2101 if (gic_data.domain)
2102 irq_domain_remove(gic_data.domain);
2103 free_percpu(gic_data.rdists.rdist);
2104 return err;
2105 }
2106
gic_validate_dist_version(void __iomem * dist_base)2107 static int __init gic_validate_dist_version(void __iomem *dist_base)
2108 {
2109 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2110
2111 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
2112 return -ENODEV;
2113
2114 return 0;
2115 }
2116
2117 /* Create all possible partitions at boot time */
gic_populate_ppi_partitions(struct device_node * gic_node)2118 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
2119 {
2120 struct device_node *parts_node, *child_part;
2121 int part_idx = 0, i;
2122 int nr_parts;
2123 struct partition_affinity *parts;
2124
2125 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
2126 if (!parts_node)
2127 return;
2128
2129 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
2130 if (!gic_data.ppi_descs)
2131 goto out_put_node;
2132
2133 nr_parts = of_get_child_count(parts_node);
2134
2135 if (!nr_parts)
2136 goto out_put_node;
2137
2138 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
2139 if (WARN_ON(!parts))
2140 goto out_put_node;
2141
2142 for_each_child_of_node(parts_node, child_part) {
2143 struct partition_affinity *part;
2144 int n;
2145
2146 part = &parts[part_idx];
2147
2148 part->partition_id = of_node_to_fwnode(child_part);
2149
2150 pr_info("GIC: PPI partition %pOFn[%d] { ",
2151 child_part, part_idx);
2152
2153 n = of_property_count_elems_of_size(child_part, "affinity",
2154 sizeof(u32));
2155 WARN_ON(n <= 0);
2156
2157 for (i = 0; i < n; i++) {
2158 int err, cpu;
2159 u32 cpu_phandle;
2160 struct device_node *cpu_node;
2161
2162 err = of_property_read_u32_index(child_part, "affinity",
2163 i, &cpu_phandle);
2164 if (WARN_ON(err))
2165 continue;
2166
2167 cpu_node = of_find_node_by_phandle(cpu_phandle);
2168 if (WARN_ON(!cpu_node))
2169 continue;
2170
2171 cpu = of_cpu_node_to_id(cpu_node);
2172 if (WARN_ON(cpu < 0)) {
2173 of_node_put(cpu_node);
2174 continue;
2175 }
2176
2177 pr_cont("%pOF[%d] ", cpu_node, cpu);
2178
2179 cpumask_set_cpu(cpu, &part->mask);
2180 of_node_put(cpu_node);
2181 }
2182
2183 pr_cont("}\n");
2184 part_idx++;
2185 }
2186
2187 for (i = 0; i < gic_data.ppi_nr; i++) {
2188 unsigned int irq;
2189 struct partition_desc *desc;
2190 struct irq_fwspec ppi_fwspec = {
2191 .fwnode = gic_data.fwnode,
2192 .param_count = 3,
2193 .param = {
2194 [0] = GIC_IRQ_TYPE_PARTITION,
2195 [1] = i,
2196 [2] = IRQ_TYPE_NONE,
2197 },
2198 };
2199
2200 irq = irq_create_fwspec_mapping(&ppi_fwspec);
2201 if (WARN_ON(!irq))
2202 continue;
2203 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
2204 irq, &partition_domain_ops);
2205 if (WARN_ON(!desc))
2206 continue;
2207
2208 gic_data.ppi_descs[i] = desc;
2209 }
2210
2211 out_put_node:
2212 of_node_put(parts_node);
2213 }
2214
gic_of_setup_kvm_info(struct device_node * node)2215 static void __init gic_of_setup_kvm_info(struct device_node *node)
2216 {
2217 int ret;
2218 struct resource r;
2219 u32 gicv_idx;
2220
2221 gic_v3_kvm_info.type = GIC_V3;
2222
2223 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
2224 if (!gic_v3_kvm_info.maint_irq)
2225 return;
2226
2227 if (of_property_read_u32(node, "#redistributor-regions",
2228 &gicv_idx))
2229 gicv_idx = 1;
2230
2231 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
2232 ret = of_address_to_resource(node, gicv_idx, &r);
2233 if (!ret)
2234 gic_v3_kvm_info.vcpu = r;
2235
2236 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2237 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2238 vgic_set_kvm_info(&gic_v3_kvm_info);
2239 }
2240
gic_request_region(resource_size_t base,resource_size_t size,const char * name)2241 static void gic_request_region(resource_size_t base, resource_size_t size,
2242 const char *name)
2243 {
2244 if (!request_mem_region(base, size, name))
2245 pr_warn_once(FW_BUG "%s region %pa has overlapping address\n",
2246 name, &base);
2247 }
2248
gic_of_iomap(struct device_node * node,int idx,const char * name,struct resource * res)2249 static void __iomem *gic_of_iomap(struct device_node *node, int idx,
2250 const char *name, struct resource *res)
2251 {
2252 void __iomem *base;
2253 int ret;
2254
2255 ret = of_address_to_resource(node, idx, res);
2256 if (ret)
2257 return IOMEM_ERR_PTR(ret);
2258
2259 gic_request_region(res->start, resource_size(res), name);
2260 base = of_iomap(node, idx);
2261
2262 return base ?: IOMEM_ERR_PTR(-ENOMEM);
2263 }
2264
gic_of_init(struct device_node * node,struct device_node * parent)2265 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
2266 {
2267 phys_addr_t dist_phys_base;
2268 void __iomem *dist_base;
2269 struct redist_region *rdist_regs;
2270 struct resource res;
2271 u64 redist_stride;
2272 u32 nr_redist_regions;
2273 int err, i;
2274
2275 dist_base = gic_of_iomap(node, 0, "GICD", &res);
2276 if (IS_ERR(dist_base)) {
2277 pr_err("%pOF: unable to map gic dist registers\n", node);
2278 return PTR_ERR(dist_base);
2279 }
2280
2281 dist_phys_base = res.start;
2282
2283 err = gic_validate_dist_version(dist_base);
2284 if (err) {
2285 pr_err("%pOF: no distributor detected, giving up\n", node);
2286 goto out_unmap_dist;
2287 }
2288
2289 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
2290 nr_redist_regions = 1;
2291
2292 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
2293 GFP_KERNEL);
2294 if (!rdist_regs) {
2295 err = -ENOMEM;
2296 goto out_unmap_dist;
2297 }
2298
2299 for (i = 0; i < nr_redist_regions; i++) {
2300 rdist_regs[i].redist_base = gic_of_iomap(node, 1 + i, "GICR", &res);
2301 if (IS_ERR(rdist_regs[i].redist_base)) {
2302 pr_err("%pOF: couldn't map region %d\n", node, i);
2303 err = -ENODEV;
2304 goto out_unmap_rdist;
2305 }
2306 rdist_regs[i].phys_base = res.start;
2307 }
2308
2309 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
2310 redist_stride = 0;
2311
2312 gic_enable_of_quirks(node, gic_quirks, &gic_data);
2313
2314 err = gic_init_bases(dist_phys_base, dist_base, rdist_regs,
2315 nr_redist_regions, redist_stride, &node->fwnode);
2316 if (err)
2317 goto out_unmap_rdist;
2318
2319 gic_populate_ppi_partitions(node);
2320
2321 if (static_branch_likely(&supports_deactivate_key))
2322 gic_of_setup_kvm_info(node);
2323 return 0;
2324
2325 out_unmap_rdist:
2326 for (i = 0; i < nr_redist_regions; i++)
2327 if (rdist_regs[i].redist_base && !IS_ERR(rdist_regs[i].redist_base))
2328 iounmap(rdist_regs[i].redist_base);
2329 kfree(rdist_regs);
2330 out_unmap_dist:
2331 iounmap(dist_base);
2332 return err;
2333 }
2334
2335 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2336
2337 #ifdef CONFIG_ACPI
2338 static struct
2339 {
2340 void __iomem *dist_base;
2341 struct redist_region *redist_regs;
2342 u32 nr_redist_regions;
2343 bool single_redist;
2344 int enabled_rdists;
2345 u32 maint_irq;
2346 int maint_irq_mode;
2347 phys_addr_t vcpu_base;
2348 } acpi_data __initdata;
2349
2350 static void __init
gic_acpi_register_redist(phys_addr_t phys_base,void __iomem * redist_base)2351 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
2352 {
2353 static int count = 0;
2354
2355 acpi_data.redist_regs[count].phys_base = phys_base;
2356 acpi_data.redist_regs[count].redist_base = redist_base;
2357 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
2358 count++;
2359 }
2360
2361 static int __init
gic_acpi_parse_madt_redist(union acpi_subtable_headers * header,const unsigned long end)2362 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
2363 const unsigned long end)
2364 {
2365 struct acpi_madt_generic_redistributor *redist =
2366 (struct acpi_madt_generic_redistributor *)header;
2367 void __iomem *redist_base;
2368
2369 redist_base = ioremap(redist->base_address, redist->length);
2370 if (!redist_base) {
2371 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
2372 return -ENOMEM;
2373 }
2374 gic_request_region(redist->base_address, redist->length, "GICR");
2375
2376 gic_acpi_register_redist(redist->base_address, redist_base);
2377 return 0;
2378 }
2379
2380 static int __init
gic_acpi_parse_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2381 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
2382 const unsigned long end)
2383 {
2384 struct acpi_madt_generic_interrupt *gicc =
2385 (struct acpi_madt_generic_interrupt *)header;
2386 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2387 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
2388 void __iomem *redist_base;
2389
2390 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
2391 if (!(gicc->flags & ACPI_MADT_ENABLED))
2392 return 0;
2393
2394 redist_base = ioremap(gicc->gicr_base_address, size);
2395 if (!redist_base)
2396 return -ENOMEM;
2397 gic_request_region(gicc->gicr_base_address, size, "GICR");
2398
2399 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
2400 return 0;
2401 }
2402
gic_acpi_collect_gicr_base(void)2403 static int __init gic_acpi_collect_gicr_base(void)
2404 {
2405 acpi_tbl_entry_handler redist_parser;
2406 enum acpi_madt_type type;
2407
2408 if (acpi_data.single_redist) {
2409 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
2410 redist_parser = gic_acpi_parse_madt_gicc;
2411 } else {
2412 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
2413 redist_parser = gic_acpi_parse_madt_redist;
2414 }
2415
2416 /* Collect redistributor base addresses in GICR entries */
2417 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
2418 return 0;
2419
2420 pr_info("No valid GICR entries exist\n");
2421 return -ENODEV;
2422 }
2423
gic_acpi_match_gicr(union acpi_subtable_headers * header,const unsigned long end)2424 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
2425 const unsigned long end)
2426 {
2427 /* Subtable presence means that redist exists, that's it */
2428 return 0;
2429 }
2430
gic_acpi_match_gicc(union acpi_subtable_headers * header,const unsigned long end)2431 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
2432 const unsigned long end)
2433 {
2434 struct acpi_madt_generic_interrupt *gicc =
2435 (struct acpi_madt_generic_interrupt *)header;
2436
2437 /*
2438 * If GICC is enabled and has valid gicr base address, then it means
2439 * GICR base is presented via GICC
2440 */
2441 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
2442 acpi_data.enabled_rdists++;
2443 return 0;
2444 }
2445
2446 /*
2447 * It's perfectly valid firmware can pass disabled GICC entry, driver
2448 * should not treat as errors, skip the entry instead of probe fail.
2449 */
2450 if (!(gicc->flags & ACPI_MADT_ENABLED))
2451 return 0;
2452
2453 return -ENODEV;
2454 }
2455
gic_acpi_count_gicr_regions(void)2456 static int __init gic_acpi_count_gicr_regions(void)
2457 {
2458 int count;
2459
2460 /*
2461 * Count how many redistributor regions we have. It is not allowed
2462 * to mix redistributor description, GICR and GICC subtables have to be
2463 * mutually exclusive.
2464 */
2465 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2466 gic_acpi_match_gicr, 0);
2467 if (count > 0) {
2468 acpi_data.single_redist = false;
2469 return count;
2470 }
2471
2472 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2473 gic_acpi_match_gicc, 0);
2474 if (count > 0) {
2475 acpi_data.single_redist = true;
2476 count = acpi_data.enabled_rdists;
2477 }
2478
2479 return count;
2480 }
2481
acpi_validate_gic_table(struct acpi_subtable_header * header,struct acpi_probe_entry * ape)2482 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2483 struct acpi_probe_entry *ape)
2484 {
2485 struct acpi_madt_generic_distributor *dist;
2486 int count;
2487
2488 dist = (struct acpi_madt_generic_distributor *)header;
2489 if (dist->version != ape->driver_data)
2490 return false;
2491
2492 /* We need to do that exercise anyway, the sooner the better */
2493 count = gic_acpi_count_gicr_regions();
2494 if (count <= 0)
2495 return false;
2496
2497 acpi_data.nr_redist_regions = count;
2498 return true;
2499 }
2500
gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2501 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2502 const unsigned long end)
2503 {
2504 struct acpi_madt_generic_interrupt *gicc =
2505 (struct acpi_madt_generic_interrupt *)header;
2506 int maint_irq_mode;
2507 static int first_madt = true;
2508
2509 /* Skip unusable CPUs */
2510 if (!(gicc->flags & ACPI_MADT_ENABLED))
2511 return 0;
2512
2513 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2514 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2515
2516 if (first_madt) {
2517 first_madt = false;
2518
2519 acpi_data.maint_irq = gicc->vgic_interrupt;
2520 acpi_data.maint_irq_mode = maint_irq_mode;
2521 acpi_data.vcpu_base = gicc->gicv_base_address;
2522
2523 return 0;
2524 }
2525
2526 /*
2527 * The maintenance interrupt and GICV should be the same for every CPU
2528 */
2529 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2530 (acpi_data.maint_irq_mode != maint_irq_mode) ||
2531 (acpi_data.vcpu_base != gicc->gicv_base_address))
2532 return -EINVAL;
2533
2534 return 0;
2535 }
2536
gic_acpi_collect_virt_info(void)2537 static bool __init gic_acpi_collect_virt_info(void)
2538 {
2539 int count;
2540
2541 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2542 gic_acpi_parse_virt_madt_gicc, 0);
2543
2544 return (count > 0);
2545 }
2546
2547 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2548 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
2549 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
2550
gic_acpi_setup_kvm_info(void)2551 static void __init gic_acpi_setup_kvm_info(void)
2552 {
2553 int irq;
2554
2555 if (!gic_acpi_collect_virt_info()) {
2556 pr_warn("Unable to get hardware information used for virtualization\n");
2557 return;
2558 }
2559
2560 gic_v3_kvm_info.type = GIC_V3;
2561
2562 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2563 acpi_data.maint_irq_mode,
2564 ACPI_ACTIVE_HIGH);
2565 if (irq <= 0)
2566 return;
2567
2568 gic_v3_kvm_info.maint_irq = irq;
2569
2570 if (acpi_data.vcpu_base) {
2571 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2572
2573 vcpu->flags = IORESOURCE_MEM;
2574 vcpu->start = acpi_data.vcpu_base;
2575 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2576 }
2577
2578 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2579 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2580 vgic_set_kvm_info(&gic_v3_kvm_info);
2581 }
2582
2583 static struct fwnode_handle *gsi_domain_handle;
2584
gic_v3_get_gsi_domain_id(u32 gsi)2585 static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
2586 {
2587 return gsi_domain_handle;
2588 }
2589
2590 static int __init
gic_acpi_init(union acpi_subtable_headers * header,const unsigned long end)2591 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
2592 {
2593 struct acpi_madt_generic_distributor *dist;
2594 size_t size;
2595 int i, err;
2596
2597 /* Get distributor base address */
2598 dist = (struct acpi_madt_generic_distributor *)header;
2599 acpi_data.dist_base = ioremap(dist->base_address,
2600 ACPI_GICV3_DIST_MEM_SIZE);
2601 if (!acpi_data.dist_base) {
2602 pr_err("Unable to map GICD registers\n");
2603 return -ENOMEM;
2604 }
2605 gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD");
2606
2607 err = gic_validate_dist_version(acpi_data.dist_base);
2608 if (err) {
2609 pr_err("No distributor detected at @%p, giving up\n",
2610 acpi_data.dist_base);
2611 goto out_dist_unmap;
2612 }
2613
2614 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2615 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2616 if (!acpi_data.redist_regs) {
2617 err = -ENOMEM;
2618 goto out_dist_unmap;
2619 }
2620
2621 err = gic_acpi_collect_gicr_base();
2622 if (err)
2623 goto out_redist_unmap;
2624
2625 gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2626 if (!gsi_domain_handle) {
2627 err = -ENOMEM;
2628 goto out_redist_unmap;
2629 }
2630
2631 err = gic_init_bases(dist->base_address, acpi_data.dist_base,
2632 acpi_data.redist_regs, acpi_data.nr_redist_regions,
2633 0, gsi_domain_handle);
2634 if (err)
2635 goto out_fwhandle_free;
2636
2637 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id);
2638
2639 if (static_branch_likely(&supports_deactivate_key))
2640 gic_acpi_setup_kvm_info();
2641
2642 return 0;
2643
2644 out_fwhandle_free:
2645 irq_domain_free_fwnode(gsi_domain_handle);
2646 out_redist_unmap:
2647 for (i = 0; i < acpi_data.nr_redist_regions; i++)
2648 if (acpi_data.redist_regs[i].redist_base)
2649 iounmap(acpi_data.redist_regs[i].redist_base);
2650 kfree(acpi_data.redist_regs);
2651 out_dist_unmap:
2652 iounmap(acpi_data.dist_base);
2653 return err;
2654 }
2655 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2656 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2657 gic_acpi_init);
2658 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2659 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2660 gic_acpi_init);
2661 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2662 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
2663 gic_acpi_init);
2664 #endif
2665