1 /*
2 * drivers/video/chipsfb.c -- frame buffer device for
3 * Chips & Technologies 65550 chip.
4 *
5 * Copyright (C) 1998-2002 Paul Mackerras
6 *
7 * This file is derived from the Powermac "chips" driver:
8 * Copyright (C) 1997 Fabio Riccardi.
9 * And from the frame buffer device for Open Firmware-initialized devices:
10 * Copyright (C) 1997 Geert Uytterhoeven.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 */
16
17 #include <linux/aperture.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/string.h>
22 #include <linux/mm.h>
23 #include <linux/vmalloc.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/fb.h>
27 #include <linux/pm.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/console.h>
31
32 #ifdef CONFIG_PMAC_BACKLIGHT
33 #include <asm/backlight.h>
34 #endif
35
36 /*
37 * Since we access the display with inb/outb to fixed port numbers,
38 * we can only handle one 6555x chip. -- paulus
39 */
40 #define write_ind(num, val, ap, dp) do { \
41 outb((num), (ap)); outb((val), (dp)); \
42 } while (0)
43 #define read_ind(num, var, ap, dp) do { \
44 outb((num), (ap)); var = inb((dp)); \
45 } while (0)
46
47 /* extension registers */
48 #define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7)
49 #define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7)
50 /* flat panel registers */
51 #define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1)
52 #define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1)
53 /* CRTC registers */
54 #define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5)
55 #define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5)
56 /* graphics registers */
57 #define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf)
58 #define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf)
59 /* sequencer registers */
60 #define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5)
61 #define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5)
62 /* attribute registers - slightly strange */
63 #define write_ar(num, val) do { \
64 inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
65 } while (0)
66 #define read_ar(num, var) do { \
67 inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
68 } while (0)
69
70 /*
71 * Exported functions
72 */
73 int chips_init(void);
74
75 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
76 static int chipsfb_check_var(struct fb_var_screeninfo *var,
77 struct fb_info *info);
78 static int chipsfb_set_par(struct fb_info *info);
79 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
80 u_int transp, struct fb_info *info);
81 static int chipsfb_blank(int blank, struct fb_info *info);
82
83 static const struct fb_ops chipsfb_ops = {
84 .owner = THIS_MODULE,
85 FB_DEFAULT_IOMEM_OPS,
86 .fb_check_var = chipsfb_check_var,
87 .fb_set_par = chipsfb_set_par,
88 .fb_setcolreg = chipsfb_setcolreg,
89 .fb_blank = chipsfb_blank,
90 };
91
chipsfb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)92 static int chipsfb_check_var(struct fb_var_screeninfo *var,
93 struct fb_info *info)
94 {
95 if (var->xres > 800 || var->yres > 600
96 || var->xres_virtual > 800 || var->yres_virtual > 600
97 || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
98 || var->nonstd
99 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
100 return -EINVAL;
101
102 var->xres = var->xres_virtual = 800;
103 var->yres = var->yres_virtual = 600;
104
105 return 0;
106 }
107
chipsfb_set_par(struct fb_info * info)108 static int chipsfb_set_par(struct fb_info *info)
109 {
110 if (info->var.bits_per_pixel == 16) {
111 write_cr(0x13, 200); // Set line length (doublewords)
112 write_xr(0x81, 0x14); // 15 bit (555) color mode
113 write_xr(0x82, 0x00); // Disable palettes
114 write_xr(0x20, 0x10); // 16 bit blitter mode
115
116 info->fix.line_length = 800*2;
117 info->fix.visual = FB_VISUAL_TRUECOLOR;
118
119 info->var.red.offset = 10;
120 info->var.green.offset = 5;
121 info->var.blue.offset = 0;
122 info->var.red.length = info->var.green.length =
123 info->var.blue.length = 5;
124
125 } else {
126 /* p->var.bits_per_pixel == 8 */
127 write_cr(0x13, 100); // Set line length (doublewords)
128 write_xr(0x81, 0x12); // 8 bit color mode
129 write_xr(0x82, 0x08); // Graphics gamma enable
130 write_xr(0x20, 0x00); // 8 bit blitter mode
131
132 info->fix.line_length = 800;
133 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
134
135 info->var.red.offset = info->var.green.offset =
136 info->var.blue.offset = 0;
137 info->var.red.length = info->var.green.length =
138 info->var.blue.length = 8;
139
140 }
141 return 0;
142 }
143
chipsfb_blank(int blank,struct fb_info * info)144 static int chipsfb_blank(int blank, struct fb_info *info)
145 {
146 return 1; /* get fb_blank to set the colormap to all black */
147 }
148
chipsfb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * info)149 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
150 u_int transp, struct fb_info *info)
151 {
152 if (regno > 255)
153 return 1;
154 red >>= 8;
155 green >>= 8;
156 blue >>= 8;
157 outb(regno, 0x3c8);
158 udelay(1);
159 outb(red, 0x3c9);
160 outb(green, 0x3c9);
161 outb(blue, 0x3c9);
162
163 return 0;
164 }
165
166 struct chips_init_reg {
167 unsigned char addr;
168 unsigned char data;
169 };
170
171 static struct chips_init_reg chips_init_sr[] = {
172 { 0x00, 0x03 },
173 { 0x01, 0x01 },
174 { 0x02, 0x0f },
175 { 0x04, 0x0e }
176 };
177
178 static struct chips_init_reg chips_init_gr[] = {
179 { 0x05, 0x00 },
180 { 0x06, 0x0d },
181 { 0x08, 0xff }
182 };
183
184 static struct chips_init_reg chips_init_ar[] = {
185 { 0x10, 0x01 },
186 { 0x12, 0x0f },
187 { 0x13, 0x00 }
188 };
189
190 static struct chips_init_reg chips_init_cr[] = {
191 { 0x00, 0x7f },
192 { 0x01, 0x63 },
193 { 0x02, 0x63 },
194 { 0x03, 0x83 },
195 { 0x04, 0x66 },
196 { 0x05, 0x10 },
197 { 0x06, 0x72 },
198 { 0x07, 0x3e },
199 { 0x08, 0x00 },
200 { 0x09, 0x40 },
201 { 0x0c, 0x00 },
202 { 0x0d, 0x00 },
203 { 0x10, 0x59 },
204 { 0x11, 0x0d },
205 { 0x12, 0x57 },
206 { 0x13, 0x64 },
207 { 0x14, 0x00 },
208 { 0x15, 0x57 },
209 { 0x16, 0x73 },
210 { 0x17, 0xe3 },
211 { 0x18, 0xff },
212 { 0x30, 0x02 },
213 { 0x31, 0x02 },
214 { 0x32, 0x02 },
215 { 0x33, 0x02 },
216 { 0x40, 0x00 },
217 { 0x41, 0x00 },
218 { 0x40, 0x80 }
219 };
220
221 static struct chips_init_reg chips_init_fr[] = {
222 { 0x01, 0x02 },
223 { 0x03, 0x08 },
224 { 0x04, 0x81 },
225 { 0x05, 0x21 },
226 { 0x08, 0x0c },
227 { 0x0a, 0x74 },
228 { 0x0b, 0x11 },
229 { 0x10, 0x0c },
230 { 0x11, 0xe0 },
231 /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
232 { 0x20, 0x63 },
233 { 0x21, 0x68 },
234 { 0x22, 0x19 },
235 { 0x23, 0x7f },
236 { 0x24, 0x68 },
237 { 0x26, 0x00 },
238 { 0x27, 0x0f },
239 { 0x30, 0x57 },
240 { 0x31, 0x58 },
241 { 0x32, 0x0d },
242 { 0x33, 0x72 },
243 { 0x34, 0x02 },
244 { 0x35, 0x22 },
245 { 0x36, 0x02 },
246 { 0x37, 0x00 }
247 };
248
249 static struct chips_init_reg chips_init_xr[] = {
250 { 0xce, 0x00 }, /* set default memory clock */
251 { 0xcc, 0x43 }, /* memory clock ratio */
252 { 0xcd, 0x18 },
253 { 0xce, 0xa1 },
254 { 0xc8, 0x84 },
255 { 0xc9, 0x0a },
256 { 0xca, 0x00 },
257 { 0xcb, 0x20 },
258 { 0xcf, 0x06 },
259 { 0xd0, 0x0e },
260 { 0x09, 0x01 },
261 { 0x0a, 0x02 },
262 { 0x0b, 0x01 },
263 { 0x20, 0x00 },
264 { 0x40, 0x03 },
265 { 0x41, 0x01 },
266 { 0x42, 0x00 },
267 { 0x80, 0x82 },
268 { 0x81, 0x12 },
269 { 0x82, 0x08 },
270 { 0xa0, 0x00 },
271 { 0xa8, 0x00 }
272 };
273
chips_hw_init(void)274 static void chips_hw_init(void)
275 {
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
279 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
280 outb(0x29, 0x3c2); /* set misc output reg */
281 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
282 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
283 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
284 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
285 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
286 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
287 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
288 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
289 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
290 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
291 }
292
293 static const struct fb_fix_screeninfo chipsfb_fix = {
294 .id = "C&T 65550",
295 .type = FB_TYPE_PACKED_PIXELS,
296 .visual = FB_VISUAL_PSEUDOCOLOR,
297 .accel = FB_ACCEL_NONE,
298 .line_length = 800,
299
300 // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
301 // * "3500" PowerBook G3 (the original PB G3) has 2MB.
302 // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
303 // Motherboard actually supports 2MB -- there are two blank locations
304 // for a second pair of DRAMs. (Thanks, Apple!)
305 // * 3400 has 1MB (I think). Don't know if it's expandable.
306 // -- Tim Seufert
307 .smem_len = 0x100000, /* 1MB */
308 };
309
310 static const struct fb_var_screeninfo chipsfb_var = {
311 .xres = 800,
312 .yres = 600,
313 .xres_virtual = 800,
314 .yres_virtual = 600,
315 .bits_per_pixel = 8,
316 .red = { .length = 8 },
317 .green = { .length = 8 },
318 .blue = { .length = 8 },
319 .height = -1,
320 .width = -1,
321 .vmode = FB_VMODE_NONINTERLACED,
322 .pixclock = 10000,
323 .left_margin = 16,
324 .right_margin = 16,
325 .upper_margin = 16,
326 .lower_margin = 16,
327 .hsync_len = 8,
328 .vsync_len = 8,
329 };
330
init_chips(struct fb_info * p,unsigned long addr)331 static void init_chips(struct fb_info *p, unsigned long addr)
332 {
333 fb_memset_io(p->screen_base, 0, 0x100000);
334
335 p->fix = chipsfb_fix;
336 p->fix.smem_start = addr;
337
338 p->var = chipsfb_var;
339
340 p->fbops = &chipsfb_ops;
341
342 fb_alloc_cmap(&p->cmap, 256, 0);
343
344 chips_hw_init();
345 }
346
chipsfb_pci_init(struct pci_dev * dp,const struct pci_device_id * ent)347 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
348 {
349 struct fb_info *p;
350 unsigned long addr;
351 unsigned short cmd;
352 int rc;
353
354 rc = aperture_remove_conflicting_pci_devices(dp, "chipsfb");
355 if (rc)
356 return rc;
357
358 rc = pci_enable_device(dp);
359 if (rc < 0) {
360 dev_err(&dp->dev, "Cannot enable PCI device\n");
361 goto err_out;
362 }
363
364 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) {
365 rc = -ENODEV;
366 goto err_disable;
367 }
368 addr = pci_resource_start(dp, 0);
369 if (addr == 0) {
370 rc = -ENODEV;
371 goto err_disable;
372 }
373
374 p = framebuffer_alloc(0, &dp->dev);
375 if (p == NULL) {
376 rc = -ENOMEM;
377 goto err_disable;
378 }
379
380 if (pci_request_region(dp, 0, "chipsfb") != 0) {
381 dev_err(&dp->dev, "Cannot request framebuffer\n");
382 rc = -EBUSY;
383 goto err_release_fb;
384 }
385
386 #ifdef __BIG_ENDIAN
387 addr += 0x800000; // Use big-endian aperture
388 #endif
389
390 /* we should use pci_enable_device here, but,
391 the device doesn't declare its I/O ports in its BARs
392 so pci_enable_device won't turn on I/O responses */
393 pci_read_config_word(dp, PCI_COMMAND, &cmd);
394 cmd |= 3; /* enable memory and IO space */
395 pci_write_config_word(dp, PCI_COMMAND, cmd);
396
397 #ifdef CONFIG_PMAC_BACKLIGHT
398 /* turn on the backlight */
399 mutex_lock(&pmac_backlight_mutex);
400 if (pmac_backlight) {
401 pmac_backlight->props.power = FB_BLANK_UNBLANK;
402 backlight_update_status(pmac_backlight);
403 }
404 mutex_unlock(&pmac_backlight_mutex);
405 #endif /* CONFIG_PMAC_BACKLIGHT */
406
407 #ifdef CONFIG_PPC
408 p->screen_base = ioremap_wc(addr, 0x200000);
409 #else
410 p->screen_base = ioremap(addr, 0x200000);
411 #endif
412 if (p->screen_base == NULL) {
413 dev_err(&dp->dev, "Cannot map framebuffer\n");
414 rc = -ENOMEM;
415 goto err_release_pci;
416 }
417
418 pci_set_drvdata(dp, p);
419
420 init_chips(p, addr);
421
422 rc = register_framebuffer(p);
423 if (rc < 0) {
424 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
425 goto err_unmap;
426 }
427
428 dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
429 " (%dK RAM detected)\n",
430 p->node, p->fix.smem_len / 1024);
431
432 return 0;
433
434 err_unmap:
435 iounmap(p->screen_base);
436 err_release_pci:
437 pci_release_region(dp, 0);
438 err_release_fb:
439 framebuffer_release(p);
440 err_disable:
441 pci_disable_device(dp);
442 err_out:
443 return rc;
444 }
445
chipsfb_remove(struct pci_dev * dp)446 static void chipsfb_remove(struct pci_dev *dp)
447 {
448 struct fb_info *p = pci_get_drvdata(dp);
449
450 if (p->screen_base == NULL)
451 return;
452 unregister_framebuffer(p);
453 iounmap(p->screen_base);
454 p->screen_base = NULL;
455 pci_release_region(dp, 0);
456 }
457
458 #ifdef CONFIG_PM
chipsfb_pci_suspend(struct pci_dev * pdev,pm_message_t state)459 static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
460 {
461 struct fb_info *p = pci_get_drvdata(pdev);
462
463 if (state.event == pdev->dev.power.power_state.event)
464 return 0;
465 if (!(state.event & PM_EVENT_SLEEP))
466 goto done;
467
468 console_lock();
469 chipsfb_blank(1, p);
470 fb_set_suspend(p, 1);
471 console_unlock();
472 done:
473 pdev->dev.power.power_state = state;
474 return 0;
475 }
476
chipsfb_pci_resume(struct pci_dev * pdev)477 static int chipsfb_pci_resume(struct pci_dev *pdev)
478 {
479 struct fb_info *p = pci_get_drvdata(pdev);
480
481 console_lock();
482 fb_set_suspend(p, 0);
483 chipsfb_blank(0, p);
484 console_unlock();
485
486 pdev->dev.power.power_state = PMSG_ON;
487 return 0;
488 }
489 #endif /* CONFIG_PM */
490
491
492 static struct pci_device_id chipsfb_pci_tbl[] = {
493 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
494 { 0 }
495 };
496
497 MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
498
499 static struct pci_driver chipsfb_driver = {
500 .name = "chipsfb",
501 .id_table = chipsfb_pci_tbl,
502 .probe = chipsfb_pci_init,
503 .remove = chipsfb_remove,
504 #ifdef CONFIG_PM
505 .suspend = chipsfb_pci_suspend,
506 .resume = chipsfb_pci_resume,
507 #endif
508 };
509
chips_init(void)510 int __init chips_init(void)
511 {
512 if (fb_modesetting_disabled("chipsfb"))
513 return -ENODEV;
514
515 if (fb_get_options("chipsfb", NULL))
516 return -ENODEV;
517
518 return pci_register_driver(&chipsfb_driver);
519 }
520
521 module_init(chips_init);
522
chipsfb_exit(void)523 static void __exit chipsfb_exit(void)
524 {
525 pci_unregister_driver(&chipsfb_driver);
526 }
527
528 MODULE_LICENSE("GPL");
529