1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
5 *
6 * Based on:
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
10 *
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 */
13
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/iopoll.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_platform.h>
28 #include <linux/pci.h>
29 #include <linux/phy/phy.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32
33 #include "pcie-rcar.h"
34
35 struct rcar_msi {
36 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
37 struct irq_domain *domain;
38 struct mutex map_lock;
39 spinlock_t mask_lock;
40 int irq1;
41 int irq2;
42 };
43
44 /* Structure representing the PCIe interface */
45 struct rcar_pcie_host {
46 struct rcar_pcie pcie;
47 struct phy *phy;
48 struct clk *bus_clk;
49 struct rcar_msi msi;
50 int (*phy_init_fn)(struct rcar_pcie_host *host);
51 };
52
53 static DEFINE_SPINLOCK(pmsr_lock);
54
rcar_pcie_wakeup(struct device * pcie_dev,void __iomem * pcie_base)55 static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base)
56 {
57 unsigned long flags;
58 u32 pmsr, val;
59 int ret = 0;
60
61 spin_lock_irqsave(&pmsr_lock, flags);
62
63 if (!pcie_base || pm_runtime_suspended(pcie_dev)) {
64 ret = -EINVAL;
65 goto unlock_exit;
66 }
67
68 pmsr = readl(pcie_base + PMSR);
69
70 /*
71 * Test if the PCIe controller received PM_ENTER_L1 DLLP and
72 * the PCIe controller is not in L1 link state. If true, apply
73 * fix, which will put the controller into L1 link state, from
74 * which it can return to L0s/L0 on its own.
75 */
76 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) {
77 writel(L1IATN, pcie_base + PMCTLR);
78 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
79 val & L1FAEG, 10, 1000);
80 if (ret) {
81 dev_warn_ratelimited(pcie_dev,
82 "Timeout waiting for L1 link state, ret=%d\n",
83 ret);
84 }
85 writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
86 }
87
88 unlock_exit:
89 spin_unlock_irqrestore(&pmsr_lock, flags);
90 return ret;
91 }
92
msi_to_host(struct rcar_msi * msi)93 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi)
94 {
95 return container_of(msi, struct rcar_pcie_host, msi);
96 }
97
rcar_read_conf(struct rcar_pcie * pcie,int where)98 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
99 {
100 unsigned int shift = BITS_PER_BYTE * (where & 3);
101 u32 val = rcar_pci_read_reg(pcie, where & ~3);
102
103 return val >> shift;
104 }
105
106 #ifdef CONFIG_ARM
107 #define __rcar_pci_rw_reg_workaround(instr) \
108 " .arch armv7-a\n" \
109 "1: " instr " %1, [%2]\n" \
110 "2: isb\n" \
111 "3: .pushsection .text.fixup,\"ax\"\n" \
112 " .align 2\n" \
113 "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \
114 " b 3b\n" \
115 " .popsection\n" \
116 " .pushsection __ex_table,\"a\"\n" \
117 " .align 3\n" \
118 " .long 1b, 4b\n" \
119 " .long 2b, 4b\n" \
120 " .popsection\n"
121 #endif
122
rcar_pci_write_reg_workaround(struct rcar_pcie * pcie,u32 val,unsigned int reg)123 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val,
124 unsigned int reg)
125 {
126 int error = PCIBIOS_SUCCESSFUL;
127 #ifdef CONFIG_ARM
128 asm volatile(
129 __rcar_pci_rw_reg_workaround("str")
130 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory");
131 #else
132 rcar_pci_write_reg(pcie, val, reg);
133 #endif
134 return error;
135 }
136
rcar_pci_read_reg_workaround(struct rcar_pcie * pcie,u32 * val,unsigned int reg)137 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val,
138 unsigned int reg)
139 {
140 int error = PCIBIOS_SUCCESSFUL;
141 #ifdef CONFIG_ARM
142 asm volatile(
143 __rcar_pci_rw_reg_workaround("ldr")
144 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory");
145
146 if (error != PCIBIOS_SUCCESSFUL)
147 PCI_SET_ERROR_RESPONSE(val);
148 #else
149 *val = rcar_pci_read_reg(pcie, reg);
150 #endif
151 return error;
152 }
153
154 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
rcar_pcie_config_access(struct rcar_pcie_host * host,unsigned char access_type,struct pci_bus * bus,unsigned int devfn,int where,u32 * data)155 static int rcar_pcie_config_access(struct rcar_pcie_host *host,
156 unsigned char access_type, struct pci_bus *bus,
157 unsigned int devfn, int where, u32 *data)
158 {
159 struct rcar_pcie *pcie = &host->pcie;
160 unsigned int dev, func, reg, index;
161 int ret;
162
163 /* Wake the bus up in case it is in L1 state. */
164 ret = rcar_pcie_wakeup(pcie->dev, pcie->base);
165 if (ret) {
166 PCI_SET_ERROR_RESPONSE(data);
167 return PCIBIOS_SET_FAILED;
168 }
169
170 dev = PCI_SLOT(devfn);
171 func = PCI_FUNC(devfn);
172 reg = where & ~3;
173 index = reg / 4;
174
175 /*
176 * While each channel has its own memory-mapped extended config
177 * space, it's generally only accessible when in endpoint mode.
178 * When in root complex mode, the controller is unable to target
179 * itself with either type 0 or type 1 accesses, and indeed, any
180 * controller initiated target transfer to its own config space
181 * result in a completer abort.
182 *
183 * Each channel effectively only supports a single device, but as
184 * the same channel <-> device access works for any PCI_SLOT()
185 * value, we cheat a bit here and bind the controller's config
186 * space to devfn 0 in order to enable self-enumeration. In this
187 * case the regular ECAR/ECDR path is sidelined and the mangled
188 * config access itself is initiated as an internal bus transaction.
189 */
190 if (pci_is_root_bus(bus)) {
191 if (dev != 0)
192 return PCIBIOS_DEVICE_NOT_FOUND;
193
194 if (access_type == RCAR_PCI_ACCESS_READ)
195 *data = rcar_pci_read_reg(pcie, PCICONF(index));
196 else
197 rcar_pci_write_reg(pcie, *data, PCICONF(index));
198
199 return PCIBIOS_SUCCESSFUL;
200 }
201
202 /* Clear errors */
203 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
204
205 /* Set the PIO address */
206 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
207 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
208
209 /* Enable the configuration access */
210 if (pci_is_root_bus(bus->parent))
211 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR);
212 else
213 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR);
214
215 /* Check for errors */
216 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
217 return PCIBIOS_DEVICE_NOT_FOUND;
218
219 /* Check for master and target aborts */
220 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
221 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
222 return PCIBIOS_DEVICE_NOT_FOUND;
223
224 if (access_type == RCAR_PCI_ACCESS_READ)
225 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR);
226 else
227 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR);
228
229 /* Disable the configuration access */
230 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
231
232 return ret;
233 }
234
rcar_pcie_read_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)235 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
236 int where, int size, u32 *val)
237 {
238 struct rcar_pcie_host *host = bus->sysdata;
239 int ret;
240
241 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
242 bus, devfn, where, val);
243 if (ret != PCIBIOS_SUCCESSFUL)
244 return ret;
245
246 if (size == 1)
247 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
248 else if (size == 2)
249 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
250
251 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
252 bus->number, devfn, where, size, *val);
253
254 return ret;
255 }
256
257 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
rcar_pcie_write_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)258 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 val)
260 {
261 struct rcar_pcie_host *host = bus->sysdata;
262 unsigned int shift;
263 u32 data;
264 int ret;
265
266 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
267 bus, devfn, where, &data);
268 if (ret != PCIBIOS_SUCCESSFUL)
269 return ret;
270
271 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
272 bus->number, devfn, where, size, val);
273
274 if (size == 1) {
275 shift = BITS_PER_BYTE * (where & 3);
276 data &= ~(0xff << shift);
277 data |= ((val & 0xff) << shift);
278 } else if (size == 2) {
279 shift = BITS_PER_BYTE * (where & 2);
280 data &= ~(0xffff << shift);
281 data |= ((val & 0xffff) << shift);
282 } else
283 data = val;
284
285 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE,
286 bus, devfn, where, &data);
287
288 return ret;
289 }
290
291 static struct pci_ops rcar_pcie_ops = {
292 .read = rcar_pcie_read_conf,
293 .write = rcar_pcie_write_conf,
294 };
295
rcar_pcie_force_speedup(struct rcar_pcie * pcie)296 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
297 {
298 struct device *dev = pcie->dev;
299 unsigned int timeout = 1000;
300 u32 macsr;
301
302 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
303 return;
304
305 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
306 dev_err(dev, "Speed change already in progress\n");
307 return;
308 }
309
310 macsr = rcar_pci_read_reg(pcie, MACSR);
311 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
312 goto done;
313
314 /* Set target link speed to 5.0 GT/s */
315 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
316 PCI_EXP_LNKSTA_CLS_5_0GB);
317
318 /* Set speed change reason as intentional factor */
319 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
320
321 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
322 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
323 rcar_pci_write_reg(pcie, macsr, MACSR);
324
325 /* Start link speed change */
326 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
327
328 while (timeout--) {
329 macsr = rcar_pci_read_reg(pcie, MACSR);
330 if (macsr & SPCHGFIN) {
331 /* Clear the interrupt bits */
332 rcar_pci_write_reg(pcie, macsr, MACSR);
333
334 if (macsr & SPCHGFAIL)
335 dev_err(dev, "Speed change failed\n");
336
337 goto done;
338 }
339
340 msleep(1);
341 }
342
343 dev_err(dev, "Speed change timed out\n");
344
345 done:
346 dev_info(dev, "Current link speed is %s GT/s\n",
347 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
348 }
349
rcar_pcie_hw_enable(struct rcar_pcie_host * host)350 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host)
351 {
352 struct rcar_pcie *pcie = &host->pcie;
353 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
354 struct resource_entry *win;
355 LIST_HEAD(res);
356 int i = 0;
357
358 /* Try setting 5 GT/s link speed */
359 rcar_pcie_force_speedup(pcie);
360
361 /* Setup PCI resources */
362 resource_list_for_each_entry(win, &bridge->windows) {
363 struct resource *res = win->res;
364
365 if (!res->flags)
366 continue;
367
368 switch (resource_type(res)) {
369 case IORESOURCE_IO:
370 case IORESOURCE_MEM:
371 rcar_pcie_set_outbound(pcie, i, win);
372 i++;
373 break;
374 }
375 }
376 }
377
rcar_pcie_enable(struct rcar_pcie_host * host)378 static int rcar_pcie_enable(struct rcar_pcie_host *host)
379 {
380 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
381
382 rcar_pcie_hw_enable(host);
383
384 pci_add_flags(PCI_REASSIGN_ALL_BUS);
385
386 bridge->sysdata = host;
387 bridge->ops = &rcar_pcie_ops;
388
389 return pci_host_probe(bridge);
390 }
391
phy_wait_for_ack(struct rcar_pcie * pcie)392 static int phy_wait_for_ack(struct rcar_pcie *pcie)
393 {
394 struct device *dev = pcie->dev;
395 unsigned int timeout = 100;
396
397 while (timeout--) {
398 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
399 return 0;
400
401 udelay(100);
402 }
403
404 dev_err(dev, "Access to PCIe phy timed out\n");
405
406 return -ETIMEDOUT;
407 }
408
phy_write_reg(struct rcar_pcie * pcie,unsigned int rate,u32 addr,unsigned int lane,u32 data)409 static void phy_write_reg(struct rcar_pcie *pcie,
410 unsigned int rate, u32 addr,
411 unsigned int lane, u32 data)
412 {
413 u32 phyaddr;
414
415 phyaddr = WRITE_CMD |
416 ((rate & 1) << RATE_POS) |
417 ((lane & 0xf) << LANE_POS) |
418 ((addr & 0xff) << ADR_POS);
419
420 /* Set write data */
421 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
422 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
423
424 /* Ignore errors as they will be dealt with if the data link is down */
425 phy_wait_for_ack(pcie);
426
427 /* Clear command */
428 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
429 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
430
431 /* Ignore errors as they will be dealt with if the data link is down */
432 phy_wait_for_ack(pcie);
433 }
434
rcar_pcie_hw_init(struct rcar_pcie * pcie)435 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
436 {
437 int err;
438
439 /* Begin initialization */
440 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
441
442 /* Set mode */
443 rcar_pci_write_reg(pcie, 1, PCIEMSR);
444
445 err = rcar_pcie_wait_for_phyrdy(pcie);
446 if (err)
447 return err;
448
449 /*
450 * Initial header for port config space is type 1, set the device
451 * class to match. Hardware takes care of propagating the IDSETR
452 * settings, so there is no need to bother with a quirk.
453 */
454 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1);
455
456 /*
457 * Setup Secondary Bus Number & Subordinate Bus Number, even though
458 * they aren't used, to avoid bridge being detected as broken.
459 */
460 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
461 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
462
463 /* Initialize default capabilities. */
464 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
465 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
466 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
467 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
468 PCI_HEADER_TYPE_BRIDGE);
469
470 /* Enable data link layer active state reporting */
471 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
472 PCI_EXP_LNKCAP_DLLLARC);
473
474 /* Write out the physical slot number = 0 */
475 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
476
477 /* Set the completion timer timeout to the maximum 50ms. */
478 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
479
480 /* Terminate list of capabilities (Next Capability Offset=0) */
481 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
482
483 /* Enable MSI */
484 if (IS_ENABLED(CONFIG_PCI_MSI))
485 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
486
487 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
488
489 /* Finish initialization - establish a PCI Express link */
490 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
491
492 /* This will timeout if we don't have a link. */
493 err = rcar_pcie_wait_for_dl(pcie);
494 if (err)
495 return err;
496
497 /* Enable INTx interrupts */
498 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
499
500 wmb();
501
502 return 0;
503 }
504
rcar_pcie_phy_init_h1(struct rcar_pcie_host * host)505 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host)
506 {
507 struct rcar_pcie *pcie = &host->pcie;
508
509 /* Initialize the phy */
510 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
511 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
512 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
513 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
514 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
515 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
516 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
517 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
518 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
519 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
520 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
521 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
522
523 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
524 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
525 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
526
527 return 0;
528 }
529
rcar_pcie_phy_init_gen2(struct rcar_pcie_host * host)530 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host)
531 {
532 struct rcar_pcie *pcie = &host->pcie;
533
534 /*
535 * These settings come from the R-Car Series, 2nd Generation User's
536 * Manual, section 50.3.1 (2) Initialization of the physical layer.
537 */
538 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
539 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
540 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
541 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
542
543 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
544 /* The following value is for DC connection, no termination resistor */
545 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
546 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
547 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
548
549 return 0;
550 }
551
rcar_pcie_phy_init_gen3(struct rcar_pcie_host * host)552 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host)
553 {
554 int err;
555
556 err = phy_init(host->phy);
557 if (err)
558 return err;
559
560 err = phy_power_on(host->phy);
561 if (err)
562 phy_exit(host->phy);
563
564 return err;
565 }
566
rcar_pcie_msi_irq(int irq,void * data)567 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
568 {
569 struct rcar_pcie_host *host = data;
570 struct rcar_pcie *pcie = &host->pcie;
571 struct rcar_msi *msi = &host->msi;
572 struct device *dev = pcie->dev;
573 unsigned long reg;
574
575 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
576
577 /* MSI & INTx share an interrupt - we only handle MSI here */
578 if (!reg)
579 return IRQ_NONE;
580
581 while (reg) {
582 unsigned int index = find_first_bit(®, 32);
583 int ret;
584
585 ret = generic_handle_domain_irq(msi->domain->parent, index);
586 if (ret) {
587 /* Unknown MSI, just clear it */
588 dev_dbg(dev, "unexpected MSI\n");
589 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
590 }
591
592 /* see if there's any more pending in this vector */
593 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
594 }
595
596 return IRQ_HANDLED;
597 }
598
rcar_msi_top_irq_ack(struct irq_data * d)599 static void rcar_msi_top_irq_ack(struct irq_data *d)
600 {
601 irq_chip_ack_parent(d);
602 }
603
rcar_msi_top_irq_mask(struct irq_data * d)604 static void rcar_msi_top_irq_mask(struct irq_data *d)
605 {
606 pci_msi_mask_irq(d);
607 irq_chip_mask_parent(d);
608 }
609
rcar_msi_top_irq_unmask(struct irq_data * d)610 static void rcar_msi_top_irq_unmask(struct irq_data *d)
611 {
612 pci_msi_unmask_irq(d);
613 irq_chip_unmask_parent(d);
614 }
615
616 static struct irq_chip rcar_msi_top_chip = {
617 .name = "PCIe MSI",
618 .irq_ack = rcar_msi_top_irq_ack,
619 .irq_mask = rcar_msi_top_irq_mask,
620 .irq_unmask = rcar_msi_top_irq_unmask,
621 };
622
rcar_msi_irq_ack(struct irq_data * d)623 static void rcar_msi_irq_ack(struct irq_data *d)
624 {
625 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
626 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
627
628 /* clear the interrupt */
629 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR);
630 }
631
rcar_msi_irq_mask(struct irq_data * d)632 static void rcar_msi_irq_mask(struct irq_data *d)
633 {
634 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
635 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
636 unsigned long flags;
637 u32 value;
638
639 spin_lock_irqsave(&msi->mask_lock, flags);
640 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
641 value &= ~BIT(d->hwirq);
642 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
643 spin_unlock_irqrestore(&msi->mask_lock, flags);
644 }
645
rcar_msi_irq_unmask(struct irq_data * d)646 static void rcar_msi_irq_unmask(struct irq_data *d)
647 {
648 struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
649 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
650 unsigned long flags;
651 u32 value;
652
653 spin_lock_irqsave(&msi->mask_lock, flags);
654 value = rcar_pci_read_reg(pcie, PCIEMSIIER);
655 value |= BIT(d->hwirq);
656 rcar_pci_write_reg(pcie, value, PCIEMSIIER);
657 spin_unlock_irqrestore(&msi->mask_lock, flags);
658 }
659
rcar_msi_set_affinity(struct irq_data * d,const struct cpumask * mask,bool force)660 static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
661 {
662 return -EINVAL;
663 }
664
rcar_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)665 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
666 {
667 struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
668 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
669
670 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
671 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
672 msg->data = data->hwirq;
673 }
674
675 static struct irq_chip rcar_msi_bottom_chip = {
676 .name = "R-Car MSI",
677 .irq_ack = rcar_msi_irq_ack,
678 .irq_mask = rcar_msi_irq_mask,
679 .irq_unmask = rcar_msi_irq_unmask,
680 .irq_set_affinity = rcar_msi_set_affinity,
681 .irq_compose_msi_msg = rcar_compose_msi_msg,
682 };
683
rcar_msi_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)684 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
685 unsigned int nr_irqs, void *args)
686 {
687 struct rcar_msi *msi = domain->host_data;
688 unsigned int i;
689 int hwirq;
690
691 mutex_lock(&msi->map_lock);
692
693 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
694
695 mutex_unlock(&msi->map_lock);
696
697 if (hwirq < 0)
698 return -ENOSPC;
699
700 for (i = 0; i < nr_irqs; i++)
701 irq_domain_set_info(domain, virq + i, hwirq + i,
702 &rcar_msi_bottom_chip, domain->host_data,
703 handle_edge_irq, NULL, NULL);
704
705 return 0;
706 }
707
rcar_msi_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)708 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq,
709 unsigned int nr_irqs)
710 {
711 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
712 struct rcar_msi *msi = domain->host_data;
713
714 mutex_lock(&msi->map_lock);
715
716 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
717
718 mutex_unlock(&msi->map_lock);
719 }
720
721 static const struct irq_domain_ops rcar_msi_domain_ops = {
722 .alloc = rcar_msi_domain_alloc,
723 .free = rcar_msi_domain_free,
724 };
725
726 static struct msi_domain_info rcar_msi_info = {
727 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
728 MSI_FLAG_MULTI_PCI_MSI),
729 .chip = &rcar_msi_top_chip,
730 };
731
rcar_allocate_domains(struct rcar_msi * msi)732 static int rcar_allocate_domains(struct rcar_msi *msi)
733 {
734 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
735 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
736 struct irq_domain *parent;
737
738 parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
739 &rcar_msi_domain_ops, msi);
740 if (!parent) {
741 dev_err(pcie->dev, "failed to create IRQ domain\n");
742 return -ENOMEM;
743 }
744 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
745
746 msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent);
747 if (!msi->domain) {
748 dev_err(pcie->dev, "failed to create MSI domain\n");
749 irq_domain_remove(parent);
750 return -ENOMEM;
751 }
752
753 return 0;
754 }
755
rcar_free_domains(struct rcar_msi * msi)756 static void rcar_free_domains(struct rcar_msi *msi)
757 {
758 struct irq_domain *parent = msi->domain->parent;
759
760 irq_domain_remove(msi->domain);
761 irq_domain_remove(parent);
762 }
763
rcar_pcie_enable_msi(struct rcar_pcie_host * host)764 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
765 {
766 struct rcar_pcie *pcie = &host->pcie;
767 struct device *dev = pcie->dev;
768 struct rcar_msi *msi = &host->msi;
769 struct resource res;
770 int err;
771
772 mutex_init(&msi->map_lock);
773 spin_lock_init(&msi->mask_lock);
774
775 err = of_address_to_resource(dev->of_node, 0, &res);
776 if (err)
777 return err;
778
779 err = rcar_allocate_domains(msi);
780 if (err)
781 return err;
782
783 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
784 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
785 IRQF_SHARED | IRQF_NO_THREAD,
786 rcar_msi_bottom_chip.name, host);
787 if (err < 0) {
788 dev_err(dev, "failed to request IRQ: %d\n", err);
789 goto err;
790 }
791
792 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
793 IRQF_SHARED | IRQF_NO_THREAD,
794 rcar_msi_bottom_chip.name, host);
795 if (err < 0) {
796 dev_err(dev, "failed to request IRQ: %d\n", err);
797 goto err;
798 }
799
800 /* disable all MSIs */
801 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
802
803 /*
804 * Setup MSI data target using RC base address address, which
805 * is guaranteed to be in the low 32bit range on any R-Car HW.
806 */
807 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
808 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
809
810 return 0;
811
812 err:
813 rcar_free_domains(msi);
814 return err;
815 }
816
rcar_pcie_teardown_msi(struct rcar_pcie_host * host)817 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host)
818 {
819 struct rcar_pcie *pcie = &host->pcie;
820
821 /* Disable all MSI interrupts */
822 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
823
824 /* Disable address decoding of the MSI interrupt, MSIFE */
825 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
826
827 rcar_free_domains(&host->msi);
828 }
829
rcar_pcie_get_resources(struct rcar_pcie_host * host)830 static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
831 {
832 struct rcar_pcie *pcie = &host->pcie;
833 struct device *dev = pcie->dev;
834 struct resource res;
835 int err, i;
836
837 host->phy = devm_phy_optional_get(dev, "pcie");
838 if (IS_ERR(host->phy))
839 return PTR_ERR(host->phy);
840
841 err = of_address_to_resource(dev->of_node, 0, &res);
842 if (err)
843 return err;
844
845 pcie->base = devm_ioremap_resource(dev, &res);
846 if (IS_ERR(pcie->base))
847 return PTR_ERR(pcie->base);
848
849 host->bus_clk = devm_clk_get(dev, "pcie_bus");
850 if (IS_ERR(host->bus_clk)) {
851 dev_err(dev, "cannot get pcie bus clock\n");
852 return PTR_ERR(host->bus_clk);
853 }
854
855 i = irq_of_parse_and_map(dev->of_node, 0);
856 if (!i) {
857 dev_err(dev, "cannot get platform resources for msi interrupt\n");
858 err = -ENOENT;
859 goto err_irq1;
860 }
861 host->msi.irq1 = i;
862
863 i = irq_of_parse_and_map(dev->of_node, 1);
864 if (!i) {
865 dev_err(dev, "cannot get platform resources for msi interrupt\n");
866 err = -ENOENT;
867 goto err_irq2;
868 }
869 host->msi.irq2 = i;
870
871 return 0;
872
873 err_irq2:
874 irq_dispose_mapping(host->msi.irq1);
875 err_irq1:
876 return err;
877 }
878
rcar_pcie_inbound_ranges(struct rcar_pcie * pcie,struct resource_entry * entry,int * index)879 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
880 struct resource_entry *entry,
881 int *index)
882 {
883 u64 restype = entry->res->flags;
884 u64 cpu_addr = entry->res->start;
885 u64 cpu_end = entry->res->end;
886 u64 pci_addr = entry->res->start - entry->offset;
887 u32 flags = LAM_64BIT | LAR_ENABLE;
888 u64 mask;
889 u64 size = resource_size(entry->res);
890 int idx = *index;
891
892 if (restype & IORESOURCE_PREFETCH)
893 flags |= LAM_PREFETCH;
894
895 while (cpu_addr < cpu_end) {
896 if (idx >= MAX_NR_INBOUND_MAPS - 1) {
897 dev_err(pcie->dev, "Failed to map inbound regions!\n");
898 return -EINVAL;
899 }
900 /*
901 * If the size of the range is larger than the alignment of
902 * the start address, we have to use multiple entries to
903 * perform the mapping.
904 */
905 if (cpu_addr > 0) {
906 unsigned long nr_zeros = __ffs64(cpu_addr);
907 u64 alignment = 1ULL << nr_zeros;
908
909 size = min(size, alignment);
910 }
911 /* Hardware supports max 4GiB inbound region */
912 size = min(size, 1ULL << 32);
913
914 mask = roundup_pow_of_two(size) - 1;
915 mask &= ~0xf;
916
917 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr,
918 lower_32_bits(mask) | flags, idx, true);
919
920 pci_addr += size;
921 cpu_addr += size;
922 idx += 2;
923 }
924 *index = idx;
925
926 return 0;
927 }
928
rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host * host)929 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host)
930 {
931 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
932 struct resource_entry *entry;
933 int index = 0, err = 0;
934
935 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
936 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index);
937 if (err)
938 break;
939 }
940
941 return err;
942 }
943
944 static const struct of_device_id rcar_pcie_of_match[] = {
945 { .compatible = "renesas,pcie-r8a7779",
946 .data = rcar_pcie_phy_init_h1 },
947 { .compatible = "renesas,pcie-r8a7790",
948 .data = rcar_pcie_phy_init_gen2 },
949 { .compatible = "renesas,pcie-r8a7791",
950 .data = rcar_pcie_phy_init_gen2 },
951 { .compatible = "renesas,pcie-rcar-gen2",
952 .data = rcar_pcie_phy_init_gen2 },
953 { .compatible = "renesas,pcie-r8a7795",
954 .data = rcar_pcie_phy_init_gen3 },
955 { .compatible = "renesas,pcie-rcar-gen3",
956 .data = rcar_pcie_phy_init_gen3 },
957 {},
958 };
959
rcar_pcie_probe(struct platform_device * pdev)960 static int rcar_pcie_probe(struct platform_device *pdev)
961 {
962 struct device *dev = &pdev->dev;
963 struct rcar_pcie_host *host;
964 struct rcar_pcie *pcie;
965 u32 data;
966 int err;
967 struct pci_host_bridge *bridge;
968
969 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
970 if (!bridge)
971 return -ENOMEM;
972
973 host = pci_host_bridge_priv(bridge);
974 pcie = &host->pcie;
975 pcie->dev = dev;
976 platform_set_drvdata(pdev, host);
977
978 pm_runtime_enable(pcie->dev);
979 err = pm_runtime_get_sync(pcie->dev);
980 if (err < 0) {
981 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
982 goto err_pm_put;
983 }
984
985 err = rcar_pcie_get_resources(host);
986 if (err < 0) {
987 dev_err(dev, "failed to request resources: %d\n", err);
988 goto err_pm_put;
989 }
990
991 err = clk_prepare_enable(host->bus_clk);
992 if (err) {
993 dev_err(dev, "failed to enable bus clock: %d\n", err);
994 goto err_unmap_msi_irqs;
995 }
996
997 err = rcar_pcie_parse_map_dma_ranges(host);
998 if (err)
999 goto err_clk_disable;
1000
1001 host->phy_init_fn = of_device_get_match_data(dev);
1002 err = host->phy_init_fn(host);
1003 if (err) {
1004 dev_err(dev, "failed to init PCIe PHY\n");
1005 goto err_clk_disable;
1006 }
1007
1008 /* Failure to get a link might just be that no cards are inserted */
1009 if (rcar_pcie_hw_init(pcie)) {
1010 dev_info(dev, "PCIe link down\n");
1011 err = -ENODEV;
1012 goto err_phy_shutdown;
1013 }
1014
1015 data = rcar_pci_read_reg(pcie, MACSR);
1016 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1017
1018 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1019 err = rcar_pcie_enable_msi(host);
1020 if (err < 0) {
1021 dev_err(dev,
1022 "failed to enable MSI support: %d\n",
1023 err);
1024 goto err_phy_shutdown;
1025 }
1026 }
1027
1028 err = rcar_pcie_enable(host);
1029 if (err)
1030 goto err_msi_teardown;
1031
1032 return 0;
1033
1034 err_msi_teardown:
1035 if (IS_ENABLED(CONFIG_PCI_MSI))
1036 rcar_pcie_teardown_msi(host);
1037
1038 err_phy_shutdown:
1039 if (host->phy) {
1040 phy_power_off(host->phy);
1041 phy_exit(host->phy);
1042 }
1043
1044 err_clk_disable:
1045 clk_disable_unprepare(host->bus_clk);
1046
1047 err_unmap_msi_irqs:
1048 irq_dispose_mapping(host->msi.irq2);
1049 irq_dispose_mapping(host->msi.irq1);
1050
1051 err_pm_put:
1052 pm_runtime_put(dev);
1053 pm_runtime_disable(dev);
1054
1055 return err;
1056 }
1057
rcar_pcie_resume(struct device * dev)1058 static int rcar_pcie_resume(struct device *dev)
1059 {
1060 struct rcar_pcie_host *host = dev_get_drvdata(dev);
1061 struct rcar_pcie *pcie = &host->pcie;
1062 unsigned int data;
1063 int err;
1064
1065 err = rcar_pcie_parse_map_dma_ranges(host);
1066 if (err)
1067 return 0;
1068
1069 /* Failure to get a link might just be that no cards are inserted */
1070 err = host->phy_init_fn(host);
1071 if (err) {
1072 dev_info(dev, "PCIe link down\n");
1073 return 0;
1074 }
1075
1076 data = rcar_pci_read_reg(pcie, MACSR);
1077 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1078
1079 /* Enable MSI */
1080 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1081 struct resource res;
1082 u32 val;
1083
1084 of_address_to_resource(dev->of_node, 0, &res);
1085 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
1086 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
1087
1088 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR);
1089 rcar_pci_write_reg(pcie, val, PCIEMSIIER);
1090 }
1091
1092 rcar_pcie_hw_enable(host);
1093
1094 return 0;
1095 }
1096
rcar_pcie_resume_noirq(struct device * dev)1097 static int rcar_pcie_resume_noirq(struct device *dev)
1098 {
1099 struct rcar_pcie_host *host = dev_get_drvdata(dev);
1100 struct rcar_pcie *pcie = &host->pcie;
1101
1102 if (rcar_pci_read_reg(pcie, PMSR) &&
1103 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1104 return 0;
1105
1106 /* Re-establish the PCIe link */
1107 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1108 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1109 return rcar_pcie_wait_for_dl(pcie);
1110 }
1111
1112 static const struct dev_pm_ops rcar_pcie_pm_ops = {
1113 SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume)
1114 .resume_noirq = rcar_pcie_resume_noirq,
1115 };
1116
1117 static struct platform_driver rcar_pcie_driver = {
1118 .driver = {
1119 .name = "rcar-pcie",
1120 .of_match_table = rcar_pcie_of_match,
1121 .pm = &rcar_pcie_pm_ops,
1122 .suppress_bind_attrs = true,
1123 },
1124 .probe = rcar_pcie_probe,
1125 };
1126
1127 #ifdef CONFIG_ARM
rcar_pcie_aarch32_abort_handler(unsigned long addr,unsigned int fsr,struct pt_regs * regs)1128 static int rcar_pcie_aarch32_abort_handler(unsigned long addr,
1129 unsigned int fsr, struct pt_regs *regs)
1130 {
1131 return !fixup_exception(regs);
1132 }
1133
1134 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = {
1135 { .compatible = "renesas,pcie-r8a7779" },
1136 { .compatible = "renesas,pcie-r8a7790" },
1137 { .compatible = "renesas,pcie-r8a7791" },
1138 { .compatible = "renesas,pcie-rcar-gen2" },
1139 {},
1140 };
1141
rcar_pcie_init(void)1142 static int __init rcar_pcie_init(void)
1143 {
1144 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) {
1145 #ifdef CONFIG_ARM_LPAE
1146 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1147 "asynchronous external abort");
1148 #else
1149 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1150 "imprecise external abort");
1151 #endif
1152 }
1153
1154 return platform_driver_register(&rcar_pcie_driver);
1155 }
1156 device_initcall(rcar_pcie_init);
1157 #else
1158 builtin_platform_driver(rcar_pcie_driver);
1159 #endif
1160