1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_VCN_H__
25 #define __AMDGPU_VCN_H__
26 
27 #include "amdgpu_ras.h"
28 
29 #define AMDGPU_VCN_STACK_SIZE		(128*1024)
30 #define AMDGPU_VCN_CONTEXT_SIZE 	(512*1024)
31 
32 #define AMDGPU_VCN_FIRMWARE_OFFSET	256
33 #define AMDGPU_VCN_MAX_ENC_RINGS	3
34 
35 #define AMDGPU_MAX_VCN_INSTANCES	4
36 #define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES
37 
38 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
39 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
40 
41 #define VCN_DEC_KMD_CMD 		0x80000000
42 #define VCN_DEC_CMD_FENCE		0x00000000
43 #define VCN_DEC_CMD_TRAP		0x00000001
44 #define VCN_DEC_CMD_WRITE_REG		0x00000004
45 #define VCN_DEC_CMD_REG_READ_COND_WAIT	0x00000006
46 #define VCN_DEC_CMD_PACKET_START	0x0000000a
47 #define VCN_DEC_CMD_PACKET_END		0x0000000b
48 
49 #define VCN_DEC_SW_CMD_NO_OP		0x00000000
50 #define VCN_DEC_SW_CMD_END		0x00000001
51 #define VCN_DEC_SW_CMD_IB		0x00000002
52 #define VCN_DEC_SW_CMD_FENCE		0x00000003
53 #define VCN_DEC_SW_CMD_TRAP		0x00000004
54 #define VCN_DEC_SW_CMD_IB_AUTO		0x00000005
55 #define VCN_DEC_SW_CMD_SEMAPHORE	0x00000006
56 #define VCN_DEC_SW_CMD_PREEMPT_FENCE	0x00000009
57 #define VCN_DEC_SW_CMD_REG_WRITE	0x0000000b
58 #define VCN_DEC_SW_CMD_REG_WAIT		0x0000000c
59 
60 #define VCN_ENC_CMD_NO_OP		0x00000000
61 #define VCN_ENC_CMD_END 		0x00000001
62 #define VCN_ENC_CMD_IB			0x00000002
63 #define VCN_ENC_CMD_FENCE		0x00000003
64 #define VCN_ENC_CMD_TRAP		0x00000004
65 #define VCN_ENC_CMD_REG_WRITE		0x0000000b
66 #define VCN_ENC_CMD_REG_WAIT		0x0000000c
67 
68 #define VCN_AON_SOC_ADDRESS_2_0 	0x1f800
69 #define VCN1_AON_SOC_ADDRESS_3_0 	0x48000
70 #define VCN_VID_IP_ADDRESS_2_0		0x0
71 #define VCN_AON_IP_ADDRESS_2_0		0x30000
72 
73 #define mmUVD_RBC_XX_IB_REG_CHECK 					0x026b
74 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 				1
75 #define mmUVD_REG_XX_MASK 						0x026c
76 #define mmUVD_REG_XX_MASK_BASE_IDX 					1
77 
78 /* 1 second timeout */
79 #define VCN_IDLE_TIMEOUT	msecs_to_jiffies(1000)
80 
81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) 			\
82 	({	WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); 			\
83 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, 				\
84 			UVD_DPG_LMA_CTL__MASK_EN_MASK | 				\
85 			((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) 	\
86 			<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | 			\
87 			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\
88 		RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); 			\
89 	})
90 
91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) 		\
92 	do { 										\
93 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); 			\
94 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); 			\
95 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, 				\
96 			UVD_DPG_LMA_CTL__READ_WRITE_MASK | 				\
97 			((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) 	\
98 			<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | 			\
99 			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\
100 	} while (0)
101 
102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) 						\
103 	({											\
104 		uint32_t internal_reg_offset, addr;						\
105 		bool video_range, video1_range, aon_range, aon1_range;				\
106 												\
107 		addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);		\
108 		addr <<= 2; 									\
109 		video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && 		\
110 				((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));	\
111 		video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && 		\
112 				((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600)))));	\
113 		aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && 		\
114 				((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));	\
115 		aon1_range   = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && 		\
116 				((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600)))));	\
117 		if (video_range) 								\
118 			internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + 	\
119 				(VCN_VID_IP_ADDRESS_2_0));					\
120 		else if (aon_range)								\
121 			internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + 	\
122 				(VCN_AON_IP_ADDRESS_2_0));					\
123 		else if (video1_range) 								\
124 			internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + 	\
125 				(VCN_VID_IP_ADDRESS_2_0));					\
126 		else if (aon1_range)								\
127 			internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + 	\
128 				(VCN_AON_IP_ADDRESS_2_0));					\
129 		else										\
130 			internal_reg_offset = (0xFFFFF & addr);					\
131 												\
132 		internal_reg_offset >>= 2;							\
133 	})
134 
135 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) 					\
136 	({											\
137 		WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, 					\
138 			(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |				\
139 			mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |				\
140 			offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));			\
141 		RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA);				\
142 	})
143 
144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect)             \
145 	do {                                                                          \
146 		if (!indirect) {                                                      \
147 			WREG32_SOC15(VCN, GET_INST(VCN, inst_idx),                    \
148 				     mmUVD_DPG_LMA_DATA, value);                      \
149 			WREG32_SOC15(                                                 \
150 				VCN, GET_INST(VCN, inst_idx),                         \
151 				mmUVD_DPG_LMA_CTL,                                    \
152 				(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |          \
153 				 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |         \
154 				 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
155 		} else {                                                              \
156 			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =              \
157 				offset;                                               \
158 			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =              \
159 				value;                                                \
160 		}                                                                     \
161 	} while (0)
162 
163 #define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2)
164 #define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4)
165 #define AMDGPU_VCN_FW_SHARED_FLAG_0_RB	(1 << 6)
166 #define AMDGPU_VCN_MULTI_QUEUE_FLAG	(1 << 8)
167 #define AMDGPU_VCN_SW_RING_FLAG		(1 << 9)
168 #define AMDGPU_VCN_FW_LOGGING_FLAG	(1 << 10)
169 #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
170 #define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
171 #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
172 
173 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001
174 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001
175 
176 #define VCN_CODEC_DISABLE_MASK_AV1  (1 << 0)
177 #define VCN_CODEC_DISABLE_MASK_VP9  (1 << 1)
178 #define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2)
179 #define VCN_CODEC_DISABLE_MASK_H264 (1 << 3)
180 
181 #define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0)
182 #define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1)
183 
184 #define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2
185 
186 enum fw_queue_mode {
187 	FW_QUEUE_RING_RESET = 1,
188 	FW_QUEUE_DPG_HOLD_OFF = 2,
189 };
190 
191 enum engine_status_constants {
192 	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
193 	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
194 	UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
195 	UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
196 	UVD_STATUS__UVD_BUSY = 0x00000004,
197 	GB_ADDR_CONFIG_DEFAULT = 0x26010011,
198 	UVD_STATUS__IDLE = 0x2,
199 	UVD_STATUS__BUSY = 0x5,
200 	UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
201 	UVD_STATUS__RBC_BUSY = 0x1,
202 	UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
203 };
204 
205 enum internal_dpg_state {
206 	VCN_DPG_STATE__UNPAUSE = 0,
207 	VCN_DPG_STATE__PAUSE,
208 };
209 
210 struct dpg_pause_state {
211 	enum internal_dpg_state fw_based;
212 	enum internal_dpg_state jpeg;
213 };
214 
215 struct amdgpu_vcn_reg{
216 	unsigned	data0;
217 	unsigned	data1;
218 	unsigned	cmd;
219 	unsigned	nop;
220 	unsigned	context_id;
221 	unsigned	ib_vmid;
222 	unsigned	ib_bar_low;
223 	unsigned	ib_bar_high;
224 	unsigned	ib_size;
225 	unsigned	gp_scratch8;
226 	unsigned	scratch9;
227 };
228 
229 struct amdgpu_vcn_fw_shared {
230 	void        *cpu_addr;
231 	uint64_t    gpu_addr;
232 	uint32_t    mem_size;
233 	uint32_t    log_offset;
234 };
235 
236 struct amdgpu_vcn_inst {
237 	struct amdgpu_bo	*vcpu_bo;
238 	void			*cpu_addr;
239 	uint64_t		gpu_addr;
240 	void			*saved_bo;
241 	struct amdgpu_ring	ring_dec;
242 	struct amdgpu_ring	ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
243 	atomic_t		sched_score;
244 	struct amdgpu_irq_src	irq;
245 	struct amdgpu_irq_src	ras_poison_irq;
246 	struct amdgpu_vcn_reg	external;
247 	struct amdgpu_bo	*dpg_sram_bo;
248 	struct dpg_pause_state	pause_state;
249 	void			*dpg_sram_cpu_addr;
250 	uint64_t		dpg_sram_gpu_addr;
251 	uint32_t		*dpg_sram_curr_addr;
252 	atomic_t		dpg_enc_submission_cnt;
253 	struct amdgpu_vcn_fw_shared fw_shared;
254 	uint8_t			aid_id;
255 };
256 
257 struct amdgpu_vcn_ras {
258 	struct amdgpu_ras_block_object ras_block;
259 };
260 
261 struct amdgpu_vcn {
262 	unsigned		fw_version;
263 	struct delayed_work	idle_work;
264 	const struct firmware	*fw;	/* VCN firmware */
265 	unsigned		num_enc_rings;
266 	enum amd_powergating_state cur_state;
267 	bool			indirect_sram;
268 
269 	uint8_t	num_vcn_inst;
270 	struct amdgpu_vcn_inst	 inst[AMDGPU_MAX_VCN_INSTANCES];
271 	uint8_t			 vcn_config[AMDGPU_MAX_VCN_INSTANCES];
272 	uint32_t		 vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];
273 	struct amdgpu_vcn_reg	 internal;
274 	struct mutex		 vcn_pg_lock;
275 	struct mutex		vcn1_jpeg1_workaround;
276 	atomic_t		 total_submission_cnt;
277 
278 	unsigned	harvest_config;
279 	int (*pause_dpg_mode)(struct amdgpu_device *adev,
280 		int inst_idx, struct dpg_pause_state *new_state);
281 
282 	struct ras_common_if    *ras_if;
283 	struct amdgpu_vcn_ras   *ras;
284 
285 	uint16_t inst_mask;
286 	uint8_t	num_inst_per_aid;
287 	bool using_unified_queue;
288 };
289 
290 struct amdgpu_fw_shared_rb_ptrs_struct {
291 	/* to WA DPG R/W ptr issues.*/
292 	uint32_t  rptr;
293 	uint32_t  wptr;
294 };
295 
296 struct amdgpu_fw_shared_multi_queue {
297 	uint8_t decode_queue_mode;
298 	uint8_t encode_generalpurpose_queue_mode;
299 	uint8_t encode_lowlatency_queue_mode;
300 	uint8_t encode_realtime_queue_mode;
301 	uint8_t padding[4];
302 };
303 
304 struct amdgpu_fw_shared_sw_ring {
305 	uint8_t is_enabled;
306 	uint8_t padding[3];
307 };
308 
309 struct amdgpu_fw_shared_unified_queue_struct {
310 	uint8_t is_enabled;
311 	uint8_t queue_mode;
312 	uint8_t queue_status;
313 	uint8_t padding[5];
314 };
315 
316 struct amdgpu_fw_shared_fw_logging {
317 	uint8_t is_enabled;
318 	uint32_t addr_lo;
319 	uint32_t addr_hi;
320 	uint32_t size;
321 };
322 
323 struct amdgpu_fw_shared_smu_interface_info {
324 	uint8_t smu_interface_type;
325 	uint8_t padding[3];
326 };
327 
328 struct amdgpu_fw_shared {
329 	uint32_t present_flag_0;
330 	uint8_t pad[44];
331 	struct amdgpu_fw_shared_rb_ptrs_struct rb;
332 	uint8_t pad1[1];
333 	struct amdgpu_fw_shared_multi_queue multi_queue;
334 	struct amdgpu_fw_shared_sw_ring sw_ring;
335 	struct amdgpu_fw_shared_fw_logging fw_log;
336 	struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
337 };
338 
339 struct amdgpu_fw_shared_rb_setup {
340 	uint32_t is_rb_enabled_flags;
341 	uint32_t rb_addr_lo;
342 	uint32_t rb_addr_hi;
343 	uint32_t  rb_size;
344 	uint32_t  rb4_addr_lo;
345 	uint32_t  rb4_addr_hi;
346 	uint32_t  rb4_size;
347 	uint32_t  reserved[6];
348 };
349 
350 struct amdgpu_fw_shared_drm_key_wa {
351 	uint8_t  method;
352 	uint8_t  reserved[3];
353 };
354 
355 struct amdgpu_vcn4_fw_shared {
356 	uint32_t present_flag_0;
357 	uint8_t pad[12];
358 	struct amdgpu_fw_shared_unified_queue_struct sq;
359 	uint8_t pad1[8];
360 	struct amdgpu_fw_shared_fw_logging fw_log;
361 	uint8_t pad2[20];
362 	struct amdgpu_fw_shared_rb_setup rb_setup;
363 	struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
364 	struct amdgpu_fw_shared_drm_key_wa drm_key_wa;
365 };
366 
367 struct amdgpu_vcn_fwlog {
368 	uint32_t rptr;
369 	uint32_t wptr;
370 	uint32_t buffer_size;
371 	uint32_t header_size;
372 	uint8_t wrapped;
373 };
374 
375 struct amdgpu_vcn_decode_buffer {
376 	uint32_t valid_buf_flag;
377 	uint32_t msg_buffer_address_hi;
378 	uint32_t msg_buffer_address_lo;
379 	uint32_t pad[30];
380 };
381 
382 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
383 #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
384 #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
385 
386 enum vcn_ring_type {
387 	VCN_ENCODE_RING,
388 	VCN_DECODE_RING,
389 	VCN_UNIFIED_RING,
390 };
391 
392 int amdgpu_vcn_early_init(struct amdgpu_device *adev);
393 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
394 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
395 int amdgpu_vcn_suspend(struct amdgpu_device *adev);
396 int amdgpu_vcn_resume(struct amdgpu_device *adev);
397 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
398 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
399 
400 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
401 				enum vcn_ring_type type, uint32_t vcn_instance);
402 
403 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
404 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
405 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
406 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
407 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout);
408 
409 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
410 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
411 
412 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
413 
414 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
415 
416 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
417 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
418                                    uint8_t i, struct amdgpu_vcn_inst *vcn);
419 
420 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
421 			struct amdgpu_irq_src *source,
422 			struct amdgpu_iv_entry *entry);
423 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev,
424 			struct ras_common_if *ras_block);
425 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);
426 
427 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
428 			       enum AMDGPU_UCODE_ID ucode_id);
429 
430 #endif
431