1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28
29 #include <drm/drm_device.h>
30 #include <drm/radeon_drm.h>
31
32 #include "radeon.h"
33
34 #include "atom.h"
35 #include "atom-bits.h"
36 #include "radeon_asic.h"
37 #include "radeon_atombios.h"
38 #include "radeon_legacy_encoders.h"
39
40 union atom_supported_devices {
41 struct _ATOM_SUPPORTED_DEVICES_INFO info;
42 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
44 };
45
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
47 ATOM_GPIO_I2C_ASSIGMENT *gpio,
48 u8 index)
49 {
50 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
51 if ((rdev->family == CHIP_R420) ||
52 (rdev->family == CHIP_R423) ||
53 (rdev->family == CHIP_RV410)) {
54 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
55 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
57 gpio->ucClkMaskShift = 0x19;
58 gpio->ucDataMaskShift = 0x18;
59 }
60 }
61
62 /* some evergreen boards have bad data for this entry */
63 if (ASIC_IS_DCE4(rdev)) {
64 if ((index == 7) &&
65 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
66 (gpio->sucI2cId.ucAccess == 0)) {
67 gpio->sucI2cId.ucAccess = 0x97;
68 gpio->ucDataMaskShift = 8;
69 gpio->ucDataEnShift = 8;
70 gpio->ucDataY_Shift = 8;
71 gpio->ucDataA_Shift = 8;
72 }
73 }
74
75 /* some DCE3 boards have bad data for this entry */
76 if (ASIC_IS_DCE3(rdev)) {
77 if ((index == 4) &&
78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
79 (gpio->sucI2cId.ucAccess == 0x94))
80 gpio->sucI2cId.ucAccess = 0x14;
81 }
82 }
83
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
85 {
86 struct radeon_i2c_bus_rec i2c;
87
88 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
89
90 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
91 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
92 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
93 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
94 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
95 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
96 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
97 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
98 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
99 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
100 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
101 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
102 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
103 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
104 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
105 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
106
107 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
108 i2c.hw_capable = true;
109 else
110 i2c.hw_capable = false;
111
112 if (gpio->sucI2cId.ucAccess == 0xa0)
113 i2c.mm_i2c = true;
114 else
115 i2c.mm_i2c = false;
116
117 i2c.i2c_id = gpio->sucI2cId.ucAccess;
118
119 if (i2c.mask_clk_reg)
120 i2c.valid = true;
121 else
122 i2c.valid = false;
123
124 return i2c;
125 }
126
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
128 uint8_t id)
129 {
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137
138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
139 i2c.valid = false;
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 gpio = &i2c_info->asGPIO_Info[0];
148 for (i = 0; i < num_indices; i++) {
149
150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
151
152 if (gpio->sucI2cId.ucAccess == id) {
153 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
154 break;
155 }
156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
158 }
159 }
160
161 return i2c;
162 }
163
radeon_atombios_i2c_init(struct radeon_device * rdev)164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
165 {
166 struct atom_context *ctx = rdev->mode_info.atom_context;
167 ATOM_GPIO_I2C_ASSIGMENT *gpio;
168 struct radeon_i2c_bus_rec i2c;
169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
170 struct _ATOM_GPIO_I2C_INFO *i2c_info;
171 uint16_t data_offset, size;
172 int i, num_indices;
173 char stmp[32];
174
175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
177
178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
179 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
180
181 gpio = &i2c_info->asGPIO_Info[0];
182 for (i = 0; i < num_indices; i++) {
183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
184
185 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
186
187 if (i2c.valid) {
188 sprintf(stmp, "0x%x", i2c.i2c_id);
189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
190 }
191 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
192 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
193 }
194 }
195 }
196
radeon_atombios_lookup_gpio(struct radeon_device * rdev,u8 id)197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
198 u8 id)
199 {
200 struct atom_context *ctx = rdev->mode_info.atom_context;
201 struct radeon_gpio_rec gpio;
202 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
203 struct _ATOM_GPIO_PIN_LUT *gpio_info;
204 ATOM_GPIO_PIN_ASSIGNMENT *pin;
205 u16 data_offset, size;
206 int i, num_indices;
207
208 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
209 gpio.valid = false;
210
211 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
212 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
213
214 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
215 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
216
217 pin = gpio_info->asGPIO_Pin;
218 for (i = 0; i < num_indices; i++) {
219 if (id == pin->ucGPIO_ID) {
220 gpio.id = pin->ucGPIO_ID;
221 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
222 gpio.shift = pin->ucGpioPinBitShift;
223 gpio.mask = (1 << pin->ucGpioPinBitShift);
224 gpio.valid = true;
225 break;
226 }
227 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
228 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
229 }
230 }
231
232 return gpio;
233 }
234
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
236 struct radeon_gpio_rec *gpio)
237 {
238 struct radeon_hpd hpd;
239 u32 reg;
240
241 memset(&hpd, 0, sizeof(struct radeon_hpd));
242
243 if (ASIC_IS_DCE6(rdev))
244 reg = SI_DC_GPIO_HPD_A;
245 else if (ASIC_IS_DCE4(rdev))
246 reg = EVERGREEN_DC_GPIO_HPD_A;
247 else
248 reg = AVIVO_DC_GPIO_HPD_A;
249
250 hpd.gpio = *gpio;
251 if (gpio->reg == reg) {
252 switch(gpio->mask) {
253 case (1 << 0):
254 hpd.hpd = RADEON_HPD_1;
255 break;
256 case (1 << 8):
257 hpd.hpd = RADEON_HPD_2;
258 break;
259 case (1 << 16):
260 hpd.hpd = RADEON_HPD_3;
261 break;
262 case (1 << 24):
263 hpd.hpd = RADEON_HPD_4;
264 break;
265 case (1 << 26):
266 hpd.hpd = RADEON_HPD_5;
267 break;
268 case (1 << 28):
269 hpd.hpd = RADEON_HPD_6;
270 break;
271 default:
272 hpd.hpd = RADEON_HPD_NONE;
273 break;
274 }
275 } else
276 hpd.hpd = RADEON_HPD_NONE;
277 return hpd;
278 }
279
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)280 static bool radeon_atom_apply_quirks(struct drm_device *dev,
281 uint32_t supported_device,
282 int *connector_type,
283 struct radeon_i2c_bus_rec *i2c_bus,
284 uint16_t *line_mux,
285 struct radeon_hpd *hpd)
286 {
287 struct pci_dev *pdev = to_pci_dev(dev->dev);
288
289 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
290 if ((pdev->device == 0x791e) &&
291 (pdev->subsystem_vendor == 0x1043) &&
292 (pdev->subsystem_device == 0x826d)) {
293 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
294 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
295 *connector_type = DRM_MODE_CONNECTOR_DVID;
296 }
297
298 /* Asrock RS600 board lists the DVI port as HDMI */
299 if ((pdev->device == 0x7941) &&
300 (pdev->subsystem_vendor == 0x1849) &&
301 (pdev->subsystem_device == 0x7941)) {
302 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
303 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
304 *connector_type = DRM_MODE_CONNECTOR_DVID;
305 }
306
307 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
308 if ((pdev->device == 0x796e) &&
309 (pdev->subsystem_vendor == 0x1462) &&
310 (pdev->subsystem_device == 0x7302)) {
311 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
312 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
313 return false;
314 }
315
316 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
317 if ((pdev->device == 0x7941) &&
318 (pdev->subsystem_vendor == 0x147b) &&
319 (pdev->subsystem_device == 0x2412)) {
320 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
321 return false;
322 }
323
324 /* Falcon NW laptop lists vga ddc line for LVDS */
325 if ((pdev->device == 0x5653) &&
326 (pdev->subsystem_vendor == 0x1462) &&
327 (pdev->subsystem_device == 0x0291)) {
328 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
329 i2c_bus->valid = false;
330 *line_mux = 53;
331 }
332 }
333
334 /* HIS X1300 is DVI+VGA, not DVI+DVI */
335 if ((pdev->device == 0x7146) &&
336 (pdev->subsystem_vendor == 0x17af) &&
337 (pdev->subsystem_device == 0x2058)) {
338 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
339 return false;
340 }
341
342 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
343 if ((pdev->device == 0x7142) &&
344 (pdev->subsystem_vendor == 0x1458) &&
345 (pdev->subsystem_device == 0x2134)) {
346 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
347 return false;
348 }
349
350
351 /* Funky macbooks */
352 if ((pdev->device == 0x71C5) &&
353 (pdev->subsystem_vendor == 0x106b) &&
354 (pdev->subsystem_device == 0x0080)) {
355 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
356 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
357 return false;
358 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
359 *line_mux = 0x90;
360 }
361
362 /* mac rv630, rv730, others */
363 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
364 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
365 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
366 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
367 }
368
369 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
370 if ((pdev->device == 0x9598) &&
371 (pdev->subsystem_vendor == 0x1043) &&
372 (pdev->subsystem_device == 0x01da)) {
373 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
374 *connector_type = DRM_MODE_CONNECTOR_DVII;
375 }
376 }
377
378 /* ASUS HD 3600 board lists the DVI port as HDMI */
379 if ((pdev->device == 0x9598) &&
380 (pdev->subsystem_vendor == 0x1043) &&
381 (pdev->subsystem_device == 0x01e4)) {
382 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
383 *connector_type = DRM_MODE_CONNECTOR_DVII;
384 }
385 }
386
387 /* ASUS HD 3450 board lists the DVI port as HDMI */
388 if ((pdev->device == 0x95C5) &&
389 (pdev->subsystem_vendor == 0x1043) &&
390 (pdev->subsystem_device == 0x01e2)) {
391 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
392 *connector_type = DRM_MODE_CONNECTOR_DVII;
393 }
394 }
395
396 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
397 * HDMI + VGA reporting as HDMI
398 */
399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
400 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
401 *connector_type = DRM_MODE_CONNECTOR_VGA;
402 *line_mux = 0;
403 }
404 }
405
406 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
407 * on the laptop and a DVI port on the docking station and
408 * both share the same encoder, hpd pin, and ddc line.
409 * So while the bios table is technically correct,
410 * we drop the DVI port here since xrandr has no concept of
411 * encoders and will try and drive both connectors
412 * with different crtcs which isn't possible on the hardware
413 * side and leaves no crtcs for LVDS or VGA.
414 */
415 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
416 (pdev->subsystem_vendor == 0x1025) &&
417 (pdev->subsystem_device == 0x013c)) {
418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 /* actually it's a DVI-D port not DVI-I */
421 *connector_type = DRM_MODE_CONNECTOR_DVID;
422 return false;
423 }
424 }
425
426 /* XFX Pine Group device rv730 reports no VGA DDC lines
427 * even though they are wired up to record 0x93
428 */
429 if ((pdev->device == 0x9498) &&
430 (pdev->subsystem_vendor == 0x1682) &&
431 (pdev->subsystem_device == 0x2452) &&
432 (i2c_bus->valid == false) &&
433 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
434 struct radeon_device *rdev = dev->dev_private;
435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
436 }
437
438 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
439 if (((pdev->device == 0x9802) ||
440 (pdev->device == 0x9805) ||
441 (pdev->device == 0x9806)) &&
442 (pdev->subsystem_vendor == 0x1734) &&
443 (pdev->subsystem_device == 0x11bd)) {
444 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
445 *connector_type = DRM_MODE_CONNECTOR_DVII;
446 *line_mux = 0x3103;
447 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
448 *connector_type = DRM_MODE_CONNECTOR_DVII;
449 }
450 }
451
452 return true;
453 }
454
455 static const int supported_devices_connector_convert[] = {
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_VGA,
458 DRM_MODE_CONNECTOR_DVII,
459 DRM_MODE_CONNECTOR_DVID,
460 DRM_MODE_CONNECTOR_DVIA,
461 DRM_MODE_CONNECTOR_SVIDEO,
462 DRM_MODE_CONNECTOR_Composite,
463 DRM_MODE_CONNECTOR_LVDS,
464 DRM_MODE_CONNECTOR_Unknown,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_HDMIA,
467 DRM_MODE_CONNECTOR_HDMIB,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_9PinDIN,
471 DRM_MODE_CONNECTOR_DisplayPort
472 };
473
474 static const uint16_t supported_devices_connector_object_id_convert[] = {
475 CONNECTOR_OBJECT_ID_NONE,
476 CONNECTOR_OBJECT_ID_VGA,
477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
480 CONNECTOR_OBJECT_ID_COMPOSITE,
481 CONNECTOR_OBJECT_ID_SVIDEO,
482 CONNECTOR_OBJECT_ID_LVDS,
483 CONNECTOR_OBJECT_ID_9PIN_DIN,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_DISPLAYPORT,
486 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
488 CONNECTOR_OBJECT_ID_SVIDEO
489 };
490
491 static const int object_connector_convert[] = {
492 DRM_MODE_CONNECTOR_Unknown,
493 DRM_MODE_CONNECTOR_DVII,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVID,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_VGA,
498 DRM_MODE_CONNECTOR_Composite,
499 DRM_MODE_CONNECTOR_SVIDEO,
500 DRM_MODE_CONNECTOR_Unknown,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_9PinDIN,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_HDMIA,
505 DRM_MODE_CONNECTOR_HDMIB,
506 DRM_MODE_CONNECTOR_LVDS,
507 DRM_MODE_CONNECTOR_9PinDIN,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_DisplayPort,
512 DRM_MODE_CONNECTOR_eDP,
513 DRM_MODE_CONNECTOR_Unknown
514 };
515
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)516 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
517 {
518 struct radeon_device *rdev = dev->dev_private;
519 struct radeon_mode_info *mode_info = &rdev->mode_info;
520 struct atom_context *ctx = mode_info->atom_context;
521 int index = GetIndexIntoMasterTable(DATA, Object_Header);
522 u16 size, data_offset;
523 u8 frev, crev;
524 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
525 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
526 ATOM_OBJECT_TABLE *router_obj;
527 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
528 ATOM_OBJECT_HEADER *obj_header;
529 int i, j, k, path_size, device_support;
530 int connector_type;
531 u16 igp_lane_info, conn_id, connector_object_id;
532 struct radeon_i2c_bus_rec ddc_bus;
533 struct radeon_router router;
534 struct radeon_gpio_rec gpio;
535 struct radeon_hpd hpd;
536
537 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
538 return false;
539
540 if (crev < 2)
541 return false;
542
543 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
544 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
545 (ctx->bios + data_offset +
546 le16_to_cpu(obj_header->usDisplayPathTableOffset));
547 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
548 (ctx->bios + data_offset +
549 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
550 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
551 (ctx->bios + data_offset +
552 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
553 router_obj = (ATOM_OBJECT_TABLE *)
554 (ctx->bios + data_offset +
555 le16_to_cpu(obj_header->usRouterObjectTableOffset));
556 device_support = le16_to_cpu(obj_header->usDeviceSupport);
557
558 path_size = 0;
559 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
560 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
561 ATOM_DISPLAY_OBJECT_PATH *path;
562 addr += path_size;
563 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
564 path_size += le16_to_cpu(path->usSize);
565
566 if (device_support & le16_to_cpu(path->usDeviceTag)) {
567 uint8_t con_obj_id, con_obj_num;
568
569 con_obj_id =
570 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
571 >> OBJECT_ID_SHIFT;
572 con_obj_num =
573 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
574 >> ENUM_ID_SHIFT;
575
576 /* TODO CV support */
577 if (le16_to_cpu(path->usDeviceTag) ==
578 ATOM_DEVICE_CV_SUPPORT)
579 continue;
580
581 /* IGP chips */
582 if ((rdev->flags & RADEON_IS_IGP) &&
583 (con_obj_id ==
584 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
585 uint16_t igp_offset = 0;
586 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
587
588 index =
589 GetIndexIntoMasterTable(DATA,
590 IntegratedSystemInfo);
591
592 if (atom_parse_data_header(ctx, index, &size, &frev,
593 &crev, &igp_offset)) {
594
595 if (crev >= 2) {
596 igp_obj =
597 (ATOM_INTEGRATED_SYSTEM_INFO_V2
598 *) (ctx->bios + igp_offset);
599
600 if (igp_obj) {
601 uint32_t slot_config, ct;
602
603 if (con_obj_num == 1)
604 slot_config =
605 igp_obj->
606 ulDDISlot1Config;
607 else
608 slot_config =
609 igp_obj->
610 ulDDISlot2Config;
611
612 ct = (slot_config >> 16) & 0xff;
613 connector_type =
614 object_connector_convert
615 [ct];
616 connector_object_id = ct;
617 igp_lane_info =
618 slot_config & 0xffff;
619 } else
620 continue;
621 } else
622 continue;
623 } else {
624 igp_lane_info = 0;
625 connector_type =
626 object_connector_convert[con_obj_id];
627 connector_object_id = con_obj_id;
628 }
629 } else {
630 igp_lane_info = 0;
631 connector_type =
632 object_connector_convert[con_obj_id];
633 connector_object_id = con_obj_id;
634 }
635
636 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
637 continue;
638
639 router.ddc_valid = false;
640 router.cd_valid = false;
641 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
642 uint8_t grph_obj_type =
643 (le16_to_cpu(path->usGraphicObjIds[j]) &
644 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
645
646 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
647 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
648 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
649 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
650 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
651 (ctx->bios + data_offset +
652 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
653 ATOM_ENCODER_CAP_RECORD *cap_record;
654 u16 caps = 0;
655
656 while (record->ucRecordSize > 0 &&
657 record->ucRecordType > 0 &&
658 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
659 switch (record->ucRecordType) {
660 case ATOM_ENCODER_CAP_RECORD_TYPE:
661 cap_record =(ATOM_ENCODER_CAP_RECORD *)
662 record;
663 caps = le16_to_cpu(cap_record->usEncoderCap);
664 break;
665 }
666 record = (ATOM_COMMON_RECORD_HEADER *)
667 ((char *)record + record->ucRecordSize);
668 }
669 radeon_add_atom_encoder(dev,
670 encoder_obj,
671 le16_to_cpu
672 (path->
673 usDeviceTag),
674 caps);
675 }
676 }
677 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
678 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
679 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
680 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
681 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
682 (ctx->bios + data_offset +
683 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
684 ATOM_I2C_RECORD *i2c_record;
685 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
686 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
687 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
688 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
689 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
690 (ctx->bios + data_offset +
691 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
692 u8 *num_dst_objs = (u8 *)
693 ((u8 *)router_src_dst_table + 1 +
694 (router_src_dst_table->ucNumberOfSrc * 2));
695 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
696 int enum_id;
697
698 router.router_id = router_obj_id;
699 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
700 if (le16_to_cpu(path->usConnObjectId) ==
701 le16_to_cpu(dst_objs[enum_id]))
702 break;
703 }
704
705 while (record->ucRecordSize > 0 &&
706 record->ucRecordType > 0 &&
707 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
708 switch (record->ucRecordType) {
709 case ATOM_I2C_RECORD_TYPE:
710 i2c_record =
711 (ATOM_I2C_RECORD *)
712 record;
713 i2c_config =
714 (ATOM_I2C_ID_CONFIG_ACCESS *)
715 &i2c_record->sucI2cId;
716 router.i2c_info =
717 radeon_lookup_i2c_gpio(rdev,
718 i2c_config->
719 ucAccess);
720 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
721 break;
722 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
723 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
724 record;
725 router.ddc_valid = true;
726 router.ddc_mux_type = ddc_path->ucMuxType;
727 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
728 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
729 break;
730 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
731 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
732 record;
733 router.cd_valid = true;
734 router.cd_mux_type = cd_path->ucMuxType;
735 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
736 router.cd_mux_state = cd_path->ucMuxState[enum_id];
737 break;
738 }
739 record = (ATOM_COMMON_RECORD_HEADER *)
740 ((char *)record + record->ucRecordSize);
741 }
742 }
743 }
744 }
745 }
746
747 /* look up gpio for ddc, hpd */
748 ddc_bus.valid = false;
749 hpd.hpd = RADEON_HPD_NONE;
750 if ((le16_to_cpu(path->usDeviceTag) &
751 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
752 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
753 if (le16_to_cpu(path->usConnObjectId) ==
754 le16_to_cpu(con_obj->asObjects[j].
755 usObjectID)) {
756 ATOM_COMMON_RECORD_HEADER
757 *record =
758 (ATOM_COMMON_RECORD_HEADER
759 *)
760 (ctx->bios + data_offset +
761 le16_to_cpu(con_obj->
762 asObjects[j].
763 usRecordOffset));
764 ATOM_I2C_RECORD *i2c_record;
765 ATOM_HPD_INT_RECORD *hpd_record;
766 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
767
768 while (record->ucRecordSize > 0 &&
769 record->ucRecordType > 0 &&
770 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
771 switch (record->ucRecordType) {
772 case ATOM_I2C_RECORD_TYPE:
773 i2c_record =
774 (ATOM_I2C_RECORD *)
775 record;
776 i2c_config =
777 (ATOM_I2C_ID_CONFIG_ACCESS *)
778 &i2c_record->sucI2cId;
779 ddc_bus = radeon_lookup_i2c_gpio(rdev,
780 i2c_config->
781 ucAccess);
782 break;
783 case ATOM_HPD_INT_RECORD_TYPE:
784 hpd_record =
785 (ATOM_HPD_INT_RECORD *)
786 record;
787 gpio = radeon_atombios_lookup_gpio(rdev,
788 hpd_record->ucHPDIntGPIOID);
789 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
790 hpd.plugged_state = hpd_record->ucPlugged_PinState;
791 break;
792 }
793 record =
794 (ATOM_COMMON_RECORD_HEADER
795 *) ((char *)record
796 +
797 record->
798 ucRecordSize);
799 }
800 break;
801 }
802 }
803 }
804
805 /* needed for aux chan transactions */
806 ddc_bus.hpd = hpd.hpd;
807
808 conn_id = le16_to_cpu(path->usConnObjectId);
809
810 if (!radeon_atom_apply_quirks
811 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
812 &ddc_bus, &conn_id, &hpd))
813 continue;
814
815 radeon_add_atom_connector(dev,
816 conn_id,
817 le16_to_cpu(path->
818 usDeviceTag),
819 connector_type, &ddc_bus,
820 igp_lane_info,
821 connector_object_id,
822 &hpd,
823 &router);
824
825 }
826 }
827
828 radeon_link_encoder_connector(dev);
829 return true;
830 }
831
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)832 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
833 int connector_type,
834 uint16_t devices)
835 {
836 struct radeon_device *rdev = dev->dev_private;
837
838 if (rdev->flags & RADEON_IS_IGP) {
839 return supported_devices_connector_object_id_convert
840 [connector_type];
841 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
842 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
843 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
844 struct radeon_mode_info *mode_info = &rdev->mode_info;
845 struct atom_context *ctx = mode_info->atom_context;
846 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
847 uint16_t size, data_offset;
848 uint8_t frev, crev;
849 ATOM_XTMDS_INFO *xtmds;
850
851 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
852 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
853
854 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
855 if (connector_type == DRM_MODE_CONNECTOR_DVII)
856 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
857 else
858 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
859 } else {
860 if (connector_type == DRM_MODE_CONNECTOR_DVII)
861 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
862 else
863 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
864 }
865 } else
866 return supported_devices_connector_object_id_convert
867 [connector_type];
868 } else {
869 return supported_devices_connector_object_id_convert
870 [connector_type];
871 }
872 }
873
874 struct bios_connector {
875 bool valid;
876 uint16_t line_mux;
877 uint16_t devices;
878 int connector_type;
879 struct radeon_i2c_bus_rec ddc_bus;
880 struct radeon_hpd hpd;
881 };
882
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)883 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
884 drm_device
885 *dev)
886 {
887 struct radeon_device *rdev = dev->dev_private;
888 struct radeon_mode_info *mode_info = &rdev->mode_info;
889 struct atom_context *ctx = mode_info->atom_context;
890 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
891 uint16_t size, data_offset;
892 uint8_t frev, crev;
893 uint16_t device_support;
894 uint8_t dac;
895 union atom_supported_devices *supported_devices;
896 int i, j, max_device;
897 struct bios_connector *bios_connectors;
898 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
899 struct radeon_router router;
900
901 router.ddc_valid = false;
902 router.cd_valid = false;
903
904 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
905 if (!bios_connectors)
906 return false;
907
908 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
909 &data_offset)) {
910 kfree(bios_connectors);
911 return false;
912 }
913
914 supported_devices =
915 (union atom_supported_devices *)(ctx->bios + data_offset);
916
917 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
918
919 if (frev > 1)
920 max_device = ATOM_MAX_SUPPORTED_DEVICE;
921 else
922 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
923
924 for (i = 0; i < max_device; i++) {
925 ATOM_CONNECTOR_INFO_I2C ci;
926
927 if (frev > 1)
928 ci = supported_devices->info_2d1.asConnInfo[i];
929 else
930 ci = supported_devices->info.asConnInfo[i];
931
932 bios_connectors[i].valid = false;
933
934 if (!(device_support & (1 << i))) {
935 continue;
936 }
937
938 if (i == ATOM_DEVICE_CV_INDEX) {
939 DRM_DEBUG_KMS("Skipping Component Video\n");
940 continue;
941 }
942
943 bios_connectors[i].connector_type =
944 supported_devices_connector_convert[ci.sucConnectorInfo.
945 sbfAccess.
946 bfConnectorType];
947
948 if (bios_connectors[i].connector_type ==
949 DRM_MODE_CONNECTOR_Unknown)
950 continue;
951
952 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
953
954 bios_connectors[i].line_mux =
955 ci.sucI2cId.ucAccess;
956
957 /* give tv unique connector ids */
958 if (i == ATOM_DEVICE_TV1_INDEX) {
959 bios_connectors[i].ddc_bus.valid = false;
960 bios_connectors[i].line_mux = 50;
961 } else if (i == ATOM_DEVICE_TV2_INDEX) {
962 bios_connectors[i].ddc_bus.valid = false;
963 bios_connectors[i].line_mux = 51;
964 } else if (i == ATOM_DEVICE_CV_INDEX) {
965 bios_connectors[i].ddc_bus.valid = false;
966 bios_connectors[i].line_mux = 52;
967 } else
968 bios_connectors[i].ddc_bus =
969 radeon_lookup_i2c_gpio(rdev,
970 bios_connectors[i].line_mux);
971
972 if ((crev > 1) && (frev > 1)) {
973 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
974 switch (isb) {
975 case 0x4:
976 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
977 break;
978 case 0xa:
979 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
980 break;
981 default:
982 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
983 break;
984 }
985 } else {
986 if (i == ATOM_DEVICE_DFP1_INDEX)
987 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
988 else if (i == ATOM_DEVICE_DFP2_INDEX)
989 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
990 else
991 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
992 }
993
994 /* Always set the connector type to VGA for CRT1/CRT2. if they are
995 * shared with a DVI port, we'll pick up the DVI connector when we
996 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
997 */
998 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
999 bios_connectors[i].connector_type =
1000 DRM_MODE_CONNECTOR_VGA;
1001
1002 if (!radeon_atom_apply_quirks
1003 (dev, (1 << i), &bios_connectors[i].connector_type,
1004 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1005 &bios_connectors[i].hpd))
1006 continue;
1007
1008 bios_connectors[i].valid = true;
1009 bios_connectors[i].devices = (1 << i);
1010
1011 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1012 radeon_add_atom_encoder(dev,
1013 radeon_get_encoder_enum(dev,
1014 (1 << i),
1015 dac),
1016 (1 << i),
1017 0);
1018 else
1019 radeon_add_legacy_encoder(dev,
1020 radeon_get_encoder_enum(dev,
1021 (1 << i),
1022 dac),
1023 (1 << i));
1024 }
1025
1026 /* combine shared connectors */
1027 for (i = 0; i < max_device; i++) {
1028 if (bios_connectors[i].valid) {
1029 for (j = 0; j < max_device; j++) {
1030 if (bios_connectors[j].valid && (i != j)) {
1031 if (bios_connectors[i].line_mux ==
1032 bios_connectors[j].line_mux) {
1033 /* make sure not to combine LVDS */
1034 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1035 bios_connectors[i].line_mux = 53;
1036 bios_connectors[i].ddc_bus.valid = false;
1037 continue;
1038 }
1039 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1040 bios_connectors[j].line_mux = 53;
1041 bios_connectors[j].ddc_bus.valid = false;
1042 continue;
1043 }
1044 /* combine analog and digital for DVI-I */
1045 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1046 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1047 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1048 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1049 bios_connectors[i].devices |=
1050 bios_connectors[j].devices;
1051 bios_connectors[i].connector_type =
1052 DRM_MODE_CONNECTOR_DVII;
1053 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1054 bios_connectors[i].hpd =
1055 bios_connectors[j].hpd;
1056 bios_connectors[j].valid = false;
1057 }
1058 }
1059 }
1060 }
1061 }
1062 }
1063
1064 /* add the connectors */
1065 for (i = 0; i < max_device; i++) {
1066 if (bios_connectors[i].valid) {
1067 uint16_t connector_object_id =
1068 atombios_get_connector_object_id(dev,
1069 bios_connectors[i].connector_type,
1070 bios_connectors[i].devices);
1071 radeon_add_atom_connector(dev,
1072 bios_connectors[i].line_mux,
1073 bios_connectors[i].devices,
1074 bios_connectors[i].
1075 connector_type,
1076 &bios_connectors[i].ddc_bus,
1077 0,
1078 connector_object_id,
1079 &bios_connectors[i].hpd,
1080 &router);
1081 }
1082 }
1083
1084 radeon_link_encoder_connector(dev);
1085
1086 kfree(bios_connectors);
1087 return true;
1088 }
1089
1090 union firmware_info {
1091 ATOM_FIRMWARE_INFO info;
1092 ATOM_FIRMWARE_INFO_V1_2 info_12;
1093 ATOM_FIRMWARE_INFO_V1_3 info_13;
1094 ATOM_FIRMWARE_INFO_V1_4 info_14;
1095 ATOM_FIRMWARE_INFO_V2_1 info_21;
1096 ATOM_FIRMWARE_INFO_V2_2 info_22;
1097 };
1098
1099 union igp_info {
1100 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1101 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1102 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1103 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1104 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1105 };
1106
radeon_atombios_get_dentist_vco_freq(struct radeon_device * rdev)1107 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1108 {
1109 struct radeon_mode_info *mode_info = &rdev->mode_info;
1110 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1111 union igp_info *igp_info;
1112 u8 frev, crev;
1113 u16 data_offset;
1114
1115 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1116 &frev, &crev, &data_offset)) {
1117 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1118 data_offset);
1119 rdev->clock.vco_freq =
1120 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1121 }
1122 }
1123
radeon_atom_get_clock_info(struct drm_device * dev)1124 bool radeon_atom_get_clock_info(struct drm_device *dev)
1125 {
1126 struct radeon_device *rdev = dev->dev_private;
1127 struct radeon_mode_info *mode_info = &rdev->mode_info;
1128 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1129 union firmware_info *firmware_info;
1130 uint8_t frev, crev;
1131 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1132 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1133 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1134 struct radeon_pll *spll = &rdev->clock.spll;
1135 struct radeon_pll *mpll = &rdev->clock.mpll;
1136 uint16_t data_offset;
1137
1138 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1139 &frev, &crev, &data_offset)) {
1140 firmware_info =
1141 (union firmware_info *)(mode_info->atom_context->bios +
1142 data_offset);
1143 /* pixel clocks */
1144 p1pll->reference_freq =
1145 le16_to_cpu(firmware_info->info.usReferenceClock);
1146 p1pll->reference_div = 0;
1147
1148 if ((frev < 2) && (crev < 2))
1149 p1pll->pll_out_min =
1150 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1151 else
1152 p1pll->pll_out_min =
1153 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1154 p1pll->pll_out_max =
1155 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1156
1157 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1158 p1pll->lcd_pll_out_min =
1159 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1160 if (p1pll->lcd_pll_out_min == 0)
1161 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1162 p1pll->lcd_pll_out_max =
1163 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1164 if (p1pll->lcd_pll_out_max == 0)
1165 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1166 } else {
1167 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1168 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1169 }
1170
1171 if (p1pll->pll_out_min == 0) {
1172 if (ASIC_IS_AVIVO(rdev))
1173 p1pll->pll_out_min = 64800;
1174 else
1175 p1pll->pll_out_min = 20000;
1176 }
1177
1178 p1pll->pll_in_min =
1179 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1180 p1pll->pll_in_max =
1181 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1182
1183 *p2pll = *p1pll;
1184
1185 /* system clock */
1186 if (ASIC_IS_DCE4(rdev))
1187 spll->reference_freq =
1188 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1189 else
1190 spll->reference_freq =
1191 le16_to_cpu(firmware_info->info.usReferenceClock);
1192 spll->reference_div = 0;
1193
1194 spll->pll_out_min =
1195 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1196 spll->pll_out_max =
1197 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1198
1199 /* ??? */
1200 if (spll->pll_out_min == 0) {
1201 if (ASIC_IS_AVIVO(rdev))
1202 spll->pll_out_min = 64800;
1203 else
1204 spll->pll_out_min = 20000;
1205 }
1206
1207 spll->pll_in_min =
1208 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1209 spll->pll_in_max =
1210 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1211
1212 /* memory clock */
1213 if (ASIC_IS_DCE4(rdev))
1214 mpll->reference_freq =
1215 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1216 else
1217 mpll->reference_freq =
1218 le16_to_cpu(firmware_info->info.usReferenceClock);
1219 mpll->reference_div = 0;
1220
1221 mpll->pll_out_min =
1222 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1223 mpll->pll_out_max =
1224 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1225
1226 /* ??? */
1227 if (mpll->pll_out_min == 0) {
1228 if (ASIC_IS_AVIVO(rdev))
1229 mpll->pll_out_min = 64800;
1230 else
1231 mpll->pll_out_min = 20000;
1232 }
1233
1234 mpll->pll_in_min =
1235 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1236 mpll->pll_in_max =
1237 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1238
1239 rdev->clock.default_sclk =
1240 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1241 rdev->clock.default_mclk =
1242 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1243
1244 if (ASIC_IS_DCE4(rdev)) {
1245 rdev->clock.default_dispclk =
1246 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1247 if (rdev->clock.default_dispclk == 0) {
1248 if (ASIC_IS_DCE6(rdev))
1249 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1250 else if (ASIC_IS_DCE5(rdev))
1251 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1252 else
1253 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1254 }
1255 /* set a reasonable default for DP */
1256 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1257 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1258 rdev->clock.default_dispclk / 100);
1259 rdev->clock.default_dispclk = 60000;
1260 }
1261 rdev->clock.dp_extclk =
1262 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1263 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1264 }
1265 *dcpll = *p1pll;
1266
1267 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1268 if (rdev->clock.max_pixel_clock == 0)
1269 rdev->clock.max_pixel_clock = 40000;
1270
1271 /* not technically a clock, but... */
1272 rdev->mode_info.firmware_flags =
1273 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1274
1275 if (ASIC_IS_DCE8(rdev))
1276 rdev->clock.vco_freq =
1277 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1278 else if (ASIC_IS_DCE5(rdev))
1279 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1280 else if (ASIC_IS_DCE41(rdev))
1281 radeon_atombios_get_dentist_vco_freq(rdev);
1282 else
1283 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1284
1285 if (rdev->clock.vco_freq == 0)
1286 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1287
1288 return true;
1289 }
1290
1291 return false;
1292 }
1293
radeon_atombios_sideport_present(struct radeon_device * rdev)1294 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1295 {
1296 struct radeon_mode_info *mode_info = &rdev->mode_info;
1297 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1298 union igp_info *igp_info;
1299 u8 frev, crev;
1300 u16 data_offset;
1301
1302 /* sideport is AMD only */
1303 if (rdev->family == CHIP_RS600)
1304 return false;
1305
1306 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1307 &frev, &crev, &data_offset)) {
1308 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1309 data_offset);
1310 switch (crev) {
1311 case 1:
1312 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1313 return true;
1314 break;
1315 case 2:
1316 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1317 return true;
1318 break;
1319 default:
1320 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1321 break;
1322 }
1323 }
1324 return false;
1325 }
1326
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1327 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1328 struct radeon_encoder_int_tmds *tmds)
1329 {
1330 struct drm_device *dev = encoder->base.dev;
1331 struct radeon_device *rdev = dev->dev_private;
1332 struct radeon_mode_info *mode_info = &rdev->mode_info;
1333 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1334 uint16_t data_offset;
1335 struct _ATOM_TMDS_INFO *tmds_info;
1336 uint8_t frev, crev;
1337 uint16_t maxfreq;
1338 int i;
1339
1340 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1341 &frev, &crev, &data_offset)) {
1342 tmds_info =
1343 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1344 data_offset);
1345
1346 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1347 for (i = 0; i < 4; i++) {
1348 tmds->tmds_pll[i].freq =
1349 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1350 tmds->tmds_pll[i].value =
1351 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1352 tmds->tmds_pll[i].value |=
1353 (tmds_info->asMiscInfo[i].
1354 ucPLL_VCO_Gain & 0x3f) << 6;
1355 tmds->tmds_pll[i].value |=
1356 (tmds_info->asMiscInfo[i].
1357 ucPLL_DutyCycle & 0xf) << 12;
1358 tmds->tmds_pll[i].value |=
1359 (tmds_info->asMiscInfo[i].
1360 ucPLL_VoltageSwing & 0xf) << 16;
1361
1362 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1363 tmds->tmds_pll[i].freq,
1364 tmds->tmds_pll[i].value);
1365
1366 if (maxfreq == tmds->tmds_pll[i].freq) {
1367 tmds->tmds_pll[i].freq = 0xffffffff;
1368 break;
1369 }
1370 }
1371 return true;
1372 }
1373 return false;
1374 }
1375
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1376 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1377 struct radeon_atom_ss *ss,
1378 int id)
1379 {
1380 struct radeon_mode_info *mode_info = &rdev->mode_info;
1381 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1382 uint16_t data_offset, size;
1383 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1384 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1385 uint8_t frev, crev;
1386 int i, num_indices;
1387
1388 memset(ss, 0, sizeof(struct radeon_atom_ss));
1389 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1390 &frev, &crev, &data_offset)) {
1391 ss_info =
1392 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1393
1394 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1395 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1396 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1397 ((u8 *)&ss_info->asSS_Info[0]);
1398 for (i = 0; i < num_indices; i++) {
1399 if (ss_assign->ucSS_Id == id) {
1400 ss->percentage =
1401 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1402 ss->type = ss_assign->ucSpreadSpectrumType;
1403 ss->step = ss_assign->ucSS_Step;
1404 ss->delay = ss_assign->ucSS_Delay;
1405 ss->range = ss_assign->ucSS_Range;
1406 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1407 return true;
1408 }
1409 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1410 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1411 }
1412 }
1413 return false;
1414 }
1415
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1416 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1417 struct radeon_atom_ss *ss,
1418 int id)
1419 {
1420 struct radeon_mode_info *mode_info = &rdev->mode_info;
1421 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1422 u16 data_offset, size;
1423 union igp_info *igp_info;
1424 u8 frev, crev;
1425 u16 percentage = 0, rate = 0;
1426
1427 /* get any igp specific overrides */
1428 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1429 &frev, &crev, &data_offset)) {
1430 igp_info = (union igp_info *)
1431 (mode_info->atom_context->bios + data_offset);
1432 switch (crev) {
1433 case 6:
1434 switch (id) {
1435 case ASIC_INTERNAL_SS_ON_TMDS:
1436 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1437 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1438 break;
1439 case ASIC_INTERNAL_SS_ON_HDMI:
1440 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1441 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1442 break;
1443 case ASIC_INTERNAL_SS_ON_LVDS:
1444 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1445 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1446 break;
1447 }
1448 break;
1449 case 7:
1450 switch (id) {
1451 case ASIC_INTERNAL_SS_ON_TMDS:
1452 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1453 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1454 break;
1455 case ASIC_INTERNAL_SS_ON_HDMI:
1456 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1457 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1458 break;
1459 case ASIC_INTERNAL_SS_ON_LVDS:
1460 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1461 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1462 break;
1463 }
1464 break;
1465 case 8:
1466 switch (id) {
1467 case ASIC_INTERNAL_SS_ON_TMDS:
1468 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1469 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1470 break;
1471 case ASIC_INTERNAL_SS_ON_HDMI:
1472 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1473 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1474 break;
1475 case ASIC_INTERNAL_SS_ON_LVDS:
1476 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1477 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1478 break;
1479 }
1480 break;
1481 default:
1482 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1483 break;
1484 }
1485 if (percentage)
1486 ss->percentage = percentage;
1487 if (rate)
1488 ss->rate = rate;
1489 }
1490 }
1491
1492 union asic_ss_info {
1493 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1494 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1495 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1496 };
1497
1498 union asic_ss_assignment {
1499 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1500 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1501 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1502 };
1503
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1504 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1505 struct radeon_atom_ss *ss,
1506 int id, u32 clock)
1507 {
1508 struct radeon_mode_info *mode_info = &rdev->mode_info;
1509 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1510 uint16_t data_offset, size;
1511 union asic_ss_info *ss_info;
1512 union asic_ss_assignment *ss_assign;
1513 uint8_t frev, crev;
1514 int i, num_indices;
1515
1516 if (id == ASIC_INTERNAL_MEMORY_SS) {
1517 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1518 return false;
1519 }
1520 if (id == ASIC_INTERNAL_ENGINE_SS) {
1521 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1522 return false;
1523 }
1524
1525 memset(ss, 0, sizeof(struct radeon_atom_ss));
1526 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1527 &frev, &crev, &data_offset)) {
1528
1529 ss_info =
1530 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1531
1532 switch (frev) {
1533 case 1:
1534 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1535 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1536
1537 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1538 for (i = 0; i < num_indices; i++) {
1539 if ((ss_assign->v1.ucClockIndication == id) &&
1540 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1541 ss->percentage =
1542 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1543 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1544 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1545 ss->percentage_divider = 100;
1546 return true;
1547 }
1548 ss_assign = (union asic_ss_assignment *)
1549 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1550 }
1551 break;
1552 case 2:
1553 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1554 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1555 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1556 for (i = 0; i < num_indices; i++) {
1557 if ((ss_assign->v2.ucClockIndication == id) &&
1558 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1559 ss->percentage =
1560 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1561 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1562 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1563 ss->percentage_divider = 100;
1564 if ((crev == 2) &&
1565 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1566 (id == ASIC_INTERNAL_MEMORY_SS)))
1567 ss->rate /= 100;
1568 return true;
1569 }
1570 ss_assign = (union asic_ss_assignment *)
1571 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1572 }
1573 break;
1574 case 3:
1575 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1576 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1577 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1578 for (i = 0; i < num_indices; i++) {
1579 if ((ss_assign->v3.ucClockIndication == id) &&
1580 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1581 ss->percentage =
1582 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1583 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1584 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1585 if (ss_assign->v3.ucSpreadSpectrumMode &
1586 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1587 ss->percentage_divider = 1000;
1588 else
1589 ss->percentage_divider = 100;
1590 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1591 (id == ASIC_INTERNAL_MEMORY_SS))
1592 ss->rate /= 100;
1593 if (rdev->flags & RADEON_IS_IGP)
1594 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1595 return true;
1596 }
1597 ss_assign = (union asic_ss_assignment *)
1598 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1599 }
1600 break;
1601 default:
1602 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1603 break;
1604 }
1605
1606 }
1607 return false;
1608 }
1609
1610 union lvds_info {
1611 struct _ATOM_LVDS_INFO info;
1612 struct _ATOM_LVDS_INFO_V12 info_12;
1613 };
1614
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1615 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1616 radeon_encoder
1617 *encoder)
1618 {
1619 struct drm_device *dev = encoder->base.dev;
1620 struct radeon_device *rdev = dev->dev_private;
1621 struct radeon_mode_info *mode_info = &rdev->mode_info;
1622 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1623 uint16_t data_offset, misc;
1624 union lvds_info *lvds_info;
1625 uint8_t frev, crev;
1626 struct radeon_encoder_atom_dig *lvds = NULL;
1627 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1628
1629 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1630 &frev, &crev, &data_offset)) {
1631 lvds_info =
1632 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1633 lvds =
1634 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1635
1636 if (!lvds)
1637 return NULL;
1638
1639 lvds->native_mode.clock =
1640 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1641 lvds->native_mode.hdisplay =
1642 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1643 lvds->native_mode.vdisplay =
1644 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1645 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1646 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1647 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1648 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1649 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1650 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1651 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1652 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1653 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1654 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1655 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1656 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1657 lvds->panel_pwr_delay =
1658 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1659 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1660
1661 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1662 if (misc & ATOM_VSYNC_POLARITY)
1663 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1664 if (misc & ATOM_HSYNC_POLARITY)
1665 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1666 if (misc & ATOM_COMPOSITESYNC)
1667 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1668 if (misc & ATOM_INTERLACE)
1669 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1670 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1671 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1672
1673 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1674 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1675
1676 /* set crtc values */
1677 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1678
1679 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1680
1681 encoder->native_mode = lvds->native_mode;
1682
1683 if (encoder_enum == 2)
1684 lvds->linkb = true;
1685 else
1686 lvds->linkb = false;
1687
1688 /* parse the lcd record table */
1689 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1690 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1691 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1692 bool bad_record = false;
1693 u8 *record;
1694
1695 if ((frev == 1) && (crev < 2))
1696 /* absolute */
1697 record = (u8 *)(mode_info->atom_context->bios +
1698 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1699 else
1700 /* relative */
1701 record = (u8 *)(mode_info->atom_context->bios +
1702 data_offset +
1703 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1704 while (*record != ATOM_RECORD_END_TYPE) {
1705 switch (*record) {
1706 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1707 record += sizeof(ATOM_PATCH_RECORD_MODE);
1708 break;
1709 case LCD_RTS_RECORD_TYPE:
1710 record += sizeof(ATOM_LCD_RTS_RECORD);
1711 break;
1712 case LCD_CAP_RECORD_TYPE:
1713 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1714 break;
1715 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1716 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1717 if (fake_edid_record->ucFakeEDIDLength) {
1718 struct edid *edid;
1719 int edid_size =
1720 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1721 edid = kmalloc(edid_size, GFP_KERNEL);
1722 if (edid) {
1723 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1724 fake_edid_record->ucFakeEDIDLength);
1725
1726 if (drm_edid_is_valid(edid)) {
1727 rdev->mode_info.bios_hardcoded_edid = edid;
1728 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1729 } else
1730 kfree(edid);
1731 }
1732 }
1733 record += fake_edid_record->ucFakeEDIDLength ?
1734 struct_size(fake_edid_record,
1735 ucFakeEDIDString,
1736 fake_edid_record->ucFakeEDIDLength) :
1737 /* empty fake edid record must be 3 bytes long */
1738 sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
1739 break;
1740 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1741 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1742 lvds->native_mode.width_mm = panel_res_record->usHSize;
1743 lvds->native_mode.height_mm = panel_res_record->usVSize;
1744 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1745 break;
1746 default:
1747 DRM_ERROR("Bad LCD record %d\n", *record);
1748 bad_record = true;
1749 break;
1750 }
1751 if (bad_record)
1752 break;
1753 }
1754 }
1755 }
1756 return lvds;
1757 }
1758
1759 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1760 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1761 {
1762 struct drm_device *dev = encoder->base.dev;
1763 struct radeon_device *rdev = dev->dev_private;
1764 struct radeon_mode_info *mode_info = &rdev->mode_info;
1765 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1766 uint16_t data_offset;
1767 struct _COMPASSIONATE_DATA *dac_info;
1768 uint8_t frev, crev;
1769 uint8_t bg, dac;
1770 struct radeon_encoder_primary_dac *p_dac = NULL;
1771
1772 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1773 &frev, &crev, &data_offset)) {
1774 dac_info = (struct _COMPASSIONATE_DATA *)
1775 (mode_info->atom_context->bios + data_offset);
1776
1777 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1778
1779 if (!p_dac)
1780 return NULL;
1781
1782 bg = dac_info->ucDAC1_BG_Adjustment;
1783 dac = dac_info->ucDAC1_DAC_Adjustment;
1784 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1785
1786 }
1787 return p_dac;
1788 }
1789
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1790 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1791 struct drm_display_mode *mode)
1792 {
1793 struct radeon_mode_info *mode_info = &rdev->mode_info;
1794 ATOM_ANALOG_TV_INFO *tv_info;
1795 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1796 ATOM_DTD_FORMAT *dtd_timings;
1797 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1798 u8 frev, crev;
1799 u16 data_offset, misc;
1800
1801 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1802 &frev, &crev, &data_offset))
1803 return false;
1804
1805 switch (crev) {
1806 case 1:
1807 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1808 if (index >= MAX_SUPPORTED_TV_TIMING)
1809 return false;
1810
1811 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1812 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1813 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1814 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1815 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1816
1817 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1818 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1819 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1820 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1821 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1822
1823 mode->flags = 0;
1824 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1825 if (misc & ATOM_VSYNC_POLARITY)
1826 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1827 if (misc & ATOM_HSYNC_POLARITY)
1828 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1829 if (misc & ATOM_COMPOSITESYNC)
1830 mode->flags |= DRM_MODE_FLAG_CSYNC;
1831 if (misc & ATOM_INTERLACE)
1832 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1833 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1834 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1835
1836 mode->crtc_clock = mode->clock =
1837 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1838
1839 if (index == 1) {
1840 /* PAL timings appear to have wrong values for totals */
1841 mode->crtc_htotal -= 1;
1842 mode->crtc_vtotal -= 1;
1843 }
1844 break;
1845 case 2:
1846 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1847 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1848 return false;
1849
1850 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1851 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1852 le16_to_cpu(dtd_timings->usHBlanking_Time);
1853 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1854 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1855 le16_to_cpu(dtd_timings->usHSyncOffset);
1856 mode->crtc_hsync_end = mode->crtc_hsync_start +
1857 le16_to_cpu(dtd_timings->usHSyncWidth);
1858
1859 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1860 le16_to_cpu(dtd_timings->usVBlanking_Time);
1861 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1862 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1863 le16_to_cpu(dtd_timings->usVSyncOffset);
1864 mode->crtc_vsync_end = mode->crtc_vsync_start +
1865 le16_to_cpu(dtd_timings->usVSyncWidth);
1866
1867 mode->flags = 0;
1868 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1869 if (misc & ATOM_VSYNC_POLARITY)
1870 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1871 if (misc & ATOM_HSYNC_POLARITY)
1872 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1873 if (misc & ATOM_COMPOSITESYNC)
1874 mode->flags |= DRM_MODE_FLAG_CSYNC;
1875 if (misc & ATOM_INTERLACE)
1876 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1877 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1878 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1879
1880 mode->crtc_clock = mode->clock =
1881 le16_to_cpu(dtd_timings->usPixClk) * 10;
1882 break;
1883 }
1884 return true;
1885 }
1886
1887 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1888 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1889 {
1890 struct radeon_mode_info *mode_info = &rdev->mode_info;
1891 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1892 uint16_t data_offset;
1893 uint8_t frev, crev;
1894 struct _ATOM_ANALOG_TV_INFO *tv_info;
1895 enum radeon_tv_std tv_std = TV_STD_NTSC;
1896
1897 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1898 &frev, &crev, &data_offset)) {
1899
1900 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1901 (mode_info->atom_context->bios + data_offset);
1902
1903 switch (tv_info->ucTV_BootUpDefaultStandard) {
1904 case ATOM_TV_NTSC:
1905 tv_std = TV_STD_NTSC;
1906 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1907 break;
1908 case ATOM_TV_NTSCJ:
1909 tv_std = TV_STD_NTSC_J;
1910 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1911 break;
1912 case ATOM_TV_PAL:
1913 tv_std = TV_STD_PAL;
1914 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1915 break;
1916 case ATOM_TV_PALM:
1917 tv_std = TV_STD_PAL_M;
1918 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1919 break;
1920 case ATOM_TV_PALN:
1921 tv_std = TV_STD_PAL_N;
1922 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1923 break;
1924 case ATOM_TV_PALCN:
1925 tv_std = TV_STD_PAL_CN;
1926 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1927 break;
1928 case ATOM_TV_PAL60:
1929 tv_std = TV_STD_PAL_60;
1930 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1931 break;
1932 case ATOM_TV_SECAM:
1933 tv_std = TV_STD_SECAM;
1934 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1935 break;
1936 default:
1937 tv_std = TV_STD_NTSC;
1938 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1939 break;
1940 }
1941 }
1942 return tv_std;
1943 }
1944
1945 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1946 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1947 {
1948 struct drm_device *dev = encoder->base.dev;
1949 struct radeon_device *rdev = dev->dev_private;
1950 struct radeon_mode_info *mode_info = &rdev->mode_info;
1951 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1952 uint16_t data_offset;
1953 struct _COMPASSIONATE_DATA *dac_info;
1954 uint8_t frev, crev;
1955 uint8_t bg, dac;
1956 struct radeon_encoder_tv_dac *tv_dac = NULL;
1957
1958 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1959 &frev, &crev, &data_offset)) {
1960
1961 dac_info = (struct _COMPASSIONATE_DATA *)
1962 (mode_info->atom_context->bios + data_offset);
1963
1964 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1965
1966 if (!tv_dac)
1967 return NULL;
1968
1969 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1970 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1971 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1972
1973 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1974 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1975 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1976
1977 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1978 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1979 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1980
1981 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1982 }
1983 return tv_dac;
1984 }
1985
1986 static const char *thermal_controller_names[] = {
1987 "NONE",
1988 "lm63",
1989 "adm1032",
1990 "adm1030",
1991 "max6649",
1992 "lm63", /* lm64 */
1993 "f75375",
1994 "asc7xxx",
1995 };
1996
1997 static const char *pp_lib_thermal_controller_names[] = {
1998 "NONE",
1999 "lm63",
2000 "adm1032",
2001 "adm1030",
2002 "max6649",
2003 "lm63", /* lm64 */
2004 "f75375",
2005 "RV6xx",
2006 "RV770",
2007 "adt7473",
2008 "NONE",
2009 "External GPIO",
2010 "Evergreen",
2011 "emc2103",
2012 "Sumo",
2013 "Northern Islands",
2014 "Southern Islands",
2015 "lm96163",
2016 "Sea Islands",
2017 };
2018
2019 union power_info {
2020 struct _ATOM_POWERPLAY_INFO info;
2021 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2022 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2023 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2024 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2025 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2026 };
2027
2028 union pplib_clock_info {
2029 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2030 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2031 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2032 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2033 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2034 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2035 };
2036
2037 union pplib_power_state {
2038 struct _ATOM_PPLIB_STATE v1;
2039 struct _ATOM_PPLIB_STATE_V2 v2;
2040 };
2041
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2042 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2043 int state_index,
2044 u32 misc, u32 misc2)
2045 {
2046 rdev->pm.power_state[state_index].misc = misc;
2047 rdev->pm.power_state[state_index].misc2 = misc2;
2048 /* order matters! */
2049 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2050 rdev->pm.power_state[state_index].type =
2051 POWER_STATE_TYPE_POWERSAVE;
2052 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2053 rdev->pm.power_state[state_index].type =
2054 POWER_STATE_TYPE_BATTERY;
2055 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2056 rdev->pm.power_state[state_index].type =
2057 POWER_STATE_TYPE_BATTERY;
2058 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2059 rdev->pm.power_state[state_index].type =
2060 POWER_STATE_TYPE_BALANCED;
2061 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2062 rdev->pm.power_state[state_index].type =
2063 POWER_STATE_TYPE_PERFORMANCE;
2064 rdev->pm.power_state[state_index].flags &=
2065 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2066 }
2067 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2068 rdev->pm.power_state[state_index].type =
2069 POWER_STATE_TYPE_BALANCED;
2070 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2071 rdev->pm.power_state[state_index].type =
2072 POWER_STATE_TYPE_DEFAULT;
2073 rdev->pm.default_power_state_index = state_index;
2074 rdev->pm.power_state[state_index].default_clock_mode =
2075 &rdev->pm.power_state[state_index].clock_info[0];
2076 } else if (state_index == 0) {
2077 rdev->pm.power_state[state_index].clock_info[0].flags |=
2078 RADEON_PM_MODE_NO_DISPLAY;
2079 }
2080 }
2081
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2082 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2083 {
2084 struct radeon_mode_info *mode_info = &rdev->mode_info;
2085 u32 misc, misc2 = 0;
2086 int num_modes = 0, i;
2087 int state_index = 0;
2088 struct radeon_i2c_bus_rec i2c_bus;
2089 union power_info *power_info;
2090 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2091 u16 data_offset;
2092 u8 frev, crev;
2093
2094 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2095 &frev, &crev, &data_offset))
2096 return state_index;
2097 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2098
2099 /* add the i2c bus for thermal/fan chip */
2100 if ((power_info->info.ucOverdriveThermalController > 0) &&
2101 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2102 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2103 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2104 power_info->info.ucOverdriveControllerAddress >> 1);
2105 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2106 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2107 if (rdev->pm.i2c_bus) {
2108 struct i2c_board_info info = { };
2109 const char *name = thermal_controller_names[power_info->info.
2110 ucOverdriveThermalController];
2111 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2112 strscpy(info.type, name, sizeof(info.type));
2113 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2114 }
2115 }
2116 num_modes = power_info->info.ucNumOfPowerModeEntries;
2117 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2118 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2119 if (num_modes == 0)
2120 return state_index;
2121 rdev->pm.power_state = kcalloc(num_modes,
2122 sizeof(struct radeon_power_state),
2123 GFP_KERNEL);
2124 if (!rdev->pm.power_state)
2125 return state_index;
2126 /* last mode is usually default, array is low to high */
2127 for (i = 0; i < num_modes; i++) {
2128 /* avoid memory leaks from invalid modes or unknown frev. */
2129 if (!rdev->pm.power_state[state_index].clock_info) {
2130 rdev->pm.power_state[state_index].clock_info =
2131 kzalloc(sizeof(struct radeon_pm_clock_info),
2132 GFP_KERNEL);
2133 }
2134 if (!rdev->pm.power_state[state_index].clock_info)
2135 goto out;
2136 rdev->pm.power_state[state_index].num_clock_modes = 1;
2137 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2138 switch (frev) {
2139 case 1:
2140 rdev->pm.power_state[state_index].clock_info[0].mclk =
2141 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2142 rdev->pm.power_state[state_index].clock_info[0].sclk =
2143 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2144 /* skip invalid modes */
2145 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2146 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2147 continue;
2148 rdev->pm.power_state[state_index].pcie_lanes =
2149 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2150 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2151 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2152 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2153 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2154 VOLTAGE_GPIO;
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2156 radeon_atombios_lookup_gpio(rdev,
2157 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2158 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2159 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2160 true;
2161 else
2162 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2163 false;
2164 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2165 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2166 VOLTAGE_VDDC;
2167 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2168 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2169 }
2170 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2171 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2172 state_index++;
2173 break;
2174 case 2:
2175 rdev->pm.power_state[state_index].clock_info[0].mclk =
2176 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2177 rdev->pm.power_state[state_index].clock_info[0].sclk =
2178 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2179 /* skip invalid modes */
2180 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2181 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2182 continue;
2183 rdev->pm.power_state[state_index].pcie_lanes =
2184 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2185 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2186 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2187 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2188 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2189 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2190 VOLTAGE_GPIO;
2191 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2192 radeon_atombios_lookup_gpio(rdev,
2193 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2194 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2195 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2196 true;
2197 else
2198 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2199 false;
2200 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2201 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2202 VOLTAGE_VDDC;
2203 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2204 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2205 }
2206 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2207 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2208 state_index++;
2209 break;
2210 case 3:
2211 rdev->pm.power_state[state_index].clock_info[0].mclk =
2212 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2213 rdev->pm.power_state[state_index].clock_info[0].sclk =
2214 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2215 /* skip invalid modes */
2216 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2217 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2218 continue;
2219 rdev->pm.power_state[state_index].pcie_lanes =
2220 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2221 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2222 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2223 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2224 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2225 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2226 VOLTAGE_GPIO;
2227 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2228 radeon_atombios_lookup_gpio(rdev,
2229 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2230 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2231 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2232 true;
2233 else
2234 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2235 false;
2236 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2237 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2238 VOLTAGE_VDDC;
2239 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2240 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2241 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2242 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2243 true;
2244 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2245 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2246 }
2247 }
2248 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2249 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2250 state_index++;
2251 break;
2252 }
2253 }
2254 out:
2255 /* free any unused clock_info allocation. */
2256 if (state_index && state_index < num_modes) {
2257 kfree(rdev->pm.power_state[state_index].clock_info);
2258 rdev->pm.power_state[state_index].clock_info = NULL;
2259 }
2260
2261 /* last mode is usually default */
2262 if (state_index && rdev->pm.default_power_state_index == -1) {
2263 rdev->pm.power_state[state_index - 1].type =
2264 POWER_STATE_TYPE_DEFAULT;
2265 rdev->pm.default_power_state_index = state_index - 1;
2266 rdev->pm.power_state[state_index - 1].default_clock_mode =
2267 &rdev->pm.power_state[state_index - 1].clock_info[0];
2268 rdev->pm.power_state[state_index - 1].flags &=
2269 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2270 rdev->pm.power_state[state_index - 1].misc = 0;
2271 rdev->pm.power_state[state_index - 1].misc2 = 0;
2272 }
2273 return state_index;
2274 }
2275
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2276 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2277 ATOM_PPLIB_THERMALCONTROLLER *controller)
2278 {
2279 struct radeon_i2c_bus_rec i2c_bus;
2280
2281 /* add the i2c bus for thermal/fan chip */
2282 if (controller->ucType > 0) {
2283 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2284 rdev->pm.no_fan = true;
2285 rdev->pm.fan_pulses_per_revolution =
2286 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2287 if (rdev->pm.fan_pulses_per_revolution) {
2288 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2289 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2290 }
2291 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2292 DRM_INFO("Internal thermal controller %s fan control\n",
2293 (controller->ucFanParameters &
2294 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2295 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2296 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2297 DRM_INFO("Internal thermal controller %s fan control\n",
2298 (controller->ucFanParameters &
2299 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2300 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2301 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2302 DRM_INFO("Internal thermal controller %s fan control\n",
2303 (controller->ucFanParameters &
2304 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2305 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2306 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2307 DRM_INFO("Internal thermal controller %s fan control\n",
2308 (controller->ucFanParameters &
2309 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2310 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2311 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2312 DRM_INFO("Internal thermal controller %s fan control\n",
2313 (controller->ucFanParameters &
2314 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2315 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2316 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2317 DRM_INFO("Internal thermal controller %s fan control\n",
2318 (controller->ucFanParameters &
2319 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2320 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2321 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2322 DRM_INFO("Internal thermal controller %s fan control\n",
2323 (controller->ucFanParameters &
2324 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2326 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2327 DRM_INFO("Internal thermal controller %s fan control\n",
2328 (controller->ucFanParameters &
2329 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2330 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2331 } else if (controller->ucType ==
2332 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2333 DRM_INFO("External GPIO thermal controller %s fan control\n",
2334 (controller->ucFanParameters &
2335 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2336 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2337 } else if (controller->ucType ==
2338 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2339 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2340 (controller->ucFanParameters &
2341 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2342 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2343 } else if (controller->ucType ==
2344 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2345 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2346 (controller->ucFanParameters &
2347 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2348 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2349 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2350 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2351 pp_lib_thermal_controller_names[controller->ucType],
2352 controller->ucI2cAddress >> 1,
2353 (controller->ucFanParameters &
2354 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2355 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2356 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2357 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2358 if (rdev->pm.i2c_bus) {
2359 struct i2c_board_info info = { };
2360 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2361 info.addr = controller->ucI2cAddress >> 1;
2362 strscpy(info.type, name, sizeof(info.type));
2363 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2364 }
2365 } else {
2366 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2367 controller->ucType,
2368 controller->ucI2cAddress >> 1,
2369 (controller->ucFanParameters &
2370 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2371 }
2372 }
2373 }
2374
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2375 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2376 u16 *vddc, u16 *vddci, u16 *mvdd)
2377 {
2378 struct radeon_mode_info *mode_info = &rdev->mode_info;
2379 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2380 u8 frev, crev;
2381 u16 data_offset;
2382 union firmware_info *firmware_info;
2383
2384 *vddc = 0;
2385 *vddci = 0;
2386 *mvdd = 0;
2387
2388 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2389 &frev, &crev, &data_offset)) {
2390 firmware_info =
2391 (union firmware_info *)(mode_info->atom_context->bios +
2392 data_offset);
2393 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2394 if ((frev == 2) && (crev >= 2)) {
2395 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2396 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2397 }
2398 }
2399 }
2400
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2401 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2402 int state_index, int mode_index,
2403 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2404 {
2405 int j;
2406 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2407 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2408 u16 vddc, vddci, mvdd;
2409
2410 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2411
2412 rdev->pm.power_state[state_index].misc = misc;
2413 rdev->pm.power_state[state_index].misc2 = misc2;
2414 rdev->pm.power_state[state_index].pcie_lanes =
2415 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2416 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2417 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2418 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2419 rdev->pm.power_state[state_index].type =
2420 POWER_STATE_TYPE_BATTERY;
2421 break;
2422 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2423 rdev->pm.power_state[state_index].type =
2424 POWER_STATE_TYPE_BALANCED;
2425 break;
2426 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2427 rdev->pm.power_state[state_index].type =
2428 POWER_STATE_TYPE_PERFORMANCE;
2429 break;
2430 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2431 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2432 rdev->pm.power_state[state_index].type =
2433 POWER_STATE_TYPE_PERFORMANCE;
2434 break;
2435 }
2436 rdev->pm.power_state[state_index].flags = 0;
2437 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2438 rdev->pm.power_state[state_index].flags |=
2439 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2440 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2441 rdev->pm.power_state[state_index].type =
2442 POWER_STATE_TYPE_DEFAULT;
2443 rdev->pm.default_power_state_index = state_index;
2444 rdev->pm.power_state[state_index].default_clock_mode =
2445 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2446 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2447 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2448 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2449 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2450 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2451 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2452 } else {
2453 u16 max_vddci = 0;
2454
2455 if (ASIC_IS_DCE4(rdev))
2456 radeon_atom_get_max_voltage(rdev,
2457 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2458 &max_vddci);
2459 /* patch the table values with the default sclk/mclk from firmware info */
2460 for (j = 0; j < mode_index; j++) {
2461 rdev->pm.power_state[state_index].clock_info[j].mclk =
2462 rdev->clock.default_mclk;
2463 rdev->pm.power_state[state_index].clock_info[j].sclk =
2464 rdev->clock.default_sclk;
2465 if (vddc)
2466 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2467 vddc;
2468 if (max_vddci)
2469 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2470 max_vddci;
2471 }
2472 }
2473 }
2474 }
2475
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2476 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2477 int state_index, int mode_index,
2478 union pplib_clock_info *clock_info)
2479 {
2480 u32 sclk, mclk;
2481 u16 vddc;
2482
2483 if (rdev->flags & RADEON_IS_IGP) {
2484 if (rdev->family >= CHIP_PALM) {
2485 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2486 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2487 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2488 } else {
2489 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2490 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2491 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2492 }
2493 } else if (rdev->family >= CHIP_BONAIRE) {
2494 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2495 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2496 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2497 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2498 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2499 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2500 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2501 VOLTAGE_NONE;
2502 } else if (rdev->family >= CHIP_TAHITI) {
2503 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2504 sclk |= clock_info->si.ucEngineClockHigh << 16;
2505 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2506 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2507 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2508 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2509 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2510 VOLTAGE_SW;
2511 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2512 le16_to_cpu(clock_info->si.usVDDC);
2513 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2514 le16_to_cpu(clock_info->si.usVDDCI);
2515 } else if (rdev->family >= CHIP_CEDAR) {
2516 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2517 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2518 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2519 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2520 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2521 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2522 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2523 VOLTAGE_SW;
2524 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2525 le16_to_cpu(clock_info->evergreen.usVDDC);
2526 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2527 le16_to_cpu(clock_info->evergreen.usVDDCI);
2528 } else {
2529 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2530 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2531 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2532 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2533 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2534 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2535 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2536 VOLTAGE_SW;
2537 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2538 le16_to_cpu(clock_info->r600.usVDDC);
2539 }
2540
2541 /* patch up vddc if necessary */
2542 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2543 case ATOM_VIRTUAL_VOLTAGE_ID0:
2544 case ATOM_VIRTUAL_VOLTAGE_ID1:
2545 case ATOM_VIRTUAL_VOLTAGE_ID2:
2546 case ATOM_VIRTUAL_VOLTAGE_ID3:
2547 case ATOM_VIRTUAL_VOLTAGE_ID4:
2548 case ATOM_VIRTUAL_VOLTAGE_ID5:
2549 case ATOM_VIRTUAL_VOLTAGE_ID6:
2550 case ATOM_VIRTUAL_VOLTAGE_ID7:
2551 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2552 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2553 &vddc) == 0)
2554 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2555 break;
2556 default:
2557 break;
2558 }
2559
2560 if (rdev->flags & RADEON_IS_IGP) {
2561 /* skip invalid modes */
2562 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2563 return false;
2564 } else {
2565 /* skip invalid modes */
2566 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2567 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2568 return false;
2569 }
2570 return true;
2571 }
2572
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2573 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2574 {
2575 struct radeon_mode_info *mode_info = &rdev->mode_info;
2576 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2577 union pplib_power_state *power_state;
2578 int i, j;
2579 int state_index = 0, mode_index = 0;
2580 union pplib_clock_info *clock_info;
2581 bool valid;
2582 union power_info *power_info;
2583 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2584 u16 data_offset;
2585 u8 frev, crev;
2586
2587 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2588 &frev, &crev, &data_offset))
2589 return state_index;
2590 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2591
2592 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2593 if (power_info->pplib.ucNumStates == 0)
2594 return state_index;
2595 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2596 sizeof(struct radeon_power_state),
2597 GFP_KERNEL);
2598 if (!rdev->pm.power_state)
2599 return state_index;
2600 /* first mode is usually default, followed by low to high */
2601 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2602 mode_index = 0;
2603 power_state = (union pplib_power_state *)
2604 (mode_info->atom_context->bios + data_offset +
2605 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2606 i * power_info->pplib.ucStateEntrySize);
2607 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2608 (mode_info->atom_context->bios + data_offset +
2609 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2610 (power_state->v1.ucNonClockStateIndex *
2611 power_info->pplib.ucNonClockSize));
2612 rdev->pm.power_state[i].clock_info =
2613 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2614 (power_info->pplib.ucStateEntrySize - 1) : 1,
2615 sizeof(struct radeon_pm_clock_info),
2616 GFP_KERNEL);
2617 if (!rdev->pm.power_state[i].clock_info)
2618 return state_index;
2619 if (power_info->pplib.ucStateEntrySize - 1) {
2620 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2621 clock_info = (union pplib_clock_info *)
2622 (mode_info->atom_context->bios + data_offset +
2623 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2624 (power_state->v1.ucClockStateIndices[j] *
2625 power_info->pplib.ucClockInfoSize));
2626 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2627 state_index, mode_index,
2628 clock_info);
2629 if (valid)
2630 mode_index++;
2631 }
2632 } else {
2633 rdev->pm.power_state[state_index].clock_info[0].mclk =
2634 rdev->clock.default_mclk;
2635 rdev->pm.power_state[state_index].clock_info[0].sclk =
2636 rdev->clock.default_sclk;
2637 mode_index++;
2638 }
2639 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2640 if (mode_index) {
2641 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2642 non_clock_info);
2643 state_index++;
2644 }
2645 }
2646 /* if multiple clock modes, mark the lowest as no display */
2647 for (i = 0; i < state_index; i++) {
2648 if (rdev->pm.power_state[i].num_clock_modes > 1)
2649 rdev->pm.power_state[i].clock_info[0].flags |=
2650 RADEON_PM_MODE_NO_DISPLAY;
2651 }
2652 /* first mode is usually default */
2653 if (rdev->pm.default_power_state_index == -1) {
2654 rdev->pm.power_state[0].type =
2655 POWER_STATE_TYPE_DEFAULT;
2656 rdev->pm.default_power_state_index = 0;
2657 rdev->pm.power_state[0].default_clock_mode =
2658 &rdev->pm.power_state[0].clock_info[0];
2659 }
2660 return state_index;
2661 }
2662
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2663 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2664 {
2665 struct radeon_mode_info *mode_info = &rdev->mode_info;
2666 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2667 union pplib_power_state *power_state;
2668 int i, j, non_clock_array_index, clock_array_index;
2669 int state_index = 0, mode_index = 0;
2670 union pplib_clock_info *clock_info;
2671 struct _StateArray *state_array;
2672 struct _ClockInfoArray *clock_info_array;
2673 struct _NonClockInfoArray *non_clock_info_array;
2674 bool valid;
2675 union power_info *power_info;
2676 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2677 u16 data_offset;
2678 u8 frev, crev;
2679 u8 *power_state_offset;
2680
2681 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2682 &frev, &crev, &data_offset))
2683 return state_index;
2684 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2685
2686 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2687 state_array = (struct _StateArray *)
2688 (mode_info->atom_context->bios + data_offset +
2689 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2690 clock_info_array = (struct _ClockInfoArray *)
2691 (mode_info->atom_context->bios + data_offset +
2692 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2693 non_clock_info_array = (struct _NonClockInfoArray *)
2694 (mode_info->atom_context->bios + data_offset +
2695 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2696 if (state_array->ucNumEntries == 0)
2697 return state_index;
2698 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2699 sizeof(struct radeon_power_state),
2700 GFP_KERNEL);
2701 if (!rdev->pm.power_state)
2702 return state_index;
2703 power_state_offset = (u8 *)state_array->states;
2704 for (i = 0; i < state_array->ucNumEntries; i++) {
2705 mode_index = 0;
2706 power_state = (union pplib_power_state *)power_state_offset;
2707 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2708 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2709 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2710 rdev->pm.power_state[i].clock_info =
2711 kcalloc(power_state->v2.ucNumDPMLevels ?
2712 power_state->v2.ucNumDPMLevels : 1,
2713 sizeof(struct radeon_pm_clock_info),
2714 GFP_KERNEL);
2715 if (!rdev->pm.power_state[i].clock_info)
2716 return state_index;
2717 if (power_state->v2.ucNumDPMLevels) {
2718 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2719 clock_array_index = power_state->v2.clockInfoIndex[j];
2720 clock_info = (union pplib_clock_info *)
2721 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2722 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2723 state_index, mode_index,
2724 clock_info);
2725 if (valid)
2726 mode_index++;
2727 }
2728 } else {
2729 rdev->pm.power_state[state_index].clock_info[0].mclk =
2730 rdev->clock.default_mclk;
2731 rdev->pm.power_state[state_index].clock_info[0].sclk =
2732 rdev->clock.default_sclk;
2733 mode_index++;
2734 }
2735 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2736 if (mode_index) {
2737 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2738 non_clock_info);
2739 state_index++;
2740 }
2741 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2742 }
2743 /* if multiple clock modes, mark the lowest as no display */
2744 for (i = 0; i < state_index; i++) {
2745 if (rdev->pm.power_state[i].num_clock_modes > 1)
2746 rdev->pm.power_state[i].clock_info[0].flags |=
2747 RADEON_PM_MODE_NO_DISPLAY;
2748 }
2749 /* first mode is usually default */
2750 if (rdev->pm.default_power_state_index == -1) {
2751 rdev->pm.power_state[0].type =
2752 POWER_STATE_TYPE_DEFAULT;
2753 rdev->pm.default_power_state_index = 0;
2754 rdev->pm.power_state[0].default_clock_mode =
2755 &rdev->pm.power_state[0].clock_info[0];
2756 }
2757 return state_index;
2758 }
2759
radeon_atombios_get_power_modes(struct radeon_device * rdev)2760 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2761 {
2762 struct radeon_mode_info *mode_info = &rdev->mode_info;
2763 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2764 u16 data_offset;
2765 u8 frev, crev;
2766 int state_index = 0;
2767
2768 rdev->pm.default_power_state_index = -1;
2769
2770 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2771 &frev, &crev, &data_offset)) {
2772 switch (frev) {
2773 case 1:
2774 case 2:
2775 case 3:
2776 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2777 break;
2778 case 4:
2779 case 5:
2780 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2781 break;
2782 case 6:
2783 state_index = radeon_atombios_parse_power_table_6(rdev);
2784 break;
2785 default:
2786 break;
2787 }
2788 }
2789
2790 if (state_index == 0) {
2791 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2792 if (rdev->pm.power_state) {
2793 rdev->pm.power_state[0].clock_info =
2794 kcalloc(1,
2795 sizeof(struct radeon_pm_clock_info),
2796 GFP_KERNEL);
2797 if (rdev->pm.power_state[0].clock_info) {
2798 /* add the default mode */
2799 rdev->pm.power_state[state_index].type =
2800 POWER_STATE_TYPE_DEFAULT;
2801 rdev->pm.power_state[state_index].num_clock_modes = 1;
2802 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2803 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2804 rdev->pm.power_state[state_index].default_clock_mode =
2805 &rdev->pm.power_state[state_index].clock_info[0];
2806 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2807 rdev->pm.power_state[state_index].pcie_lanes = 16;
2808 rdev->pm.default_power_state_index = state_index;
2809 rdev->pm.power_state[state_index].flags = 0;
2810 state_index++;
2811 }
2812 }
2813 }
2814
2815 rdev->pm.num_power_states = state_index;
2816
2817 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2818 rdev->pm.current_clock_mode_index = 0;
2819 if (rdev->pm.default_power_state_index >= 0)
2820 rdev->pm.current_vddc =
2821 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2822 else
2823 rdev->pm.current_vddc = 0;
2824 }
2825
2826 union get_clock_dividers {
2827 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2828 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2829 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2830 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2831 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2832 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2833 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2834 };
2835
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2836 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2837 u8 clock_type,
2838 u32 clock,
2839 bool strobe_mode,
2840 struct atom_clock_dividers *dividers)
2841 {
2842 union get_clock_dividers args;
2843 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2844 u8 frev, crev;
2845
2846 memset(&args, 0, sizeof(args));
2847 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2848
2849 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2850 return -EINVAL;
2851
2852 switch (crev) {
2853 case 1:
2854 /* r4xx, r5xx */
2855 args.v1.ucAction = clock_type;
2856 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2857
2858 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2859
2860 dividers->post_div = args.v1.ucPostDiv;
2861 dividers->fb_div = args.v1.ucFbDiv;
2862 dividers->enable_post_div = true;
2863 break;
2864 case 2:
2865 case 3:
2866 case 5:
2867 /* r6xx, r7xx, evergreen, ni, si */
2868 if (rdev->family <= CHIP_RV770) {
2869 args.v2.ucAction = clock_type;
2870 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2871
2872 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2873
2874 dividers->post_div = args.v2.ucPostDiv;
2875 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2876 dividers->ref_div = args.v2.ucAction;
2877 if (rdev->family == CHIP_RV770) {
2878 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2879 true : false;
2880 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2881 } else
2882 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2883 } else {
2884 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2885 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2886
2887 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2888
2889 dividers->post_div = args.v3.ucPostDiv;
2890 dividers->enable_post_div = (args.v3.ucCntlFlag &
2891 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2892 dividers->enable_dithen = (args.v3.ucCntlFlag &
2893 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2894 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2895 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2896 dividers->ref_div = args.v3.ucRefDiv;
2897 dividers->vco_mode = (args.v3.ucCntlFlag &
2898 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2899 } else {
2900 /* for SI we use ComputeMemoryClockParam for memory plls */
2901 if (rdev->family >= CHIP_TAHITI)
2902 return -EINVAL;
2903 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2904 if (strobe_mode)
2905 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2906
2907 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2908
2909 dividers->post_div = args.v5.ucPostDiv;
2910 dividers->enable_post_div = (args.v5.ucCntlFlag &
2911 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2912 dividers->enable_dithen = (args.v5.ucCntlFlag &
2913 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2914 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2915 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2916 dividers->ref_div = args.v5.ucRefDiv;
2917 dividers->vco_mode = (args.v5.ucCntlFlag &
2918 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2919 }
2920 }
2921 break;
2922 case 4:
2923 /* fusion */
2924 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2925
2926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2927
2928 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2929 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2930 break;
2931 case 6:
2932 /* CI */
2933 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2934 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2935 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2936
2937 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2938
2939 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2940 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2941 dividers->ref_div = args.v6_out.ucPllRefDiv;
2942 dividers->post_div = args.v6_out.ucPllPostDiv;
2943 dividers->flags = args.v6_out.ucPllCntlFlag;
2944 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2945 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2946 break;
2947 default:
2948 return -EINVAL;
2949 }
2950 return 0;
2951 }
2952
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2953 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2954 u32 clock,
2955 bool strobe_mode,
2956 struct atom_mpll_param *mpll_param)
2957 {
2958 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2959 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2960 u8 frev, crev;
2961
2962 memset(&args, 0, sizeof(args));
2963 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2964
2965 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2966 return -EINVAL;
2967
2968 switch (frev) {
2969 case 2:
2970 switch (crev) {
2971 case 1:
2972 /* SI */
2973 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2974 args.ucInputFlag = 0;
2975 if (strobe_mode)
2976 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2977
2978 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2979
2980 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2981 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2982 mpll_param->post_div = args.ucPostDiv;
2983 mpll_param->dll_speed = args.ucDllSpeed;
2984 mpll_param->bwcntl = args.ucBWCntl;
2985 mpll_param->vco_mode =
2986 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2987 mpll_param->yclk_sel =
2988 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2989 mpll_param->qdr =
2990 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2991 mpll_param->half_rate =
2992 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2993 break;
2994 default:
2995 return -EINVAL;
2996 }
2997 break;
2998 default:
2999 return -EINVAL;
3000 }
3001 return 0;
3002 }
3003
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)3004 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3005 {
3006 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3007 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3008
3009 args.ucEnable = enable;
3010
3011 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3012 }
3013
radeon_atom_get_engine_clock(struct radeon_device * rdev)3014 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3015 {
3016 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3017 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3018
3019 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3020 return le32_to_cpu(args.ulReturnEngineClock);
3021 }
3022
radeon_atom_get_memory_clock(struct radeon_device * rdev)3023 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3024 {
3025 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3026 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3027
3028 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3029 return le32_to_cpu(args.ulReturnMemoryClock);
3030 }
3031
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)3032 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3033 uint32_t eng_clock)
3034 {
3035 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3036 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3037
3038 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3039
3040 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3041 }
3042
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)3043 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3044 uint32_t mem_clock)
3045 {
3046 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3047 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3048
3049 if (rdev->flags & RADEON_IS_IGP)
3050 return;
3051
3052 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3053
3054 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3055 }
3056
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3057 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3058 u32 eng_clock, u32 mem_clock)
3059 {
3060 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3061 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3062 u32 tmp;
3063
3064 memset(&args, 0, sizeof(args));
3065
3066 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3067 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3068
3069 args.ulTargetEngineClock = cpu_to_le32(tmp);
3070 if (mem_clock)
3071 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3072
3073 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3074 }
3075
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3076 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3077 u32 mem_clock)
3078 {
3079 u32 args;
3080 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3081
3082 args = cpu_to_le32(mem_clock); /* 10 khz */
3083
3084 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3085 }
3086
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3087 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3088 u32 mem_clock)
3089 {
3090 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3091 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3092 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3093
3094 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3095
3096 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3097 }
3098
3099 union set_voltage {
3100 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3101 struct _SET_VOLTAGE_PARAMETERS v1;
3102 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3103 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3104 };
3105
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3106 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3107 {
3108 union set_voltage args;
3109 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3110 u8 frev, crev, volt_index = voltage_level;
3111
3112 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3113 return;
3114
3115 /* 0xff01 is a flag rather then an actual voltage */
3116 if (voltage_level == 0xff01)
3117 return;
3118
3119 switch (crev) {
3120 case 1:
3121 args.v1.ucVoltageType = voltage_type;
3122 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3123 args.v1.ucVoltageIndex = volt_index;
3124 break;
3125 case 2:
3126 args.v2.ucVoltageType = voltage_type;
3127 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3128 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3129 break;
3130 case 3:
3131 args.v3.ucVoltageType = voltage_type;
3132 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3133 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3134 break;
3135 default:
3136 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3137 return;
3138 }
3139
3140 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3141 }
3142
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3143 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3144 u16 voltage_id, u16 *voltage)
3145 {
3146 union set_voltage args;
3147 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3148 u8 frev, crev;
3149
3150 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3151 return -EINVAL;
3152
3153 switch (crev) {
3154 case 1:
3155 return -EINVAL;
3156 case 2:
3157 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3158 args.v2.ucVoltageMode = 0;
3159 args.v2.usVoltageLevel = 0;
3160
3161 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3162
3163 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3164 break;
3165 case 3:
3166 args.v3.ucVoltageType = voltage_type;
3167 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3168 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3169
3170 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3171
3172 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3173 break;
3174 default:
3175 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3176 return -EINVAL;
3177 }
3178
3179 return 0;
3180 }
3181
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3182 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3183 u16 *voltage,
3184 u16 leakage_idx)
3185 {
3186 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3187 }
3188
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3189 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3190 u16 *leakage_id)
3191 {
3192 union set_voltage args;
3193 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3194 u8 frev, crev;
3195
3196 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3197 return -EINVAL;
3198
3199 switch (crev) {
3200 case 3:
3201 case 4:
3202 args.v3.ucVoltageType = 0;
3203 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3204 args.v3.usVoltageLevel = 0;
3205
3206 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3207
3208 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3209 break;
3210 default:
3211 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3212 return -EINVAL;
3213 }
3214
3215 return 0;
3216 }
3217
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3218 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3219 u16 *vddc, u16 *vddci,
3220 u16 virtual_voltage_id,
3221 u16 vbios_voltage_id)
3222 {
3223 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3224 u8 frev, crev;
3225 u16 data_offset, size;
3226 int i, j;
3227 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3228 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3229
3230 *vddc = 0;
3231 *vddci = 0;
3232
3233 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3234 &frev, &crev, &data_offset))
3235 return -EINVAL;
3236
3237 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3238 (rdev->mode_info.atom_context->bios + data_offset);
3239
3240 switch (frev) {
3241 case 1:
3242 return -EINVAL;
3243 case 2:
3244 switch (crev) {
3245 case 1:
3246 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3247 return -EINVAL;
3248 leakage_bin = (u16 *)
3249 (rdev->mode_info.atom_context->bios + data_offset +
3250 le16_to_cpu(profile->usLeakageBinArrayOffset));
3251 vddc_id_buf = (u16 *)
3252 (rdev->mode_info.atom_context->bios + data_offset +
3253 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3254 vddc_buf = (u16 *)
3255 (rdev->mode_info.atom_context->bios + data_offset +
3256 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3257 vddci_id_buf = (u16 *)
3258 (rdev->mode_info.atom_context->bios + data_offset +
3259 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3260 vddci_buf = (u16 *)
3261 (rdev->mode_info.atom_context->bios + data_offset +
3262 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3263
3264 if (profile->ucElbVDDC_Num > 0) {
3265 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3266 if (vddc_id_buf[i] == virtual_voltage_id) {
3267 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3268 if (vbios_voltage_id <= leakage_bin[j]) {
3269 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3270 break;
3271 }
3272 }
3273 break;
3274 }
3275 }
3276 }
3277 if (profile->ucElbVDDCI_Num > 0) {
3278 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3279 if (vddci_id_buf[i] == virtual_voltage_id) {
3280 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3281 if (vbios_voltage_id <= leakage_bin[j]) {
3282 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3283 break;
3284 }
3285 }
3286 break;
3287 }
3288 }
3289 }
3290 break;
3291 default:
3292 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3293 return -EINVAL;
3294 }
3295 break;
3296 default:
3297 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3298 return -EINVAL;
3299 }
3300
3301 return 0;
3302 }
3303
3304 union get_voltage_info {
3305 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3306 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3307 };
3308
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3309 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3310 u16 virtual_voltage_id,
3311 u16 *voltage)
3312 {
3313 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3314 u32 entry_id;
3315 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3316 union get_voltage_info args;
3317
3318 for (entry_id = 0; entry_id < count; entry_id++) {
3319 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3320 virtual_voltage_id)
3321 break;
3322 }
3323
3324 if (entry_id >= count)
3325 return -EINVAL;
3326
3327 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3328 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3329 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3330 args.in.ulSCLKFreq =
3331 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3332
3333 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3334
3335 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3336
3337 return 0;
3338 }
3339
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3340 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3341 u16 voltage_level, u8 voltage_type,
3342 u32 *gpio_value, u32 *gpio_mask)
3343 {
3344 union set_voltage args;
3345 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3346 u8 frev, crev;
3347
3348 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3349 return -EINVAL;
3350
3351 switch (crev) {
3352 case 1:
3353 return -EINVAL;
3354 case 2:
3355 args.v2.ucVoltageType = voltage_type;
3356 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3357 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3358
3359 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3360
3361 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3362
3363 args.v2.ucVoltageType = voltage_type;
3364 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3365 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3366
3367 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3368
3369 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3370 break;
3371 default:
3372 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3373 return -EINVAL;
3374 }
3375
3376 return 0;
3377 }
3378
3379 union voltage_object_info {
3380 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3381 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3382 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3383 };
3384
3385 union voltage_object {
3386 struct _ATOM_VOLTAGE_OBJECT v1;
3387 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3388 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3389 };
3390
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3391 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3392 u8 voltage_type)
3393 {
3394 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3395 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3396 u8 *start = (u8 *)v1;
3397
3398 while (offset < size) {
3399 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3400 if (vo->ucVoltageType == voltage_type)
3401 return vo;
3402 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3403 vo->asFormula.ucNumOfVoltageEntries;
3404 }
3405 return NULL;
3406 }
3407
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3408 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3409 u8 voltage_type)
3410 {
3411 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3412 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3413 u8 *start = (u8 *)v2;
3414
3415 while (offset < size) {
3416 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3417 if (vo->ucVoltageType == voltage_type)
3418 return vo;
3419 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3420 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3421 }
3422 return NULL;
3423 }
3424
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3425 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3426 u8 voltage_type, u8 voltage_mode)
3427 {
3428 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3429 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3430 u8 *start = (u8 *)v3;
3431
3432 while (offset < size) {
3433 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3434 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3435 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3436 return vo;
3437 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3438 }
3439 return NULL;
3440 }
3441
3442 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3443 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3444 u8 voltage_type, u8 voltage_mode)
3445 {
3446 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3447 u8 frev, crev;
3448 u16 data_offset, size;
3449 union voltage_object_info *voltage_info;
3450 union voltage_object *voltage_object = NULL;
3451
3452 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3453 &frev, &crev, &data_offset)) {
3454 voltage_info = (union voltage_object_info *)
3455 (rdev->mode_info.atom_context->bios + data_offset);
3456
3457 switch (frev) {
3458 case 1:
3459 case 2:
3460 switch (crev) {
3461 case 1:
3462 voltage_object = (union voltage_object *)
3463 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3464 if (voltage_object &&
3465 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3466 return true;
3467 break;
3468 case 2:
3469 voltage_object = (union voltage_object *)
3470 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3471 if (voltage_object &&
3472 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3473 return true;
3474 break;
3475 default:
3476 DRM_ERROR("unknown voltage object table\n");
3477 return false;
3478 }
3479 break;
3480 case 3:
3481 switch (crev) {
3482 case 1:
3483 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3484 voltage_type, voltage_mode))
3485 return true;
3486 break;
3487 default:
3488 DRM_ERROR("unknown voltage object table\n");
3489 return false;
3490 }
3491 break;
3492 default:
3493 DRM_ERROR("unknown voltage object table\n");
3494 return false;
3495 }
3496
3497 }
3498 return false;
3499 }
3500
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3501 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3502 u8 voltage_type,
3503 u8 *svd_gpio_id, u8 *svc_gpio_id)
3504 {
3505 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3506 u8 frev, crev;
3507 u16 data_offset, size;
3508 union voltage_object_info *voltage_info;
3509 union voltage_object *voltage_object = NULL;
3510
3511 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3512 &frev, &crev, &data_offset)) {
3513 voltage_info = (union voltage_object_info *)
3514 (rdev->mode_info.atom_context->bios + data_offset);
3515
3516 switch (frev) {
3517 case 3:
3518 switch (crev) {
3519 case 1:
3520 voltage_object = (union voltage_object *)
3521 atom_lookup_voltage_object_v3(&voltage_info->v3,
3522 voltage_type,
3523 VOLTAGE_OBJ_SVID2);
3524 if (voltage_object) {
3525 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3526 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3527 } else {
3528 return -EINVAL;
3529 }
3530 break;
3531 default:
3532 DRM_ERROR("unknown voltage object table\n");
3533 return -EINVAL;
3534 }
3535 break;
3536 default:
3537 DRM_ERROR("unknown voltage object table\n");
3538 return -EINVAL;
3539 }
3540
3541 }
3542 return 0;
3543 }
3544
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3545 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3546 u8 voltage_type, u16 *max_voltage)
3547 {
3548 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3549 u8 frev, crev;
3550 u16 data_offset, size;
3551 union voltage_object_info *voltage_info;
3552 union voltage_object *voltage_object = NULL;
3553
3554 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3555 &frev, &crev, &data_offset)) {
3556 voltage_info = (union voltage_object_info *)
3557 (rdev->mode_info.atom_context->bios + data_offset);
3558
3559 switch (crev) {
3560 case 1:
3561 voltage_object = (union voltage_object *)
3562 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3563 if (voltage_object) {
3564 ATOM_VOLTAGE_FORMULA *formula =
3565 &voltage_object->v1.asFormula;
3566 if (formula->ucFlag & 1)
3567 *max_voltage =
3568 le16_to_cpu(formula->usVoltageBaseLevel) +
3569 formula->ucNumOfVoltageEntries / 2 *
3570 le16_to_cpu(formula->usVoltageStep);
3571 else
3572 *max_voltage =
3573 le16_to_cpu(formula->usVoltageBaseLevel) +
3574 (formula->ucNumOfVoltageEntries - 1) *
3575 le16_to_cpu(formula->usVoltageStep);
3576 return 0;
3577 }
3578 break;
3579 case 2:
3580 voltage_object = (union voltage_object *)
3581 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3582 if (voltage_object) {
3583 ATOM_VOLTAGE_FORMULA_V2 *formula =
3584 &voltage_object->v2.asFormula;
3585 if (formula->ucNumOfVoltageEntries) {
3586 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3587 ((u8 *)&formula->asVIDAdjustEntries[0] +
3588 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3589 *max_voltage =
3590 le16_to_cpu(lut->usVoltageValue);
3591 return 0;
3592 }
3593 }
3594 break;
3595 default:
3596 DRM_ERROR("unknown voltage object table\n");
3597 return -EINVAL;
3598 }
3599
3600 }
3601 return -EINVAL;
3602 }
3603
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3604 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3605 u8 voltage_type, u16 *min_voltage)
3606 {
3607 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3608 u8 frev, crev;
3609 u16 data_offset, size;
3610 union voltage_object_info *voltage_info;
3611 union voltage_object *voltage_object = NULL;
3612
3613 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3614 &frev, &crev, &data_offset)) {
3615 voltage_info = (union voltage_object_info *)
3616 (rdev->mode_info.atom_context->bios + data_offset);
3617
3618 switch (crev) {
3619 case 1:
3620 voltage_object = (union voltage_object *)
3621 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3622 if (voltage_object) {
3623 ATOM_VOLTAGE_FORMULA *formula =
3624 &voltage_object->v1.asFormula;
3625 *min_voltage =
3626 le16_to_cpu(formula->usVoltageBaseLevel);
3627 return 0;
3628 }
3629 break;
3630 case 2:
3631 voltage_object = (union voltage_object *)
3632 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3633 if (voltage_object) {
3634 ATOM_VOLTAGE_FORMULA_V2 *formula =
3635 &voltage_object->v2.asFormula;
3636 if (formula->ucNumOfVoltageEntries) {
3637 *min_voltage =
3638 le16_to_cpu(formula->asVIDAdjustEntries[
3639 0
3640 ].usVoltageValue);
3641 return 0;
3642 }
3643 }
3644 break;
3645 default:
3646 DRM_ERROR("unknown voltage object table\n");
3647 return -EINVAL;
3648 }
3649
3650 }
3651 return -EINVAL;
3652 }
3653
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3654 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3655 u8 voltage_type, u16 *voltage_step)
3656 {
3657 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3658 u8 frev, crev;
3659 u16 data_offset, size;
3660 union voltage_object_info *voltage_info;
3661 union voltage_object *voltage_object = NULL;
3662
3663 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3664 &frev, &crev, &data_offset)) {
3665 voltage_info = (union voltage_object_info *)
3666 (rdev->mode_info.atom_context->bios + data_offset);
3667
3668 switch (crev) {
3669 case 1:
3670 voltage_object = (union voltage_object *)
3671 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3672 if (voltage_object) {
3673 ATOM_VOLTAGE_FORMULA *formula =
3674 &voltage_object->v1.asFormula;
3675 if (formula->ucFlag & 1)
3676 *voltage_step =
3677 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3678 else
3679 *voltage_step =
3680 le16_to_cpu(formula->usVoltageStep);
3681 return 0;
3682 }
3683 break;
3684 case 2:
3685 return -EINVAL;
3686 default:
3687 DRM_ERROR("unknown voltage object table\n");
3688 return -EINVAL;
3689 }
3690
3691 }
3692 return -EINVAL;
3693 }
3694
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3695 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3696 u8 voltage_type,
3697 u16 nominal_voltage,
3698 u16 *true_voltage)
3699 {
3700 u16 min_voltage, max_voltage, voltage_step;
3701
3702 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3703 return -EINVAL;
3704 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3705 return -EINVAL;
3706 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3707 return -EINVAL;
3708
3709 if (nominal_voltage <= min_voltage)
3710 *true_voltage = min_voltage;
3711 else if (nominal_voltage >= max_voltage)
3712 *true_voltage = max_voltage;
3713 else
3714 *true_voltage = min_voltage +
3715 ((nominal_voltage - min_voltage) / voltage_step) *
3716 voltage_step;
3717
3718 return 0;
3719 }
3720
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3721 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3722 u8 voltage_type, u8 voltage_mode,
3723 struct atom_voltage_table *voltage_table)
3724 {
3725 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3726 u8 frev, crev;
3727 u16 data_offset, size;
3728 int i, ret;
3729 union voltage_object_info *voltage_info;
3730 union voltage_object *voltage_object = NULL;
3731
3732 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3733 &frev, &crev, &data_offset)) {
3734 voltage_info = (union voltage_object_info *)
3735 (rdev->mode_info.atom_context->bios + data_offset);
3736
3737 switch (frev) {
3738 case 1:
3739 case 2:
3740 switch (crev) {
3741 case 1:
3742 DRM_ERROR("old table version %d, %d\n", frev, crev);
3743 return -EINVAL;
3744 case 2:
3745 voltage_object = (union voltage_object *)
3746 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3747 if (voltage_object) {
3748 ATOM_VOLTAGE_FORMULA_V2 *formula =
3749 &voltage_object->v2.asFormula;
3750 VOLTAGE_LUT_ENTRY *lut;
3751 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3752 return -EINVAL;
3753 lut = &formula->asVIDAdjustEntries[0];
3754 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3755 voltage_table->entries[i].value =
3756 le16_to_cpu(lut->usVoltageValue);
3757 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3758 voltage_table->entries[i].value,
3759 voltage_type,
3760 &voltage_table->entries[i].smio_low,
3761 &voltage_table->mask_low);
3762 if (ret)
3763 return ret;
3764 lut = (VOLTAGE_LUT_ENTRY *)
3765 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3766 }
3767 voltage_table->count = formula->ucNumOfVoltageEntries;
3768 return 0;
3769 }
3770 break;
3771 default:
3772 DRM_ERROR("unknown voltage object table\n");
3773 return -EINVAL;
3774 }
3775 break;
3776 case 3:
3777 switch (crev) {
3778 case 1:
3779 voltage_object = (union voltage_object *)
3780 atom_lookup_voltage_object_v3(&voltage_info->v3,
3781 voltage_type, voltage_mode);
3782 if (voltage_object) {
3783 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3784 &voltage_object->v3.asGpioVoltageObj;
3785 VOLTAGE_LUT_ENTRY_V2 *lut;
3786 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3787 return -EINVAL;
3788 lut = &gpio->asVolGpioLut[0];
3789 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3790 voltage_table->entries[i].value =
3791 le16_to_cpu(lut->usVoltageValue);
3792 voltage_table->entries[i].smio_low =
3793 le32_to_cpu(lut->ulVoltageId);
3794 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3795 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3796 }
3797 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3798 voltage_table->count = gpio->ucGpioEntryNum;
3799 voltage_table->phase_delay = gpio->ucPhaseDelay;
3800 return 0;
3801 }
3802 break;
3803 default:
3804 DRM_ERROR("unknown voltage object table\n");
3805 return -EINVAL;
3806 }
3807 break;
3808 default:
3809 DRM_ERROR("unknown voltage object table\n");
3810 return -EINVAL;
3811 }
3812 }
3813 return -EINVAL;
3814 }
3815
3816 union vram_info {
3817 struct _ATOM_VRAM_INFO_V3 v1_3;
3818 struct _ATOM_VRAM_INFO_V4 v1_4;
3819 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3820 };
3821
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3822 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3823 u8 module_index, struct atom_memory_info *mem_info)
3824 {
3825 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3826 u8 frev, crev, i;
3827 u16 data_offset, size;
3828 union vram_info *vram_info;
3829
3830 memset(mem_info, 0, sizeof(struct atom_memory_info));
3831
3832 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3833 &frev, &crev, &data_offset)) {
3834 vram_info = (union vram_info *)
3835 (rdev->mode_info.atom_context->bios + data_offset);
3836 switch (frev) {
3837 case 1:
3838 switch (crev) {
3839 case 3:
3840 /* r6xx */
3841 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3842 ATOM_VRAM_MODULE_V3 *vram_module =
3843 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3844
3845 for (i = 0; i < module_index; i++) {
3846 if (le16_to_cpu(vram_module->usSize) == 0)
3847 return -EINVAL;
3848 vram_module = (ATOM_VRAM_MODULE_V3 *)
3849 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3850 }
3851 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3852 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3853 } else
3854 return -EINVAL;
3855 break;
3856 case 4:
3857 /* r7xx, evergreen */
3858 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3859 ATOM_VRAM_MODULE_V4 *vram_module =
3860 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3861
3862 for (i = 0; i < module_index; i++) {
3863 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3864 return -EINVAL;
3865 vram_module = (ATOM_VRAM_MODULE_V4 *)
3866 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3867 }
3868 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3869 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3870 } else
3871 return -EINVAL;
3872 break;
3873 default:
3874 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3875 return -EINVAL;
3876 }
3877 break;
3878 case 2:
3879 switch (crev) {
3880 case 1:
3881 /* ni */
3882 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3883 ATOM_VRAM_MODULE_V7 *vram_module =
3884 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3885
3886 for (i = 0; i < module_index; i++) {
3887 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3888 return -EINVAL;
3889 vram_module = (ATOM_VRAM_MODULE_V7 *)
3890 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3891 }
3892 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3893 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3894 } else
3895 return -EINVAL;
3896 break;
3897 default:
3898 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3899 return -EINVAL;
3900 }
3901 break;
3902 default:
3903 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3904 return -EINVAL;
3905 }
3906 return 0;
3907 }
3908 return -EINVAL;
3909 }
3910
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3911 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3912 bool gddr5, u8 module_index,
3913 struct atom_memory_clock_range_table *mclk_range_table)
3914 {
3915 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3916 u8 frev, crev, i;
3917 u16 data_offset, size;
3918 union vram_info *vram_info;
3919 u32 mem_timing_size = gddr5 ?
3920 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3921
3922 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3923
3924 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3925 &frev, &crev, &data_offset)) {
3926 vram_info = (union vram_info *)
3927 (rdev->mode_info.atom_context->bios + data_offset);
3928 switch (frev) {
3929 case 1:
3930 switch (crev) {
3931 case 3:
3932 DRM_ERROR("old table version %d, %d\n", frev, crev);
3933 return -EINVAL;
3934 case 4:
3935 /* r7xx, evergreen */
3936 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3937 ATOM_VRAM_MODULE_V4 *vram_module =
3938 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3939 ATOM_MEMORY_TIMING_FORMAT *format;
3940
3941 for (i = 0; i < module_index; i++) {
3942 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3943 return -EINVAL;
3944 vram_module = (ATOM_VRAM_MODULE_V4 *)
3945 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3946 }
3947 mclk_range_table->num_entries = (u8)
3948 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3949 mem_timing_size);
3950 format = &vram_module->asMemTiming[0];
3951 for (i = 0; i < mclk_range_table->num_entries; i++) {
3952 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3953 format = (ATOM_MEMORY_TIMING_FORMAT *)
3954 ((u8 *)format + mem_timing_size);
3955 }
3956 } else
3957 return -EINVAL;
3958 break;
3959 default:
3960 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3961 return -EINVAL;
3962 }
3963 break;
3964 case 2:
3965 DRM_ERROR("new table version %d, %d\n", frev, crev);
3966 return -EINVAL;
3967 default:
3968 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3969 return -EINVAL;
3970 }
3971 return 0;
3972 }
3973 return -EINVAL;
3974 }
3975
3976 #define MEM_ID_MASK 0xff000000
3977 #define MEM_ID_SHIFT 24
3978 #define CLOCK_RANGE_MASK 0x00ffffff
3979 #define CLOCK_RANGE_SHIFT 0
3980 #define LOW_NIBBLE_MASK 0xf
3981 #define DATA_EQU_PREV 0
3982 #define DATA_FROM_TABLE 4
3983
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3984 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3985 u8 module_index,
3986 struct atom_mc_reg_table *reg_table)
3987 {
3988 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3989 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3990 u32 i = 0, j;
3991 u16 data_offset, size;
3992 union vram_info *vram_info;
3993
3994 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3995
3996 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3997 &frev, &crev, &data_offset)) {
3998 vram_info = (union vram_info *)
3999 (rdev->mode_info.atom_context->bios + data_offset);
4000 switch (frev) {
4001 case 1:
4002 DRM_ERROR("old table version %d, %d\n", frev, crev);
4003 return -EINVAL;
4004 case 2:
4005 switch (crev) {
4006 case 1:
4007 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4008 ATOM_INIT_REG_BLOCK *reg_block =
4009 (ATOM_INIT_REG_BLOCK *)
4010 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4011 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4012 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4013 ((u8 *)reg_block + (2 * sizeof(u16)) +
4014 le16_to_cpu(reg_block->usRegIndexTblSize));
4015 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4016 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4017 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4018 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4019 return -EINVAL;
4020 while (i < num_entries) {
4021 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4022 break;
4023 reg_table->mc_reg_address[i].s1 =
4024 (u16)(le16_to_cpu(format->usRegIndex));
4025 reg_table->mc_reg_address[i].pre_reg_data =
4026 (u8)(format->ucPreRegDataLength);
4027 i++;
4028 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4029 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4030 }
4031 reg_table->last = i;
4032 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4033 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4034 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4035 >> MEM_ID_SHIFT);
4036 if (module_index == t_mem_id) {
4037 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4038 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4039 >> CLOCK_RANGE_SHIFT);
4040 for (i = 0, j = 1; i < reg_table->last; i++) {
4041 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4042 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4043 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4044 j++;
4045 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4046 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4047 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4048 }
4049 }
4050 num_ranges++;
4051 }
4052 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4053 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4054 }
4055 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4056 return -EINVAL;
4057 reg_table->num_entries = num_ranges;
4058 } else
4059 return -EINVAL;
4060 break;
4061 default:
4062 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4063 return -EINVAL;
4064 }
4065 break;
4066 default:
4067 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4068 return -EINVAL;
4069 }
4070 return 0;
4071 }
4072 return -EINVAL;
4073 }
4074
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4075 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4076 {
4077 struct radeon_device *rdev = dev->dev_private;
4078 uint32_t bios_2_scratch, bios_6_scratch;
4079
4080 if (rdev->family >= CHIP_R600) {
4081 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4082 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4083 } else {
4084 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4085 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4086 }
4087
4088 /* let the bios control the backlight */
4089 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4090
4091 /* tell the bios not to handle mode switching */
4092 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4093
4094 /* clear the vbios dpms state */
4095 if (ASIC_IS_DCE4(rdev))
4096 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4097
4098 if (rdev->family >= CHIP_R600) {
4099 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4100 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4101 } else {
4102 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4103 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4104 }
4105
4106 }
4107
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4108 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4109 {
4110 uint32_t scratch_reg;
4111 int i;
4112
4113 if (rdev->family >= CHIP_R600)
4114 scratch_reg = R600_BIOS_0_SCRATCH;
4115 else
4116 scratch_reg = RADEON_BIOS_0_SCRATCH;
4117
4118 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4119 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4120 }
4121
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4122 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4123 {
4124 uint32_t scratch_reg;
4125 int i;
4126
4127 if (rdev->family >= CHIP_R600)
4128 scratch_reg = R600_BIOS_0_SCRATCH;
4129 else
4130 scratch_reg = RADEON_BIOS_0_SCRATCH;
4131
4132 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4133 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4134 }
4135
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4136 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4137 {
4138 struct drm_device *dev = encoder->dev;
4139 struct radeon_device *rdev = dev->dev_private;
4140 uint32_t bios_6_scratch;
4141
4142 if (rdev->family >= CHIP_R600)
4143 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4144 else
4145 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4146
4147 if (lock) {
4148 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4149 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4150 } else {
4151 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4152 bios_6_scratch |= ATOM_S6_ACC_MODE;
4153 }
4154
4155 if (rdev->family >= CHIP_R600)
4156 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4157 else
4158 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4159 }
4160
4161 /* at some point we may want to break this out into individual functions */
4162 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4163 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4164 struct drm_encoder *encoder,
4165 bool connected)
4166 {
4167 struct drm_device *dev = connector->dev;
4168 struct radeon_device *rdev = dev->dev_private;
4169 struct radeon_connector *radeon_connector =
4170 to_radeon_connector(connector);
4171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4172 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4173
4174 if (rdev->family >= CHIP_R600) {
4175 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4176 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4177 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4178 } else {
4179 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4180 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4181 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4182 }
4183
4184 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4185 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4186 if (connected) {
4187 DRM_DEBUG_KMS("TV1 connected\n");
4188 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4189 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4190 } else {
4191 DRM_DEBUG_KMS("TV1 disconnected\n");
4192 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4193 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4194 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4195 }
4196 }
4197 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4198 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4199 if (connected) {
4200 DRM_DEBUG_KMS("CV connected\n");
4201 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4202 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4203 } else {
4204 DRM_DEBUG_KMS("CV disconnected\n");
4205 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4206 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4207 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4208 }
4209 }
4210 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4211 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4212 if (connected) {
4213 DRM_DEBUG_KMS("LCD1 connected\n");
4214 bios_0_scratch |= ATOM_S0_LCD1;
4215 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4216 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4217 } else {
4218 DRM_DEBUG_KMS("LCD1 disconnected\n");
4219 bios_0_scratch &= ~ATOM_S0_LCD1;
4220 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4221 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4222 }
4223 }
4224 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4225 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4226 if (connected) {
4227 DRM_DEBUG_KMS("CRT1 connected\n");
4228 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4229 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4230 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4231 } else {
4232 DRM_DEBUG_KMS("CRT1 disconnected\n");
4233 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4234 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4235 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4236 }
4237 }
4238 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4239 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4240 if (connected) {
4241 DRM_DEBUG_KMS("CRT2 connected\n");
4242 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4243 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4244 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4245 } else {
4246 DRM_DEBUG_KMS("CRT2 disconnected\n");
4247 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4248 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4249 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4250 }
4251 }
4252 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4253 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4254 if (connected) {
4255 DRM_DEBUG_KMS("DFP1 connected\n");
4256 bios_0_scratch |= ATOM_S0_DFP1;
4257 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4258 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4259 } else {
4260 DRM_DEBUG_KMS("DFP1 disconnected\n");
4261 bios_0_scratch &= ~ATOM_S0_DFP1;
4262 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4263 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4264 }
4265 }
4266 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4267 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4268 if (connected) {
4269 DRM_DEBUG_KMS("DFP2 connected\n");
4270 bios_0_scratch |= ATOM_S0_DFP2;
4271 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4272 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4273 } else {
4274 DRM_DEBUG_KMS("DFP2 disconnected\n");
4275 bios_0_scratch &= ~ATOM_S0_DFP2;
4276 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4277 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4278 }
4279 }
4280 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4281 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4282 if (connected) {
4283 DRM_DEBUG_KMS("DFP3 connected\n");
4284 bios_0_scratch |= ATOM_S0_DFP3;
4285 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4286 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4287 } else {
4288 DRM_DEBUG_KMS("DFP3 disconnected\n");
4289 bios_0_scratch &= ~ATOM_S0_DFP3;
4290 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4291 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4292 }
4293 }
4294 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4295 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4296 if (connected) {
4297 DRM_DEBUG_KMS("DFP4 connected\n");
4298 bios_0_scratch |= ATOM_S0_DFP4;
4299 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4300 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4301 } else {
4302 DRM_DEBUG_KMS("DFP4 disconnected\n");
4303 bios_0_scratch &= ~ATOM_S0_DFP4;
4304 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4305 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4306 }
4307 }
4308 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4309 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4310 if (connected) {
4311 DRM_DEBUG_KMS("DFP5 connected\n");
4312 bios_0_scratch |= ATOM_S0_DFP5;
4313 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4314 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4315 } else {
4316 DRM_DEBUG_KMS("DFP5 disconnected\n");
4317 bios_0_scratch &= ~ATOM_S0_DFP5;
4318 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4319 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4320 }
4321 }
4322 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4323 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4324 if (connected) {
4325 DRM_DEBUG_KMS("DFP6 connected\n");
4326 bios_0_scratch |= ATOM_S0_DFP6;
4327 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4328 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4329 } else {
4330 DRM_DEBUG_KMS("DFP6 disconnected\n");
4331 bios_0_scratch &= ~ATOM_S0_DFP6;
4332 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4333 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4334 }
4335 }
4336
4337 if (rdev->family >= CHIP_R600) {
4338 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4339 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4340 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4341 } else {
4342 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4343 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4344 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4345 }
4346 }
4347
4348 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4349 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4350 {
4351 struct drm_device *dev = encoder->dev;
4352 struct radeon_device *rdev = dev->dev_private;
4353 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4354 uint32_t bios_3_scratch;
4355
4356 if (ASIC_IS_DCE4(rdev))
4357 return;
4358
4359 if (rdev->family >= CHIP_R600)
4360 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4361 else
4362 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4363
4364 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4365 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4366 bios_3_scratch |= (crtc << 18);
4367 }
4368 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4369 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4370 bios_3_scratch |= (crtc << 24);
4371 }
4372 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4373 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4374 bios_3_scratch |= (crtc << 16);
4375 }
4376 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4377 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4378 bios_3_scratch |= (crtc << 20);
4379 }
4380 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4381 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4382 bios_3_scratch |= (crtc << 17);
4383 }
4384 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4385 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4386 bios_3_scratch |= (crtc << 19);
4387 }
4388 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4389 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4390 bios_3_scratch |= (crtc << 23);
4391 }
4392 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4393 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4394 bios_3_scratch |= (crtc << 25);
4395 }
4396
4397 if (rdev->family >= CHIP_R600)
4398 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4399 else
4400 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4401 }
4402
4403 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4404 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4405 {
4406 struct drm_device *dev = encoder->dev;
4407 struct radeon_device *rdev = dev->dev_private;
4408 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4409 uint32_t bios_2_scratch;
4410
4411 if (ASIC_IS_DCE4(rdev))
4412 return;
4413
4414 if (rdev->family >= CHIP_R600)
4415 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4416 else
4417 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4418
4419 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4420 if (on)
4421 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4422 else
4423 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4424 }
4425 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4426 if (on)
4427 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4428 else
4429 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4430 }
4431 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4432 if (on)
4433 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4434 else
4435 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4436 }
4437 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4438 if (on)
4439 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4440 else
4441 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4442 }
4443 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4444 if (on)
4445 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4446 else
4447 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4448 }
4449 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4450 if (on)
4451 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4452 else
4453 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4454 }
4455 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4456 if (on)
4457 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4458 else
4459 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4460 }
4461 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4462 if (on)
4463 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4464 else
4465 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4466 }
4467 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4468 if (on)
4469 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4470 else
4471 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4472 }
4473 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4474 if (on)
4475 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4476 else
4477 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4478 }
4479
4480 if (rdev->family >= CHIP_R600)
4481 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4482 else
4483 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4484 }
4485