1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8 #include <asm/byteorder.h> 9 10 #define RTL8XXXU_DEBUG_REG_WRITE 0x01 11 #define RTL8XXXU_DEBUG_REG_READ 0x02 12 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 13 #define RTL8XXXU_DEBUG_RFREG_READ 0x08 14 #define RTL8XXXU_DEBUG_CHANNEL 0x10 15 #define RTL8XXXU_DEBUG_TX 0x20 16 #define RTL8XXXU_DEBUG_TX_DUMP 0x40 17 #define RTL8XXXU_DEBUG_RX 0x80 18 #define RTL8XXXU_DEBUG_RX_DUMP 0x100 19 #define RTL8XXXU_DEBUG_USB 0x200 20 #define RTL8XXXU_DEBUG_KEY 0x400 21 #define RTL8XXXU_DEBUG_H2C 0x800 22 #define RTL8XXXU_DEBUG_ACTION 0x1000 23 #define RTL8XXXU_DEBUG_EFUSE 0x2000 24 #define RTL8XXXU_DEBUG_INTERRUPT 0x4000 25 26 #define RTW_USB_CONTROL_MSG_TIMEOUT 500 27 #define RTL8XXXU_MAX_REG_POLL 500 28 #define USB_INTR_CONTENT_LENGTH 56 29 30 #define RTL8XXXU_OUT_ENDPOINTS 6 31 32 #define REALTEK_USB_READ 0xc0 33 #define REALTEK_USB_WRITE 0x40 34 #define REALTEK_USB_CMD_REQ 0x05 35 #define REALTEK_USB_CMD_IDX 0x00 36 37 #define TX_TOTAL_PAGE_NUM 0xf8 38 #define TX_TOTAL_PAGE_NUM_8188F 0xf7 39 #define TX_TOTAL_PAGE_NUM_8188E 0xa9 40 #define TX_TOTAL_PAGE_NUM_8192E 0xf3 41 #define TX_TOTAL_PAGE_NUM_8723B 0xf7 42 #define TX_TOTAL_PAGE_NUM_8192F 0xf7 43 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 44 #define TX_PAGE_NUM_PUBQ 0xe7 45 #define TX_PAGE_NUM_HI_PQ 0x0c 46 #define TX_PAGE_NUM_LO_PQ 0x02 47 #define TX_PAGE_NUM_NORM_PQ 0x02 48 49 #define TX_PAGE_NUM_PUBQ_8188F 0xe5 50 #define TX_PAGE_NUM_HI_PQ_8188F 0x0c 51 #define TX_PAGE_NUM_LO_PQ_8188F 0x02 52 #define TX_PAGE_NUM_NORM_PQ_8188F 0x02 53 54 #define TX_PAGE_NUM_PUBQ_8188E 0x47 55 #define TX_PAGE_NUM_HI_PQ_8188E 0x29 56 #define TX_PAGE_NUM_LO_PQ_8188E 0x1c 57 #define TX_PAGE_NUM_NORM_PQ_8188E 0x1c 58 59 #define TX_PAGE_NUM_PUBQ_8192E 0xe7 60 #define TX_PAGE_NUM_HI_PQ_8192E 0x08 61 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c 62 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 63 64 #define TX_PAGE_NUM_PUBQ_8723B 0xe7 65 #define TX_PAGE_NUM_HI_PQ_8723B 0x0c 66 #define TX_PAGE_NUM_LO_PQ_8723B 0x02 67 #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 68 69 #define TX_PAGE_NUM_PUBQ_8192F 0xde 70 #define TX_PAGE_NUM_HI_PQ_8192F 0x08 71 #define TX_PAGE_NUM_LO_PQ_8192F 0x08 72 #define TX_PAGE_NUM_NORM_PQ_8192F 0x08 73 74 #define RTL_FW_PAGE_SIZE 4096 75 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 76 77 #define RTL8723A_CHANNEL_GROUPS 3 78 #define RTL8723A_MAX_RF_PATHS 2 79 #define RTL8723B_CHANNEL_GROUPS 6 80 #define RTL8723B_TX_COUNT 4 81 #define RTL8723B_MAX_RF_PATHS 4 82 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 83 #define RF6052_MAX_TX_PWR 0x3f 84 85 #define EFUSE_MAP_LEN 512 86 #define EFUSE_MAX_SECTION_8723A 64 87 #define EFUSE_REAL_CONTENT_LEN_8723A 512 88 #define EFUSE_BT_MAP_LEN_8723A 1024 89 #define EFUSE_MAX_WORD_UNIT 4 90 #define EFUSE_UNDEFINED 0xff 91 92 enum rtl8xxxu_rtl_chip { 93 RTL8192S = 0x81920, 94 RTL8191S = 0x81910, 95 RTL8192C = 0x8192c, 96 RTL8191C = 0x8191c, 97 RTL8188C = 0x8188c, 98 RTL8188R = 0x81889, 99 RTL8192D = 0x8192d, 100 RTL8723A = 0x8723a, 101 RTL8188E = 0x8188e, 102 RTL8812 = 0x88120, 103 RTL8821 = 0x88210, 104 RTL8192E = 0x8192e, 105 RTL8191E = 0x8191e, 106 RTL8723B = 0x8723b, 107 RTL8814A = 0x8814a, 108 RTL8881A = 0x8881a, 109 RTL8821B = 0x8821b, 110 RTL8822B = 0x8822b, 111 RTL8703B = 0x8703b, 112 RTL8195A = 0x8195a, 113 RTL8188F = 0x8188f, 114 RTL8710B = 0x8710b, 115 RTL8192F = 0x8192f, 116 }; 117 118 enum rtl8xxxu_rx_type { 119 RX_TYPE_DATA_PKT = 0, 120 RX_TYPE_C2H = 1, 121 RX_TYPE_ERROR = -1 122 }; 123 124 enum rtl8xxxu_rx_desc_enc { 125 RX_DESC_ENC_NONE = 0, 126 RX_DESC_ENC_WEP40 = 1, 127 RX_DESC_ENC_TKIP_WO_MIC = 2, 128 RX_DESC_ENC_TKIP_MIC = 3, 129 RX_DESC_ENC_AES = 4, 130 RX_DESC_ENC_WEP104 = 5, 131 }; 132 133 struct rtl8xxxu_rxdesc16 { 134 #ifdef __LITTLE_ENDIAN 135 u32 pktlen:14; 136 u32 crc32:1; 137 u32 icverr:1; 138 u32 drvinfo_sz:4; 139 u32 security:3; 140 u32 qos:1; 141 u32 shift:2; 142 u32 phy_stats:1; 143 u32 swdec:1; 144 u32 ls:1; 145 u32 fs:1; 146 u32 eor:1; 147 u32 own:1; 148 149 u32 macid:5; 150 u32 tid:4; 151 u32 hwrsvd:4; 152 u32 amsdu:1; 153 u32 paggr:1; 154 u32 faggr:1; 155 u32 a1fit:4; 156 u32 a2fit:4; 157 u32 pam:1; 158 u32 pwr:1; 159 u32 md:1; 160 u32 mf:1; 161 u32 type:2; 162 u32 mc:1; 163 u32 bc:1; 164 165 u32 seq:12; 166 u32 frag:4; 167 u32 pkt_cnt:8; 168 u32 reserved:6; 169 u32 nextind:1; 170 u32 reserved0:1; 171 172 u32 rxmcs:6; 173 u32 rxht:1; 174 u32 gf:1; 175 u32 splcp:1; 176 u32 bw:1; 177 u32 htc:1; 178 u32 eosp:1; 179 u32 bssidfit:2; 180 u32 rpt_sel:2; /* 8188e */ 181 u32 reserved1:14; 182 u32 unicastwake:1; 183 u32 magicwake:1; 184 185 u32 pattern0match:1; 186 u32 pattern1match:1; 187 u32 pattern2match:1; 188 u32 pattern3match:1; 189 u32 pattern4match:1; 190 u32 pattern5match:1; 191 u32 pattern6match:1; 192 u32 pattern7match:1; 193 u32 pattern8match:1; 194 u32 pattern9match:1; 195 u32 patternamatch:1; 196 u32 patternbmatch:1; 197 u32 patterncmatch:1; 198 u32 reserved2:19; 199 #else 200 u32 own:1; 201 u32 eor:1; 202 u32 fs:1; 203 u32 ls:1; 204 u32 swdec:1; 205 u32 phy_stats:1; 206 u32 shift:2; 207 u32 qos:1; 208 u32 security:3; 209 u32 drvinfo_sz:4; 210 u32 icverr:1; 211 u32 crc32:1; 212 u32 pktlen:14; 213 214 u32 bc:1; 215 u32 mc:1; 216 u32 type:2; 217 u32 mf:1; 218 u32 md:1; 219 u32 pwr:1; 220 u32 pam:1; 221 u32 a2fit:4; 222 u32 a1fit:4; 223 u32 faggr:1; 224 u32 paggr:1; 225 u32 amsdu:1; 226 u32 hwrsvd:4; 227 u32 tid:4; 228 u32 macid:5; 229 230 u32 reserved0:1; 231 u32 nextind:1; 232 u32 reserved:6; 233 u32 pkt_cnt:8; 234 u32 frag:4; 235 u32 seq:12; 236 237 u32 magicwake:1; 238 u32 unicastwake:1; 239 u32 reserved1:14; 240 u32 rpt_sel:2; /* 8188e */ 241 u32 bssidfit:2; 242 u32 eosp:1; 243 u32 htc:1; 244 u32 bw:1; 245 u32 splcp:1; 246 u32 gf:1; 247 u32 rxht:1; 248 u32 rxmcs:6; 249 250 u32 reserved2:19; 251 u32 patterncmatch:1; 252 u32 patternbmatch:1; 253 u32 patternamatch:1; 254 u32 pattern9match:1; 255 u32 pattern8match:1; 256 u32 pattern7match:1; 257 u32 pattern6match:1; 258 u32 pattern5match:1; 259 u32 pattern4match:1; 260 u32 pattern3match:1; 261 u32 pattern2match:1; 262 u32 pattern1match:1; 263 u32 pattern0match:1; 264 #endif 265 u32 tsfl; 266 #if 0 267 u32 bassn:12; 268 u32 bavld:1; 269 u32 reserved3:19; 270 #endif 271 }; 272 273 struct rtl8xxxu_rxdesc24 { 274 #ifdef __LITTLE_ENDIAN 275 u32 pktlen:14; 276 u32 crc32:1; 277 u32 icverr:1; 278 u32 drvinfo_sz:4; 279 u32 security:3; 280 u32 qos:1; 281 u32 shift:2; 282 u32 phy_stats:1; 283 u32 swdec:1; 284 u32 ls:1; 285 u32 fs:1; 286 u32 eor:1; 287 u32 own:1; 288 289 u32 macid:7; 290 u32 dummy1_0:1; 291 u32 tid:4; 292 u32 dummy1_1:1; 293 u32 amsdu:1; 294 u32 rxid_match:1; 295 u32 paggr:1; 296 u32 a1fit:4; /* 16 */ 297 u32 chkerr:1; 298 u32 ipver:1; 299 u32 tcpudp:1; 300 u32 chkvld:1; 301 u32 pam:1; 302 u32 pwr:1; 303 u32 more_data:1; 304 u32 more_frag:1; 305 u32 type:2; 306 u32 mc:1; 307 u32 bc:1; 308 309 u32 seq:12; 310 u32 frag:4; 311 u32 rx_is_qos:1; /* 16 */ 312 u32 dummy2_0:1; 313 u32 wlanhd_iv_len:6; 314 u32 dummy2_1:4; 315 u32 rpt_sel:1; 316 u32 dummy2_2:3; 317 318 u32 rxmcs:7; 319 u32 dummy3_0:3; 320 u32 htc:1; 321 u32 eosp:1; 322 u32 bssidfit:2; 323 u32 dummy3_1:2; 324 u32 usb_agg_pktnum:8; /* 16 */ 325 u32 dummy3_2:5; 326 u32 pattern_match:1; 327 u32 unicast_match:1; 328 u32 magic_match:1; 329 330 u32 splcp:1; 331 u32 ldcp:1; 332 u32 stbc:1; 333 u32 dummy4_0:1; 334 u32 bw:2; 335 u32 dummy4_1:26; 336 #else 337 u32 own:1; 338 u32 eor:1; 339 u32 fs:1; 340 u32 ls:1; 341 u32 swdec:1; 342 u32 phy_stats:1; 343 u32 shift:2; 344 u32 qos:1; 345 u32 security:3; 346 u32 drvinfo_sz:4; 347 u32 icverr:1; 348 u32 crc32:1; 349 u32 pktlen:14; 350 351 u32 bc:1; 352 u32 mc:1; 353 u32 type:2; 354 u32 mf:1; 355 u32 md:1; 356 u32 pwr:1; 357 u32 pam:1; 358 u32 a2fit:4; 359 u32 a1fit:4; 360 u32 faggr:1; 361 u32 paggr:1; 362 u32 amsdu:1; 363 u32 hwrsvd:4; 364 u32 tid:4; 365 u32 macid:5; 366 367 u32 dummy2_2:3; 368 u32 rpt_sel:1; 369 u32 dummy2_1:4; 370 u32 wlanhd_iv_len:6; 371 u32 dummy2_0:1; 372 u32 rx_is_qos:1; 373 u32 frag:4; /* 16 */ 374 u32 seq:12; 375 376 u32 magic_match:1; 377 u32 unicast_match:1; 378 u32 pattern_match:1; 379 u32 dummy3_2:5; 380 u32 usb_agg_pktnum:8; 381 u32 dummy3_1:2; /* 16 */ 382 u32 bssidfit:2; 383 u32 eosp:1; 384 u32 htc:1; 385 u32 dummy3_0:3; 386 u32 rxmcs:7; 387 388 u32 dumm4_1:26; 389 u32 bw:2; 390 u32 dummy4_0:1; 391 u32 stbc:1; 392 u32 ldcp:1; 393 u32 splcp:1; 394 #endif 395 u32 tsfl; 396 }; 397 398 struct rtl8xxxu_txdesc32 { 399 __le16 pkt_size; 400 u8 pkt_offset; 401 u8 txdw0; 402 __le32 txdw1; 403 __le32 txdw2; 404 __le32 txdw3; 405 __le32 txdw4; 406 __le32 txdw5; 407 __le32 txdw6; 408 __le16 csum; 409 __le16 txdw7; 410 }; 411 412 struct rtl8xxxu_txdesc40 { 413 __le16 pkt_size; 414 u8 pkt_offset; 415 u8 txdw0; 416 __le32 txdw1; 417 __le32 txdw2; 418 __le32 txdw3; 419 __le32 txdw4; 420 __le32 txdw5; 421 __le32 txdw6; 422 __le16 csum; 423 __le16 txdw7; 424 __le32 txdw8; 425 __le32 txdw9; 426 }; 427 428 /* CCK Rates, TxHT = 0 */ 429 #define DESC_RATE_1M 0x00 430 #define DESC_RATE_2M 0x01 431 #define DESC_RATE_5_5M 0x02 432 #define DESC_RATE_11M 0x03 433 434 /* OFDM Rates, TxHT = 0 */ 435 #define DESC_RATE_6M 0x04 436 #define DESC_RATE_9M 0x05 437 #define DESC_RATE_12M 0x06 438 #define DESC_RATE_18M 0x07 439 #define DESC_RATE_24M 0x08 440 #define DESC_RATE_36M 0x09 441 #define DESC_RATE_48M 0x0a 442 #define DESC_RATE_54M 0x0b 443 444 /* MCS Rates, TxHT = 1 */ 445 #define DESC_RATE_MCS0 0x0c 446 #define DESC_RATE_MCS1 0x0d 447 #define DESC_RATE_MCS2 0x0e 448 #define DESC_RATE_MCS3 0x0f 449 #define DESC_RATE_MCS4 0x10 450 #define DESC_RATE_MCS5 0x11 451 #define DESC_RATE_MCS6 0x12 452 #define DESC_RATE_MCS7 0x13 453 #define DESC_RATE_MCS8 0x14 454 #define DESC_RATE_MCS9 0x15 455 #define DESC_RATE_MCS10 0x16 456 #define DESC_RATE_MCS11 0x17 457 #define DESC_RATE_MCS12 0x18 458 #define DESC_RATE_MCS13 0x19 459 #define DESC_RATE_MCS14 0x1a 460 #define DESC_RATE_MCS15 0x1b 461 #define DESC_RATE_MCS15_SG 0x1c 462 #define DESC_RATE_MCS32 0x20 463 464 #define TXDESC_OFFSET_SZ 0 465 #define TXDESC_OFFSET_SHT 16 466 #if 0 467 #define TXDESC_BMC BIT(24) 468 #define TXDESC_LSG BIT(26) 469 #define TXDESC_FSG BIT(27) 470 #define TXDESC_OWN BIT(31) 471 #else 472 #define TXDESC_BROADMULTICAST BIT(0) 473 #define TXDESC_HTC BIT(1) 474 #define TXDESC_LAST_SEGMENT BIT(2) 475 #define TXDESC_FIRST_SEGMENT BIT(3) 476 #define TXDESC_LINIP BIT(4) 477 #define TXDESC_NO_ACM BIT(5) 478 #define TXDESC_GF BIT(6) 479 #define TXDESC_OWN BIT(7) 480 #endif 481 482 /* Word 1 */ 483 /* 484 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 485 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 486 */ 487 #define TXDESC_PKT_OFFSET_SZ 0 488 #define TXDESC32_AGG_ENABLE BIT(5) 489 #define TXDESC32_AGG_BREAK BIT(6) 490 #define TXDESC40_MACID_SHIFT 0 491 #define TXDESC40_MACID_MASK 0x00f0 492 #define TXDESC_QUEUE_SHIFT 8 493 #define TXDESC_QUEUE_MASK 0x1f00 494 #define TXDESC_QUEUE_BK 0x2 495 #define TXDESC_QUEUE_BE 0x0 496 #define TXDESC_QUEUE_VI 0x5 497 #define TXDESC_QUEUE_VO 0x7 498 #define TXDESC_QUEUE_BEACON 0x10 499 #define TXDESC_QUEUE_HIGH 0x11 500 #define TXDESC_QUEUE_MGNT 0x12 501 #define TXDESC_QUEUE_CMD 0x13 502 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 503 #define TXDESC40_RDG_NAV_EXT BIT(13) 504 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 505 #define TXDESC40_PIFS BIT(15) 506 507 #define DESC_RATE_ID_SHIFT 16 508 #define DESC_RATE_ID_MASK 0xf 509 #define TXDESC_NAVUSEHDR BIT(20) 510 #define TXDESC_SEC_RC4 0x00400000 511 #define TXDESC_SEC_AES 0x00c00000 512 #define TXDESC_PKT_OFFSET_SHIFT 26 513 #define TXDESC_AGG_EN BIT(29) 514 #define TXDESC_HWPC BIT(31) 515 516 /* Word 2 */ 517 #define TXDESC40_PAID_SHIFT 0 518 #define TXDESC40_PAID_MASK 0x1ff 519 #define TXDESC40_CCA_RTS_SHIFT 10 520 #define TXDESC40_CCA_RTS_MASK 0xc00 521 #define TXDESC40_AGG_ENABLE BIT(12) 522 #define TXDESC40_RDG_ENABLE BIT(13) 523 #define TXDESC40_AGG_BREAK BIT(16) 524 #define TXDESC40_MORE_FRAG BIT(17) 525 #define TXDESC40_RAW BIT(18) 526 #define TXDESC32_ACK_REPORT BIT(19) 527 #define TXDESC40_SPE_RPT BIT(19) 528 #define TXDESC_AMPDU_DENSITY_SHIFT 20 529 #define TXDESC40_BT_INT BIT(23) 530 #define TXDESC40_GID_SHIFT 24 531 #define TXDESC_ANTENNA_SELECT_A BIT(24) 532 #define TXDESC_ANTENNA_SELECT_B BIT(25) 533 534 /* Word 3 */ 535 #define TXDESC40_USE_DRIVER_RATE BIT(8) 536 #define TXDESC40_CTS_SELF_ENABLE BIT(11) 537 #define TXDESC40_RTS_CTS_ENABLE BIT(12) 538 #define TXDESC40_HW_RTS_ENABLE BIT(13) 539 #define TXDESC32_SEQ_SHIFT 16 540 #define TXDESC32_SEQ_MASK 0x0fff0000 541 542 /* Word 4 */ 543 #define TXDESC32_RTS_RATE_SHIFT 0 544 #define TXDESC32_RTS_RATE_MASK 0x3f 545 #define TXDESC32_QOS BIT(6) 546 #define TXDESC32_HW_SEQ_ENABLE BIT(7) 547 #define TXDESC32_USE_DRIVER_RATE BIT(8) 548 #define TXDESC_DISABLE_DATA_FB BIT(10) 549 #define TXDESC32_CTS_SELF_ENABLE BIT(11) 550 #define TXDESC32_RTS_CTS_ENABLE BIT(12) 551 #define TXDESC32_HW_RTS_ENABLE BIT(13) 552 #define TXDESC32_PT_STAGE_MASK GENMASK(17, 15) 553 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 554 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 555 #define TXDESC32_SHORT_PREAMBLE BIT(24) 556 #define TXDESC_DATA_BW BIT(25) 557 #define TXDESC_RTS_DATA_BW BIT(27) 558 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 559 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 560 #define TXDESC40_DATA_RATE_FB_SHIFT 8 561 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 562 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 563 #define TXDESC40_RETRY_LIMIT_SHIFT 18 564 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 565 #define TXDESC40_RTS_RATE_SHIFT 24 566 #define TXDESC40_RTS_RATE_MASK 0x3f000000 567 568 /* Word 5 */ 569 #define TXDESC40_SHORT_PREAMBLE BIT(4) 570 #define TXDESC32_SHORT_GI BIT(6) 571 #define TXDESC_CCX_TAG BIT(7) 572 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 573 #define TXDESC32_RETRY_LIMIT_SHIFT 18 574 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 575 576 /* Word 6 */ 577 #define TXDESC_MAX_AGG_SHIFT 11 578 #define TXDESC_USB_TX_AGG_SHIT 24 579 580 /* Word 7 */ 581 #define TXDESC_ANTENNA_SELECT_C BIT(29) 582 583 /* Word 8 */ 584 #define TXDESC40_HW_SEQ_ENABLE BIT(15) 585 586 /* Word 9 */ 587 #define TXDESC40_SEQ_SHIFT 12 588 #define TXDESC40_SEQ_MASK 0x00fff000 589 590 struct phy_rx_agc_info { 591 #ifdef __LITTLE_ENDIAN 592 u8 gain:7, trsw:1; 593 #else 594 u8 trsw:1, gain:7; 595 #endif 596 }; 597 598 #define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5) 599 #define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0) 600 601 struct rtl8723au_phy_stats { 602 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 603 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 604 u8 cck_sig_qual_ofdm_pwdb_all; 605 u8 cck_agc_rpt_ofdm_cfosho_a; 606 u8 cck_rpt_b_ofdm_cfosho_b; 607 u8 reserved_1; 608 u8 noise_power_db_msb; 609 s8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 610 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 611 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 612 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 613 u8 noise_power_db_lsb; 614 u8 reserved_2[3]; 615 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 616 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 617 s8 sig_evm; 618 u8 reserved_3; 619 620 #ifdef __LITTLE_ENDIAN 621 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 622 u8 sgi_en:1; 623 u8 rxsc:2; 624 u8 idle_long:1; 625 u8 r_ant_train_en:1; 626 u8 antenna_select_b:1; 627 u8 antenna_select:1; 628 #else /* _BIG_ENDIAN_ */ 629 u8 antenna_select:1; 630 u8 antenna_select_b:1; 631 u8 r_ant_train_en:1; 632 u8 idle_long:1; 633 u8 rxsc:2; 634 u8 sgi_en:1; 635 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 636 #endif 637 }; 638 639 struct jaguar2_phy_stats_type0 { 640 /* DW0 */ 641 u8 page_num; 642 u8 pwdb; 643 #ifdef __LITTLE_ENDIAN 644 u8 gain: 6; 645 u8 rsvd_0: 1; 646 u8 trsw: 1; 647 #else 648 u8 trsw: 1; 649 u8 rsvd_0: 1; 650 u8 gain: 6; 651 #endif 652 u8 rsvd_1; 653 654 /* DW1 */ 655 u8 rsvd_2; 656 #ifdef __LITTLE_ENDIAN 657 u8 rxsc: 4; 658 u8 agc_table: 4; 659 #else 660 u8 agc_table: 4; 661 u8 rxsc: 4; 662 #endif 663 u8 channel; 664 u8 band; 665 666 /* DW2 */ 667 u16 length; 668 #ifdef __LITTLE_ENDIAN 669 u8 antidx_a: 3; 670 u8 antidx_b: 3; 671 u8 rsvd_3: 2; 672 u8 antidx_c: 3; 673 u8 antidx_d: 3; 674 u8 rsvd_4:2; 675 #else 676 u8 rsvd_3: 2; 677 u8 antidx_b: 3; 678 u8 antidx_a: 3; 679 u8 rsvd_4:2; 680 u8 antidx_d: 3; 681 u8 antidx_c: 3; 682 #endif 683 684 /* DW3 */ 685 u8 signal_quality; 686 #ifdef __LITTLE_ENDIAN 687 u8 vga:5; 688 u8 lna_l:3; 689 u8 bb_power:6; 690 u8 rsvd_9:1; 691 u8 lna_h:1; 692 #else 693 u8 lna_l:3; 694 u8 vga:5; 695 u8 lna_h:1; 696 u8 rsvd_9:1; 697 u8 bb_power:6; 698 #endif 699 u8 rsvd_5; 700 701 /* DW4 */ 702 u32 rsvd_6; 703 704 /* DW5 */ 705 u32 rsvd_7; 706 707 /* DW6 */ 708 u32 rsvd_8; 709 } __packed; 710 711 struct jaguar2_phy_stats_type1 { 712 /* DW0 and DW1 */ 713 u8 page_num; 714 u8 pwdb[4]; 715 #ifdef __LITTLE_ENDIAN 716 u8 l_rxsc: 4; 717 u8 ht_rxsc: 4; 718 #else 719 u8 ht_rxsc: 4; 720 u8 l_rxsc: 4; 721 #endif 722 u8 channel; 723 #ifdef __LITTLE_ENDIAN 724 u8 band: 2; 725 u8 rsvd_0: 1; 726 u8 hw_antsw_occu: 1; 727 u8 gnt_bt: 1; 728 u8 ldpc: 1; 729 u8 stbc: 1; 730 u8 beamformed: 1; 731 #else 732 u8 beamformed: 1; 733 u8 stbc: 1; 734 u8 ldpc: 1; 735 u8 gnt_bt: 1; 736 u8 hw_antsw_occu: 1; 737 u8 rsvd_0: 1; 738 u8 band: 2; 739 #endif 740 741 /* DW2 */ 742 u16 lsig_length; 743 #ifdef __LITTLE_ENDIAN 744 u8 antidx_a: 3; 745 u8 antidx_b: 3; 746 u8 rsvd_1: 2; 747 u8 antidx_c: 3; 748 u8 antidx_d: 3; 749 u8 rsvd_2: 2; 750 #else 751 u8 rsvd_1: 2; 752 u8 antidx_b: 3; 753 u8 antidx_a: 3; 754 u8 rsvd_2: 2; 755 u8 antidx_d: 3; 756 u8 antidx_c: 3; 757 #endif 758 759 /* DW3 */ 760 u8 paid; 761 #ifdef __LITTLE_ENDIAN 762 u8 paid_msb: 1; 763 u8 gid: 6; 764 u8 rsvd_3: 1; 765 #else 766 u8 rsvd_3: 1; 767 u8 gid: 6; 768 u8 paid_msb: 1; 769 #endif 770 u8 intf_pos; 771 #ifdef __LITTLE_ENDIAN 772 u8 intf_pos_msb: 1; 773 u8 rsvd_4: 2; 774 u8 nb_intf_flag: 1; 775 u8 rf_mode: 2; 776 u8 rsvd_5: 2; 777 #else 778 u8 rsvd_5: 2; 779 u8 rf_mode: 2; 780 u8 nb_intf_flag: 1; 781 u8 rsvd_4: 2; 782 u8 intf_pos_msb: 1; 783 #endif 784 785 /* DW4 */ 786 s8 rxevm[4]; /* s(8,1) */ 787 788 /* DW5 */ 789 s8 cfo_tail[4]; /* s(8,7) */ 790 791 /* DW6 */ 792 s8 rxsnr[4]; /* s(8,1) */ 793 } __packed; 794 795 struct jaguar2_phy_stats_type2 { 796 /* DW0 ane DW1 */ 797 u8 page_num; 798 u8 pwdb[4]; 799 #ifdef __LITTLE_ENDIAN 800 u8 l_rxsc: 4; 801 u8 ht_rxsc: 4; 802 #else 803 u8 ht_rxsc: 4; 804 u8 l_rxsc: 4; 805 #endif 806 u8 channel; 807 #ifdef __LITTLE_ENDIAN 808 u8 band: 2; 809 u8 rsvd_0: 1; 810 u8 hw_antsw_occu: 1; 811 u8 gnt_bt: 1; 812 u8 ldpc: 1; 813 u8 stbc: 1; 814 u8 beamformed: 1; 815 #else 816 u8 beamformed: 1; 817 u8 stbc: 1; 818 u8 ldpc: 1; 819 u8 gnt_bt: 1; 820 u8 hw_antsw_occu: 1; 821 u8 rsvd_0: 1; 822 u8 band: 2; 823 #endif 824 825 /* DW2 */ 826 #ifdef __LITTLE_ENDIAN 827 u8 shift_l_map: 6; 828 u8 rsvd_1: 2; 829 #else 830 u8 rsvd_1: 2; 831 u8 shift_l_map: 6; 832 #endif 833 u8 cnt_pw2cca; 834 #ifdef __LITTLE_ENDIAN 835 u8 agc_table_a: 4; 836 u8 agc_table_b: 4; 837 u8 agc_table_c: 4; 838 u8 agc_table_d: 4; 839 #else 840 u8 agc_table_b: 4; 841 u8 agc_table_a: 4; 842 u8 agc_table_d: 4; 843 u8 agc_table_c: 4; 844 #endif 845 846 /* DW3 ~ DW6*/ 847 u8 cnt_cca2agc_rdy; 848 #ifdef __LITTLE_ENDIAN 849 u8 gain_a: 6; 850 u8 rsvd_2: 1; 851 u8 trsw_a: 1; 852 u8 gain_b: 6; 853 u8 rsvd_3: 1; 854 u8 trsw_b: 1; 855 u8 gain_c: 6; 856 u8 rsvd_4: 1; 857 u8 trsw_c: 1; 858 u8 gain_d: 6; 859 u8 rsvd_5: 1; 860 u8 trsw_d: 1; 861 u8 aagc_step_a: 2; 862 u8 aagc_step_b: 2; 863 u8 aagc_step_c: 2; 864 u8 aagc_step_d: 2; 865 #else 866 u8 trsw_a: 1; 867 u8 rsvd_2: 1; 868 u8 gain_a: 6; 869 u8 trsw_b: 1; 870 u8 rsvd_3: 1; 871 u8 gain_b: 6; 872 u8 trsw_c: 1; 873 u8 rsvd_4: 1; 874 u8 gain_c: 6; 875 u8 trsw_d: 1; 876 u8 rsvd_5: 1; 877 u8 gain_d: 6; 878 u8 aagc_step_d: 2; 879 u8 aagc_step_c: 2; 880 u8 aagc_step_b: 2; 881 u8 aagc_step_a: 2; 882 #endif 883 u8 ht_aagc_gain[4]; 884 u8 dagc_gain[4]; 885 #ifdef __LITTLE_ENDIAN 886 u8 counter: 6; 887 u8 rsvd_6: 2; 888 u8 syn_count: 5; 889 u8 rsvd_7:3; 890 #else 891 u8 rsvd_6: 2; 892 u8 counter: 6; 893 u8 rsvd_7:3; 894 u8 syn_count: 5; 895 #endif 896 } __packed; 897 898 /* 899 * Regs to backup 900 */ 901 #define RTL8XXXU_ADDA_REGS 16 902 #define RTL8XXXU_MAC_REGS 4 903 #define RTL8XXXU_BB_REGS 9 904 905 struct rtl8xxxu_firmware_header { 906 __le16 signature; /* 92C0: test chip; 92C, 907 88C0: test chip; 908 88C1: MP A-cut; 909 92C1: MP A-cut */ 910 u8 category; /* AP/NIC and USB/PCI */ 911 u8 function; 912 913 __le16 major_version; /* FW Version */ 914 u8 minor_version; /* FW Subversion, default 0x00 */ 915 u8 reserved1; 916 917 u8 month; /* Release time Month field */ 918 u8 date; /* Release time Date field */ 919 u8 hour; /* Release time Hour field */ 920 u8 minute; /* Release time Minute field */ 921 922 __le16 ramcodesize; /* Size of RAM code */ 923 u16 reserved2; 924 925 __le32 svn_idx; /* SVN entry index */ 926 u32 reserved3; 927 928 u32 reserved4; 929 u32 reserved5; 930 931 u8 data[]; 932 }; 933 934 /* 935 * 8723au/8192cu/8188ru required base power index offset tables. 936 */ 937 struct rtl8xxxu_power_base { 938 u32 reg_0e00; 939 u32 reg_0e04; 940 u32 reg_0e08; 941 u32 reg_086c; 942 943 u32 reg_0e10; 944 u32 reg_0e14; 945 u32 reg_0e18; 946 u32 reg_0e1c; 947 948 u32 reg_0830; 949 u32 reg_0834; 950 u32 reg_0838; 951 u32 reg_086c_2; 952 953 u32 reg_083c; 954 u32 reg_0848; 955 u32 reg_084c; 956 u32 reg_0868; 957 }; 958 959 /* 960 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 961 */ 962 struct rtl8723au_idx { 963 #ifdef __LITTLE_ENDIAN 964 int a:4; 965 int b:4; 966 #else 967 int b:4; 968 int a:4; 969 #endif 970 } __attribute__((packed)); 971 972 struct rtl8723au_efuse { 973 __le16 rtl_id; 974 u8 res0[0xe]; 975 u8 cck_tx_power_index_A[3]; /* 0x10 */ 976 u8 cck_tx_power_index_B[3]; 977 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 978 u8 ht40_1s_tx_power_index_B[3]; 979 /* 980 * The following entries are half-bytes split as: 981 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 982 */ 983 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 984 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 985 struct rtl8723au_idx ht40_max_power_offset[3]; 986 struct rtl8723au_idx ht20_max_power_offset[3]; 987 u8 channel_plan; /* 0x28 */ 988 u8 tssi_a; 989 u8 thermal_meter; 990 u8 rf_regulatory; 991 u8 rf_option_2; 992 u8 rf_option_3; 993 u8 rf_option_4; 994 u8 res7; 995 u8 version /* 0x30 */; 996 u8 customer_id_major; 997 u8 customer_id_minor; 998 u8 xtal_k; 999 u8 chipset; /* 0x34 */ 1000 u8 res8[0x82]; 1001 u8 vid; /* 0xb7 */ 1002 u8 res9; 1003 u8 pid; /* 0xb9 */ 1004 u8 res10[0x0c]; 1005 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 1006 u8 res11[2]; 1007 u8 vendor_name[7]; 1008 u8 res12[2]; 1009 u8 device_name[0x29]; /* 0xd7 */ 1010 }; 1011 1012 struct rtl8192cu_efuse { 1013 __le16 rtl_id; 1014 __le16 hpon; 1015 u8 res0[2]; 1016 __le16 clk; 1017 __le16 testr; 1018 __le16 vid; 1019 __le16 did; 1020 __le16 svid; 1021 __le16 smid; /* 0x10 */ 1022 u8 res1[4]; 1023 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 1024 u8 res2[2]; 1025 u8 vendor_name[7]; 1026 u8 res3[3]; 1027 u8 device_name[0x14]; /* 0x28 */ 1028 u8 res4[0x1e]; /* 0x3c */ 1029 u8 cck_tx_power_index_A[3]; /* 0x5a */ 1030 u8 cck_tx_power_index_B[3]; 1031 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 1032 u8 ht40_1s_tx_power_index_B[3]; 1033 /* 1034 * The following entries are half-bytes split as: 1035 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1036 */ 1037 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 1038 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 1039 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 1040 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 1041 struct rtl8723au_idx ht20_max_power_offset[3]; 1042 u8 channel_plan; /* 0x75 */ 1043 u8 tssi_a; 1044 u8 tssi_b; 1045 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 1046 u8 rf_regulatory; 1047 u8 rf_option_2; 1048 u8 rf_option_3; 1049 u8 rf_option_4; 1050 u8 res5[1]; /* 0x7d */ 1051 u8 version; 1052 u8 customer_id; 1053 }; 1054 1055 struct rtl8723bu_pwr_idx { 1056 #ifdef __LITTLE_ENDIAN 1057 int ht20:4; 1058 int ht40:4; 1059 int ofdm:4; 1060 int cck:4; 1061 #else 1062 int cck:4; 1063 int ofdm:4; 1064 int ht40:4; 1065 int ht20:4; 1066 #endif 1067 } __attribute__((packed)); 1068 1069 struct rtl8723bu_efuse_tx_power { 1070 u8 cck_base[6]; 1071 u8 ht40_base[5]; 1072 struct rtl8723au_idx ht20_ofdm_1s_diff; 1073 struct rtl8723bu_pwr_idx pwr_diff[3]; 1074 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1075 }; 1076 1077 struct rtl8723bu_efuse { 1078 __le16 rtl_id; 1079 u8 res0[0x0e]; 1080 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1081 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1082 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 1083 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 1084 u8 channel_plan; /* 0xb8 */ 1085 u8 xtal_k; 1086 u8 thermal_meter; 1087 u8 iqk_lck; 1088 u8 pa_type; /* 0xbc */ 1089 u8 lna_type_2g; /* 0xbd */ 1090 u8 res2[3]; 1091 u8 rf_board_option; 1092 u8 rf_feature_option; 1093 u8 rf_bt_setting; 1094 u8 eeprom_version; 1095 u8 eeprom_customer_id; 1096 u8 res3[2]; 1097 u8 tx_pwr_calibrate_rate; 1098 u8 rf_antenna_option; /* 0xc9 */ 1099 u8 rfe_option; 1100 u8 res4[9]; 1101 u8 usb_optional_function; 1102 u8 res5[0x1e]; 1103 u8 res6[2]; 1104 u8 serial[0x0b]; /* 0xf5 */ 1105 u8 vid; /* 0x100 */ 1106 u8 res7; 1107 u8 pid; 1108 u8 res8[4]; 1109 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1110 u8 res9[2]; 1111 u8 vendor_name[0x07]; 1112 u8 res10[2]; 1113 u8 device_name[0x14]; 1114 u8 res11[0xcf]; 1115 u8 package_type; /* 0x1fb */ 1116 u8 res12[0x4]; 1117 }; 1118 1119 struct rtl8192eu_efuse_tx_power { 1120 u8 cck_base[6]; 1121 u8 ht40_base[5]; 1122 struct rtl8723au_idx ht20_ofdm_1s_diff; 1123 struct rtl8723bu_pwr_idx pwr_diff[3]; 1124 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1125 }; 1126 1127 struct rtl8192eu_efuse { 1128 __le16 rtl_id; 1129 u8 res0[0x0e]; 1130 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1131 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1132 u8 res2[0x54]; 1133 u8 channel_plan; /* 0xb8 */ 1134 u8 xtal_k; 1135 u8 thermal_meter; 1136 u8 iqk_lck; 1137 u8 pa_type; /* 0xbc */ 1138 u8 lna_type_2g; /* 0xbd */ 1139 u8 res3[1]; 1140 u8 lna_type_5g; /* 0xbf */ 1141 u8 res4[1]; 1142 u8 rf_board_option; 1143 u8 rf_feature_option; 1144 u8 rf_bt_setting; 1145 u8 eeprom_version; 1146 u8 eeprom_customer_id; 1147 u8 res5[3]; 1148 u8 rf_antenna_option; /* 0xc9 */ 1149 u8 res6[6]; 1150 u8 vid; /* 0xd0 */ 1151 u8 res7[1]; 1152 u8 pid; /* 0xd2 */ 1153 u8 res8[1]; 1154 u8 usb_optional_function; 1155 u8 res9[2]; 1156 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1157 u8 device_info[80]; 1158 u8 res11[3]; 1159 u8 unknown[0x0d]; /* 0x130 */ 1160 u8 res12[0xc3]; 1161 }; 1162 1163 struct rtl8188fu_efuse_tx_power { 1164 u8 cck_base[6]; 1165 u8 ht40_base[5]; 1166 /* a: ofdm; b: ht20 */ 1167 struct rtl8723au_idx ht20_ofdm_1s_diff; 1168 }; 1169 1170 struct rtl8188fu_efuse { 1171 __le16 rtl_id; 1172 u8 res0[0x0e]; 1173 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1174 u8 res1[0x9c]; /* 0x1c */ 1175 u8 channel_plan; /* 0xb8 */ 1176 u8 xtal_k; 1177 u8 thermal_meter; 1178 u8 iqk_lck; 1179 u8 res2[5]; 1180 u8 rf_board_option; 1181 u8 rf_feature_option; 1182 u8 rf_bt_setting; 1183 u8 eeprom_version; 1184 u8 eeprom_customer_id; 1185 u8 res3[2]; 1186 u8 kfree_thermal_k_on; 1187 u8 rf_antenna_option; /* 0xc9 */ 1188 u8 rfe_option; 1189 u8 country_code; 1190 u8 res4[4]; 1191 u8 vid; /* 0xd0 */ 1192 u8 res5[1]; 1193 u8 pid; /* 0xd2 */ 1194 u8 res6[1]; 1195 u8 usb_optional_function; 1196 u8 res7[2]; 1197 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1198 u8 res8[2]; 1199 u8 vendor_name[7]; 1200 u8 res9[2]; 1201 u8 device_name[7]; /* 0xe8 */ 1202 u8 res10[0x41]; 1203 u8 unknown[0x0d]; /* 0x130 */ 1204 u8 res11[0xc3]; 1205 }; 1206 1207 struct rtl8188eu_efuse { 1208 __le16 rtl_id; 1209 u8 res0[0x0e]; 1210 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1211 u8 res1[0x7e]; /* 0x3a */ 1212 u8 channel_plan; /* 0xb8 */ 1213 u8 xtal_k; 1214 u8 thermal_meter; 1215 u8 iqk_lck; 1216 u8 res2[5]; 1217 u8 rf_board_option; 1218 u8 rf_feature_option; 1219 u8 rf_bt_setting; 1220 u8 eeprom_version; 1221 u8 eeprom_customer_id; 1222 u8 res3[3]; 1223 u8 rf_antenna_option; /* 0xc9 */ 1224 u8 res4[6]; 1225 u8 vid; /* 0xd0 */ 1226 u8 res5[1]; 1227 u8 pid; /* 0xd2 */ 1228 u8 res6[1]; 1229 u8 usb_optional_function; 1230 u8 res7[2]; 1231 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1232 u8 res8[2]; 1233 u8 vendor_name[7]; 1234 u8 res9[2]; 1235 u8 device_name[0x0b]; /* 0xe8 */ 1236 u8 res10[2]; 1237 u8 serial[0x0b]; /* 0xf5 */ 1238 u8 res11[0x30]; 1239 u8 unknown[0x0d]; /* 0x130 */ 1240 u8 res12[0xc3]; 1241 } __packed; 1242 1243 struct rtl8710bu_efuse { 1244 __le16 rtl_id; 1245 u8 res0[0x1e]; 1246 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x20 */ 1247 u8 res1[0x9c]; /* 0x2c */ 1248 u8 channel_plan; /* 0xc8 */ 1249 u8 xtal_k; /* 0xc9 */ 1250 u8 thermal_meter; /* 0xca */ 1251 u8 res2[0x4f]; 1252 u8 mac_addr[ETH_ALEN]; /* 0x11a */ 1253 u8 res3[0x11]; 1254 u8 rf_board_option; /* 0x131 */ 1255 u8 res4[2]; 1256 u8 eeprom_version; /* 0x134 */ 1257 u8 eeprom_customer_id; /* 0x135 */ 1258 u8 res5[5]; 1259 u8 country_code; /* 0x13b */ 1260 u8 res6[0x84]; 1261 u8 vid[2]; /* 0x1c0 */ 1262 u8 pid[2]; /* 0x1c2 */ 1263 u8 res7[0x3c]; 1264 } __packed; 1265 1266 struct rtl8192fu_efuse { 1267 __le16 rtl_id; 1268 u8 res0[0x0e]; 1269 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1270 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1271 u8 res2[0x54]; 1272 u8 channel_plan; /* 0xb8 */ 1273 u8 xtal_k; /* 0xb9 */ 1274 u8 thermal_meter; /* 0xba */ 1275 u8 iqk_lck; /* 0xbb */ 1276 u8 pa_type; /* 0xbc */ 1277 u8 lna_type_2g; /* 0xbd */ 1278 u8 res3[1]; 1279 u8 lna_type_5g; /* 0xbf */ 1280 u8 res4[1]; 1281 u8 rf_board_option; /* 0xc1 */ 1282 u8 rf_feature_option; /* 0xc2 */ 1283 u8 rf_bt_setting; /* 0xc3 */ 1284 u8 eeprom_version; /* 0xc4 */ 1285 u8 eeprom_customer_id; /* 0xc5 */ 1286 u8 res5[3]; 1287 u8 rf_antenna_option; /* 0xc9 */ 1288 u8 rfe_option; /* 0xca */ 1289 u8 country_code; /* 0xcb */ 1290 u8 res6[52]; 1291 u8 vid[2]; /* 0x100 */ 1292 u8 pid[2]; /* 0x102 */ 1293 u8 usb_optional_function; /* 0x104 */ 1294 u8 res7[2]; 1295 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1296 u8 device_info[80]; /* 0x10d */ 1297 u8 res9[163]; 1298 } __packed; 1299 1300 struct rtl8xxxu_reg8val { 1301 u16 reg; 1302 u8 val; 1303 }; 1304 1305 struct rtl8xxxu_reg32val { 1306 u16 reg; 1307 u32 val; 1308 }; 1309 1310 struct rtl8xxxu_rfregval { 1311 u8 reg; 1312 u32 val; 1313 }; 1314 1315 enum rtl8xxxu_rfpath { 1316 RF_A = 0, 1317 RF_B = 1, 1318 }; 1319 1320 struct rtl8xxxu_rfregs { 1321 u16 hssiparm1; 1322 u16 hssiparm2; 1323 u16 lssiparm; 1324 u16 hspiread; 1325 u16 lssiread; 1326 u16 rf_sw_ctrl; 1327 }; 1328 1329 #define H2C_MAX_MBOX 4 1330 #define H2C_EXT BIT(7) 1331 #define H2C_JOIN_BSS_DISCONNECT 0 1332 #define H2C_JOIN_BSS_CONNECT 1 1333 1334 #define H2C_MACID_ROLE_STA 1 1335 #define H2C_MACID_ROLE_AP 2 1336 1337 /* 1338 * H2C (firmware) commands differ between the older generation chips 1339 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 1340 * 8192[de]u, 8192eu, and 8812. 1341 */ 1342 enum h2c_cmd_8723a { 1343 H2C_SET_POWER_MODE = 1, 1344 H2C_JOIN_BSS_REPORT = 2, 1345 H2C_SET_RSSI = 5, 1346 H2C_SET_RATE_MASK = (6 | H2C_EXT), 1347 }; 1348 1349 enum h2c_cmd_8723b { 1350 /* 1351 * Common Class: 000 1352 */ 1353 H2C_8723B_RSVD_PAGE = 0x00, 1354 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 1355 H2C_8723B_SCAN_ENABLE = 0x02, 1356 H2C_8723B_KEEP_ALIVE = 0x03, 1357 H2C_8723B_DISCON_DECISION = 0x04, 1358 H2C_8723B_PSD_OFFLOAD = 0x05, 1359 H2C_8723B_AP_OFFLOAD = 0x08, 1360 H2C_8723B_BCN_RSVDPAGE = 0x09, 1361 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 1362 H2C_8723B_FCS_RSVDPAGE = 0x10, 1363 H2C_8723B_FCS_INFO = 0x11, 1364 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 1365 1366 /* 1367 * PoweSave Class: 001 1368 */ 1369 H2C_8723B_SET_PWR_MODE = 0x20, 1370 H2C_8723B_PS_TUNING_PARA = 0x21, 1371 H2C_8723B_PS_TUNING_PARA2 = 0x22, 1372 H2C_8723B_P2P_LPS_PARAM = 0x23, 1373 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 1374 H2C_8723B_PS_SCAN_ENABLE = 0x25, 1375 H2C_8723B_SAP_PS_ = 0x26, 1376 H2C_8723B_INACTIVE_PS_ = 0x27, 1377 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 1378 1379 /* 1380 * Dynamic Mechanism Class: 010 1381 */ 1382 H2C_8723B_MACID_CFG_RAID = 0x40, 1383 H2C_8723B_TXBF = 0x41, 1384 H2C_8723B_RSSI_SETTING = 0x42, 1385 H2C_8723B_AP_REQ_TXRPT = 0x43, 1386 H2C_8723B_INIT_RATE_COLLECT = 0x44, 1387 1388 /* 1389 * BT Class: 011 1390 */ 1391 H2C_8723B_B_TYPE_TDMA = 0x60, 1392 H2C_8723B_BT_INFO = 0x61, 1393 H2C_8723B_FORCE_BT_TXPWR = 0x62, 1394 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 1395 H2C_8723B_DAC_SWING_VALUE = 0x64, 1396 H2C_8723B_ANT_SEL_RSV = 0x65, 1397 H2C_8723B_WL_OPMODE = 0x66, 1398 H2C_8723B_BT_MP_OPER = 0x67, 1399 H2C_8723B_BT_CONTROL = 0x68, 1400 H2C_8723B_BT_WIFI_CTRL = 0x69, 1401 H2C_8723B_BT_FW_PATCH = 0x6a, 1402 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 1403 H2C_8723B_BT_GRANT = 0x6e, 1404 1405 /* 1406 * WOWLAN Class: 100 1407 */ 1408 H2C_8723B_WOWLAN = 0x80, 1409 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 1410 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 1411 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 1412 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 1413 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 1414 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 1415 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 1416 1417 H2C_8723B_RESET_TSF = 0xC0, 1418 }; 1419 1420 1421 struct h2c_cmd { 1422 union { 1423 struct { 1424 u8 cmd; 1425 u8 data[7]; 1426 } __packed cmd; 1427 struct { 1428 __le32 data; 1429 __le16 ext; 1430 } __packed raw; 1431 struct { 1432 __le32 data; 1433 __le32 ext; 1434 } __packed raw_wide; 1435 struct { 1436 u8 cmd; 1437 u8 data; 1438 } __packed joinbss; 1439 struct { 1440 u8 cmd; 1441 __le16 mask_hi; 1442 u8 arg; 1443 __le16 mask_lo; 1444 } __packed ramask; 1445 struct { 1446 u8 cmd; 1447 u8 parm; 1448 u8 macid; 1449 u8 macid_end; 1450 } __packed media_status_rpt; 1451 struct { 1452 u8 cmd; 1453 u8 macid; 1454 /* 1455 * [0:4] - RAID 1456 * [7] - SGI 1457 */ 1458 u8 data1; 1459 /* 1460 * [0:1] - Bandwidth 1461 * [3] - No Update 1462 * [4:5] - VHT enable 1463 * [6] - DISPT 1464 * [7] - DISRA 1465 */ 1466 u8 data2; 1467 u8 ramask0; 1468 u8 ramask1; 1469 u8 ramask2; 1470 u8 ramask3; 1471 } __packed b_macid_cfg; 1472 struct { 1473 u8 cmd; 1474 u8 data1; 1475 u8 data2; 1476 u8 data3; 1477 u8 data4; 1478 u8 data5; 1479 } __packed b_type_dma; 1480 struct { 1481 u8 cmd; 1482 u8 data; 1483 } __packed bt_info; 1484 struct { 1485 u8 cmd; 1486 u8 operreq; 1487 u8 opcode; 1488 u8 data; 1489 u8 addr; 1490 } __packed bt_mp_oper; 1491 struct { 1492 u8 cmd; 1493 u8 data; 1494 } __packed bt_wlan_calibration; 1495 struct { 1496 u8 cmd; 1497 u8 data; 1498 } __packed ignore_wlan; 1499 struct { 1500 u8 cmd; 1501 u8 ant_inverse; 1502 u8 int_switch_type; 1503 } __packed ant_sel_rsv; 1504 struct { 1505 u8 cmd; 1506 u8 data; 1507 } __packed bt_grant; 1508 struct { 1509 u8 cmd; 1510 u8 macid; 1511 u8 unknown0; 1512 u8 rssi; 1513 /* 1514 * [0] - is_rx 1515 * [1] - stbc_en 1516 * [2] - noisy_decision 1517 * [6] - bf_en 1518 */ 1519 u8 data; 1520 /* 1521 * [0:6] - ra_th_offset 1522 * [7] - ra_offset_direction 1523 */ 1524 u8 ra_th_offset; 1525 u8 unknown1; 1526 u8 unknown2; 1527 } __packed rssi_report; 1528 }; 1529 }; 1530 1531 enum c2h_evt_8723b { 1532 C2H_8723B_DEBUG = 0, 1533 C2H_8723B_TSF = 1, 1534 C2H_8723B_AP_RPT_RSP = 2, 1535 C2H_8723B_CCX_TX_RPT = 3, 1536 C2H_8723B_BT_RSSI = 4, 1537 C2H_8723B_BT_OP_MODE = 5, 1538 C2H_8723B_EXT_RA_RPT = 6, 1539 C2H_8723B_BT_INFO = 9, 1540 C2H_8723B_HW_INFO_EXCH = 0x0a, 1541 C2H_8723B_BT_MP_INFO = 0x0b, 1542 C2H_8723B_RA_REPORT = 0x0c, 1543 C2H_8723B_FW_DEBUG = 0xff, 1544 }; 1545 1546 enum bt_info_src_8723b { 1547 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1548 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1549 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1550 }; 1551 1552 enum bt_mp_oper_opcode_8723b { 1553 BT_MP_OP_GET_BT_VERSION = 0x00, 1554 BT_MP_OP_RESET = 0x01, 1555 BT_MP_OP_TEST_CTRL = 0x02, 1556 BT_MP_OP_SET_BT_MODE = 0x03, 1557 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1558 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1559 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1560 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1561 BT_MP_OP_SET_PKT_HEADER = 0x08, 1562 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1563 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1564 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1565 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1566 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1567 BT_MP_OP_GET_BT_STATUS = 0x0e, 1568 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1569 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1570 BT_MP_OP_READ_REG = 0x11, 1571 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1572 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1573 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1574 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1575 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1576 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1577 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1578 BT_MP_OP_GET_RSSI = 0x19, 1579 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1580 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1581 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1582 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1583 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1584 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1585 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1586 BT_MP_OP_GET_AFH_STATUS = 0x21, 1587 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1588 BT_MP_OP_SET_THERMAL_METER = 0x23, 1589 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1590 }; 1591 1592 enum rtl8xxxu_bw_mode { 1593 RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1594 RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1595 RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1596 RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1597 RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1598 RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1599 }; 1600 1601 struct rtl8723bu_c2h { 1602 u8 id; 1603 u8 seq; 1604 union { 1605 struct { 1606 u8 payload[0]; 1607 } __packed raw; 1608 struct { 1609 u8 ext_id; 1610 u8 status:4; 1611 u8 retlen:4; 1612 u8 opcode_ver:4; 1613 u8 req_num:4; 1614 u8 payload[2]; 1615 } __packed bt_mp_info; 1616 struct { 1617 u8 response_source:4; 1618 u8 dummy0_0:4; 1619 1620 u8 bt_info; 1621 1622 u8 retry_count:4; 1623 u8 dummy2_0:1; 1624 u8 bt_page:1; 1625 u8 tx_rx_mask:1; 1626 u8 dummy2_2:1; 1627 1628 u8 rssi; 1629 1630 u8 basic_rate:1; 1631 u8 bt_has_reset:1; 1632 u8 dummy4_1:1; 1633 u8 ignore_wlan:1; 1634 u8 auto_report:1; 1635 u8 dummy4_2:3; 1636 1637 u8 a4; 1638 u8 a5; 1639 } __packed bt_info; 1640 struct { 1641 u8 rate:7; 1642 u8 sgi:1; 1643 u8 macid; 1644 u8 ldpc:1; 1645 u8 txbf:1; 1646 u8 noisy_state:1; 1647 u8 dummy2_0:5; 1648 u8 dummy3_0; 1649 u8 dummy4_0; 1650 u8 dummy5_0; 1651 u8 bw; 1652 } __packed ra_report; 1653 }; 1654 } __packed; 1655 1656 struct rtl8xxxu_fileops; 1657 1658 /*mlme related.*/ 1659 enum wireless_mode { 1660 WIRELESS_MODE_UNKNOWN = 0, 1661 /* Sub-Element */ 1662 WIRELESS_MODE_B = BIT(0), 1663 WIRELESS_MODE_G = BIT(1), 1664 WIRELESS_MODE_A = BIT(2), 1665 WIRELESS_MODE_N_24G = BIT(3), 1666 WIRELESS_MODE_N_5G = BIT(4), 1667 WIRELESS_AUTO = BIT(5), 1668 WIRELESS_MODE_AC = BIT(6), 1669 WIRELESS_MODE_MAX = 0x7F, 1670 }; 1671 1672 /* from rtlwifi/wifi.h */ 1673 enum ratr_table_mode_new { 1674 RATEID_IDX_BGN_40M_2SS = 0, 1675 RATEID_IDX_BGN_40M_1SS = 1, 1676 RATEID_IDX_BGN_20M_2SS_BN = 2, 1677 RATEID_IDX_BGN_20M_1SS_BN = 3, 1678 RATEID_IDX_GN_N2SS = 4, 1679 RATEID_IDX_GN_N1SS = 5, 1680 RATEID_IDX_BG = 6, 1681 RATEID_IDX_G = 7, 1682 RATEID_IDX_B = 8, 1683 RATEID_IDX_VHT_2SS = 9, 1684 RATEID_IDX_VHT_1SS = 10, 1685 RATEID_IDX_MIX1 = 11, 1686 RATEID_IDX_MIX2 = 12, 1687 RATEID_IDX_VHT_3SS = 13, 1688 RATEID_IDX_BGN_3SS = 14, 1689 }; 1690 1691 #define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1692 #define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1693 #define BT_INFO_8723B_1ANT_B_HID BIT(5) 1694 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1695 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1696 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1697 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1698 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1699 1700 enum _BT_8723B_1ANT_STATUS { 1701 BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1702 BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1703 BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1704 BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1705 BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1706 BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1707 BT_8723B_1ANT_STATUS_MAX 1708 }; 1709 1710 struct rtl8xxxu_btcoex { 1711 u8 bt_status; 1712 bool bt_busy; 1713 bool has_sco; 1714 bool has_a2dp; 1715 bool has_hid; 1716 bool has_pan; 1717 bool hid_only; 1718 bool a2dp_only; 1719 bool c2h_bt_inquiry; 1720 }; 1721 1722 #define RTL8XXXU_RATR_STA_INIT 0 1723 #define RTL8XXXU_RATR_STA_HIGH 1 1724 #define RTL8XXXU_RATR_STA_MID 2 1725 #define RTL8XXXU_RATR_STA_LOW 3 1726 1727 #define RTL8XXXU_NOISE_FLOOR_MIN -100 1728 #define RTL8XXXU_SNR_THRESH_HIGH 50 1729 #define RTL8XXXU_SNR_THRESH_LOW 20 1730 1731 struct rtl8xxxu_ra_report { 1732 struct rate_info txrate; 1733 u32 bit_rate; 1734 u8 desc_rate; 1735 }; 1736 1737 struct rtl8xxxu_ra_info { 1738 u8 rate_id; 1739 u32 rate_mask; 1740 u32 ra_use_rate; 1741 u8 rate_sgi; 1742 u8 rssi_sta_ra; /* Percentage */ 1743 u8 pre_rssi_sta_ra; 1744 u8 sgi_enable; 1745 u8 decision_rate; 1746 u8 pre_rate; 1747 u8 highest_rate; 1748 u8 lowest_rate; 1749 u32 nsc_up; 1750 u32 nsc_down; 1751 u32 total; 1752 u16 retry[5]; 1753 u16 drop; 1754 u16 rpt_time; 1755 u16 pre_min_rpt_time; 1756 u8 dynamic_tx_rpt_timing_counter; 1757 u8 ra_waiting_counter; 1758 u8 ra_pending_counter; 1759 u8 ra_drop_after_down; 1760 u8 pt_try_state; /* 0 trying state, 1 for decision state */ 1761 u8 pt_stage; /* 0~6 */ 1762 u8 pt_stop_count; /* Stop PT counter */ 1763 u8 pt_pre_rate; /* if rate change do PT */ 1764 u8 pt_pre_rssi; /* if RSSI change 5% do PT */ 1765 u8 pt_mode_ss; /* decide which rate should do PT */ 1766 u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ 1767 u8 pt_smooth_factor; 1768 }; 1769 1770 #define CFO_TH_XTAL_HIGH 20 /* kHz */ 1771 #define CFO_TH_XTAL_LOW 10 /* kHz */ 1772 #define CFO_TH_ATC 80 /* kHz */ 1773 1774 struct rtl8xxxu_cfo_tracking { 1775 bool adjust; 1776 bool atc_status; 1777 int cfo_tail[2]; 1778 u8 crystal_cap; 1779 u32 packet_count; 1780 u32 packet_count_pre; 1781 }; 1782 1783 #define RTL8XXXU_HW_LED_CONTROL 2 1784 #define RTL8XXXU_MAX_MAC_ID_NUM 128 1785 #define RTL8XXXU_BC_MC_MACID 0 1786 1787 struct rtl8xxxu_priv { 1788 struct ieee80211_hw *hw; 1789 struct usb_device *udev; 1790 struct rtl8xxxu_fileops *fops; 1791 1792 spinlock_t tx_urb_lock; 1793 struct list_head tx_urb_free_list; 1794 int tx_urb_free_count; 1795 bool tx_stopped; 1796 1797 spinlock_t rx_urb_lock; 1798 struct list_head rx_urb_pending_list; 1799 int rx_urb_pending_count; 1800 bool shutdown; 1801 struct work_struct rx_urb_wq; 1802 1803 u8 mac_addr[ETH_ALEN]; 1804 char chip_name[8]; 1805 char chip_vendor[8]; 1806 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1807 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1808 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1809 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1810 /* 1811 * The following entries are half-bytes split as: 1812 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1813 */ 1814 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1815 RTL8723A_CHANNEL_GROUPS]; 1816 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1817 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1818 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1819 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1820 /* 1821 * Newer generation chips only keep power diffs per TX count, 1822 * not per channel group. 1823 */ 1824 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1825 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1826 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1827 struct rtl8xxxu_power_base *power_base; 1828 u8 package_type; 1829 u32 chip_cut:4; 1830 u32 rom_rev:4; 1831 u32 is_multi_func:1; 1832 u32 has_wifi:1; 1833 u32 has_bluetooth:1; 1834 u32 enable_bluetooth:1; 1835 u32 has_gps:1; 1836 u32 hi_pa:1; 1837 u32 vendor_umc:1; 1838 u32 vendor_smic:1; 1839 u32 has_polarity_ctrl:1; 1840 u32 has_eeprom:1; 1841 u32 boot_eeprom:1; 1842 u32 usb_interrupts:1; 1843 u32 ep_tx_high_queue:1; 1844 u32 ep_tx_normal_queue:1; 1845 u32 ep_tx_low_queue:1; 1846 u32 rx_buf_aggregation:1; 1847 u32 cck_agc_report_type:1; 1848 u32 cck_new_agc:1; 1849 u8 default_crystal_cap; 1850 u8 rfe_type; 1851 unsigned int pipe_interrupt; 1852 unsigned int pipe_in; 1853 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1854 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1855 u8 ep_tx_count; 1856 u8 rf_paths; 1857 u8 rx_paths; 1858 u8 tx_paths; 1859 u32 rege94; 1860 u32 rege9c; 1861 u32 regeb4; 1862 u32 regebc; 1863 u32 regrcr; 1864 int next_mbox; 1865 int nr_out_eps; 1866 1867 struct mutex h2c_mutex; 1868 /* Protect the indirect register accesses of RTL8710BU. */ 1869 struct mutex syson_indirect_access_mutex; 1870 1871 struct usb_anchor rx_anchor; 1872 struct usb_anchor tx_anchor; 1873 struct usb_anchor int_anchor; 1874 struct rtl8xxxu_firmware_header *fw_data; 1875 size_t fw_size; 1876 struct mutex usb_buf_mutex; 1877 union { 1878 __le32 val32; 1879 __le16 val16; 1880 u8 val8; 1881 } usb_buf; 1882 union { 1883 u8 raw[EFUSE_MAP_LEN]; 1884 struct rtl8723au_efuse efuse8723; 1885 struct rtl8723bu_efuse efuse8723bu; 1886 struct rtl8192cu_efuse efuse8192; 1887 struct rtl8192eu_efuse efuse8192eu; 1888 struct rtl8188fu_efuse efuse8188fu; 1889 struct rtl8188eu_efuse efuse8188eu; 1890 struct rtl8710bu_efuse efuse8710bu; 1891 struct rtl8192fu_efuse efuse8192fu; 1892 } efuse_wifi; 1893 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1894 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1895 u32 bb_backup[RTL8XXXU_BB_REGS]; 1896 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1897 enum rtl8xxxu_rtl_chip rtl_chip; 1898 u8 pi_enabled:1; 1899 u8 no_pape:1; 1900 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1901 u8 rssi_level; 1902 DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS); 1903 DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS); 1904 /* 1905 * Only one virtual interface permitted because only STA mode 1906 * is supported and no iface_combinations are provided. 1907 */ 1908 struct ieee80211_vif *vif; 1909 struct delayed_work ra_watchdog; 1910 struct work_struct c2hcmd_work; 1911 struct sk_buff_head c2hcmd_queue; 1912 struct work_struct update_beacon_work; 1913 struct rtl8xxxu_btcoex bt_coex; 1914 struct rtl8xxxu_ra_report ra_report; 1915 struct rtl8xxxu_cfo_tracking cfo_tracking; 1916 struct rtl8xxxu_ra_info ra_info; 1917 1918 bool led_registered; 1919 char led_name[32]; 1920 struct led_classdev led_cdev; 1921 DECLARE_BITMAP(mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); 1922 }; 1923 1924 struct rtl8xxxu_sta_info { 1925 struct ieee80211_sta *sta; 1926 struct ieee80211_vif *vif; 1927 1928 u8 macid; 1929 }; 1930 1931 struct rtl8xxxu_rx_urb { 1932 struct urb urb; 1933 struct ieee80211_hw *hw; 1934 struct list_head list; 1935 }; 1936 1937 struct rtl8xxxu_tx_urb { 1938 struct urb urb; 1939 struct ieee80211_hw *hw; 1940 struct list_head list; 1941 }; 1942 1943 struct rtl8xxxu_fileops { 1944 int (*identify_chip) (struct rtl8xxxu_priv *priv); 1945 int (*read_efuse) (struct rtl8xxxu_priv *priv); 1946 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1947 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1948 int (*power_on) (struct rtl8xxxu_priv *priv); 1949 void (*power_off) (struct rtl8xxxu_priv *priv); 1950 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1951 int (*llt_init) (struct rtl8xxxu_priv *priv); 1952 void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1953 int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1954 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1955 void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv); 1956 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1957 void (*config_channel) (struct ieee80211_hw *hw); 1958 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1959 void (*parse_phystats) (struct rtl8xxxu_priv *priv, 1960 struct ieee80211_rx_status *rx_status, 1961 struct rtl8723au_phy_stats *phy_stats, 1962 u32 rxmcs, struct ieee80211_hdr *hdr, 1963 bool crc_icv_err); 1964 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1965 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1966 void (*init_burst) (struct rtl8xxxu_priv *priv); 1967 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1968 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1969 void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1970 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1971 bool ht40); 1972 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1973 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 1974 u8 macid); 1975 void (*report_connect) (struct rtl8xxxu_priv *priv, 1976 u8 macid, u8 role, bool connect); 1977 void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1978 void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1979 struct ieee80211_tx_info *tx_info, 1980 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1981 bool short_preamble, bool ampdu_enable, 1982 u32 rts_rate, u8 macid); 1983 void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap); 1984 s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 1985 int (*led_classdev_brightness_set) (struct led_classdev *led_cdev, 1986 enum led_brightness brightness); 1987 int writeN_block_size; 1988 int rx_agg_buf_size; 1989 char tx_desc_size; 1990 char rx_desc_size; 1991 u8 has_s0s1:1; 1992 u8 has_tx_report:1; 1993 u8 gen2_thermal_meter:1; 1994 u8 needs_full_init:1; 1995 u8 init_reg_rxfltmap:1; 1996 u8 init_reg_pkt_life_time:1; 1997 u8 init_reg_hmtfr:1; 1998 u8 ampdu_max_time; 1999 u8 ustime_tsf_edca; 2000 u16 max_aggr_num; 2001 u8 supports_ap:1; 2002 u16 max_macid_num; 2003 u32 adda_1t_init; 2004 u32 adda_1t_path_on; 2005 u32 adda_2t_path_on_a; 2006 u32 adda_2t_path_on_b; 2007 u16 trxff_boundary; 2008 u8 pbp_rx; 2009 u8 pbp_tx; 2010 const struct rtl8xxxu_reg8val *mactable; 2011 u8 total_page_num; 2012 u8 page_num_hi; 2013 u8 page_num_lo; 2014 u8 page_num_norm; 2015 u8 last_llt_entry; 2016 }; 2017 2018 extern int rtl8xxxu_debug; 2019 2020 extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 2021 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 2022 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 2023 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 2024 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 2025 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 2026 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 2027 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 2028 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 2029 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 2030 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 2031 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 2032 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 2033 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 2034 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 2035 u32 mask, u32 val); 2036 2037 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 2038 enum rtl8xxxu_rfpath path, u8 reg); 2039 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 2040 enum rtl8xxxu_rfpath path, u8 reg, u32 data); 2041 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 2042 enum rtl8xxxu_rfpath path, u8 reg, 2043 u32 mask, u32 val); 2044 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2045 u32 *backup, int count); 2046 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2047 u32 *backup, int count); 2048 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 2049 const u32 *reg, u32 *backup); 2050 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 2051 const u32 *reg, u32 *backup); 2052 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2053 bool path_a_on); 2054 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 2055 const u32 *regs, u32 *backup); 2056 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2057 int result[][8], int candidate, bool tx_only); 2058 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2059 int result[][8], int candidate, bool tx_only); 2060 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2061 const struct rtl8xxxu_rfregval *table, 2062 enum rtl8xxxu_rfpath path); 2063 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2064 const struct rtl8xxxu_reg32val *array); 2065 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name); 2066 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 2067 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 2068 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor); 2069 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor); 2070 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv); 2071 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv); 2072 int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); 2073 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv); 2074 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 2075 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 2076 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 2077 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2078 void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2079 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 2080 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 2081 struct h2c_cmd *h2c, int len); 2082 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 2083 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 2084 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 2085 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 2086 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 2087 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 2088 int channel, bool ht40); 2089 void rtl8188f_channel_to_group(int channel, int *group, int *cck_group); 2090 void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, 2091 int channel, bool ht40); 2092 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 2093 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 2094 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 2095 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 2096 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 2097 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2098 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 2099 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2100 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 2101 u8 macid, u8 role, bool connect); 2102 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 2103 u8 macid, u8 role, bool connect); 2104 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2105 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2106 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 2107 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 2108 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 2109 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 2110 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv); 2111 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2112 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2113 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2114 struct ieee80211_rx_status *rx_status, 2115 struct rtl8723au_phy_stats *phy_stats, 2116 u32 rxmcs, struct ieee80211_hdr *hdr, 2117 bool crc_icv_err); 2118 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2119 struct ieee80211_rx_status *rx_status, 2120 struct rtl8723au_phy_stats *phy_stats, 2121 u32 rxmcs, struct ieee80211_hdr *hdr, 2122 bool crc_icv_err); 2123 int rtl8xxxu_gen2_channel_to_group(int channel); 2124 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2125 int result[][8], int c1, int c2); 2126 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2127 int result[][8], int c1, int c2); 2128 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2129 struct ieee80211_tx_info *tx_info, 2130 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 2131 bool short_preamble, bool ampdu_enable, 2132 u32 rts_rate, u8 macid); 2133 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2134 struct ieee80211_tx_info *tx_info, 2135 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2136 bool short_preamble, bool ampdu_enable, 2137 u32 rts_rate, u8 macid); 2138 void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2139 struct ieee80211_tx_info *tx_info, 2140 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2141 bool short_preamble, bool ampdu_enable, 2142 u32 rts_rate, u8 macid); 2143 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 2144 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 2145 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); 2146 void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2147 void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2148 s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 2149 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 2150 u8 rate, u8 sgi, u8 bw); 2151 void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra); 2152 void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2153 2154 extern struct rtl8xxxu_fileops rtl8192fu_fops; 2155 extern struct rtl8xxxu_fileops rtl8710bu_fops; 2156 extern struct rtl8xxxu_fileops rtl8188fu_fops; 2157 extern struct rtl8xxxu_fileops rtl8188eu_fops; 2158 extern struct rtl8xxxu_fileops rtl8192cu_fops; 2159 extern struct rtl8xxxu_fileops rtl8192eu_fops; 2160 extern struct rtl8xxxu_fileops rtl8723au_fops; 2161 extern struct rtl8xxxu_fileops rtl8723bu_fops; 2162