1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*****************************************************************************
3  *	Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
4  *
5  * Module:	__INC_HAL8192SPHYREG_H
6  *
7  *
8  * Note:	1. Define PMAC/BB register map
9  *			2. Define RF register map
10  *			3. PMAC/BB register bit mask.
11  *			4. RF reg bit mask.
12  *			5. Other BB/RF relative definition.
13  *
14  *
15  * Export:	Constants, macro, functions(API), global variables(None).
16  *
17  * Abbrev:
18  *
19  * History:
20  *	Data			Who		Remark
21  *	08/07/2007	MHC		1. Porting from 9x series PHYCFG.h.
22  *						2. Reorganize code architecture.
23  *	09/25/2008	MH		1. Add RL6052 register definition
24  *
25  *****************************************************************************/
26 #ifndef __RTL871X_MP_PHY_REGDEF_H
27 #define __RTL871X_MP_PHY_REGDEF_H
28 
29 /*--------------------------Define Parameters-------------------------------*/
30 
31 /*============================================================
32  *       8192S Register offset definition
33  *============================================================
34  *
35  *
36  * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
37  * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
38  * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39  * 3. RF register 0x00-2E
40  * 4. Bit Mask for BB/RF register
41  * 5. Other definition for BB/RF R/W
42  *
43  * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
44  * 1. Page1(0x100)
45  */
46 #define	rPMAC_Reset			0x100
47 #define	rPMAC_TxStart			0x104
48 #define	rPMAC_TxLegacySIG		0x108
49 #define	rPMAC_TxHTSIG1			0x10c
50 #define	rPMAC_TxHTSIG2			0x110
51 #define	rPMAC_PHYDebug			0x114
52 #define	rPMAC_TxPacketNum		0x118
53 #define	rPMAC_TxIdle			0x11c
54 #define	rPMAC_TxMACHeader0		0x120
55 #define	rPMAC_TxMACHeader1		0x124
56 #define	rPMAC_TxMACHeader2		0x128
57 #define	rPMAC_TxMACHeader3		0x12c
58 #define	rPMAC_TxMACHeader4		0x130
59 #define	rPMAC_TxMACHeader5		0x134
60 #define	rPMAC_TxDataType		0x138
61 #define	rPMAC_TxRandomSeed		0x13c
62 #define	rPMAC_CCKPLCPPreamble		0x140
63 #define	rPMAC_CCKPLCPHeader		0x144
64 #define	rPMAC_CCKCRC16			0x148
65 #define	rPMAC_OFDMRxCRC32OK		0x170
66 #define	rPMAC_OFDMRxCRC32Er		0x174
67 #define	rPMAC_OFDMRxParityEr		0x178
68 #define	rPMAC_OFDMRxCRC8Er		0x17c
69 #define	rPMAC_CCKCRxRC16Er		0x180
70 #define	rPMAC_CCKCRxRC32Er		0x184
71 #define	rPMAC_CCKCRxRC32OK		0x188
72 #define	rPMAC_TxStatus			0x18c
73 
74 /*
75  * 2. Page2(0x200)
76  *
77  * The following two definition are only used for USB interface.
78  *#define RF_BB_CMD_ADDR	0x02c0	// RF/BB read/write command address.
79  *#define RF_BB_CMD_DATA	0x02c4	// RF/BB read/write command data.
80  *
81  *
82  * 3. Page8(0x800)
83  */
84 #define	rFPGA0_RFMOD			0x800	/*RF mode & CCK TxSC RF
85 						 * BW Setting??
86 						 */
87 #define	rFPGA0_TxInfo			0x804	/* Status report?? */
88 #define	rFPGA0_PSDFunction		0x808
89 #define	rFPGA0_TxGainStage		0x80c	/* Set TX PWR init gain? */
90 #define	rFPGA0_RFTiming1		0x810	/* Useless now */
91 #define	rFPGA0_RFTiming2		0x814
92 #define	rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
93 #define	rFPGA0_XA_HSSIParameter2	0x824
94 #define	rFPGA0_XB_HSSIParameter1	0x828
95 #define	rFPGA0_XB_HSSIParameter2	0x82c
96 #define	rFPGA0_XC_HSSIParameter1	0x830
97 #define	rFPGA0_XC_HSSIParameter2	0x834
98 #define	rFPGA0_XD_HSSIParameter1	0x838
99 #define	rFPGA0_XD_HSSIParameter2	0x83c
100 #define	rFPGA0_XA_LSSIParameter		0x840
101 #define	rFPGA0_XB_LSSIParameter		0x844
102 #define	rFPGA0_XC_LSSIParameter		0x848
103 #define	rFPGA0_XD_LSSIParameter		0x84c
104 
105 #define	rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
106 #define	rFPGA0_RFSleepUpParameter	0x854
107 
108 #define	rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
109 #define	rFPGA0_XCD_SwitchControl	0x85c
110 
111 #define	rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
112 #define	rFPGA0_XB_RFInterfaceOE		0x864
113 #define	rFPGA0_XC_RFInterfaceOE		0x868
114 #define	rFPGA0_XD_RFInterfaceOE		0x86c
115 #define	rFPGA0_XAB_RFInterfaceSW	0x870	/* RF Interface Software Ctrl */
116 #define	rFPGA0_XCD_RFInterfaceSW	0x874
117 
118 #define	rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
119 #define	rFPGA0_XCD_RFParameter		0x87c
120 
121 #define	rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting
122 						 * RF-R/W protection
123 						 * for parameter4??
124 						 */
125 #define	rFPGA0_AnalogParameter2		0x884
126 #define	rFPGA0_AnalogParameter3		0x888	/* Useless now */
127 #define	rFPGA0_AnalogParameter4		0x88c
128 
129 #define	rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
130 #define	rFPGA0_XB_LSSIReadBack		0x8a4
131 #define	rFPGA0_XC_LSSIReadBack		0x8a8
132 #define	rFPGA0_XD_LSSIReadBack		0x8ac
133 
134 #define	rFPGA0_PSDReport		0x8b4	/* Useless now */
135 #define	rFPGA0_XAB_RFInterfaceRB	0x8e0	/* Useless now */
136 #define	rFPGA0_XCD_RFInterfaceRB	0x8e4	/* Useless now */
137 
138 /*
139  * 4. Page9(0x900)
140  */
141 #define	rFPGA1_RFMOD			0x900	/* RF mode & OFDM TxSC */
142 
143 #define	rFPGA1_TxBlock			0x904	/* Useless now */
144 #define	rFPGA1_DebugSelect		0x908	/* Useless now */
145 #define	rFPGA1_TxInfo			0x90c	/* Useless now */
146 
147 /*
148  * 5. PageA(0xA00)
149  *
150  * Set Control channel to upper or lower.
151  * These settings are required only for 40MHz
152  */
153 #define	rCCK0_System			0xa00
154 
155 #define	rCCK0_AFESetting		0xa04	/* Disable init gain now */
156 #define	rCCK0_CCA			0xa08	/* Disable init gain now */
157 
158 #define	rCCK0_RxAGC1			0xa0c
159 /* AGC default value, saturation level
160  * Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now.
161  * Not the same as 90 series
162  */
163 #define	rCCK0_RxAGC2			0xa10	/* AGC & DAGC */
164 
165 #define	rCCK0_RxHP			0xa14
166 
167 #define	rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel
168 						 * estimation threshold
169 						 */
170 #define	rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
171 
172 #define	rCCK0_TxFilter1			0xa20
173 #define	rCCK0_TxFilter2			0xa24
174 #define	rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
175 #define	rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d useless now 0xa30-a4f
176 						 * channel report
177 						 */
178 #define	rCCK0_TRSSIReport		0xa50
179 #define	rCCK0_RxReport			0xa54   /* 0xa57 */
180 #define	rCCK0_FACounterLower		0xa5c   /* 0xa5b */
181 #define	rCCK0_FACounterUpper		0xa58   /* 0xa5c */
182 
183 /*
184  * 6. PageC(0xC00)
185  */
186 #define	rOFDM0_LSTF			0xc00
187 #define	rOFDM0_TRxPathEnable		0xc04
188 #define	rOFDM0_TRMuxPar			0xc08
189 #define	rOFDM0_TRSWIsolation		0xc0c
190 
191 /*RxIQ DC offset, Rx digital filter, DC notch filter */
192 #define	rOFDM0_XARxAFE			0xc10
193 #define	rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
194 #define	rOFDM0_XBRxAFE			0xc18
195 #define	rOFDM0_XBRxIQImbalance		0xc1c
196 #define	rOFDM0_XCRxAFE			0xc20
197 #define	rOFDM0_XCRxIQImbalance		0xc24
198 #define	rOFDM0_XDRxAFE			0xc28
199 #define	rOFDM0_XDRxIQImbalance		0xc2c
200 
201 #define	rOFDM0_RxDetector1		0xc30  /* PD,BW & SBD DM tune
202 						* init gain
203 						*/
204 #define	rOFDM0_RxDetector2		0xc34  /* SBD & Fame Sync. */
205 #define	rOFDM0_RxDetector3		0xc38  /* Frame Sync. */
206 #define	rOFDM0_RxDetector4		0xc3c  /* PD, SBD, Frame Sync &
207 						* Short-GI
208 						*/
209 
210 #define	rOFDM0_RxDSP			0xc40  /* Rx Sync Path */
211 #define	rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
212 #define	rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
213 #define	rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
214 
215 #define	rOFDM0_XAAGCCore1		0xc50	/* DIG */
216 #define	rOFDM0_XAAGCCore2		0xc54
217 #define	rOFDM0_XBAGCCore1		0xc58
218 #define	rOFDM0_XBAGCCore2		0xc5c
219 #define	rOFDM0_XCAGCCore1		0xc60
220 #define	rOFDM0_XCAGCCore2		0xc64
221 #define	rOFDM0_XDAGCCore1		0xc68
222 #define	rOFDM0_XDAGCCore2		0xc6c
223 #define	rOFDM0_AGCParameter1		0xc70
224 #define	rOFDM0_AGCParameter2		0xc74
225 #define	rOFDM0_AGCRSSITable		0xc78
226 #define	rOFDM0_HTSTFAGC			0xc7c
227 
228 #define	rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
229 #define	rOFDM0_XATxAFE			0xc84
230 #define	rOFDM0_XBTxIQImbalance		0xc88
231 #define	rOFDM0_XBTxAFE			0xc8c
232 #define	rOFDM0_XCTxIQImbalance		0xc90
233 #define	rOFDM0_XCTxAFE			0xc94
234 #define	rOFDM0_XDTxIQImbalance		0xc98
235 #define	rOFDM0_XDTxAFE			0xc9c
236 
237 #define	rOFDM0_RxHPParameter		0xce0
238 #define	rOFDM0_TxPseudoNoiseWgt		0xce4
239 #define	rOFDM0_FrameSync		0xcf0
240 #define	rOFDM0_DFSReport		0xcf4
241 #define	rOFDM0_TxCoeff1			0xca4
242 #define	rOFDM0_TxCoeff2			0xca8
243 #define	rOFDM0_TxCoeff3			0xcac
244 #define	rOFDM0_TxCoeff4			0xcb0
245 #define	rOFDM0_TxCoeff5			0xcb4
246 #define	rOFDM0_TxCoeff6			0xcb8
247 
248 /*
249  * 7. PageD(0xD00)
250  */
251 #define	rOFDM1_LSTF			0xd00
252 #define	rOFDM1_TRxPathEnable		0xd04
253 
254 #define	rOFDM1_CFO			0xd08	/* No setting now */
255 #define	rOFDM1_CSI1			0xd10
256 #define	rOFDM1_SBD			0xd14
257 #define	rOFDM1_CSI2			0xd18
258 #define	rOFDM1_CFOTracking		0xd2c
259 #define	rOFDM1_TRxMesaure1		0xd34
260 #define	rOFDM1_IntfDet			0xd3c
261 #define	rOFDM1_PseudoNoiseStateAB	0xd50
262 #define	rOFDM1_PseudoNoiseStateCD	0xd54
263 #define	rOFDM1_RxPseudoNoiseWgt		0xd58
264 
265 #define	rOFDM_PHYCounter1		0xda0  /* cca, parity fail */
266 #define	rOFDM_PHYCounter2		0xda4  /* rate illegal, crc8 fail */
267 #define	rOFDM_PHYCounter3		0xda8  /* MCS not support */
268 #define	rOFDM_ShortCFOAB		0xdac  /* No setting now */
269 #define	rOFDM_ShortCFOCD		0xdb0
270 #define	rOFDM_LongCFOAB			0xdb4
271 #define	rOFDM_LongCFOCD			0xdb8
272 #define	rOFDM_TailCFOAB			0xdbc
273 #define	rOFDM_TailCFOCD			0xdc0
274 #define	rOFDM_PWMeasure1		0xdc4
275 #define	rOFDM_PWMeasure2		0xdc8
276 #define	rOFDM_BWReport			0xdcc
277 #define	rOFDM_AGCReport			0xdd0
278 #define	rOFDM_RxSNR			0xdd4
279 #define	rOFDM_RxEVMCSI			0xdd8
280 #define	rOFDM_SIGReport			0xddc
281 
282 /*
283  * 8. PageE(0xE00)
284  */
285 #define	rTxAGC_Rate18_06		0xe00
286 #define	rTxAGC_Rate54_24		0xe04
287 #define	rTxAGC_CCK_Mcs32		0xe08
288 #define	rTxAGC_Mcs03_Mcs00		0xe10
289 #define	rTxAGC_Mcs07_Mcs04		0xe14
290 #define	rTxAGC_Mcs11_Mcs08		0xe18
291 #define	rTxAGC_Mcs15_Mcs12		0xe1c
292 
293 /* Analog- control in RX_WAIT_CCA : REG: EE0
294  * [Analog- Power & Control Register]
295  */
296 #define		rRx_Wait_CCCA		0xe70
297 #define	rAnapar_Ctrl_BB			0xee0
298 
299 /*
300  * 7. RF Register 0x00-0x2E (RF 8256)
301  *    RF-0222D 0x00-3F
302  *
303  * Zebra1
304  */
305 #define	rZebra1_HSSIEnable		0x0	/* Useless now */
306 #define	rZebra1_TRxEnable1		0x1
307 #define	rZebra1_TRxEnable2		0x2
308 #define	rZebra1_AGC			0x4
309 #define	rZebra1_ChargePump		0x5
310 #define	rZebra1_Channel			0x7	/* RF channel switch */
311 #define	rZebra1_TxGain			0x8	/* Useless now */
312 #define	rZebra1_TxLPF			0x9
313 #define	rZebra1_RxLPF			0xb
314 #define	rZebra1_RxHPFCorner		0xc
315 
316 /* Zebra4 */
317 #define	rGlobalCtrl			0	/* Useless now */
318 #define	rRTL8256_TxLPF			19
319 #define	rRTL8256_RxLPF			11
320 
321 /* RTL8258 */
322 #define	rRTL8258_TxLPF			0x11	/* Useless now */
323 #define	rRTL8258_RxLPF			0x13
324 #define	rRTL8258_RSSILPF		0xa
325 
326 /* RL6052 Register definition */
327 #define	RF_AC				0x00
328 #define	RF_IQADJ_G1			0x01
329 #define	RF_IQADJ_G2			0x02
330 #define	RF_POW_TRSW			0x05
331 
332 #define	RF_GAIN_RX			0x06
333 #define	RF_GAIN_TX			0x07
334 
335 #define	RF_TXM_IDAC			0x08
336 #define	RF_BS_IQGEN			0x0F
337 
338 #define	RF_MODE1			0x10
339 #define	RF_MODE2			0x11
340 
341 #define	RF_RX_AGC_HP			0x12
342 #define	RF_TX_AGC			0x13
343 #define	RF_BIAS				0x14
344 #define	RF_IPA				0x15
345 #define	RF_POW_ABILITY			0x17
346 #define	RF_MODE_AG			0x18
347 #define	rRfChannel			0x18	/* RF channel and BW switch */
348 #define	RF_CHNLBW			0x18	/* RF channel and BW switch */
349 #define	RF_TOP				0x19
350 #define	RF_RX_G1			0x1A
351 #define	RF_RX_G2			0x1B
352 #define	RF_RX_BB2			0x1C
353 #define	RF_RX_BB1			0x1D
354 
355 #define	RF_RCK1				0x1E
356 #define	RF_RCK2				0x1F
357 
358 #define	RF_TX_G1			0x20
359 #define	RF_TX_G2			0x21
360 #define	RF_TX_G3			0x22
361 
362 #define	RF_TX_BB1			0x23
363 #define	RF_T_METER			0x24
364 
365 #define	RF_SYN_G1			0x25	/* RF TX Power control */
366 #define	RF_SYN_G2			0x26	/* RF TX Power control */
367 #define	RF_SYN_G3			0x27	/* RF TX Power control */
368 #define	RF_SYN_G4			0x28	/* RF TX Power control */
369 #define	RF_SYN_G5			0x29	/* RF TX Power control */
370 #define	RF_SYN_G6			0x2A	/* RF TX Power control */
371 #define	RF_SYN_G7			0x2B	/* RF TX Power control */
372 #define	RF_SYN_G8			0x2C	/* RF TX Power control */
373 
374 #define	RF_RCK_OS			0x30	/* RF TX PA control */
375 
376 #define	RF_TXPA_G1			0x31	/* RF TX PA control */
377 #define	RF_TXPA_G2			0x32	/* RF TX PA control */
378 #define	RF_TXPA_G3			0x33	/* RF TX PA control */
379 
380 /*
381  * Bit Mask
382  *
383  * 1. Page1(0x100)
384  */
385 #define	bBBResetB			0x100	/* Useless now? */
386 #define	bGlobalResetB			0x200
387 #define	bOFDMTxStart			0x4
388 #define	bCCKTxStart			0x8
389 #define	bCRC32Debug			0x100
390 #define	bPMACLoopback			0x10
391 #define	bTxLSIG				0xffffff
392 #define	bOFDMTxRate			0xf
393 #define	bOFDMTxReserved			0x10
394 #define	bOFDMTxLength			0x1ffe0
395 #define	bOFDMTxParity			0x20000
396 #define	bTxHTSIG1			0xffffff
397 #define	bTxHTMCSRate			0x7f
398 #define	bTxHTBW				0x80
399 #define	bTxHTLength			0xffff00
400 #define	bTxHTSIG2			0xffffff
401 #define	bTxHTSmoothing			0x1
402 #define	bTxHTSounding			0x2
403 #define	bTxHTReserved			0x4
404 #define	bTxHTAggreation			0x8
405 #define	bTxHTSTBC			0x30
406 #define	bTxHTAdvanceCoding		0x40
407 #define	bTxHTShortGI			0x80
408 #define	bTxHTNumberHT_LTF		0x300
409 #define	bTxHTCRC8			0x3fc00
410 #define	bCounterReset			0x10000
411 #define	bNumOfOFDMTx			0xffff
412 #define	bNumOfCCKTx			0xffff0000
413 #define	bTxIdleInterval			0xffff
414 #define	bOFDMService			0xffff0000
415 #define	bTxMACHeader			0xffffffff
416 #define	bTxDataInit			0xff
417 #define	bTxHTMode			0x100
418 #define	bTxDataType			0x30000
419 #define	bTxRandomSeed			0xffffffff
420 #define	bCCKTxPreamble			0x1
421 #define	bCCKTxSFD			0xffff0000
422 #define	bCCKTxSIG			0xff
423 #define	bCCKTxService			0xff00
424 #define	bCCKLengthExt			0x8000
425 #define	bCCKTxLength			0xffff0000
426 #define	bCCKTxCRC16			0xffff
427 #define	bCCKTxStatus			0x1
428 #define	bOFDMTxStatus			0x2
429 #define IS_BB_REG_OFFSET_92S(_Offset)	((_Offset >= 0x800) && \
430 					(_Offset <= 0xfff))
431 
432 /* 2. Page8(0x800) */
433 #define	bRFMOD			0x1	/* Reg 0x800 rFPGA0_RFMOD */
434 #define	bJapanMode		0x2
435 #define	bCCKTxSC		0x30
436 #define	bCCKEn			0x1000000
437 #define	bOFDMEn			0x2000000
438 
439 #define	bOFDMRxADCPhase         0x10000	/* Useless now */
440 #define	bOFDMTxDACPhase         0x40000
441 #define	bXATxAGC                0x3f
442 #define	bXBTxAGC                0xf00	/* Reg 80c rFPGA0_TxGainStage */
443 #define	bXCTxAGC                0xf000
444 #define	bXDTxAGC                0xf0000
445 
446 #define	bPAStart		0xf0000000	/* Useless now */
447 #define	bTRStart		0x00f00000
448 #define	bRFStart		0x0000f000
449 #define	bBBStart		0x000000f0
450 #define	bBBCCKStart		0x0000000f
451 #define	bPAEnd			0xf          /* Reg0x814 */
452 #define	bTREnd			0x0f000000
453 #define	bRFEnd			0x000f0000
454 #define	bCCAMask		0x000000f0   /* T2R */
455 #define	bR2RCCAMask		0x00000f00
456 #define	bHSSI_R2TDelay		0xf8000000
457 #define	bHSSI_T2RDelay		0xf80000
458 #define	bContTxHSSI		0x400     /* change gain at continue Tx */
459 #define	bIGFromCCK		0x200
460 #define	bAGCAddress		0x3f
461 #define	bRxHPTx			0x7000
462 #define	bRxHPT2R		0x38000
463 #define	bRxHPCCKIni		0xc0000
464 #define	bAGCTxCode		0xc00000
465 #define	bAGCRxCode		0x300000
466 #define	b3WireDataLength	0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParm1 */
467 #define	b3WireAddressLength	0x400
468 #define	b3WireRFPowerDown	0x1	/* Useless now */
469 #define	b5GPAPEPolarity		0x40000000
470 #define	b2GPAPEPolarity		0x80000000
471 #define	bRFSW_TxDefaultAnt	0x3
472 #define	bRFSW_TxOptionAnt	0x30
473 #define	bRFSW_RxDefaultAnt	0x300
474 #define	bRFSW_RxOptionAnt	0x3000
475 #define	bRFSI_3WireData		0x1
476 #define	bRFSI_3WireClock	0x2
477 #define	bRFSI_3WireLoad		0x4
478 #define	bRFSI_3WireRW		0x8
479 #define	bRFSI_3Wire		0xf
480 #define	bRFSI_RFENV		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
481 #define	bRFSI_TRSW		0x20	/* Useless now */
482 #define	bRFSI_TRSWB		0x40
483 #define	bRFSI_ANTSW		0x100
484 #define	bRFSI_ANTSWB		0x200
485 #define	bRFSI_PAPE		0x400
486 #define	bRFSI_PAPE5G		0x800
487 #define	bBandSelect		0x1
488 #define	bHTSIG2_GI		0x80
489 #define	bHTSIG2_Smoothing	0x01
490 #define	bHTSIG2_Sounding	0x02
491 #define	bHTSIG2_Aggreaton	0x08
492 #define	bHTSIG2_STBC		0x30
493 #define	bHTSIG2_AdvCoding	0x40
494 #define	bHTSIG2_NumOfHTLTF	0x300
495 #define	bHTSIG2_CRC8		0x3fc
496 #define	bHTSIG1_MCS		0x7f
497 #define	bHTSIG1_BandWidth	0x80
498 #define	bHTSIG1_HTLength	0xffff
499 #define	bLSIG_Rate		0xf
500 #define	bLSIG_Reserved		0x10
501 #define	bLSIG_Length		0x1fffe
502 #define	bLSIG_Parity		0x20
503 #define	bCCKRxPhase		0x4
504 #define	bLSSIReadAddress	0x7f800000   /* T65 RF */
505 #define	bLSSIReadEdge		0x80000000   /* LSSI "Read" edge signal */
506 #define	bLSSIReadBackData	0xfffff		/* T65 RF */
507 #define	bLSSIReadOKFlag		0x1000	/* Useless now */
508 #define	bCCKSampleRate		0x8       /*0: 44MHz, 1:88MHz*/
509 #define	bRegulator0Standby	0x1
510 #define	bRegulatorPLLStandby	0x2
511 #define	bRegulator1Standby	0x4
512 #define	bPLLPowerUp		0x8
513 #define	bDPLLPowerUp		0x10
514 #define	bDA10PowerUp		0x20
515 #define	bAD7PowerUp		0x200
516 #define	bDA6PowerUp		0x2000
517 #define	bXtalPowerUp		0x4000
518 #define	b40MDClkPowerUP		0x8000
519 #define	bDA6DebugMode		0x20000
520 #define	bDA6Swing		0x380000
521 
522 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
523 #define	bADClkPhase		0x4000000
524 
525 #define	b80MClkDelay		0x18000000	/* Useless */
526 #define	bAFEWatchDogEnable	0x20000000
527 
528 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
529 #define	bXtalCap01		0xc0000000
530 #define	bXtalCap23		0x3
531 #define	bXtalCap92x		0x0f000000
532 #define bXtalCap		0x0f000000
533 #define	bIntDifClkEnable	0x400	/* Useless */
534 #define	bExtSigClkEnable	0x800
535 #define	bBandgapMbiasPowerUp	0x10000
536 #define	bAD11SHGain		0xc0000
537 #define	bAD11InputRange		0x700000
538 #define	bAD11OPCurrent		0x3800000
539 #define	bIPathLoopback		0x4000000
540 #define	bQPathLoopback		0x8000000
541 #define	bAFELoopback		0x10000000
542 #define	bDA10Swing		0x7e0
543 #define	bDA10Reverse		0x800
544 #define	bDAClkSource		0x1000
545 #define	bAD7InputRange		0x6000
546 #define	bAD7Gain		0x38000
547 #define	bAD7OutputCMMode	0x40000
548 #define	bAD7InputCMMode		0x380000
549 #define	bAD7Current		0xc00000
550 #define	bRegulatorAdjust	0x7000000
551 #define	bAD11PowerUpAtTx	0x1
552 #define	bDA10PSAtTx		0x10
553 #define	bAD11PowerUpAtRx	0x100
554 #define	bDA10PSAtRx		0x1000
555 #define	bCCKRxAGCFormat		0x200
556 #define	bPSDFFTSamplepPoint	0xc000
557 #define	bPSDAverageNum		0x3000
558 #define	bIQPathControl		0xc00
559 #define	bPSDFreq		0x3ff
560 #define	bPSDAntennaPath		0x30
561 #define	bPSDIQSwitch		0x40
562 #define	bPSDRxTrigger		0x400000
563 #define	bPSDTxTrigger		0x80000000
564 #define	bPSDSineToneScale	0x7f000000
565 #define	bPSDReport		0xffff
566 
567 /* 3. Page9(0x900) */
568 #define	bOFDMTxSC		0x30000000	/* Useless */
569 #define	bCCKTxOn		0x1
570 #define	bOFDMTxOn		0x2
571 #define	bDebugPage		0xfff  /* reset debug page and HWord, LWord */
572 #define	bDebugItem		0xff   /* reset debug page and LWord */
573 #define	bAntL			0x10
574 #define	bAntNonHT		0x100
575 #define	bAntHT1			0x1000
576 #define	bAntHT2			0x10000
577 #define	bAntHT1S1		0x100000
578 #define	bAntNonHTS1		0x1000000
579 
580 /* 4. PageA(0xA00) */
581 #define	bCCKBBMode		0x3	/* Useless */
582 #define	bCCKTxPowerSaving	0x80
583 #define	bCCKRxPowerSaving	0x40
584 
585 #define	bCCKSideBand		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch*/
586 #define	bCCKScramble		0x8	/* Useless */
587 #define	bCCKAntDiversity	0x8000
588 #define	bCCKCarrierRecovery	0x4000
589 #define	bCCKTxRate		0x3000
590 #define	bCCKDCCancel		0x0800
591 #define	bCCKISICancel		0x0400
592 #define	bCCKMatchFilter		0x0200
593 #define	bCCKEqualizer		0x0100
594 #define	bCCKPreambleDetect	0x800000
595 #define	bCCKFastFalseCCA	0x400000
596 #define	bCCKChEstStart		0x300000
597 #define	bCCKCCACount		0x080000
598 #define	bCCKcs_lim		0x070000
599 #define	bCCKBistMode		0x80000000
600 #define	bCCKCCAMask		0x40000000
601 #define	bCCKTxDACPhase		0x4
602 #define	bCCKRxADCPhase		0x20000000   /* r_rx_clk */
603 #define	bCCKr_cp_mode0		0x0100
604 #define	bCCKTxDCOffset		0xf0
605 #define	bCCKRxDCOffset		0xf
606 #define	bCCKCCAMode		0xc000
607 #define	bCCKFalseCS_lim		0x3f00
608 #define	bCCKCS_ratio		0xc00000
609 #define	bCCKCorgBit_sel		0x300000
610 #define	bCCKPD_lim		0x0f0000
611 #define	bCCKNewCCA		0x80000000
612 #define	bCCKRxHPofIG		0x8000
613 #define	bCCKRxIG		0x7f00
614 #define	bCCKLNAPolarity		0x800000
615 #define	bCCKRx1stGain		0x7f0000
616 #define	bCCKRFExtend		0x20000000 /* CCK Rx initial gain polarity */
617 #define	bCCKRxAGCSatLevel	0x1f000000
618 #define	bCCKRxAGCSatCount       0xe0
619 #define	bCCKRxRFSettle          0x1f       /* AGCsamp_dly */
620 #define	bCCKFixedRxAGC          0x8000
621 #define	bCCKAntennaPolarity     0x2000
622 #define	bCCKTxFilterType        0x0c00
623 #define	bCCKRxAGCReportType	0x0300
624 #define	bCCKRxDAGCEn            0x80000000
625 #define	bCCKRxDAGCPeriod        0x20000000
626 #define	bCCKRxDAGCSatLevel	0x1f000000
627 #define	bCCKTimingRecovery      0x800000
628 #define	bCCKTxC0                0x3f0000
629 #define	bCCKTxC1                0x3f000000
630 #define	bCCKTxC2                0x3f
631 #define	bCCKTxC3                0x3f00
632 #define	bCCKTxC4                0x3f0000
633 #define	bCCKTxC5		0x3f000000
634 #define	bCCKTxC6		0x3f
635 #define	bCCKTxC7		0x3f00
636 #define	bCCKDebugPort		0xff0000
637 #define	bCCKDACDebug		0x0f000000
638 #define	bCCKFalseAlarmEnable	0x8000
639 #define	bCCKFalseAlarmRead	0x4000
640 #define	bCCKTRSSI		0x7f
641 #define	bCCKRxAGCReport		0xfe
642 #define	bCCKRxReport_AntSel	0x80000000
643 #define	bCCKRxReport_MFOff	0x40000000
644 #define	bCCKRxRxReport_SQLoss	0x20000000
645 #define	bCCKRxReport_Pktloss	0x10000000
646 #define	bCCKRxReport_Lockedbit	0x08000000
647 #define	bCCKRxReport_RateError	0x04000000
648 #define	bCCKRxReport_RxRate	0x03000000
649 #define	bCCKRxFACounterLower	0xff
650 #define	bCCKRxFACounterUpper	0xff000000
651 #define	bCCKRxHPAGCStart	0xe000
652 #define	bCCKRxHPAGCFinal	0x1c00
653 #define	bCCKRxFalseAlarmEnable	0x8000
654 #define	bCCKFACounterFreeze	0x4000
655 #define	bCCKTxPathSel		0x10000000
656 #define	bCCKDefaultRxPath	0xc000000
657 #define	bCCKOptionRxPath	0x3000000
658 
659 /* 5. PageC(0xC00) */
660 #define	bNumOfSTF		0x3	/* Useless */
661 #define	bShift_L                0xc0
662 #define	bGI_TH			0xc
663 #define	bRxPathA		0x1
664 #define	bRxPathB		0x2
665 #define	bRxPathC		0x4
666 #define	bRxPathD		0x8
667 #define	bTxPathA		0x1
668 #define	bTxPathB		0x2
669 #define	bTxPathC		0x4
670 #define	bTxPathD		0x8
671 #define	bTRSSIFreq		0x200
672 #define	bADCBackoff		0x3000
673 #define	bDFIRBackoff		0xc000
674 #define	bTRSSILatchPhase	0x10000
675 #define	bRxIDCOffset		0xff
676 #define	bRxQDCOffset		0xff00
677 #define	bRxDFIRMode		0x1800000
678 #define	bRxDCNFType		0xe000000
679 #define	bRXIQImb_A		0x3ff
680 #define	bRXIQImb_B		0xfc00
681 #define	bRXIQImb_C		0x3f0000
682 #define	bRXIQImb_D		0xffc00000
683 #define	bDC_dc_Notch		0x60000
684 #define	bRxNBINotch		0x1f000000
685 #define	bPD_TH			0xf
686 #define	bPD_TH_Opt2		0xc000
687 #define	bPWED_TH		0x700
688 #define	bIfMF_Win_L		0x800
689 #define	bPD_Option		0x1000
690 #define	bMF_Win_L		0xe000
691 #define	bBW_Search_L		0x30000
692 #define	bwin_enh_L		0xc0000
693 #define	bBW_TH			0x700000
694 #define	bED_TH2			0x3800000
695 #define	bBW_option		0x4000000
696 #define	bRatio_TH		0x18000000
697 #define	bWindow_L		0xe0000000
698 #define	bSBD_Option		0x1
699 #define	bFrame_TH		0x1c
700 #define	bFS_Option		0x60
701 #define	bDC_Slope_check		0x80
702 #define	bFGuard_Counter_DC_L	0xe00
703 #define	bFrame_Weight_Short	0x7000
704 #define	bSub_Tune		0xe00000
705 #define	bFrame_DC_Length	0xe000000
706 #define	bSBD_start_offset	0x30000000
707 #define	bFrame_TH_2		0x7
708 #define	bFrame_GI2_TH		0x38
709 #define	bGI2_Sync_en		0x40
710 #define	bSarch_Short_Early	0x300
711 #define	bSarch_Short_Late	0xc00
712 #define	bSarch_GI2_Late		0x70000
713 #define	bCFOAntSum		0x1
714 #define	bCFOAcc			0x2
715 #define	bCFOStartOffset		0xc
716 #define	bCFOLookBack		0x70
717 #define	bCFOSumWeight		0x80
718 #define	bDAGCEnable		0x10000
719 #define	bTXIQImb_A		0x3ff
720 #define	bTXIQImb_B		0xfc00
721 #define	bTXIQImb_C		0x3f0000
722 #define	bTXIQImb_D		0xffc00000
723 #define	bTxIDCOffset		0xff
724 #define	bTxQDCOffset		0xff00
725 #define	bTxDFIRMode		0x10000
726 #define	bTxPesudoNoiseOn	0x4000000
727 #define	bTxPesudoNoise_A	0xff
728 #define	bTxPesudoNoise_B	0xff00
729 #define	bTxPesudoNoise_C	0xff0000
730 #define	bTxPesudoNoise_D	0xff000000
731 #define	bCCADropOption		0x20000
732 #define	bCCADropThres		0xfff00000
733 #define	bEDCCA_H		0xf
734 #define	bEDCCA_L		0xf0
735 #define	bLambda_ED              0x300
736 #define	bRxInitialGain          0x7f
737 #define	bRxAntDivEn             0x80
738 #define	bRxAGCAddressForLNA     0x7f00
739 #define	bRxHighPowerFlow        0x8000
740 #define	bRxAGCFreezeThres       0xc0000
741 #define	bRxFreezeStep_AGC1      0x300000
742 #define	bRxFreezeStep_AGC2      0xc00000
743 #define	bRxFreezeStep_AGC3      0x3000000
744 #define	bRxFreezeStep_AGC0      0xc000000
745 #define	bRxRssi_Cmp_En          0x10000000
746 #define	bRxQuickAGCEn           0x20000000
747 #define	bRxAGCFreezeThresMode   0x40000000
748 #define	bRxOverFlowCheckType    0x80000000
749 #define	bRxAGCShift             0x7f
750 #define	bTRSW_Tri_Only          0x80
751 #define	bPowerThres             0x300
752 #define	bRxAGCEn                0x1
753 #define	bRxAGCTogetherEn        0x2
754 #define	bRxAGCMin               0x4
755 #define	bRxHP_Ini               0x7
756 #define	bRxHP_TRLNA             0x70
757 #define	bRxHP_RSSI              0x700
758 #define	bRxHP_BBP1              0x7000
759 #define	bRxHP_BBP2              0x70000
760 #define	bRxHP_BBP3              0x700000
761 #define	bRSSI_H                 0x7f0000     /* the threshold for high power */
762 #define	bRSSI_Gen               0x7f000000   /* the threshold for ant divers */
763 #define	bRxSettle_TRSW          0x7
764 #define	bRxSettle_LNA           0x38
765 #define	bRxSettle_RSSI          0x1c0
766 #define	bRxSettle_BBP           0xe00
767 #define	bRxSettle_RxHP          0x7000
768 #define	bRxSettle_AntSW_RSSI    0x38000
769 #define	bRxSettle_AntSW         0xc0000
770 #define	bRxProcessTime_DAGC     0x300000
771 #define	bRxSettle_HSSI          0x400000
772 #define	bRxProcessTime_BBPPW    0x800000
773 #define	bRxAntennaPowerShift    0x3000000
774 #define	bRSSITableSelect        0xc000000
775 #define	bRxHP_Final             0x7000000
776 #define	bRxHTSettle_BBP         0x7
777 #define	bRxHTSettle_HSSI        0x8
778 #define	bRxHTSettle_RxHP        0x70
779 #define	bRxHTSettle_BBPPW       0x80
780 #define	bRxHTSettle_Idle        0x300
781 #define	bRxHTSettle_Reserved    0x1c00
782 #define	bRxHTRxHPEn             0x8000
783 #define	bRxHTAGCFreezeThres     0x30000
784 #define	bRxHTAGCTogetherEn      0x40000
785 #define	bRxHTAGCMin             0x80000
786 #define	bRxHTAGCEn              0x100000
787 #define	bRxHTDAGCEn             0x200000
788 #define	bRxHTRxHP_BBP           0x1c00000
789 #define	bRxHTRxHP_Final         0xe0000000
790 #define	bRxPWRatioTH            0x3
791 #define	bRxPWRatioEn            0x4
792 #define	bRxMFHold               0x3800
793 #define	bRxPD_Delay_TH1         0x38
794 #define	bRxPD_Delay_TH2         0x1c0
795 #define	bRxPD_DC_COUNT_MAX      0x600
796 #define	bRxPD_Delay_TH          0x8000
797 #define	bRxProcess_Delay        0xf0000
798 #define	bRxSearchrange_GI2_Early 0x700000
799 #define	bRxFrame_Guard_Counter_L 0x3800000
800 #define	bRxSGI_Guard_L          0xc000000
801 #define	bRxSGI_Search_L         0x30000000
802 #define	bRxSGI_TH               0xc0000000
803 #define	bDFSCnt0                0xff
804 #define	bDFSCnt1                0xff00
805 #define	bDFSFlag                0xf0000
806 #define	bMFWeightSum            0x300000
807 #define	bMinIdxTH               0x7f000000
808 #define	bDAFormat               0x40000
809 #define	bTxChEmuEnable          0x01000000
810 #define	bTRSWIsolation_A        0x7f
811 #define	bTRSWIsolation_B        0x7f00
812 #define	bTRSWIsolation_C        0x7f0000
813 #define	bTRSWIsolation_D        0x7f000000
814 #define	bExtLNAGain             0x7c00
815 
816 /* 6. PageE(0xE00) */
817 #define	bSTBCEn                 0x4	/* Useless */
818 #define	bAntennaMapping         0x10
819 #define	bNss                    0x20
820 #define	bCFOAntSumD             0x200
821 #define	bPHYCounterReset        0x8000000
822 #define	bCFOReportGet           0x4000000
823 #define	bOFDMContinueTx         0x10000000
824 #define	bOFDMSingleCarrier      0x20000000
825 #define	bOFDMSingleTone         0x40000000
826 #define	bHTDetect               0x100
827 #define	bCFOEn                  0x10000
828 #define	bCFOValue               0xfff00000
829 #define	bSigTone_Re             0x3f
830 #define	bSigTone_Im             0x7f00
831 #define	bCounter_CCA            0xffff
832 #define	bCounter_ParityFail     0xffff0000
833 #define	bCounter_RateIllegal    0xffff
834 #define	bCounter_CRC8Fail       0xffff0000
835 #define	bCounter_MCSNoSupport   0xffff
836 #define	bCounter_FastSync       0xffff
837 #define	bShortCFO               0xfff
838 #define	bShortCFOTLength        12   /* total */
839 #define	bShortCFOFLength        11   /* fraction */
840 #define	bLongCFO                0x7ff
841 #define	bLongCFOTLength         11
842 #define	bLongCFOFLength         11
843 #define	bTailCFO                0x1fff
844 #define	bTailCFOTLength         13
845 #define	bTailCFOFLength         12
846 #define	bmax_en_pwdB            0xffff
847 #define	bCC_power_dB            0xffff0000
848 #define	bnoise_pwdB             0xffff
849 #define	bPowerMeasTLength       10
850 #define	bPowerMeasFLength       3
851 #define	bRx_HT_BW               0x1
852 #define	bRxSC                   0x6
853 #define	bRx_HT                  0x8
854 #define	bNB_intf_det_on         0x1
855 #define	bIntf_win_len_cfg       0x30
856 #define	bNB_Intf_TH_cfg         0x1c0
857 #define	bRFGain                 0x3f
858 #define	bTableSel               0x40
859 #define	bTRSW                   0x80
860 #define	bRxSNR_A                0xff
861 #define	bRxSNR_B                0xff00
862 #define	bRxSNR_C                0xff0000
863 #define	bRxSNR_D                0xff000000
864 #define	bSNREVMTLength          8
865 #define	bSNREVMFLength          1
866 #define	bCSI1st                 0xff
867 #define	bCSI2nd                 0xff00
868 #define	bRxEVM1st               0xff0000
869 #define	bRxEVM2nd               0xff000000
870 #define	bSIGEVM                 0xff
871 #define	bPWDB                   0xff00
872 #define	bSGIEN                  0x10000
873 
874 #define	bSFactorQAM1            0xf	/* Useless */
875 #define	bSFactorQAM2            0xf0
876 #define	bSFactorQAM3            0xf00
877 #define	bSFactorQAM4            0xf000
878 #define	bSFactorQAM5            0xf0000
879 #define	bSFactorQAM6            0xf0000
880 #define	bSFactorQAM7            0xf00000
881 #define	bSFactorQAM8            0xf000000
882 #define	bSFactorQAM9            0xf0000000
883 #define	bCSIScheme              0x100000
884 
885 #define	bNoiseLvlTopSet         0x3	/* Useless */
886 #define	bChSmooth               0x4
887 #define	bChSmoothCfg1           0x38
888 #define	bChSmoothCfg2           0x1c0
889 #define	bChSmoothCfg3           0xe00
890 #define	bChSmoothCfg4           0x7000
891 #define	bMRCMode                0x800000
892 #define	bTHEVMCfg               0x7000000
893 
894 #define	bLoopFitType            0x1	/* Useless */
895 #define	bUpdCFO                 0x40
896 #define	bUpdCFOOffData          0x80
897 #define	bAdvUpdCFO              0x100
898 #define	bAdvTimeCtrl            0x800
899 #define	bUpdClko                0x1000
900 #define	bFC                     0x6000
901 #define	bTrackingMode           0x8000
902 #define	bPhCmpEnable            0x10000
903 #define	bUpdClkoLTF             0x20000
904 #define	bComChCFO               0x40000
905 #define	bCSIEstiMode            0x80000
906 #define	bAdvUpdEqz              0x100000
907 #define	bUChCfg                 0x7000000
908 #define	bUpdEqz			0x8000000
909 
910 #define	bTxAGCRate18_06		0x7f7f7f7f	/* Useless */
911 #define	bTxAGCRate54_24		0x7f7f7f7f
912 #define	bTxAGCRateMCS32		0x7f
913 #define	bTxAGCRateCCK		0x7f00
914 #define	bTxAGCRateMCS3_MCS0	0x7f7f7f7f
915 #define	bTxAGCRateMCS7_MCS4	0x7f7f7f7f
916 #define	bTxAGCRateMCS11_MCS8	0x7f7f7f7f
917 #define	bTxAGCRateMCS15_MCS12	0x7f7f7f7f
918 
919 /* Rx Pseduo noise */
920 #define	bRxPesudoNoiseOn         0x20000000	/* Useless */
921 #define	bRxPesudoNoise_A         0xff
922 #define	bRxPesudoNoise_B         0xff00
923 #define	bRxPesudoNoise_C         0xff0000
924 #define	bRxPesudoNoise_D         0xff000000
925 #define	bPesudoNoiseState_A      0xffff
926 #define	bPesudoNoiseState_B      0xffff0000
927 #define	bPesudoNoiseState_C      0xffff
928 #define	bPesudoNoiseState_D      0xffff0000
929 
930 /* 7. RF Register
931  * Zebra1
932  */
933 #define	bZebra1_HSSIEnable        0x8		/* Useless */
934 #define	bZebra1_TRxControl        0xc00
935 #define	bZebra1_TRxGainSetting    0x07f
936 #define	bZebra1_RxCorner          0xc00
937 #define	bZebra1_TxChargePump      0x38
938 #define	bZebra1_RxChargePump      0x7
939 #define	bZebra1_ChannelNum        0xf80
940 #define	bZebra1_TxLPFBW           0x400
941 #define	bZebra1_RxLPFBW           0x600
942 
943 /*Zebra4 */
944 #define	bRTL8256RegModeCtrl1      0x100	/* Useless */
945 #define	bRTL8256RegModeCtrl0      0x40
946 #define	bRTL8256_TxLPFBW          0x18
947 #define	bRTL8256_RxLPFBW          0x600
948 
949 /* RTL8258 */
950 #define	bRTL8258_TxLPFBW          0xc	/* Useless */
951 #define	bRTL8258_RxLPFBW          0xc00
952 #define	bRTL8258_RSSILPFBW        0xc0
953 
954 /*
955  * Other Definition
956  */
957 
958 /* byte endable for sb_write */
959 #define	bByte0                    0x1	/* Useless */
960 #define	bByte1                    0x2
961 #define	bByte2                    0x4
962 #define	bByte3                    0x8
963 #define	bWord0                    0x3
964 #define	bWord1                    0xc
965 #define	bDWord                    0xf
966 
967 /* for PutRegsetting & GetRegSetting BitMask */
968 #define	bMaskByte0                0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
969 #define	bMaskByte1                0xff00
970 #define	bMaskByte2                0xff0000
971 #define	bMaskByte3                0xff000000
972 #define	bMaskHWord                0xffff0000
973 #define	bMaskLWord                0x0000ffff
974 #define	bMaskDWord                0xffffffff
975 
976 /* for PutRFRegsetting & GetRFRegSetting BitMask */
977 #define	bRFRegOffsetMask	0xfffff
978 #define	bEnable                   0x1	/* Useless */
979 #define	bDisable                  0x0
980 
981 #define	LeftAntenna               0x0	/* Useless */
982 #define	RightAntenna              0x1
983 
984 #define	tCheckTxStatus            500   /* 500ms Useless */
985 #define	tUpdateRxCounter          100   /* 100ms */
986 
987 #define	rateCCK     0	/* Useless */
988 #define	rateOFDM    1
989 #define	rateHT      2
990 
991 /* define Register-End */
992 #define	bPMAC_End       0x1ff	/* Useless */
993 #define	bFPGAPHY0_End   0x8ff
994 #define	bFPGAPHY1_End   0x9ff
995 #define	bCCKPHY0_End    0xaff
996 #define	bOFDMPHY0_End   0xcff
997 #define	bOFDMPHY1_End   0xdff
998 
999 #define	bPMACControl	0x0	/* Useless */
1000 #define	bWMACControl	0x1
1001 #define	bWNICControl	0x2
1002 
1003 #define	ANTENNA_A	0x1	/* Useless */
1004 #define	ANTENNA_B	0x2
1005 #define	ANTENNA_AB	0x3	/* ANTENNA_A |ANTENNA_B */
1006 
1007 #define	ANTENNA_C	0x4
1008 #define	ANTENNA_D	0x8
1009 
1010 /* accept all physical address */
1011 #define RCR_AAP		BIT(0)
1012 #define RCR_APM		BIT(1)		/* accept physical match */
1013 #define RCR_AM		BIT(2)		/* accept multicast */
1014 #define RCR_AB		BIT(3)		/* accept broadcast */
1015 #define RCR_ACRC32	BIT(5)		/* accept error packet */
1016 #define RCR_9356SEL	BIT(6)
1017 #define RCR_AICV	BIT(12)		/* Accept ICV error packet */
1018 #define RCR_RXFTH0	(BIT(13)|BIT(14)|BIT(15))	/* Rx FIFO threshold */
1019 #define RCR_ADF		BIT(18)		/* Accept Data(frame type) frame */
1020 #define RCR_ACF		BIT(19)		/* Accept control frame */
1021 #define RCR_AMF		BIT(20)		/* Accept management frame */
1022 #define RCR_ADD3	BIT(21)
1023 #define RCR_APWRMGT	BIT(22)		/* Accept power management packet */
1024 #define RCR_CBSSID	BIT(23)		/* Accept BSSID match packet */
1025 #define RCR_ENMARP	BIT(28)		/* enable mac auto reset phy */
1026 #define RCR_EnCS1	BIT(29)		/* enable carrier sense method 1 */
1027 #define RCR_EnCS2	BIT(30)		/* enable carrier sense method 2 */
1028 /* Rx Early mode is performed for packet size greater than 1536 */
1029 #define RCR_OnlyErlPkt	BIT(31)
1030 
1031 /*--------------------------Define Parameters-------------------------------*/
1032 
1033 #endif	/*__INC_HAL8192SPHYREG_H */
1034 
1035