1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A7795 ES2.0+ processor support - PFC hardware block.
4  *
5  * Copyright (C) 2015-2019 Renesas Electronics Corporation
6  */
7 
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <dm/pinctrl.h>
12 #include <linux/kernel.h>
13 
14 #include "sh_pfc.h"
15 
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 		   SH_PFC_PIN_CFG_PULL_UP | \
18 		   SH_PFC_PIN_CFG_PULL_DOWN)
19 
20 #define CPU_ALL_PORT(fn, sfx)						\
21 	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
22 	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
23 	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
24 	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
25 	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
26 	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
27 	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
28 	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
29 	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
30 	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
31 	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
32 	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
33 /*
34  * F_() : just information
35  * FM() : macro for FN_xxx / xxx_MARK
36  */
37 
38 /* GPSR0 */
39 #define GPSR0_15	F_(D15,			IP7_11_8)
40 #define GPSR0_14	F_(D14,			IP7_7_4)
41 #define GPSR0_13	F_(D13,			IP7_3_0)
42 #define GPSR0_12	F_(D12,			IP6_31_28)
43 #define GPSR0_11	F_(D11,			IP6_27_24)
44 #define GPSR0_10	F_(D10,			IP6_23_20)
45 #define GPSR0_9		F_(D9,			IP6_19_16)
46 #define GPSR0_8		F_(D8,			IP6_15_12)
47 #define GPSR0_7		F_(D7,			IP6_11_8)
48 #define GPSR0_6		F_(D6,			IP6_7_4)
49 #define GPSR0_5		F_(D5,			IP6_3_0)
50 #define GPSR0_4		F_(D4,			IP5_31_28)
51 #define GPSR0_3		F_(D3,			IP5_27_24)
52 #define GPSR0_2		F_(D2,			IP5_23_20)
53 #define GPSR0_1		F_(D1,			IP5_19_16)
54 #define GPSR0_0		F_(D0,			IP5_15_12)
55 
56 /* GPSR1 */
57 #define GPSR1_28	FM(CLKOUT)
58 #define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
59 #define GPSR1_26	F_(WE1_N,		IP5_7_4)
60 #define GPSR1_25	F_(WE0_N,		IP5_3_0)
61 #define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
62 #define GPSR1_23	F_(RD_N,		IP4_27_24)
63 #define GPSR1_22	F_(BS_N,		IP4_23_20)
64 #define GPSR1_21	F_(CS1_N,		IP4_19_16)
65 #define GPSR1_20	F_(CS0_N,		IP4_15_12)
66 #define GPSR1_19	F_(A19,			IP4_11_8)
67 #define GPSR1_18	F_(A18,			IP4_7_4)
68 #define GPSR1_17	F_(A17,			IP4_3_0)
69 #define GPSR1_16	F_(A16,			IP3_31_28)
70 #define GPSR1_15	F_(A15,			IP3_27_24)
71 #define GPSR1_14	F_(A14,			IP3_23_20)
72 #define GPSR1_13	F_(A13,			IP3_19_16)
73 #define GPSR1_12	F_(A12,			IP3_15_12)
74 #define GPSR1_11	F_(A11,			IP3_11_8)
75 #define GPSR1_10	F_(A10,			IP3_7_4)
76 #define GPSR1_9		F_(A9,			IP3_3_0)
77 #define GPSR1_8		F_(A8,			IP2_31_28)
78 #define GPSR1_7		F_(A7,			IP2_27_24)
79 #define GPSR1_6		F_(A6,			IP2_23_20)
80 #define GPSR1_5		F_(A5,			IP2_19_16)
81 #define GPSR1_4		F_(A4,			IP2_15_12)
82 #define GPSR1_3		F_(A3,			IP2_11_8)
83 #define GPSR1_2		F_(A2,			IP2_7_4)
84 #define GPSR1_1		F_(A1,			IP2_3_0)
85 #define GPSR1_0		F_(A0,			IP1_31_28)
86 
87 /* GPSR2 */
88 #define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
89 #define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
90 #define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
91 #define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
92 #define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
93 #define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
94 #define GPSR2_8		F_(PWM2_A,		IP1_27_24)
95 #define GPSR2_7		F_(PWM1_A,		IP1_23_20)
96 #define GPSR2_6		F_(PWM0,		IP1_19_16)
97 #define GPSR2_5		F_(IRQ5,		IP1_15_12)
98 #define GPSR2_4		F_(IRQ4,		IP1_11_8)
99 #define GPSR2_3		F_(IRQ3,		IP1_7_4)
100 #define GPSR2_2		F_(IRQ2,		IP1_3_0)
101 #define GPSR2_1		F_(IRQ1,		IP0_31_28)
102 #define GPSR2_0		F_(IRQ0,		IP0_27_24)
103 
104 /* GPSR3 */
105 #define GPSR3_15	F_(SD1_WP,		IP11_23_20)
106 #define GPSR3_14	F_(SD1_CD,		IP11_19_16)
107 #define GPSR3_13	F_(SD0_WP,		IP11_15_12)
108 #define GPSR3_12	F_(SD0_CD,		IP11_11_8)
109 #define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
110 #define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
111 #define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
112 #define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
113 #define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
114 #define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
115 #define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
116 #define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
117 #define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
118 #define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
119 #define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
120 #define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
121 
122 /* GPSR4 */
123 #define GPSR4_17	F_(SD3_DS,		IP11_7_4)
124 #define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
125 #define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
126 #define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
127 #define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
128 #define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
129 #define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
130 #define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
131 #define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
132 #define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
133 #define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
134 #define GPSR4_6		F_(SD2_DS,		IP9_27_24)
135 #define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
136 #define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
137 #define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
138 #define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
139 #define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
140 #define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
141 
142 /* GPSR5 */
143 #define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
144 #define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
145 #define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
146 #define GPSR5_22	FM(MSIOF0_RXD)
147 #define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
148 #define GPSR5_20	FM(MSIOF0_TXD)
149 #define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
150 #define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
151 #define GPSR5_17	FM(MSIOF0_SCK)
152 #define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
153 #define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
154 #define GPSR5_14	F_(HTX0,		IP13_19_16)
155 #define GPSR5_13	F_(HRX0,		IP13_15_12)
156 #define GPSR5_12	F_(HSCK0,		IP13_11_8)
157 #define GPSR5_11	F_(RX2_A,		IP13_7_4)
158 #define GPSR5_10	F_(TX2_A,		IP13_3_0)
159 #define GPSR5_9		F_(SCK2,		IP12_31_28)
160 #define GPSR5_8		F_(RTS1_N,		IP12_27_24)
161 #define GPSR5_7		F_(CTS1_N,		IP12_23_20)
162 #define GPSR5_6		F_(TX1_A,		IP12_19_16)
163 #define GPSR5_5		F_(RX1_A,		IP12_15_12)
164 #define GPSR5_4		F_(RTS0_N,		IP12_11_8)
165 #define GPSR5_3		F_(CTS0_N,		IP12_7_4)
166 #define GPSR5_2		F_(TX0,			IP12_3_0)
167 #define GPSR5_1		F_(RX0,			IP11_31_28)
168 #define GPSR5_0		F_(SCK0,		IP11_27_24)
169 
170 /* GPSR6 */
171 #define GPSR6_31	F_(USB2_CH3_OVC,	IP18_7_4)
172 #define GPSR6_30	F_(USB2_CH3_PWEN,	IP18_3_0)
173 #define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
174 #define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
175 #define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
176 #define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
177 #define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
178 #define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
179 #define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
180 #define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
181 #define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
182 #define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
183 #define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
184 #define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
185 #define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
186 #define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
187 #define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
188 #define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
189 #define GPSR6_13	FM(SSI_SDATA5)
190 #define GPSR6_12	FM(SSI_WS5)
191 #define GPSR6_11	FM(SSI_SCK5)
192 #define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
193 #define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
194 #define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
195 #define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
196 #define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
197 #define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
198 #define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
199 #define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
200 #define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
201 #define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
202 #define GPSR6_0		F_(SSI_SCK01239,		IP14_23_20)
203 
204 /* GPSR7 */
205 #define GPSR7_3		FM(GP7_03)
206 #define GPSR7_2		FM(GP7_02)
207 #define GPSR7_1		FM(AVS2)
208 #define GPSR7_0		FM(AVS1)
209 
210 
211 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
212 #define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 
232 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
233 #define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 
275 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
276 #define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 
307 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
308 #define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329 #define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 
337 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
338 #define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP16_3_0	FM(SSI_SCK6)		FM(USB2_PWEN)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_7_4	FM(SSI_WS6)		FM(USB2_OVC)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358 #define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359 #define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360 #define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361 #define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362 #define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP18_3_0	FM(USB2_CH3_PWEN)	F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364 #define IP18_7_4	FM(USB2_CH3_OVC)	F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
365 
366 #define PINMUX_GPSR	\
367 \
368 												GPSR6_31 \
369 												GPSR6_30 \
370 												GPSR6_29 \
371 		GPSR1_28									GPSR6_28 \
372 		GPSR1_27									GPSR6_27 \
373 		GPSR1_26									GPSR6_26 \
374 		GPSR1_25							GPSR5_25	GPSR6_25 \
375 		GPSR1_24							GPSR5_24	GPSR6_24 \
376 		GPSR1_23							GPSR5_23	GPSR6_23 \
377 		GPSR1_22							GPSR5_22	GPSR6_22 \
378 		GPSR1_21							GPSR5_21	GPSR6_21 \
379 		GPSR1_20							GPSR5_20	GPSR6_20 \
380 		GPSR1_19							GPSR5_19	GPSR6_19 \
381 		GPSR1_18							GPSR5_18	GPSR6_18 \
382 		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
383 		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
384 GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
385 GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
386 GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
387 GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
388 GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
389 GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
390 GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
391 GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
392 GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
393 GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
394 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
395 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
396 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
397 GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
398 GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
399 GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
400 
401 #define PINMUX_IPSR				\
402 \
403 FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
404 FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
405 FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
406 FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
407 FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
408 FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
409 FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
410 FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
411 \
412 FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
413 FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
414 FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
415 FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
416 FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
417 FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
418 FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
419 FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
420 \
421 FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
422 FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
423 FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
424 FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
425 FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
426 FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
427 FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
428 FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
429 \
430 FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
431 FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
432 FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
433 FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
434 FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
435 FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
436 FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
437 FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
438 \
439 FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
440 FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
441 FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
442 FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
443 FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
444 FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
445 FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
446 FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
447 
448 /* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
449 #define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
450 #define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
451 #define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
452 #define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
453 #define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
454 #define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
455 #define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
456 #define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
457 #define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
458 #define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
459 #define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
460 #define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
461 #define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
462 #define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
463 #define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
464 #define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
465 #define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
466 #define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
467 
468 /* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
469 #define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
470 #define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
471 #define MOD_SEL1_26		FM(SEL_TIMER_TMU1_0)	FM(SEL_TIMER_TMU1_1)
472 #define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
473 #define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
474 #define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
475 #define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
476 #define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
477 #define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
478 #define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
479 #define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
480 #define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
481 #define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
482 #define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
483 #define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
484 #define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
485 #define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
486 #define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
487 #define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
488 #define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
489 #define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
490 #define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
491 
492 /* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */
493 #define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
494 #define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
495 #define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
496 #define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
497 #define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
498 #define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
499 #define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
500 #define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
501 #define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
502 #define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
503 #define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
504 #define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
505 
506 #define PINMUX_MOD_SELS	\
507 \
508 MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
509 						MOD_SEL2_30 \
510 			MOD_SEL1_29_28_27	MOD_SEL2_29 \
511 MOD_SEL0_28_27					MOD_SEL2_28_27 \
512 MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
513 			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
514 MOD_SEL0_23		MOD_SEL1_23_22_21 \
515 MOD_SEL0_22 \
516 MOD_SEL0_21					MOD_SEL2_21 \
517 MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
518 MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
519 MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
520 						MOD_SEL2_17 \
521 MOD_SEL0_16		MOD_SEL1_16 \
522 			MOD_SEL1_15_14 \
523 MOD_SEL0_14_13 \
524 			MOD_SEL1_13 \
525 MOD_SEL0_12		MOD_SEL1_12 \
526 MOD_SEL0_11		MOD_SEL1_11 \
527 MOD_SEL0_10		MOD_SEL1_10 \
528 MOD_SEL0_9_8		MOD_SEL1_9 \
529 MOD_SEL0_7_6 \
530 			MOD_SEL1_6 \
531 MOD_SEL0_5		MOD_SEL1_5 \
532 MOD_SEL0_4_3		MOD_SEL1_4 \
533 			MOD_SEL1_3 \
534 			MOD_SEL1_2 \
535 			MOD_SEL1_1 \
536 			MOD_SEL1_0		MOD_SEL2_0
537 
538 /*
539  * These pins are not able to be muxed but have other properties
540  * that can be set, such as drive-strength or pull-up/pull-down enable.
541  */
542 #define PINMUX_STATIC \
543 	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 	FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 	FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
551 	FM(PRESETOUT) \
552 	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
554 
555 enum {
556 	PINMUX_RESERVED = 0,
557 
558 	PINMUX_DATA_BEGIN,
559 	GP_ALL(DATA),
560 	PINMUX_DATA_END,
561 
562 #define F_(x, y)
563 #define FM(x)	FN_##x,
564 	PINMUX_FUNCTION_BEGIN,
565 	GP_ALL(FN),
566 	PINMUX_GPSR
567 	PINMUX_IPSR
568 	PINMUX_MOD_SELS
569 	PINMUX_FUNCTION_END,
570 #undef F_
571 #undef FM
572 
573 #define F_(x, y)
574 #define FM(x)	x##_MARK,
575 	PINMUX_MARK_BEGIN,
576 	PINMUX_GPSR
577 	PINMUX_IPSR
578 	PINMUX_MOD_SELS
579 	PINMUX_STATIC
580 	PINMUX_MARK_END,
581 #undef F_
582 #undef FM
583 };
584 
585 static const u16 pinmux_data[] = {
586 	PINMUX_DATA_GP_ALL(),
587 
588 	PINMUX_SINGLE(AVS1),
589 	PINMUX_SINGLE(AVS2),
590 	PINMUX_SINGLE(CLKOUT),
591 	PINMUX_SINGLE(GP7_02),
592 	PINMUX_SINGLE(GP7_03),
593 	PINMUX_SINGLE(I2C_SEL_0_1),
594 	PINMUX_SINGLE(I2C_SEL_3_1),
595 	PINMUX_SINGLE(I2C_SEL_5_1),
596 	PINMUX_SINGLE(MSIOF0_RXD),
597 	PINMUX_SINGLE(MSIOF0_SCK),
598 	PINMUX_SINGLE(MSIOF0_TXD),
599 	PINMUX_SINGLE(SSI_SCK5),
600 	PINMUX_SINGLE(SSI_SDATA5),
601 	PINMUX_SINGLE(SSI_WS5),
602 
603 	/* IPSR0 */
604 	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
605 	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
606 
607 	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
608 	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
609 	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
610 
611 	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
612 	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
613 	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
614 
615 	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
616 	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
617 	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
618 
619 	PINMUX_IPSR_MSEL(IP0_19_16,	AVB_AVTP_MATCH_A,	SEL_ETHERAVB_0),
620 	PINMUX_IPSR_MSEL(IP0_19_16,	MSIOF2_RXD_C,		SEL_MSIOF2_2),
621 	PINMUX_IPSR_MSEL(IP0_19_16,	CTS4_N_A,		SEL_SCIF4_0),
622 	PINMUX_IPSR_GPSR(IP0_19_16,	FSCLKST2_N_A),
623 
624 	PINMUX_IPSR_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	SEL_ETHERAVB_0),
625 	PINMUX_IPSR_MSEL(IP0_23_20,	MSIOF2_TXD_C,		SEL_MSIOF2_2),
626 	PINMUX_IPSR_MSEL(IP0_23_20,	RTS4_N_A,		SEL_SCIF4_0),
627 
628 	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
629 	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
630 	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
631 	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
632 	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
633 	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
634 	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
635 
636 	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
637 	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
638 	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
639 	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
640 	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
641 	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
642 	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
643 
644 	/* IPSR1 */
645 	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
646 	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
647 	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
648 	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
649 	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
650 	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
651 
652 	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
653 	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
654 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
655 	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
656 	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
657 	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
658 
659 	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
660 	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
661 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
662 	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
663 	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
664 	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
665 
666 	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
667 	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
668 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
669 	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
670 	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
671 	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
672 	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
673 
674 	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
675 	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
676 	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
677 	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
678 
679 	PINMUX_IPSR_MSEL(IP1_23_20,	PWM1_A,			SEL_PWM1_0),
680 	PINMUX_IPSR_MSEL(IP1_23_20,	HRX3_D,			SEL_HSCIF3_3),
681 	PINMUX_IPSR_MSEL(IP1_23_20,	VI4_DATA7_B,		SEL_VIN4_1),
682 	PINMUX_IPSR_MSEL(IP1_23_20,	IERX_B,			SEL_IEBUS_1),
683 
684 	PINMUX_IPSR_MSEL(IP1_27_24,	PWM2_A,			SEL_PWM2_0),
685 	PINMUX_IPSR_MSEL(IP1_27_24,	HTX3_D,			SEL_HSCIF3_3),
686 	PINMUX_IPSR_MSEL(IP1_27_24,	IETX_B,			SEL_IEBUS_1),
687 
688 	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
689 	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
690 	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
691 	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
692 	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
693 	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
694 
695 	/* IPSR2 */
696 	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
697 	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
698 	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
699 	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
700 	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
701 	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
702 
703 	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
704 	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
705 	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
706 	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
707 	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
708 	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
709 
710 	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
711 	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
712 	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
713 	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
714 	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
715 	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
716 
717 	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
718 	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
719 	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
720 	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
721 	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
722 	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
723 
724 	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
725 	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
726 	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
727 	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
728 	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
729 	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
730 	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
731 
732 	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
733 	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
734 	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
735 	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
736 	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
737 	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
738 	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
739 
740 	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
741 	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
742 	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
743 	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
744 	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
745 	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
746 	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
747 
748 	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
749 	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
750 	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
751 	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
752 	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
753 	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
754 	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
755 
756 	/* IPSR3 */
757 	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
758 	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
759 	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
760 	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
761 
762 	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
763 	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
764 	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
765 	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
766 
767 	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
768 	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
769 	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
770 	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
771 	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
772 	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
773 	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
774 	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
775 	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
776 
777 	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
778 	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
779 	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
780 	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
781 	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
782 	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
783 
784 	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
785 	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
786 	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
787 	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
788 	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
789 	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
790 
791 	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
792 	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
793 	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
794 	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
795 	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
796 	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
797 
798 	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
799 	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
800 	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
801 	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
802 	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
803 	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
804 
805 	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
806 	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
807 	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
808 	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
809 
810 	/* IPSR4 */
811 	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
812 	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
813 	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
814 	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
815 
816 	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
817 	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
818 	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
819 	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
820 
821 	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
822 	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
823 	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
824 	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
825 
826 	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
827 	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
828 
829 	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
830 	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
831 	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
832 
833 	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
834 	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
835 	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
836 	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
837 	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
838 	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
839 	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
840 	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
841 
842 	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
843 	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
844 	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
845 	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
846 	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
847 	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
848 
849 	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
850 	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
851 	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
852 	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
853 	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
854 	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
855 
856 	/* IPSR5 */
857 	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
858 	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
859 	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
860 	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
861 	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
862 	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
863 	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
864 
865 	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
866 	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
867 	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
868 	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
869 	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
870 	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
871 	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
872 	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
873 
874 	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
875 	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
876 	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
877 	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
878 
879 	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
880 	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
881 	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
882 	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
883 	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
884 
885 	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
886 	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
887 	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
888 	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
889 	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
890 
891 	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
892 	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
893 	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
894 	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
895 
896 	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
897 	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
898 	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
899 	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
900 
901 	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
902 	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
903 	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
904 	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
905 
906 	/* IPSR6 */
907 	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
908 	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
909 	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
910 	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
911 
912 	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
913 	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
914 	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
915 	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
916 
917 	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
918 	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
919 	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
920 	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
921 
922 	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
923 	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
924 	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
925 	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
926 	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
927 	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
928 
929 	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
930 	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
931 	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
932 	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
933 	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
934 
935 	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
936 	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
937 	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
938 	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
939 	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
940 	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
941 	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
942 
943 	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
944 	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
945 	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
946 	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
947 	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
948 	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
949 	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
950 
951 	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
952 	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
953 	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
954 	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
955 	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
956 	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
957 
958 	/* IPSR7 */
959 	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
960 	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
961 	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
962 	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
963 	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
964 	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
965 
966 	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
967 	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
968 	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
969 	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
970 	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
971 	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
972 	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
973 
974 	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
975 	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
976 	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
977 	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
978 	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
979 	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
980 	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
981 
982 	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
983 	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
984 	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
985 
986 	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
987 	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
988 	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
989 
990 	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
991 	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
992 	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
993 	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
994 
995 	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
996 	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
997 	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
998 	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
999 
1000 	/* IPSR8 */
1001 	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
1002 	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
1003 	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
1004 	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
1005 
1006 	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
1007 	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
1008 	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
1009 	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
1010 
1011 	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
1012 	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
1013 	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
1014 
1015 	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
1016 	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
1017 	PINMUX_IPSR_GPSR(IP8_15_12,	NFCE_N_B),
1018 	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
1019 	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
1020 
1021 	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
1022 	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
1023 	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
1024 	PINMUX_IPSR_GPSR(IP8_19_16,	NFWP_N_B),
1025 	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
1026 	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
1027 
1028 	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
1029 	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
1030 	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
1031 	PINMUX_IPSR_GPSR(IP8_23_20,	NFDATA14_B),
1032 	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
1033 	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
1034 
1035 	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
1036 	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
1037 	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
1038 	PINMUX_IPSR_GPSR(IP8_27_24,	NFDATA15_B),
1039 	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
1040 	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
1041 
1042 	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
1043 	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
1044 	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
1045 	PINMUX_IPSR_GPSR(IP8_31_28,	NFRB_N_B),
1046 	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
1047 	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
1048 
1049 	/* IPSR9 */
1050 	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
1051 	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
1052 
1053 	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
1054 	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
1055 
1056 	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
1057 	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
1058 
1059 	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
1060 	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
1061 
1062 	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
1063 	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
1064 
1065 	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
1066 	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
1067 
1068 	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
1069 	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
1070 	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
1071 
1072 	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
1073 	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
1074 
1075 	/* IPSR10 */
1076 	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
1077 	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
1078 
1079 	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
1080 	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
1081 
1082 	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
1083 	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
1084 
1085 	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
1086 	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
1087 
1088 	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
1089 	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
1090 
1091 	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
1092 	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
1093 	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
1094 
1095 	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
1096 	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
1097 	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
1098 
1099 	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
1100 	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
1101 	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
1102 
1103 	/* IPSR11 */
1104 	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
1105 	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
1106 	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
1107 
1108 	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
1109 	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
1110 
1111 	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
1112 	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
1113 	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
1114 
1115 	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
1116 	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
1117 
1118 	PINMUX_IPSR_GPSR(IP11_19_16,	SD1_CD),
1119 	PINMUX_IPSR_MSEL(IP11_19_16,	SIM0_CLK_B,		SEL_SIMCARD_1),
1120 
1121 	PINMUX_IPSR_GPSR(IP11_23_20,	SD1_WP),
1122 	PINMUX_IPSR_MSEL(IP11_23_20,	SIM0_D_B,		SEL_SIMCARD_1),
1123 
1124 	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
1125 	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
1126 	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
1127 	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
1128 	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
1129 	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
1130 	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
1131 	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
1132 	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
1133 	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
1134 
1135 	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
1136 	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
1137 	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
1138 	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
1139 	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
1140 
1141 	/* IPSR12 */
1142 	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
1143 	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
1144 	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
1145 	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
1146 	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
1147 
1148 	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
1149 	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
1150 	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
1151 	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
1152 	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
1153 	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
1154 	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
1155 	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
1156 
1157 	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
1158 	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
1159 	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
1160 	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
1161 	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
1162 	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
1163 	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
1164 	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
1165 
1166 	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
1167 	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
1168 	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
1169 	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
1170 	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
1171 
1172 	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
1173 	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
1174 	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
1175 	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
1176 	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
1177 
1178 	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
1179 	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
1180 	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
1181 	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
1182 	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
1183 	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
1184 	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
1185 
1186 	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
1187 	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
1188 	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
1189 	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
1190 	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
1191 	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
1192 	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
1193 
1194 	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
1195 	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
1196 	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
1197 	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
1198 	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
1199 	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
1200 	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
1201 
1202 	/* IPSR13 */
1203 	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
1204 	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
1205 	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
1206 	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
1207 	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
1208 	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
1209 
1210 	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
1211 	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
1212 	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
1213 	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
1214 	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
1215 	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
1216 
1217 	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
1218 	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
1219 	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
1220 	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
1221 	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
1222 	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
1223 	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
1224 	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
1225 
1226 	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
1227 	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
1228 	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
1229 	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
1230 	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
1231 	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
1232 
1233 	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
1234 	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
1235 	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
1236 	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
1237 	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
1238 	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
1239 
1240 	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
1241 	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
1242 	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
1243 	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
1244 	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
1245 	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
1246 	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
1247 	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
1248 
1249 	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
1250 	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
1251 	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
1252 	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
1253 	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
1254 	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
1255 	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
1256 
1257 	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
1258 	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
1259 	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
1260 	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
1261 
1262 	/* IPSR14 */
1263 	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
1264 	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
1265 	PINMUX_IPSR_GPSR(IP14_3_0,	NFWP_N_A),
1266 	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
1267 	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
1268 	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
1269 	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
1270 	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU1_1),
1271 
1272 	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
1273 	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
1274 	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
1275 	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
1276 	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
1277 	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
1278 	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
1279 	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
1280 
1281 	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
1282 	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
1283 	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
1284 
1285 	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
1286 	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
1287 	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
1288 	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
1289 
1290 	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
1291 	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
1292 	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
1293 
1294 	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
1295 	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
1296 
1297 	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
1298 	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
1299 
1300 	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
1301 	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
1302 
1303 	/* IPSR15 */
1304 	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
1305 
1306 	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
1307 	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
1308 
1309 	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
1310 	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
1311 	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
1312 
1313 	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
1314 	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
1315 	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
1316 	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
1317 
1318 	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
1319 	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
1320 	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
1321 	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
1322 	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
1323 	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
1324 	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
1325 
1326 	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
1327 	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
1328 	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
1329 	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
1330 	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
1331 	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
1332 	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
1333 
1334 	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
1335 	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
1336 	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
1337 	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
1338 	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
1339 	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
1340 	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
1341 
1342 	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
1343 	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
1344 	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
1345 	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
1346 	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
1347 	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
1348 	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
1349 
1350 	/* IPSR16 */
1351 	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
1352 	PINMUX_IPSR_GPSR(IP16_3_0,	USB2_PWEN),
1353 	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
1354 
1355 	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
1356 	PINMUX_IPSR_GPSR(IP16_7_4,	USB2_OVC),
1357 	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
1358 
1359 	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
1360 	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
1361 	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
1362 
1363 	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
1364 	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
1365 	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
1366 	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
1367 	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
1368 	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
1369 	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
1370 
1371 	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
1372 	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
1373 	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
1374 	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
1375 	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
1376 	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
1377 	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
1378 
1379 	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
1380 	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
1381 	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
1382 	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
1383 	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
1384 	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
1385 	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
1386 	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
1387 
1388 	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
1389 	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
1390 	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
1391 	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
1392 	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
1393 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
1394 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
1395 
1396 	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
1397 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
1398 	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
1399 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
1400 	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
1401 	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
1402 	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
1403 	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
1404 
1405 	/* IPSR17 */
1406 	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
1407 
1408 	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
1409 	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
1410 	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
1411 	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
1412 	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU1_0),
1413 
1414 	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
1415 	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
1416 	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
1417 	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
1418 	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
1419 	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
1420 	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
1421 
1422 	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
1423 	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
1424 	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
1425 	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
1426 	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
1427 	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
1428 
1429 	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
1430 	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
1431 	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
1432 	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
1433 	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
1434 	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
1435 	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
1436 	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
1437 	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
1438 
1439 	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
1440 	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
1441 	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
1442 	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
1443 	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
1444 	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
1445 	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
1446 	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
1447 	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
1448 
1449 	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
1450 	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
1451 	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
1452 	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
1453 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
1454 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
1455 	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
1456 	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
1457 	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
1458 	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
1459 	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
1460 
1461 	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
1462 	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
1463 	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
1464 	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
1465 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
1466 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
1467 	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
1468 	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
1469 	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
1470 
1471 	/* IPSR18 */
1472 	PINMUX_IPSR_GPSR(IP18_3_0,	USB2_CH3_PWEN),
1473 	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
1474 	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
1475 	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
1476 	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
1477 	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
1478 	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
1479 	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
1480 	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
1481 
1482 	PINMUX_IPSR_GPSR(IP18_7_4,	USB2_CH3_OVC),
1483 	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
1484 	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
1485 	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
1486 	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
1487 	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
1488 	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
1489 	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
1490 	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
1491 
1492 /*
1493  * Static pins can not be muxed between different functions but
1494  * still needs a mark entry in the pinmux list. Add each static
1495  * pin to the list without an associated function. The sh-pfc
1496  * core will do the right thing and skip trying to mux then pin
1497  * while still applying configuration to it
1498  */
1499 #define FM(x)	PINMUX_DATA(x##_MARK, 0),
1500 	PINMUX_STATIC
1501 #undef FM
1502 };
1503 
1504 /*
1505  * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1506  * Physical layout rows: A - AW, cols: 1 - 39.
1507  */
1508 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1509 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1510 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1511 #define PIN_NONE U16_MAX
1512 
1513 static const struct sh_pfc_pin pinmux_pins[] = {
1514 	PINMUX_GPIO_GP_ALL(),
1515 
1516 	/*
1517 	 * Pins not associated with a GPIO port.
1518 	 *
1519 	 * The pin positions are different between different r8a7795
1520 	 * packages, all that is needed for the pfc driver is a unique
1521 	 * number for each pin. To this end use the pin layout from
1522 	 * R-Car H3SiP to calculate a unique number for each pin.
1523 	 */
1524 	SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1525 	SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1526 	SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1527 	SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1528 	SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1529 	SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1530 	SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1531 	SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1532 	SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1533 	SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1534 	SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1535 	SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1536 	SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1537 	SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1538 	SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1539 	SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1540 	SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1541 	SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1542 	SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1543 	SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1544 	SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1545 	SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1546 	SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1547 	SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1548 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1549 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1550 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1551 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1552 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1553 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1554 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1555 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1556 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1557 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1558 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1559 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),
1560 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1561 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1562 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1563 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1564 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1566 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1567 };
1568 
1569 /* - AUDIO CLOCK ------------------------------------------------------------ */
1570 static const unsigned int audio_clk_a_a_pins[] = {
1571 	/* CLK A */
1572 	RCAR_GP_PIN(6, 22),
1573 };
1574 static const unsigned int audio_clk_a_a_mux[] = {
1575 	AUDIO_CLKA_A_MARK,
1576 };
1577 static const unsigned int audio_clk_a_b_pins[] = {
1578 	/* CLK A */
1579 	RCAR_GP_PIN(5, 4),
1580 };
1581 static const unsigned int audio_clk_a_b_mux[] = {
1582 	AUDIO_CLKA_B_MARK,
1583 };
1584 static const unsigned int audio_clk_a_c_pins[] = {
1585 	/* CLK A */
1586 	RCAR_GP_PIN(5, 19),
1587 };
1588 static const unsigned int audio_clk_a_c_mux[] = {
1589 	AUDIO_CLKA_C_MARK,
1590 };
1591 static const unsigned int audio_clk_b_a_pins[] = {
1592 	/* CLK B */
1593 	RCAR_GP_PIN(5, 12),
1594 };
1595 static const unsigned int audio_clk_b_a_mux[] = {
1596 	AUDIO_CLKB_A_MARK,
1597 };
1598 static const unsigned int audio_clk_b_b_pins[] = {
1599 	/* CLK B */
1600 	RCAR_GP_PIN(6, 23),
1601 };
1602 static const unsigned int audio_clk_b_b_mux[] = {
1603 	AUDIO_CLKB_B_MARK,
1604 };
1605 static const unsigned int audio_clk_c_a_pins[] = {
1606 	/* CLK C */
1607 	RCAR_GP_PIN(5, 21),
1608 };
1609 static const unsigned int audio_clk_c_a_mux[] = {
1610 	AUDIO_CLKC_A_MARK,
1611 };
1612 static const unsigned int audio_clk_c_b_pins[] = {
1613 	/* CLK C */
1614 	RCAR_GP_PIN(5, 0),
1615 };
1616 static const unsigned int audio_clk_c_b_mux[] = {
1617 	AUDIO_CLKC_B_MARK,
1618 };
1619 static const unsigned int audio_clkout_a_pins[] = {
1620 	/* CLKOUT */
1621 	RCAR_GP_PIN(5, 18),
1622 };
1623 static const unsigned int audio_clkout_a_mux[] = {
1624 	AUDIO_CLKOUT_A_MARK,
1625 };
1626 static const unsigned int audio_clkout_b_pins[] = {
1627 	/* CLKOUT */
1628 	RCAR_GP_PIN(6, 28),
1629 };
1630 static const unsigned int audio_clkout_b_mux[] = {
1631 	AUDIO_CLKOUT_B_MARK,
1632 };
1633 static const unsigned int audio_clkout_c_pins[] = {
1634 	/* CLKOUT */
1635 	RCAR_GP_PIN(5, 3),
1636 };
1637 static const unsigned int audio_clkout_c_mux[] = {
1638 	AUDIO_CLKOUT_C_MARK,
1639 };
1640 static const unsigned int audio_clkout_d_pins[] = {
1641 	/* CLKOUT */
1642 	RCAR_GP_PIN(5, 21),
1643 };
1644 static const unsigned int audio_clkout_d_mux[] = {
1645 	AUDIO_CLKOUT_D_MARK,
1646 };
1647 static const unsigned int audio_clkout1_a_pins[] = {
1648 	/* CLKOUT1 */
1649 	RCAR_GP_PIN(5, 15),
1650 };
1651 static const unsigned int audio_clkout1_a_mux[] = {
1652 	AUDIO_CLKOUT1_A_MARK,
1653 };
1654 static const unsigned int audio_clkout1_b_pins[] = {
1655 	/* CLKOUT1 */
1656 	RCAR_GP_PIN(6, 29),
1657 };
1658 static const unsigned int audio_clkout1_b_mux[] = {
1659 	AUDIO_CLKOUT1_B_MARK,
1660 };
1661 static const unsigned int audio_clkout2_a_pins[] = {
1662 	/* CLKOUT2 */
1663 	RCAR_GP_PIN(5, 16),
1664 };
1665 static const unsigned int audio_clkout2_a_mux[] = {
1666 	AUDIO_CLKOUT2_A_MARK,
1667 };
1668 static const unsigned int audio_clkout2_b_pins[] = {
1669 	/* CLKOUT2 */
1670 	RCAR_GP_PIN(6, 30),
1671 };
1672 static const unsigned int audio_clkout2_b_mux[] = {
1673 	AUDIO_CLKOUT2_B_MARK,
1674 };
1675 static const unsigned int audio_clkout3_a_pins[] = {
1676 	/* CLKOUT3 */
1677 	RCAR_GP_PIN(5, 19),
1678 };
1679 static const unsigned int audio_clkout3_a_mux[] = {
1680 	AUDIO_CLKOUT3_A_MARK,
1681 };
1682 static const unsigned int audio_clkout3_b_pins[] = {
1683 	/* CLKOUT3 */
1684 	RCAR_GP_PIN(6, 31),
1685 };
1686 static const unsigned int audio_clkout3_b_mux[] = {
1687 	AUDIO_CLKOUT3_B_MARK,
1688 };
1689 
1690 /* - EtherAVB --------------------------------------------------------------- */
1691 static const unsigned int avb_link_pins[] = {
1692 	/* AVB_LINK */
1693 	RCAR_GP_PIN(2, 12),
1694 };
1695 static const unsigned int avb_link_mux[] = {
1696 	AVB_LINK_MARK,
1697 };
1698 static const unsigned int avb_magic_pins[] = {
1699 	/* AVB_MAGIC_ */
1700 	RCAR_GP_PIN(2, 10),
1701 };
1702 static const unsigned int avb_magic_mux[] = {
1703 	AVB_MAGIC_MARK,
1704 };
1705 static const unsigned int avb_phy_int_pins[] = {
1706 	/* AVB_PHY_INT */
1707 	RCAR_GP_PIN(2, 11),
1708 };
1709 static const unsigned int avb_phy_int_mux[] = {
1710 	AVB_PHY_INT_MARK,
1711 };
1712 static const unsigned int avb_mdio_pins[] = {
1713 	/* AVB_MDC, AVB_MDIO */
1714 	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1715 };
1716 static const unsigned int avb_mdio_mux[] = {
1717 	AVB_MDC_MARK, AVB_MDIO_MARK,
1718 };
1719 static const unsigned int avb_mii_pins[] = {
1720 	/*
1721 	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1722 	 * AVB_TD1, AVB_TD2, AVB_TD3,
1723 	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1724 	 * AVB_RD1, AVB_RD2, AVB_RD3,
1725 	 * AVB_TXCREFCLK
1726 	 */
1727 	PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1728 	PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1729 	PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1730 	PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1731 	PIN_NUMBER('A', 12),
1732 
1733 };
1734 static const unsigned int avb_mii_mux[] = {
1735 	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1736 	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1737 	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1738 	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1739 	AVB_TXCREFCLK_MARK,
1740 };
1741 static const unsigned int avb_avtp_pps_pins[] = {
1742 	/* AVB_AVTP_PPS */
1743 	RCAR_GP_PIN(2, 6),
1744 };
1745 static const unsigned int avb_avtp_pps_mux[] = {
1746 	AVB_AVTP_PPS_MARK,
1747 };
1748 static const unsigned int avb_avtp_match_a_pins[] = {
1749 	/* AVB_AVTP_MATCH_A */
1750 	RCAR_GP_PIN(2, 13),
1751 };
1752 static const unsigned int avb_avtp_match_a_mux[] = {
1753 	AVB_AVTP_MATCH_A_MARK,
1754 };
1755 static const unsigned int avb_avtp_capture_a_pins[] = {
1756 	/* AVB_AVTP_CAPTURE_A */
1757 	RCAR_GP_PIN(2, 14),
1758 };
1759 static const unsigned int avb_avtp_capture_a_mux[] = {
1760 	AVB_AVTP_CAPTURE_A_MARK,
1761 };
1762 static const unsigned int avb_avtp_match_b_pins[] = {
1763 	/*  AVB_AVTP_MATCH_B */
1764 	RCAR_GP_PIN(1, 8),
1765 };
1766 static const unsigned int avb_avtp_match_b_mux[] = {
1767 	AVB_AVTP_MATCH_B_MARK,
1768 };
1769 static const unsigned int avb_avtp_capture_b_pins[] = {
1770 	/* AVB_AVTP_CAPTURE_B */
1771 	RCAR_GP_PIN(1, 11),
1772 };
1773 static const unsigned int avb_avtp_capture_b_mux[] = {
1774 	AVB_AVTP_CAPTURE_B_MARK,
1775 };
1776 
1777 /* - CAN ------------------------------------------------------------------ */
1778 static const unsigned int can0_data_a_pins[] = {
1779 	/* TX, RX */
1780 	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
1781 };
1782 static const unsigned int can0_data_a_mux[] = {
1783 	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
1784 };
1785 static const unsigned int can0_data_b_pins[] = {
1786 	/* TX, RX */
1787 	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
1788 };
1789 static const unsigned int can0_data_b_mux[] = {
1790 	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
1791 };
1792 static const unsigned int can1_data_pins[] = {
1793 	/* TX, RX */
1794 	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
1795 };
1796 static const unsigned int can1_data_mux[] = {
1797 	CAN1_TX_MARK,		CAN1_RX_MARK,
1798 };
1799 
1800 /* - CAN Clock -------------------------------------------------------------- */
1801 static const unsigned int can_clk_pins[] = {
1802 	/* CLK */
1803 	RCAR_GP_PIN(1, 25),
1804 };
1805 static const unsigned int can_clk_mux[] = {
1806 	CAN_CLK_MARK,
1807 };
1808 
1809 /* - CAN FD --------------------------------------------------------------- */
1810 static const unsigned int canfd0_data_a_pins[] = {
1811 	/* TX, RX */
1812 	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1813 };
1814 static const unsigned int canfd0_data_a_mux[] = {
1815 	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1816 };
1817 static const unsigned int canfd0_data_b_pins[] = {
1818 	/* TX, RX */
1819 	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1820 };
1821 static const unsigned int canfd0_data_b_mux[] = {
1822 	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1823 };
1824 static const unsigned int canfd1_data_pins[] = {
1825 	/* TX, RX */
1826 	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1827 };
1828 static const unsigned int canfd1_data_mux[] = {
1829 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
1830 };
1831 
1832 /* - DRIF0 --------------------------------------------------------------- */
1833 static const unsigned int drif0_ctrl_a_pins[] = {
1834 	/* CLK, SYNC */
1835 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1836 };
1837 static const unsigned int drif0_ctrl_a_mux[] = {
1838 	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1839 };
1840 static const unsigned int drif0_data0_a_pins[] = {
1841 	/* D0 */
1842 	RCAR_GP_PIN(6, 10),
1843 };
1844 static const unsigned int drif0_data0_a_mux[] = {
1845 	RIF0_D0_A_MARK,
1846 };
1847 static const unsigned int drif0_data1_a_pins[] = {
1848 	/* D1 */
1849 	RCAR_GP_PIN(6, 7),
1850 };
1851 static const unsigned int drif0_data1_a_mux[] = {
1852 	RIF0_D1_A_MARK,
1853 };
1854 static const unsigned int drif0_ctrl_b_pins[] = {
1855 	/* CLK, SYNC */
1856 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1857 };
1858 static const unsigned int drif0_ctrl_b_mux[] = {
1859 	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1860 };
1861 static const unsigned int drif0_data0_b_pins[] = {
1862 	/* D0 */
1863 	RCAR_GP_PIN(5, 1),
1864 };
1865 static const unsigned int drif0_data0_b_mux[] = {
1866 	RIF0_D0_B_MARK,
1867 };
1868 static const unsigned int drif0_data1_b_pins[] = {
1869 	/* D1 */
1870 	RCAR_GP_PIN(5, 2),
1871 };
1872 static const unsigned int drif0_data1_b_mux[] = {
1873 	RIF0_D1_B_MARK,
1874 };
1875 static const unsigned int drif0_ctrl_c_pins[] = {
1876 	/* CLK, SYNC */
1877 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1878 };
1879 static const unsigned int drif0_ctrl_c_mux[] = {
1880 	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1881 };
1882 static const unsigned int drif0_data0_c_pins[] = {
1883 	/* D0 */
1884 	RCAR_GP_PIN(5, 13),
1885 };
1886 static const unsigned int drif0_data0_c_mux[] = {
1887 	RIF0_D0_C_MARK,
1888 };
1889 static const unsigned int drif0_data1_c_pins[] = {
1890 	/* D1 */
1891 	RCAR_GP_PIN(5, 14),
1892 };
1893 static const unsigned int drif0_data1_c_mux[] = {
1894 	RIF0_D1_C_MARK,
1895 };
1896 /* - DRIF1 --------------------------------------------------------------- */
1897 static const unsigned int drif1_ctrl_a_pins[] = {
1898 	/* CLK, SYNC */
1899 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1900 };
1901 static const unsigned int drif1_ctrl_a_mux[] = {
1902 	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1903 };
1904 static const unsigned int drif1_data0_a_pins[] = {
1905 	/* D0 */
1906 	RCAR_GP_PIN(6, 19),
1907 };
1908 static const unsigned int drif1_data0_a_mux[] = {
1909 	RIF1_D0_A_MARK,
1910 };
1911 static const unsigned int drif1_data1_a_pins[] = {
1912 	/* D1 */
1913 	RCAR_GP_PIN(6, 20),
1914 };
1915 static const unsigned int drif1_data1_a_mux[] = {
1916 	RIF1_D1_A_MARK,
1917 };
1918 static const unsigned int drif1_ctrl_b_pins[] = {
1919 	/* CLK, SYNC */
1920 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1921 };
1922 static const unsigned int drif1_ctrl_b_mux[] = {
1923 	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1924 };
1925 static const unsigned int drif1_data0_b_pins[] = {
1926 	/* D0 */
1927 	RCAR_GP_PIN(5, 7),
1928 };
1929 static const unsigned int drif1_data0_b_mux[] = {
1930 	RIF1_D0_B_MARK,
1931 };
1932 static const unsigned int drif1_data1_b_pins[] = {
1933 	/* D1 */
1934 	RCAR_GP_PIN(5, 8),
1935 };
1936 static const unsigned int drif1_data1_b_mux[] = {
1937 	RIF1_D1_B_MARK,
1938 };
1939 static const unsigned int drif1_ctrl_c_pins[] = {
1940 	/* CLK, SYNC */
1941 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1942 };
1943 static const unsigned int drif1_ctrl_c_mux[] = {
1944 	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1945 };
1946 static const unsigned int drif1_data0_c_pins[] = {
1947 	/* D0 */
1948 	RCAR_GP_PIN(5, 6),
1949 };
1950 static const unsigned int drif1_data0_c_mux[] = {
1951 	RIF1_D0_C_MARK,
1952 };
1953 static const unsigned int drif1_data1_c_pins[] = {
1954 	/* D1 */
1955 	RCAR_GP_PIN(5, 10),
1956 };
1957 static const unsigned int drif1_data1_c_mux[] = {
1958 	RIF1_D1_C_MARK,
1959 };
1960 /* - DRIF2 --------------------------------------------------------------- */
1961 static const unsigned int drif2_ctrl_a_pins[] = {
1962 	/* CLK, SYNC */
1963 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1964 };
1965 static const unsigned int drif2_ctrl_a_mux[] = {
1966 	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1967 };
1968 static const unsigned int drif2_data0_a_pins[] = {
1969 	/* D0 */
1970 	RCAR_GP_PIN(6, 7),
1971 };
1972 static const unsigned int drif2_data0_a_mux[] = {
1973 	RIF2_D0_A_MARK,
1974 };
1975 static const unsigned int drif2_data1_a_pins[] = {
1976 	/* D1 */
1977 	RCAR_GP_PIN(6, 10),
1978 };
1979 static const unsigned int drif2_data1_a_mux[] = {
1980 	RIF2_D1_A_MARK,
1981 };
1982 static const unsigned int drif2_ctrl_b_pins[] = {
1983 	/* CLK, SYNC */
1984 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1985 };
1986 static const unsigned int drif2_ctrl_b_mux[] = {
1987 	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1988 };
1989 static const unsigned int drif2_data0_b_pins[] = {
1990 	/* D0 */
1991 	RCAR_GP_PIN(6, 30),
1992 };
1993 static const unsigned int drif2_data0_b_mux[] = {
1994 	RIF2_D0_B_MARK,
1995 };
1996 static const unsigned int drif2_data1_b_pins[] = {
1997 	/* D1 */
1998 	RCAR_GP_PIN(6, 31),
1999 };
2000 static const unsigned int drif2_data1_b_mux[] = {
2001 	RIF2_D1_B_MARK,
2002 };
2003 /* - DRIF3 --------------------------------------------------------------- */
2004 static const unsigned int drif3_ctrl_a_pins[] = {
2005 	/* CLK, SYNC */
2006 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2007 };
2008 static const unsigned int drif3_ctrl_a_mux[] = {
2009 	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2010 };
2011 static const unsigned int drif3_data0_a_pins[] = {
2012 	/* D0 */
2013 	RCAR_GP_PIN(6, 19),
2014 };
2015 static const unsigned int drif3_data0_a_mux[] = {
2016 	RIF3_D0_A_MARK,
2017 };
2018 static const unsigned int drif3_data1_a_pins[] = {
2019 	/* D1 */
2020 	RCAR_GP_PIN(6, 20),
2021 };
2022 static const unsigned int drif3_data1_a_mux[] = {
2023 	RIF3_D1_A_MARK,
2024 };
2025 static const unsigned int drif3_ctrl_b_pins[] = {
2026 	/* CLK, SYNC */
2027 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2028 };
2029 static const unsigned int drif3_ctrl_b_mux[] = {
2030 	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2031 };
2032 static const unsigned int drif3_data0_b_pins[] = {
2033 	/* D0 */
2034 	RCAR_GP_PIN(6, 28),
2035 };
2036 static const unsigned int drif3_data0_b_mux[] = {
2037 	RIF3_D0_B_MARK,
2038 };
2039 static const unsigned int drif3_data1_b_pins[] = {
2040 	/* D1 */
2041 	RCAR_GP_PIN(6, 29),
2042 };
2043 static const unsigned int drif3_data1_b_mux[] = {
2044 	RIF3_D1_B_MARK,
2045 };
2046 
2047 /* - DU --------------------------------------------------------------------- */
2048 static const unsigned int du_rgb666_pins[] = {
2049 	/* R[7:2], G[7:2], B[7:2] */
2050 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2051 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2052 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2053 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2054 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2055 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2056 };
2057 static const unsigned int du_rgb666_mux[] = {
2058 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2059 	DU_DR3_MARK, DU_DR2_MARK,
2060 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2061 	DU_DG3_MARK, DU_DG2_MARK,
2062 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2063 	DU_DB3_MARK, DU_DB2_MARK,
2064 };
2065 static const unsigned int du_rgb888_pins[] = {
2066 	/* R[7:0], G[7:0], B[7:0] */
2067 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2068 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2069 	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2070 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2071 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2072 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2073 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2074 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2075 	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2076 };
2077 static const unsigned int du_rgb888_mux[] = {
2078 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2079 	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2080 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2081 	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2082 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2083 	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2084 };
2085 static const unsigned int du_clk_out_0_pins[] = {
2086 	/* CLKOUT */
2087 	RCAR_GP_PIN(1, 27),
2088 };
2089 static const unsigned int du_clk_out_0_mux[] = {
2090 	DU_DOTCLKOUT0_MARK
2091 };
2092 static const unsigned int du_clk_out_1_pins[] = {
2093 	/* CLKOUT */
2094 	RCAR_GP_PIN(2, 3),
2095 };
2096 static const unsigned int du_clk_out_1_mux[] = {
2097 	DU_DOTCLKOUT1_MARK
2098 };
2099 static const unsigned int du_sync_pins[] = {
2100 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2101 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2102 };
2103 static const unsigned int du_sync_mux[] = {
2104 	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2105 };
2106 static const unsigned int du_oddf_pins[] = {
2107 	/* EXDISP/EXODDF/EXCDE */
2108 	RCAR_GP_PIN(2, 2),
2109 };
2110 static const unsigned int du_oddf_mux[] = {
2111 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2112 };
2113 static const unsigned int du_cde_pins[] = {
2114 	/* CDE */
2115 	RCAR_GP_PIN(2, 0),
2116 };
2117 static const unsigned int du_cde_mux[] = {
2118 	DU_CDE_MARK,
2119 };
2120 static const unsigned int du_disp_pins[] = {
2121 	/* DISP */
2122 	RCAR_GP_PIN(2, 1),
2123 };
2124 static const unsigned int du_disp_mux[] = {
2125 	DU_DISP_MARK,
2126 };
2127 
2128 /* - GP7_02/03 -------------------------------------------------------------- */
2129 static const unsigned int gp7_02_pins[] = {
2130 	/* GP7_02 */
2131 	RCAR_GP_PIN(7, 2),
2132 };
2133 
2134 static const unsigned int gp7_02_mux[] = {
2135 	GP7_02_MARK,
2136 };
2137 
2138 static const unsigned int gp7_03_pins[] = {
2139 	/* GP7_03 */
2140 	RCAR_GP_PIN(7, 3),
2141 };
2142 
2143 static const unsigned int gp7_03_mux[] = {
2144 	GP7_03_MARK,
2145 };
2146 
2147 /* - HSCIF0 ----------------------------------------------------------------- */
2148 static const unsigned int hscif0_data_pins[] = {
2149 	/* RX, TX */
2150 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2151 };
2152 static const unsigned int hscif0_data_mux[] = {
2153 	HRX0_MARK, HTX0_MARK,
2154 };
2155 static const unsigned int hscif0_clk_pins[] = {
2156 	/* SCK */
2157 	RCAR_GP_PIN(5, 12),
2158 };
2159 static const unsigned int hscif0_clk_mux[] = {
2160 	HSCK0_MARK,
2161 };
2162 static const unsigned int hscif0_ctrl_pins[] = {
2163 	/* RTS, CTS */
2164 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2165 };
2166 static const unsigned int hscif0_ctrl_mux[] = {
2167 	HRTS0_N_MARK, HCTS0_N_MARK,
2168 };
2169 /* - HSCIF1 ----------------------------------------------------------------- */
2170 static const unsigned int hscif1_data_a_pins[] = {
2171 	/* RX, TX */
2172 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2173 };
2174 static const unsigned int hscif1_data_a_mux[] = {
2175 	HRX1_A_MARK, HTX1_A_MARK,
2176 };
2177 static const unsigned int hscif1_clk_a_pins[] = {
2178 	/* SCK */
2179 	RCAR_GP_PIN(6, 21),
2180 };
2181 static const unsigned int hscif1_clk_a_mux[] = {
2182 	HSCK1_A_MARK,
2183 };
2184 static const unsigned int hscif1_ctrl_a_pins[] = {
2185 	/* RTS, CTS */
2186 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2187 };
2188 static const unsigned int hscif1_ctrl_a_mux[] = {
2189 	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2190 };
2191 
2192 static const unsigned int hscif1_data_b_pins[] = {
2193 	/* RX, TX */
2194 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2195 };
2196 static const unsigned int hscif1_data_b_mux[] = {
2197 	HRX1_B_MARK, HTX1_B_MARK,
2198 };
2199 static const unsigned int hscif1_clk_b_pins[] = {
2200 	/* SCK */
2201 	RCAR_GP_PIN(5, 0),
2202 };
2203 static const unsigned int hscif1_clk_b_mux[] = {
2204 	HSCK1_B_MARK,
2205 };
2206 static const unsigned int hscif1_ctrl_b_pins[] = {
2207 	/* RTS, CTS */
2208 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2209 };
2210 static const unsigned int hscif1_ctrl_b_mux[] = {
2211 	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2212 };
2213 /* - HSCIF2 ----------------------------------------------------------------- */
2214 static const unsigned int hscif2_data_a_pins[] = {
2215 	/* RX, TX */
2216 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2217 };
2218 static const unsigned int hscif2_data_a_mux[] = {
2219 	HRX2_A_MARK, HTX2_A_MARK,
2220 };
2221 static const unsigned int hscif2_clk_a_pins[] = {
2222 	/* SCK */
2223 	RCAR_GP_PIN(6, 10),
2224 };
2225 static const unsigned int hscif2_clk_a_mux[] = {
2226 	HSCK2_A_MARK,
2227 };
2228 static const unsigned int hscif2_ctrl_a_pins[] = {
2229 	/* RTS, CTS */
2230 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2231 };
2232 static const unsigned int hscif2_ctrl_a_mux[] = {
2233 	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2234 };
2235 
2236 static const unsigned int hscif2_data_b_pins[] = {
2237 	/* RX, TX */
2238 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2239 };
2240 static const unsigned int hscif2_data_b_mux[] = {
2241 	HRX2_B_MARK, HTX2_B_MARK,
2242 };
2243 static const unsigned int hscif2_clk_b_pins[] = {
2244 	/* SCK */
2245 	RCAR_GP_PIN(6, 21),
2246 };
2247 static const unsigned int hscif2_clk_b_mux[] = {
2248 	HSCK2_B_MARK,
2249 };
2250 static const unsigned int hscif2_ctrl_b_pins[] = {
2251 	/* RTS, CTS */
2252 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2253 };
2254 static const unsigned int hscif2_ctrl_b_mux[] = {
2255 	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2256 };
2257 
2258 static const unsigned int hscif2_data_c_pins[] = {
2259 	/* RX, TX */
2260 	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2261 };
2262 static const unsigned int hscif2_data_c_mux[] = {
2263 	HRX2_C_MARK, HTX2_C_MARK,
2264 };
2265 static const unsigned int hscif2_clk_c_pins[] = {
2266 	/* SCK */
2267 	RCAR_GP_PIN(6, 24),
2268 };
2269 static const unsigned int hscif2_clk_c_mux[] = {
2270 	HSCK2_C_MARK,
2271 };
2272 static const unsigned int hscif2_ctrl_c_pins[] = {
2273 	/* RTS, CTS */
2274 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2275 };
2276 static const unsigned int hscif2_ctrl_c_mux[] = {
2277 	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2278 };
2279 /* - HSCIF3 ----------------------------------------------------------------- */
2280 static const unsigned int hscif3_data_a_pins[] = {
2281 	/* RX, TX */
2282 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2283 };
2284 static const unsigned int hscif3_data_a_mux[] = {
2285 	HRX3_A_MARK, HTX3_A_MARK,
2286 };
2287 static const unsigned int hscif3_clk_pins[] = {
2288 	/* SCK */
2289 	RCAR_GP_PIN(1, 22),
2290 };
2291 static const unsigned int hscif3_clk_mux[] = {
2292 	HSCK3_MARK,
2293 };
2294 static const unsigned int hscif3_ctrl_pins[] = {
2295 	/* RTS, CTS */
2296 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2297 };
2298 static const unsigned int hscif3_ctrl_mux[] = {
2299 	HRTS3_N_MARK, HCTS3_N_MARK,
2300 };
2301 
2302 static const unsigned int hscif3_data_b_pins[] = {
2303 	/* RX, TX */
2304 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2305 };
2306 static const unsigned int hscif3_data_b_mux[] = {
2307 	HRX3_B_MARK, HTX3_B_MARK,
2308 };
2309 static const unsigned int hscif3_data_c_pins[] = {
2310 	/* RX, TX */
2311 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2312 };
2313 static const unsigned int hscif3_data_c_mux[] = {
2314 	HRX3_C_MARK, HTX3_C_MARK,
2315 };
2316 static const unsigned int hscif3_data_d_pins[] = {
2317 	/* RX, TX */
2318 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2319 };
2320 static const unsigned int hscif3_data_d_mux[] = {
2321 	HRX3_D_MARK, HTX3_D_MARK,
2322 };
2323 /* - HSCIF4 ----------------------------------------------------------------- */
2324 static const unsigned int hscif4_data_a_pins[] = {
2325 	/* RX, TX */
2326 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2327 };
2328 static const unsigned int hscif4_data_a_mux[] = {
2329 	HRX4_A_MARK, HTX4_A_MARK,
2330 };
2331 static const unsigned int hscif4_clk_pins[] = {
2332 	/* SCK */
2333 	RCAR_GP_PIN(1, 11),
2334 };
2335 static const unsigned int hscif4_clk_mux[] = {
2336 	HSCK4_MARK,
2337 };
2338 static const unsigned int hscif4_ctrl_pins[] = {
2339 	/* RTS, CTS */
2340 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2341 };
2342 static const unsigned int hscif4_ctrl_mux[] = {
2343 	HRTS4_N_MARK, HCTS4_N_MARK,
2344 };
2345 
2346 static const unsigned int hscif4_data_b_pins[] = {
2347 	/* RX, TX */
2348 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2349 };
2350 static const unsigned int hscif4_data_b_mux[] = {
2351 	HRX4_B_MARK, HTX4_B_MARK,
2352 };
2353 
2354 /* - I2C -------------------------------------------------------------------- */
2355 static const unsigned int i2c1_a_pins[] = {
2356 	/* SDA, SCL */
2357 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2358 };
2359 static const unsigned int i2c1_a_mux[] = {
2360 	SDA1_A_MARK, SCL1_A_MARK,
2361 };
2362 static const unsigned int i2c1_b_pins[] = {
2363 	/* SDA, SCL */
2364 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2365 };
2366 static const unsigned int i2c1_b_mux[] = {
2367 	SDA1_B_MARK, SCL1_B_MARK,
2368 };
2369 static const unsigned int i2c2_a_pins[] = {
2370 	/* SDA, SCL */
2371 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2372 };
2373 static const unsigned int i2c2_a_mux[] = {
2374 	SDA2_A_MARK, SCL2_A_MARK,
2375 };
2376 static const unsigned int i2c2_b_pins[] = {
2377 	/* SDA, SCL */
2378 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2379 };
2380 static const unsigned int i2c2_b_mux[] = {
2381 	SDA2_B_MARK, SCL2_B_MARK,
2382 };
2383 static const unsigned int i2c6_a_pins[] = {
2384 	/* SDA, SCL */
2385 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2386 };
2387 static const unsigned int i2c6_a_mux[] = {
2388 	SDA6_A_MARK, SCL6_A_MARK,
2389 };
2390 static const unsigned int i2c6_b_pins[] = {
2391 	/* SDA, SCL */
2392 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2393 };
2394 static const unsigned int i2c6_b_mux[] = {
2395 	SDA6_B_MARK, SCL6_B_MARK,
2396 };
2397 static const unsigned int i2c6_c_pins[] = {
2398 	/* SDA, SCL */
2399 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2400 };
2401 static const unsigned int i2c6_c_mux[] = {
2402 	SDA6_C_MARK, SCL6_C_MARK,
2403 };
2404 
2405 /* - INTC-EX ---------------------------------------------------------------- */
2406 static const unsigned int intc_ex_irq0_pins[] = {
2407 	/* IRQ0 */
2408 	RCAR_GP_PIN(2, 0),
2409 };
2410 static const unsigned int intc_ex_irq0_mux[] = {
2411 	IRQ0_MARK,
2412 };
2413 static const unsigned int intc_ex_irq1_pins[] = {
2414 	/* IRQ1 */
2415 	RCAR_GP_PIN(2, 1),
2416 };
2417 static const unsigned int intc_ex_irq1_mux[] = {
2418 	IRQ1_MARK,
2419 };
2420 static const unsigned int intc_ex_irq2_pins[] = {
2421 	/* IRQ2 */
2422 	RCAR_GP_PIN(2, 2),
2423 };
2424 static const unsigned int intc_ex_irq2_mux[] = {
2425 	IRQ2_MARK,
2426 };
2427 static const unsigned int intc_ex_irq3_pins[] = {
2428 	/* IRQ3 */
2429 	RCAR_GP_PIN(2, 3),
2430 };
2431 static const unsigned int intc_ex_irq3_mux[] = {
2432 	IRQ3_MARK,
2433 };
2434 static const unsigned int intc_ex_irq4_pins[] = {
2435 	/* IRQ4 */
2436 	RCAR_GP_PIN(2, 4),
2437 };
2438 static const unsigned int intc_ex_irq4_mux[] = {
2439 	IRQ4_MARK,
2440 };
2441 static const unsigned int intc_ex_irq5_pins[] = {
2442 	/* IRQ5 */
2443 	RCAR_GP_PIN(2, 5),
2444 };
2445 static const unsigned int intc_ex_irq5_mux[] = {
2446 	IRQ5_MARK,
2447 };
2448 
2449 /* - MSIOF0 ----------------------------------------------------------------- */
2450 static const unsigned int msiof0_clk_pins[] = {
2451 	/* SCK */
2452 	RCAR_GP_PIN(5, 17),
2453 };
2454 static const unsigned int msiof0_clk_mux[] = {
2455 	MSIOF0_SCK_MARK,
2456 };
2457 static const unsigned int msiof0_sync_pins[] = {
2458 	/* SYNC */
2459 	RCAR_GP_PIN(5, 18),
2460 };
2461 static const unsigned int msiof0_sync_mux[] = {
2462 	MSIOF0_SYNC_MARK,
2463 };
2464 static const unsigned int msiof0_ss1_pins[] = {
2465 	/* SS1 */
2466 	RCAR_GP_PIN(5, 19),
2467 };
2468 static const unsigned int msiof0_ss1_mux[] = {
2469 	MSIOF0_SS1_MARK,
2470 };
2471 static const unsigned int msiof0_ss2_pins[] = {
2472 	/* SS2 */
2473 	RCAR_GP_PIN(5, 21),
2474 };
2475 static const unsigned int msiof0_ss2_mux[] = {
2476 	MSIOF0_SS2_MARK,
2477 };
2478 static const unsigned int msiof0_txd_pins[] = {
2479 	/* TXD */
2480 	RCAR_GP_PIN(5, 20),
2481 };
2482 static const unsigned int msiof0_txd_mux[] = {
2483 	MSIOF0_TXD_MARK,
2484 };
2485 static const unsigned int msiof0_rxd_pins[] = {
2486 	/* RXD */
2487 	RCAR_GP_PIN(5, 22),
2488 };
2489 static const unsigned int msiof0_rxd_mux[] = {
2490 	MSIOF0_RXD_MARK,
2491 };
2492 /* - MSIOF1 ----------------------------------------------------------------- */
2493 static const unsigned int msiof1_clk_a_pins[] = {
2494 	/* SCK */
2495 	RCAR_GP_PIN(6, 8),
2496 };
2497 static const unsigned int msiof1_clk_a_mux[] = {
2498 	MSIOF1_SCK_A_MARK,
2499 };
2500 static const unsigned int msiof1_sync_a_pins[] = {
2501 	/* SYNC */
2502 	RCAR_GP_PIN(6, 9),
2503 };
2504 static const unsigned int msiof1_sync_a_mux[] = {
2505 	MSIOF1_SYNC_A_MARK,
2506 };
2507 static const unsigned int msiof1_ss1_a_pins[] = {
2508 	/* SS1 */
2509 	RCAR_GP_PIN(6, 5),
2510 };
2511 static const unsigned int msiof1_ss1_a_mux[] = {
2512 	MSIOF1_SS1_A_MARK,
2513 };
2514 static const unsigned int msiof1_ss2_a_pins[] = {
2515 	/* SS2 */
2516 	RCAR_GP_PIN(6, 6),
2517 };
2518 static const unsigned int msiof1_ss2_a_mux[] = {
2519 	MSIOF1_SS2_A_MARK,
2520 };
2521 static const unsigned int msiof1_txd_a_pins[] = {
2522 	/* TXD */
2523 	RCAR_GP_PIN(6, 7),
2524 };
2525 static const unsigned int msiof1_txd_a_mux[] = {
2526 	MSIOF1_TXD_A_MARK,
2527 };
2528 static const unsigned int msiof1_rxd_a_pins[] = {
2529 	/* RXD */
2530 	RCAR_GP_PIN(6, 10),
2531 };
2532 static const unsigned int msiof1_rxd_a_mux[] = {
2533 	MSIOF1_RXD_A_MARK,
2534 };
2535 static const unsigned int msiof1_clk_b_pins[] = {
2536 	/* SCK */
2537 	RCAR_GP_PIN(5, 9),
2538 };
2539 static const unsigned int msiof1_clk_b_mux[] = {
2540 	MSIOF1_SCK_B_MARK,
2541 };
2542 static const unsigned int msiof1_sync_b_pins[] = {
2543 	/* SYNC */
2544 	RCAR_GP_PIN(5, 3),
2545 };
2546 static const unsigned int msiof1_sync_b_mux[] = {
2547 	MSIOF1_SYNC_B_MARK,
2548 };
2549 static const unsigned int msiof1_ss1_b_pins[] = {
2550 	/* SS1 */
2551 	RCAR_GP_PIN(5, 4),
2552 };
2553 static const unsigned int msiof1_ss1_b_mux[] = {
2554 	MSIOF1_SS1_B_MARK,
2555 };
2556 static const unsigned int msiof1_ss2_b_pins[] = {
2557 	/* SS2 */
2558 	RCAR_GP_PIN(5, 0),
2559 };
2560 static const unsigned int msiof1_ss2_b_mux[] = {
2561 	MSIOF1_SS2_B_MARK,
2562 };
2563 static const unsigned int msiof1_txd_b_pins[] = {
2564 	/* TXD */
2565 	RCAR_GP_PIN(5, 8),
2566 };
2567 static const unsigned int msiof1_txd_b_mux[] = {
2568 	MSIOF1_TXD_B_MARK,
2569 };
2570 static const unsigned int msiof1_rxd_b_pins[] = {
2571 	/* RXD */
2572 	RCAR_GP_PIN(5, 7),
2573 };
2574 static const unsigned int msiof1_rxd_b_mux[] = {
2575 	MSIOF1_RXD_B_MARK,
2576 };
2577 static const unsigned int msiof1_clk_c_pins[] = {
2578 	/* SCK */
2579 	RCAR_GP_PIN(6, 17),
2580 };
2581 static const unsigned int msiof1_clk_c_mux[] = {
2582 	MSIOF1_SCK_C_MARK,
2583 };
2584 static const unsigned int msiof1_sync_c_pins[] = {
2585 	/* SYNC */
2586 	RCAR_GP_PIN(6, 18),
2587 };
2588 static const unsigned int msiof1_sync_c_mux[] = {
2589 	MSIOF1_SYNC_C_MARK,
2590 };
2591 static const unsigned int msiof1_ss1_c_pins[] = {
2592 	/* SS1 */
2593 	RCAR_GP_PIN(6, 21),
2594 };
2595 static const unsigned int msiof1_ss1_c_mux[] = {
2596 	MSIOF1_SS1_C_MARK,
2597 };
2598 static const unsigned int msiof1_ss2_c_pins[] = {
2599 	/* SS2 */
2600 	RCAR_GP_PIN(6, 27),
2601 };
2602 static const unsigned int msiof1_ss2_c_mux[] = {
2603 	MSIOF1_SS2_C_MARK,
2604 };
2605 static const unsigned int msiof1_txd_c_pins[] = {
2606 	/* TXD */
2607 	RCAR_GP_PIN(6, 20),
2608 };
2609 static const unsigned int msiof1_txd_c_mux[] = {
2610 	MSIOF1_TXD_C_MARK,
2611 };
2612 static const unsigned int msiof1_rxd_c_pins[] = {
2613 	/* RXD */
2614 	RCAR_GP_PIN(6, 19),
2615 };
2616 static const unsigned int msiof1_rxd_c_mux[] = {
2617 	MSIOF1_RXD_C_MARK,
2618 };
2619 static const unsigned int msiof1_clk_d_pins[] = {
2620 	/* SCK */
2621 	RCAR_GP_PIN(5, 12),
2622 };
2623 static const unsigned int msiof1_clk_d_mux[] = {
2624 	MSIOF1_SCK_D_MARK,
2625 };
2626 static const unsigned int msiof1_sync_d_pins[] = {
2627 	/* SYNC */
2628 	RCAR_GP_PIN(5, 15),
2629 };
2630 static const unsigned int msiof1_sync_d_mux[] = {
2631 	MSIOF1_SYNC_D_MARK,
2632 };
2633 static const unsigned int msiof1_ss1_d_pins[] = {
2634 	/* SS1 */
2635 	RCAR_GP_PIN(5, 16),
2636 };
2637 static const unsigned int msiof1_ss1_d_mux[] = {
2638 	MSIOF1_SS1_D_MARK,
2639 };
2640 static const unsigned int msiof1_ss2_d_pins[] = {
2641 	/* SS2 */
2642 	RCAR_GP_PIN(5, 21),
2643 };
2644 static const unsigned int msiof1_ss2_d_mux[] = {
2645 	MSIOF1_SS2_D_MARK,
2646 };
2647 static const unsigned int msiof1_txd_d_pins[] = {
2648 	/* TXD */
2649 	RCAR_GP_PIN(5, 14),
2650 };
2651 static const unsigned int msiof1_txd_d_mux[] = {
2652 	MSIOF1_TXD_D_MARK,
2653 };
2654 static const unsigned int msiof1_rxd_d_pins[] = {
2655 	/* RXD */
2656 	RCAR_GP_PIN(5, 13),
2657 };
2658 static const unsigned int msiof1_rxd_d_mux[] = {
2659 	MSIOF1_RXD_D_MARK,
2660 };
2661 static const unsigned int msiof1_clk_e_pins[] = {
2662 	/* SCK */
2663 	RCAR_GP_PIN(3, 0),
2664 };
2665 static const unsigned int msiof1_clk_e_mux[] = {
2666 	MSIOF1_SCK_E_MARK,
2667 };
2668 static const unsigned int msiof1_sync_e_pins[] = {
2669 	/* SYNC */
2670 	RCAR_GP_PIN(3, 1),
2671 };
2672 static const unsigned int msiof1_sync_e_mux[] = {
2673 	MSIOF1_SYNC_E_MARK,
2674 };
2675 static const unsigned int msiof1_ss1_e_pins[] = {
2676 	/* SS1 */
2677 	RCAR_GP_PIN(3, 4),
2678 };
2679 static const unsigned int msiof1_ss1_e_mux[] = {
2680 	MSIOF1_SS1_E_MARK,
2681 };
2682 static const unsigned int msiof1_ss2_e_pins[] = {
2683 	/* SS2 */
2684 	RCAR_GP_PIN(3, 5),
2685 };
2686 static const unsigned int msiof1_ss2_e_mux[] = {
2687 	MSIOF1_SS2_E_MARK,
2688 };
2689 static const unsigned int msiof1_txd_e_pins[] = {
2690 	/* TXD */
2691 	RCAR_GP_PIN(3, 3),
2692 };
2693 static const unsigned int msiof1_txd_e_mux[] = {
2694 	MSIOF1_TXD_E_MARK,
2695 };
2696 static const unsigned int msiof1_rxd_e_pins[] = {
2697 	/* RXD */
2698 	RCAR_GP_PIN(3, 2),
2699 };
2700 static const unsigned int msiof1_rxd_e_mux[] = {
2701 	MSIOF1_RXD_E_MARK,
2702 };
2703 static const unsigned int msiof1_clk_f_pins[] = {
2704 	/* SCK */
2705 	RCAR_GP_PIN(5, 23),
2706 };
2707 static const unsigned int msiof1_clk_f_mux[] = {
2708 	MSIOF1_SCK_F_MARK,
2709 };
2710 static const unsigned int msiof1_sync_f_pins[] = {
2711 	/* SYNC */
2712 	RCAR_GP_PIN(5, 24),
2713 };
2714 static const unsigned int msiof1_sync_f_mux[] = {
2715 	MSIOF1_SYNC_F_MARK,
2716 };
2717 static const unsigned int msiof1_ss1_f_pins[] = {
2718 	/* SS1 */
2719 	RCAR_GP_PIN(6, 1),
2720 };
2721 static const unsigned int msiof1_ss1_f_mux[] = {
2722 	MSIOF1_SS1_F_MARK,
2723 };
2724 static const unsigned int msiof1_ss2_f_pins[] = {
2725 	/* SS2 */
2726 	RCAR_GP_PIN(6, 2),
2727 };
2728 static const unsigned int msiof1_ss2_f_mux[] = {
2729 	MSIOF1_SS2_F_MARK,
2730 };
2731 static const unsigned int msiof1_txd_f_pins[] = {
2732 	/* TXD */
2733 	RCAR_GP_PIN(6, 0),
2734 };
2735 static const unsigned int msiof1_txd_f_mux[] = {
2736 	MSIOF1_TXD_F_MARK,
2737 };
2738 static const unsigned int msiof1_rxd_f_pins[] = {
2739 	/* RXD */
2740 	RCAR_GP_PIN(5, 25),
2741 };
2742 static const unsigned int msiof1_rxd_f_mux[] = {
2743 	MSIOF1_RXD_F_MARK,
2744 };
2745 static const unsigned int msiof1_clk_g_pins[] = {
2746 	/* SCK */
2747 	RCAR_GP_PIN(3, 6),
2748 };
2749 static const unsigned int msiof1_clk_g_mux[] = {
2750 	MSIOF1_SCK_G_MARK,
2751 };
2752 static const unsigned int msiof1_sync_g_pins[] = {
2753 	/* SYNC */
2754 	RCAR_GP_PIN(3, 7),
2755 };
2756 static const unsigned int msiof1_sync_g_mux[] = {
2757 	MSIOF1_SYNC_G_MARK,
2758 };
2759 static const unsigned int msiof1_ss1_g_pins[] = {
2760 	/* SS1 */
2761 	RCAR_GP_PIN(3, 10),
2762 };
2763 static const unsigned int msiof1_ss1_g_mux[] = {
2764 	MSIOF1_SS1_G_MARK,
2765 };
2766 static const unsigned int msiof1_ss2_g_pins[] = {
2767 	/* SS2 */
2768 	RCAR_GP_PIN(3, 11),
2769 };
2770 static const unsigned int msiof1_ss2_g_mux[] = {
2771 	MSIOF1_SS2_G_MARK,
2772 };
2773 static const unsigned int msiof1_txd_g_pins[] = {
2774 	/* TXD */
2775 	RCAR_GP_PIN(3, 9),
2776 };
2777 static const unsigned int msiof1_txd_g_mux[] = {
2778 	MSIOF1_TXD_G_MARK,
2779 };
2780 static const unsigned int msiof1_rxd_g_pins[] = {
2781 	/* RXD */
2782 	RCAR_GP_PIN(3, 8),
2783 };
2784 static const unsigned int msiof1_rxd_g_mux[] = {
2785 	MSIOF1_RXD_G_MARK,
2786 };
2787 /* - MSIOF2 ----------------------------------------------------------------- */
2788 static const unsigned int msiof2_clk_a_pins[] = {
2789 	/* SCK */
2790 	RCAR_GP_PIN(1, 9),
2791 };
2792 static const unsigned int msiof2_clk_a_mux[] = {
2793 	MSIOF2_SCK_A_MARK,
2794 };
2795 static const unsigned int msiof2_sync_a_pins[] = {
2796 	/* SYNC */
2797 	RCAR_GP_PIN(1, 8),
2798 };
2799 static const unsigned int msiof2_sync_a_mux[] = {
2800 	MSIOF2_SYNC_A_MARK,
2801 };
2802 static const unsigned int msiof2_ss1_a_pins[] = {
2803 	/* SS1 */
2804 	RCAR_GP_PIN(1, 6),
2805 };
2806 static const unsigned int msiof2_ss1_a_mux[] = {
2807 	MSIOF2_SS1_A_MARK,
2808 };
2809 static const unsigned int msiof2_ss2_a_pins[] = {
2810 	/* SS2 */
2811 	RCAR_GP_PIN(1, 7),
2812 };
2813 static const unsigned int msiof2_ss2_a_mux[] = {
2814 	MSIOF2_SS2_A_MARK,
2815 };
2816 static const unsigned int msiof2_txd_a_pins[] = {
2817 	/* TXD */
2818 	RCAR_GP_PIN(1, 11),
2819 };
2820 static const unsigned int msiof2_txd_a_mux[] = {
2821 	MSIOF2_TXD_A_MARK,
2822 };
2823 static const unsigned int msiof2_rxd_a_pins[] = {
2824 	/* RXD */
2825 	RCAR_GP_PIN(1, 10),
2826 };
2827 static const unsigned int msiof2_rxd_a_mux[] = {
2828 	MSIOF2_RXD_A_MARK,
2829 };
2830 static const unsigned int msiof2_clk_b_pins[] = {
2831 	/* SCK */
2832 	RCAR_GP_PIN(0, 4),
2833 };
2834 static const unsigned int msiof2_clk_b_mux[] = {
2835 	MSIOF2_SCK_B_MARK,
2836 };
2837 static const unsigned int msiof2_sync_b_pins[] = {
2838 	/* SYNC */
2839 	RCAR_GP_PIN(0, 5),
2840 };
2841 static const unsigned int msiof2_sync_b_mux[] = {
2842 	MSIOF2_SYNC_B_MARK,
2843 };
2844 static const unsigned int msiof2_ss1_b_pins[] = {
2845 	/* SS1 */
2846 	RCAR_GP_PIN(0, 0),
2847 };
2848 static const unsigned int msiof2_ss1_b_mux[] = {
2849 	MSIOF2_SS1_B_MARK,
2850 };
2851 static const unsigned int msiof2_ss2_b_pins[] = {
2852 	/* SS2 */
2853 	RCAR_GP_PIN(0, 1),
2854 };
2855 static const unsigned int msiof2_ss2_b_mux[] = {
2856 	MSIOF2_SS2_B_MARK,
2857 };
2858 static const unsigned int msiof2_txd_b_pins[] = {
2859 	/* TXD */
2860 	RCAR_GP_PIN(0, 7),
2861 };
2862 static const unsigned int msiof2_txd_b_mux[] = {
2863 	MSIOF2_TXD_B_MARK,
2864 };
2865 static const unsigned int msiof2_rxd_b_pins[] = {
2866 	/* RXD */
2867 	RCAR_GP_PIN(0, 6),
2868 };
2869 static const unsigned int msiof2_rxd_b_mux[] = {
2870 	MSIOF2_RXD_B_MARK,
2871 };
2872 static const unsigned int msiof2_clk_c_pins[] = {
2873 	/* SCK */
2874 	RCAR_GP_PIN(2, 12),
2875 };
2876 static const unsigned int msiof2_clk_c_mux[] = {
2877 	MSIOF2_SCK_C_MARK,
2878 };
2879 static const unsigned int msiof2_sync_c_pins[] = {
2880 	/* SYNC */
2881 	RCAR_GP_PIN(2, 11),
2882 };
2883 static const unsigned int msiof2_sync_c_mux[] = {
2884 	MSIOF2_SYNC_C_MARK,
2885 };
2886 static const unsigned int msiof2_ss1_c_pins[] = {
2887 	/* SS1 */
2888 	RCAR_GP_PIN(2, 10),
2889 };
2890 static const unsigned int msiof2_ss1_c_mux[] = {
2891 	MSIOF2_SS1_C_MARK,
2892 };
2893 static const unsigned int msiof2_ss2_c_pins[] = {
2894 	/* SS2 */
2895 	RCAR_GP_PIN(2, 9),
2896 };
2897 static const unsigned int msiof2_ss2_c_mux[] = {
2898 	MSIOF2_SS2_C_MARK,
2899 };
2900 static const unsigned int msiof2_txd_c_pins[] = {
2901 	/* TXD */
2902 	RCAR_GP_PIN(2, 14),
2903 };
2904 static const unsigned int msiof2_txd_c_mux[] = {
2905 	MSIOF2_TXD_C_MARK,
2906 };
2907 static const unsigned int msiof2_rxd_c_pins[] = {
2908 	/* RXD */
2909 	RCAR_GP_PIN(2, 13),
2910 };
2911 static const unsigned int msiof2_rxd_c_mux[] = {
2912 	MSIOF2_RXD_C_MARK,
2913 };
2914 static const unsigned int msiof2_clk_d_pins[] = {
2915 	/* SCK */
2916 	RCAR_GP_PIN(0, 8),
2917 };
2918 static const unsigned int msiof2_clk_d_mux[] = {
2919 	MSIOF2_SCK_D_MARK,
2920 };
2921 static const unsigned int msiof2_sync_d_pins[] = {
2922 	/* SYNC */
2923 	RCAR_GP_PIN(0, 9),
2924 };
2925 static const unsigned int msiof2_sync_d_mux[] = {
2926 	MSIOF2_SYNC_D_MARK,
2927 };
2928 static const unsigned int msiof2_ss1_d_pins[] = {
2929 	/* SS1 */
2930 	RCAR_GP_PIN(0, 12),
2931 };
2932 static const unsigned int msiof2_ss1_d_mux[] = {
2933 	MSIOF2_SS1_D_MARK,
2934 };
2935 static const unsigned int msiof2_ss2_d_pins[] = {
2936 	/* SS2 */
2937 	RCAR_GP_PIN(0, 13),
2938 };
2939 static const unsigned int msiof2_ss2_d_mux[] = {
2940 	MSIOF2_SS2_D_MARK,
2941 };
2942 static const unsigned int msiof2_txd_d_pins[] = {
2943 	/* TXD */
2944 	RCAR_GP_PIN(0, 11),
2945 };
2946 static const unsigned int msiof2_txd_d_mux[] = {
2947 	MSIOF2_TXD_D_MARK,
2948 };
2949 static const unsigned int msiof2_rxd_d_pins[] = {
2950 	/* RXD */
2951 	RCAR_GP_PIN(0, 10),
2952 };
2953 static const unsigned int msiof2_rxd_d_mux[] = {
2954 	MSIOF2_RXD_D_MARK,
2955 };
2956 /* - MSIOF3 ----------------------------------------------------------------- */
2957 static const unsigned int msiof3_clk_a_pins[] = {
2958 	/* SCK */
2959 	RCAR_GP_PIN(0, 0),
2960 };
2961 static const unsigned int msiof3_clk_a_mux[] = {
2962 	MSIOF3_SCK_A_MARK,
2963 };
2964 static const unsigned int msiof3_sync_a_pins[] = {
2965 	/* SYNC */
2966 	RCAR_GP_PIN(0, 1),
2967 };
2968 static const unsigned int msiof3_sync_a_mux[] = {
2969 	MSIOF3_SYNC_A_MARK,
2970 };
2971 static const unsigned int msiof3_ss1_a_pins[] = {
2972 	/* SS1 */
2973 	RCAR_GP_PIN(0, 14),
2974 };
2975 static const unsigned int msiof3_ss1_a_mux[] = {
2976 	MSIOF3_SS1_A_MARK,
2977 };
2978 static const unsigned int msiof3_ss2_a_pins[] = {
2979 	/* SS2 */
2980 	RCAR_GP_PIN(0, 15),
2981 };
2982 static const unsigned int msiof3_ss2_a_mux[] = {
2983 	MSIOF3_SS2_A_MARK,
2984 };
2985 static const unsigned int msiof3_txd_a_pins[] = {
2986 	/* TXD */
2987 	RCAR_GP_PIN(0, 3),
2988 };
2989 static const unsigned int msiof3_txd_a_mux[] = {
2990 	MSIOF3_TXD_A_MARK,
2991 };
2992 static const unsigned int msiof3_rxd_a_pins[] = {
2993 	/* RXD */
2994 	RCAR_GP_PIN(0, 2),
2995 };
2996 static const unsigned int msiof3_rxd_a_mux[] = {
2997 	MSIOF3_RXD_A_MARK,
2998 };
2999 static const unsigned int msiof3_clk_b_pins[] = {
3000 	/* SCK */
3001 	RCAR_GP_PIN(1, 2),
3002 };
3003 static const unsigned int msiof3_clk_b_mux[] = {
3004 	MSIOF3_SCK_B_MARK,
3005 };
3006 static const unsigned int msiof3_sync_b_pins[] = {
3007 	/* SYNC */
3008 	RCAR_GP_PIN(1, 0),
3009 };
3010 static const unsigned int msiof3_sync_b_mux[] = {
3011 	MSIOF3_SYNC_B_MARK,
3012 };
3013 static const unsigned int msiof3_ss1_b_pins[] = {
3014 	/* SS1 */
3015 	RCAR_GP_PIN(1, 4),
3016 };
3017 static const unsigned int msiof3_ss1_b_mux[] = {
3018 	MSIOF3_SS1_B_MARK,
3019 };
3020 static const unsigned int msiof3_ss2_b_pins[] = {
3021 	/* SS2 */
3022 	RCAR_GP_PIN(1, 5),
3023 };
3024 static const unsigned int msiof3_ss2_b_mux[] = {
3025 	MSIOF3_SS2_B_MARK,
3026 };
3027 static const unsigned int msiof3_txd_b_pins[] = {
3028 	/* TXD */
3029 	RCAR_GP_PIN(1, 1),
3030 };
3031 static const unsigned int msiof3_txd_b_mux[] = {
3032 	MSIOF3_TXD_B_MARK,
3033 };
3034 static const unsigned int msiof3_rxd_b_pins[] = {
3035 	/* RXD */
3036 	RCAR_GP_PIN(1, 3),
3037 };
3038 static const unsigned int msiof3_rxd_b_mux[] = {
3039 	MSIOF3_RXD_B_MARK,
3040 };
3041 static const unsigned int msiof3_clk_c_pins[] = {
3042 	/* SCK */
3043 	RCAR_GP_PIN(1, 12),
3044 };
3045 static const unsigned int msiof3_clk_c_mux[] = {
3046 	MSIOF3_SCK_C_MARK,
3047 };
3048 static const unsigned int msiof3_sync_c_pins[] = {
3049 	/* SYNC */
3050 	RCAR_GP_PIN(1, 13),
3051 };
3052 static const unsigned int msiof3_sync_c_mux[] = {
3053 	MSIOF3_SYNC_C_MARK,
3054 };
3055 static const unsigned int msiof3_txd_c_pins[] = {
3056 	/* TXD */
3057 	RCAR_GP_PIN(1, 15),
3058 };
3059 static const unsigned int msiof3_txd_c_mux[] = {
3060 	MSIOF3_TXD_C_MARK,
3061 };
3062 static const unsigned int msiof3_rxd_c_pins[] = {
3063 	/* RXD */
3064 	RCAR_GP_PIN(1, 14),
3065 };
3066 static const unsigned int msiof3_rxd_c_mux[] = {
3067 	MSIOF3_RXD_C_MARK,
3068 };
3069 static const unsigned int msiof3_clk_d_pins[] = {
3070 	/* SCK */
3071 	RCAR_GP_PIN(1, 22),
3072 };
3073 static const unsigned int msiof3_clk_d_mux[] = {
3074 	MSIOF3_SCK_D_MARK,
3075 };
3076 static const unsigned int msiof3_sync_d_pins[] = {
3077 	/* SYNC */
3078 	RCAR_GP_PIN(1, 23),
3079 };
3080 static const unsigned int msiof3_sync_d_mux[] = {
3081 	MSIOF3_SYNC_D_MARK,
3082 };
3083 static const unsigned int msiof3_ss1_d_pins[] = {
3084 	/* SS1 */
3085 	RCAR_GP_PIN(1, 26),
3086 };
3087 static const unsigned int msiof3_ss1_d_mux[] = {
3088 	MSIOF3_SS1_D_MARK,
3089 };
3090 static const unsigned int msiof3_txd_d_pins[] = {
3091 	/* TXD */
3092 	RCAR_GP_PIN(1, 25),
3093 };
3094 static const unsigned int msiof3_txd_d_mux[] = {
3095 	MSIOF3_TXD_D_MARK,
3096 };
3097 static const unsigned int msiof3_rxd_d_pins[] = {
3098 	/* RXD */
3099 	RCAR_GP_PIN(1, 24),
3100 };
3101 static const unsigned int msiof3_rxd_d_mux[] = {
3102 	MSIOF3_RXD_D_MARK,
3103 };
3104 static const unsigned int msiof3_clk_e_pins[] = {
3105 	/* SCK */
3106 	RCAR_GP_PIN(2, 3),
3107 };
3108 static const unsigned int msiof3_clk_e_mux[] = {
3109 	MSIOF3_SCK_E_MARK,
3110 };
3111 static const unsigned int msiof3_sync_e_pins[] = {
3112 	/* SYNC */
3113 	RCAR_GP_PIN(2, 2),
3114 };
3115 static const unsigned int msiof3_sync_e_mux[] = {
3116 	MSIOF3_SYNC_E_MARK,
3117 };
3118 static const unsigned int msiof3_ss1_e_pins[] = {
3119 	/* SS1 */
3120 	RCAR_GP_PIN(2, 1),
3121 };
3122 static const unsigned int msiof3_ss1_e_mux[] = {
3123 	MSIOF3_SS1_E_MARK,
3124 };
3125 static const unsigned int msiof3_ss2_e_pins[] = {
3126 	/* SS1 */
3127 	RCAR_GP_PIN(2, 0),
3128 };
3129 static const unsigned int msiof3_ss2_e_mux[] = {
3130 	MSIOF3_SS2_E_MARK,
3131 };
3132 static const unsigned int msiof3_txd_e_pins[] = {
3133 	/* TXD */
3134 	RCAR_GP_PIN(2, 5),
3135 };
3136 static const unsigned int msiof3_txd_e_mux[] = {
3137 	MSIOF3_TXD_E_MARK,
3138 };
3139 static const unsigned int msiof3_rxd_e_pins[] = {
3140 	/* RXD */
3141 	RCAR_GP_PIN(2, 4),
3142 };
3143 static const unsigned int msiof3_rxd_e_mux[] = {
3144 	MSIOF3_RXD_E_MARK,
3145 };
3146 
3147 /* - PWM0 --------------------------------------------------------------------*/
3148 static const unsigned int pwm0_pins[] = {
3149 	/* PWM */
3150 	RCAR_GP_PIN(2, 6),
3151 };
3152 static const unsigned int pwm0_mux[] = {
3153 	PWM0_MARK,
3154 };
3155 /* - PWM1 --------------------------------------------------------------------*/
3156 static const unsigned int pwm1_a_pins[] = {
3157 	/* PWM */
3158 	RCAR_GP_PIN(2, 7),
3159 };
3160 static const unsigned int pwm1_a_mux[] = {
3161 	PWM1_A_MARK,
3162 };
3163 static const unsigned int pwm1_b_pins[] = {
3164 	/* PWM */
3165 	RCAR_GP_PIN(1, 8),
3166 };
3167 static const unsigned int pwm1_b_mux[] = {
3168 	PWM1_B_MARK,
3169 };
3170 /* - PWM2 --------------------------------------------------------------------*/
3171 static const unsigned int pwm2_a_pins[] = {
3172 	/* PWM */
3173 	RCAR_GP_PIN(2, 8),
3174 };
3175 static const unsigned int pwm2_a_mux[] = {
3176 	PWM2_A_MARK,
3177 };
3178 static const unsigned int pwm2_b_pins[] = {
3179 	/* PWM */
3180 	RCAR_GP_PIN(1, 11),
3181 };
3182 static const unsigned int pwm2_b_mux[] = {
3183 	PWM2_B_MARK,
3184 };
3185 /* - PWM3 --------------------------------------------------------------------*/
3186 static const unsigned int pwm3_a_pins[] = {
3187 	/* PWM */
3188 	RCAR_GP_PIN(1, 0),
3189 };
3190 static const unsigned int pwm3_a_mux[] = {
3191 	PWM3_A_MARK,
3192 };
3193 static const unsigned int pwm3_b_pins[] = {
3194 	/* PWM */
3195 	RCAR_GP_PIN(2, 2),
3196 };
3197 static const unsigned int pwm3_b_mux[] = {
3198 	PWM3_B_MARK,
3199 };
3200 /* - PWM4 --------------------------------------------------------------------*/
3201 static const unsigned int pwm4_a_pins[] = {
3202 	/* PWM */
3203 	RCAR_GP_PIN(1, 1),
3204 };
3205 static const unsigned int pwm4_a_mux[] = {
3206 	PWM4_A_MARK,
3207 };
3208 static const unsigned int pwm4_b_pins[] = {
3209 	/* PWM */
3210 	RCAR_GP_PIN(2, 3),
3211 };
3212 static const unsigned int pwm4_b_mux[] = {
3213 	PWM4_B_MARK,
3214 };
3215 /* - PWM5 --------------------------------------------------------------------*/
3216 static const unsigned int pwm5_a_pins[] = {
3217 	/* PWM */
3218 	RCAR_GP_PIN(1, 2),
3219 };
3220 static const unsigned int pwm5_a_mux[] = {
3221 	PWM5_A_MARK,
3222 };
3223 static const unsigned int pwm5_b_pins[] = {
3224 	/* PWM */
3225 	RCAR_GP_PIN(2, 4),
3226 };
3227 static const unsigned int pwm5_b_mux[] = {
3228 	PWM5_B_MARK,
3229 };
3230 /* - PWM6 --------------------------------------------------------------------*/
3231 static const unsigned int pwm6_a_pins[] = {
3232 	/* PWM */
3233 	RCAR_GP_PIN(1, 3),
3234 };
3235 static const unsigned int pwm6_a_mux[] = {
3236 	PWM6_A_MARK,
3237 };
3238 static const unsigned int pwm6_b_pins[] = {
3239 	/* PWM */
3240 	RCAR_GP_PIN(2, 5),
3241 };
3242 static const unsigned int pwm6_b_mux[] = {
3243 	PWM6_B_MARK,
3244 };
3245 
3246 /* - SATA --------------------------------------------------------------------*/
3247 static const unsigned int sata0_devslp_a_pins[] = {
3248 	/* DEVSLP */
3249 	RCAR_GP_PIN(6, 16),
3250 };
3251 static const unsigned int sata0_devslp_a_mux[] = {
3252 	SATA_DEVSLP_A_MARK,
3253 };
3254 static const unsigned int sata0_devslp_b_pins[] = {
3255 	/* DEVSLP */
3256 	RCAR_GP_PIN(4, 6),
3257 };
3258 static const unsigned int sata0_devslp_b_mux[] = {
3259 	SATA_DEVSLP_B_MARK,
3260 };
3261 
3262 /* - SCIF0 ------------------------------------------------------------------ */
3263 static const unsigned int scif0_data_pins[] = {
3264 	/* RX, TX */
3265 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3266 };
3267 static const unsigned int scif0_data_mux[] = {
3268 	RX0_MARK, TX0_MARK,
3269 };
3270 static const unsigned int scif0_clk_pins[] = {
3271 	/* SCK */
3272 	RCAR_GP_PIN(5, 0),
3273 };
3274 static const unsigned int scif0_clk_mux[] = {
3275 	SCK0_MARK,
3276 };
3277 static const unsigned int scif0_ctrl_pins[] = {
3278 	/* RTS, CTS */
3279 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3280 };
3281 static const unsigned int scif0_ctrl_mux[] = {
3282 	RTS0_N_MARK, CTS0_N_MARK,
3283 };
3284 /* - SCIF1 ------------------------------------------------------------------ */
3285 static const unsigned int scif1_data_a_pins[] = {
3286 	/* RX, TX */
3287 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3288 };
3289 static const unsigned int scif1_data_a_mux[] = {
3290 	RX1_A_MARK, TX1_A_MARK,
3291 };
3292 static const unsigned int scif1_clk_pins[] = {
3293 	/* SCK */
3294 	RCAR_GP_PIN(6, 21),
3295 };
3296 static const unsigned int scif1_clk_mux[] = {
3297 	SCK1_MARK,
3298 };
3299 static const unsigned int scif1_ctrl_pins[] = {
3300 	/* RTS, CTS */
3301 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3302 };
3303 static const unsigned int scif1_ctrl_mux[] = {
3304 	RTS1_N_MARK, CTS1_N_MARK,
3305 };
3306 
3307 static const unsigned int scif1_data_b_pins[] = {
3308 	/* RX, TX */
3309 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3310 };
3311 static const unsigned int scif1_data_b_mux[] = {
3312 	RX1_B_MARK, TX1_B_MARK,
3313 };
3314 /* - SCIF2 ------------------------------------------------------------------ */
3315 static const unsigned int scif2_data_a_pins[] = {
3316 	/* RX, TX */
3317 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3318 };
3319 static const unsigned int scif2_data_a_mux[] = {
3320 	RX2_A_MARK, TX2_A_MARK,
3321 };
3322 static const unsigned int scif2_clk_pins[] = {
3323 	/* SCK */
3324 	RCAR_GP_PIN(5, 9),
3325 };
3326 static const unsigned int scif2_clk_mux[] = {
3327 	SCK2_MARK,
3328 };
3329 static const unsigned int scif2_data_b_pins[] = {
3330 	/* RX, TX */
3331 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3332 };
3333 static const unsigned int scif2_data_b_mux[] = {
3334 	RX2_B_MARK, TX2_B_MARK,
3335 };
3336 /* - SCIF3 ------------------------------------------------------------------ */
3337 static const unsigned int scif3_data_a_pins[] = {
3338 	/* RX, TX */
3339 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3340 };
3341 static const unsigned int scif3_data_a_mux[] = {
3342 	RX3_A_MARK, TX3_A_MARK,
3343 };
3344 static const unsigned int scif3_clk_pins[] = {
3345 	/* SCK */
3346 	RCAR_GP_PIN(1, 22),
3347 };
3348 static const unsigned int scif3_clk_mux[] = {
3349 	SCK3_MARK,
3350 };
3351 static const unsigned int scif3_ctrl_pins[] = {
3352 	/* RTS, CTS */
3353 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3354 };
3355 static const unsigned int scif3_ctrl_mux[] = {
3356 	RTS3_N_MARK, CTS3_N_MARK,
3357 };
3358 static const unsigned int scif3_data_b_pins[] = {
3359 	/* RX, TX */
3360 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3361 };
3362 static const unsigned int scif3_data_b_mux[] = {
3363 	RX3_B_MARK, TX3_B_MARK,
3364 };
3365 /* - SCIF4 ------------------------------------------------------------------ */
3366 static const unsigned int scif4_data_a_pins[] = {
3367 	/* RX, TX */
3368 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3369 };
3370 static const unsigned int scif4_data_a_mux[] = {
3371 	RX4_A_MARK, TX4_A_MARK,
3372 };
3373 static const unsigned int scif4_clk_a_pins[] = {
3374 	/* SCK */
3375 	RCAR_GP_PIN(2, 10),
3376 };
3377 static const unsigned int scif4_clk_a_mux[] = {
3378 	SCK4_A_MARK,
3379 };
3380 static const unsigned int scif4_ctrl_a_pins[] = {
3381 	/* RTS, CTS */
3382 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3383 };
3384 static const unsigned int scif4_ctrl_a_mux[] = {
3385 	RTS4_N_A_MARK, CTS4_N_A_MARK,
3386 };
3387 static const unsigned int scif4_data_b_pins[] = {
3388 	/* RX, TX */
3389 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3390 };
3391 static const unsigned int scif4_data_b_mux[] = {
3392 	RX4_B_MARK, TX4_B_MARK,
3393 };
3394 static const unsigned int scif4_clk_b_pins[] = {
3395 	/* SCK */
3396 	RCAR_GP_PIN(1, 5),
3397 };
3398 static const unsigned int scif4_clk_b_mux[] = {
3399 	SCK4_B_MARK,
3400 };
3401 static const unsigned int scif4_ctrl_b_pins[] = {
3402 	/* RTS, CTS */
3403 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3404 };
3405 static const unsigned int scif4_ctrl_b_mux[] = {
3406 	RTS4_N_B_MARK, CTS4_N_B_MARK,
3407 };
3408 static const unsigned int scif4_data_c_pins[] = {
3409 	/* RX, TX */
3410 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3411 };
3412 static const unsigned int scif4_data_c_mux[] = {
3413 	RX4_C_MARK, TX4_C_MARK,
3414 };
3415 static const unsigned int scif4_clk_c_pins[] = {
3416 	/* SCK */
3417 	RCAR_GP_PIN(0, 8),
3418 };
3419 static const unsigned int scif4_clk_c_mux[] = {
3420 	SCK4_C_MARK,
3421 };
3422 static const unsigned int scif4_ctrl_c_pins[] = {
3423 	/* RTS, CTS */
3424 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3425 };
3426 static const unsigned int scif4_ctrl_c_mux[] = {
3427 	RTS4_N_C_MARK, CTS4_N_C_MARK,
3428 };
3429 /* - SCIF5 ------------------------------------------------------------------ */
3430 static const unsigned int scif5_data_a_pins[] = {
3431 	/* RX, TX */
3432 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3433 };
3434 static const unsigned int scif5_data_a_mux[] = {
3435 	RX5_A_MARK, TX5_A_MARK,
3436 };
3437 static const unsigned int scif5_clk_a_pins[] = {
3438 	/* SCK */
3439 	RCAR_GP_PIN(6, 21),
3440 };
3441 static const unsigned int scif5_clk_a_mux[] = {
3442 	SCK5_A_MARK,
3443 };
3444 static const unsigned int scif5_data_b_pins[] = {
3445 	/* RX, TX */
3446 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3447 };
3448 static const unsigned int scif5_data_b_mux[] = {
3449 	RX5_B_MARK, TX5_B_MARK,
3450 };
3451 static const unsigned int scif5_clk_b_pins[] = {
3452 	/* SCK */
3453 	RCAR_GP_PIN(5, 0),
3454 };
3455 static const unsigned int scif5_clk_b_mux[] = {
3456 	SCK5_B_MARK,
3457 };
3458 
3459 /* - SCIF Clock ------------------------------------------------------------- */
3460 static const unsigned int scif_clk_a_pins[] = {
3461 	/* SCIF_CLK */
3462 	RCAR_GP_PIN(6, 23),
3463 };
3464 static const unsigned int scif_clk_a_mux[] = {
3465 	SCIF_CLK_A_MARK,
3466 };
3467 static const unsigned int scif_clk_b_pins[] = {
3468 	/* SCIF_CLK */
3469 	RCAR_GP_PIN(5, 9),
3470 };
3471 static const unsigned int scif_clk_b_mux[] = {
3472 	SCIF_CLK_B_MARK,
3473 };
3474 
3475 /* - SDHI0 ------------------------------------------------------------------ */
3476 static const unsigned int sdhi0_data1_pins[] = {
3477 	/* D0 */
3478 	RCAR_GP_PIN(3, 2),
3479 };
3480 static const unsigned int sdhi0_data1_mux[] = {
3481 	SD0_DAT0_MARK,
3482 };
3483 static const unsigned int sdhi0_data4_pins[] = {
3484 	/* D[0:3] */
3485 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3486 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3487 };
3488 static const unsigned int sdhi0_data4_mux[] = {
3489 	SD0_DAT0_MARK, SD0_DAT1_MARK,
3490 	SD0_DAT2_MARK, SD0_DAT3_MARK,
3491 };
3492 static const unsigned int sdhi0_ctrl_pins[] = {
3493 	/* CLK, CMD */
3494 	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3495 };
3496 static const unsigned int sdhi0_ctrl_mux[] = {
3497 	SD0_CLK_MARK, SD0_CMD_MARK,
3498 };
3499 static const unsigned int sdhi0_cd_pins[] = {
3500 	/* CD */
3501 	RCAR_GP_PIN(3, 12),
3502 };
3503 static const unsigned int sdhi0_cd_mux[] = {
3504 	SD0_CD_MARK,
3505 };
3506 static const unsigned int sdhi0_wp_pins[] = {
3507 	/* WP */
3508 	RCAR_GP_PIN(3, 13),
3509 };
3510 static const unsigned int sdhi0_wp_mux[] = {
3511 	SD0_WP_MARK,
3512 };
3513 /* - SDHI1 ------------------------------------------------------------------ */
3514 static const unsigned int sdhi1_data1_pins[] = {
3515 	/* D0 */
3516 	RCAR_GP_PIN(3, 8),
3517 };
3518 static const unsigned int sdhi1_data1_mux[] = {
3519 	SD1_DAT0_MARK,
3520 };
3521 static const unsigned int sdhi1_data4_pins[] = {
3522 	/* D[0:3] */
3523 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3524 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3525 };
3526 static const unsigned int sdhi1_data4_mux[] = {
3527 	SD1_DAT0_MARK, SD1_DAT1_MARK,
3528 	SD1_DAT2_MARK, SD1_DAT3_MARK,
3529 };
3530 static const unsigned int sdhi1_ctrl_pins[] = {
3531 	/* CLK, CMD */
3532 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3533 };
3534 static const unsigned int sdhi1_ctrl_mux[] = {
3535 	SD1_CLK_MARK, SD1_CMD_MARK,
3536 };
3537 static const unsigned int sdhi1_cd_pins[] = {
3538 	/* CD */
3539 	RCAR_GP_PIN(3, 14),
3540 };
3541 static const unsigned int sdhi1_cd_mux[] = {
3542 	SD1_CD_MARK,
3543 };
3544 static const unsigned int sdhi1_wp_pins[] = {
3545 	/* WP */
3546 	RCAR_GP_PIN(3, 15),
3547 };
3548 static const unsigned int sdhi1_wp_mux[] = {
3549 	SD1_WP_MARK,
3550 };
3551 /* - SDHI2 ------------------------------------------------------------------ */
3552 static const unsigned int sdhi2_data1_pins[] = {
3553 	/* D0 */
3554 	RCAR_GP_PIN(4, 2),
3555 };
3556 static const unsigned int sdhi2_data1_mux[] = {
3557 	SD2_DAT0_MARK,
3558 };
3559 static const unsigned int sdhi2_data4_pins[] = {
3560 	/* D[0:3] */
3561 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3562 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3563 };
3564 static const unsigned int sdhi2_data4_mux[] = {
3565 	SD2_DAT0_MARK, SD2_DAT1_MARK,
3566 	SD2_DAT2_MARK, SD2_DAT3_MARK,
3567 };
3568 static const unsigned int sdhi2_data8_pins[] = {
3569 	/* D[0:7] */
3570 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3571 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3572 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3573 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3574 };
3575 static const unsigned int sdhi2_data8_mux[] = {
3576 	SD2_DAT0_MARK, SD2_DAT1_MARK,
3577 	SD2_DAT2_MARK, SD2_DAT3_MARK,
3578 	SD2_DAT4_MARK, SD2_DAT5_MARK,
3579 	SD2_DAT6_MARK, SD2_DAT7_MARK,
3580 };
3581 static const unsigned int sdhi2_ctrl_pins[] = {
3582 	/* CLK, CMD */
3583 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3584 };
3585 static const unsigned int sdhi2_ctrl_mux[] = {
3586 	SD2_CLK_MARK, SD2_CMD_MARK,
3587 };
3588 static const unsigned int sdhi2_cd_a_pins[] = {
3589 	/* CD */
3590 	RCAR_GP_PIN(4, 13),
3591 };
3592 static const unsigned int sdhi2_cd_a_mux[] = {
3593 	SD2_CD_A_MARK,
3594 };
3595 static const unsigned int sdhi2_cd_b_pins[] = {
3596 	/* CD */
3597 	RCAR_GP_PIN(5, 10),
3598 };
3599 static const unsigned int sdhi2_cd_b_mux[] = {
3600 	SD2_CD_B_MARK,
3601 };
3602 static const unsigned int sdhi2_wp_a_pins[] = {
3603 	/* WP */
3604 	RCAR_GP_PIN(4, 14),
3605 };
3606 static const unsigned int sdhi2_wp_a_mux[] = {
3607 	SD2_WP_A_MARK,
3608 };
3609 static const unsigned int sdhi2_wp_b_pins[] = {
3610 	/* WP */
3611 	RCAR_GP_PIN(5, 11),
3612 };
3613 static const unsigned int sdhi2_wp_b_mux[] = {
3614 	SD2_WP_B_MARK,
3615 };
3616 static const unsigned int sdhi2_ds_pins[] = {
3617 	/* DS */
3618 	RCAR_GP_PIN(4, 6),
3619 };
3620 static const unsigned int sdhi2_ds_mux[] = {
3621 	SD2_DS_MARK,
3622 };
3623 /* - SDHI3 ------------------------------------------------------------------ */
3624 static const unsigned int sdhi3_data1_pins[] = {
3625 	/* D0 */
3626 	RCAR_GP_PIN(4, 9),
3627 };
3628 static const unsigned int sdhi3_data1_mux[] = {
3629 	SD3_DAT0_MARK,
3630 };
3631 static const unsigned int sdhi3_data4_pins[] = {
3632 	/* D[0:3] */
3633 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3634 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3635 };
3636 static const unsigned int sdhi3_data4_mux[] = {
3637 	SD3_DAT0_MARK, SD3_DAT1_MARK,
3638 	SD3_DAT2_MARK, SD3_DAT3_MARK,
3639 };
3640 static const unsigned int sdhi3_data8_pins[] = {
3641 	/* D[0:7] */
3642 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3643 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3644 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3645 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3646 };
3647 static const unsigned int sdhi3_data8_mux[] = {
3648 	SD3_DAT0_MARK, SD3_DAT1_MARK,
3649 	SD3_DAT2_MARK, SD3_DAT3_MARK,
3650 	SD3_DAT4_MARK, SD3_DAT5_MARK,
3651 	SD3_DAT6_MARK, SD3_DAT7_MARK,
3652 };
3653 static const unsigned int sdhi3_ctrl_pins[] = {
3654 	/* CLK, CMD */
3655 	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3656 };
3657 static const unsigned int sdhi3_ctrl_mux[] = {
3658 	SD3_CLK_MARK, SD3_CMD_MARK,
3659 };
3660 static const unsigned int sdhi3_cd_pins[] = {
3661 	/* CD */
3662 	RCAR_GP_PIN(4, 15),
3663 };
3664 static const unsigned int sdhi3_cd_mux[] = {
3665 	SD3_CD_MARK,
3666 };
3667 static const unsigned int sdhi3_wp_pins[] = {
3668 	/* WP */
3669 	RCAR_GP_PIN(4, 16),
3670 };
3671 static const unsigned int sdhi3_wp_mux[] = {
3672 	SD3_WP_MARK,
3673 };
3674 static const unsigned int sdhi3_ds_pins[] = {
3675 	/* DS */
3676 	RCAR_GP_PIN(4, 17),
3677 };
3678 static const unsigned int sdhi3_ds_mux[] = {
3679 	SD3_DS_MARK,
3680 };
3681 
3682 /* - SSI -------------------------------------------------------------------- */
3683 static const unsigned int ssi0_data_pins[] = {
3684 	/* SDATA */
3685 	RCAR_GP_PIN(6, 2),
3686 };
3687 static const unsigned int ssi0_data_mux[] = {
3688 	SSI_SDATA0_MARK,
3689 };
3690 static const unsigned int ssi01239_ctrl_pins[] = {
3691 	/* SCK, WS */
3692 	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3693 };
3694 static const unsigned int ssi01239_ctrl_mux[] = {
3695 	SSI_SCK01239_MARK, SSI_WS01239_MARK,
3696 };
3697 static const unsigned int ssi1_data_a_pins[] = {
3698 	/* SDATA */
3699 	RCAR_GP_PIN(6, 3),
3700 };
3701 static const unsigned int ssi1_data_a_mux[] = {
3702 	SSI_SDATA1_A_MARK,
3703 };
3704 static const unsigned int ssi1_data_b_pins[] = {
3705 	/* SDATA */
3706 	RCAR_GP_PIN(5, 12),
3707 };
3708 static const unsigned int ssi1_data_b_mux[] = {
3709 	SSI_SDATA1_B_MARK,
3710 };
3711 static const unsigned int ssi1_ctrl_a_pins[] = {
3712 	/* SCK, WS */
3713 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3714 };
3715 static const unsigned int ssi1_ctrl_a_mux[] = {
3716 	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3717 };
3718 static const unsigned int ssi1_ctrl_b_pins[] = {
3719 	/* SCK, WS */
3720 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3721 };
3722 static const unsigned int ssi1_ctrl_b_mux[] = {
3723 	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3724 };
3725 static const unsigned int ssi2_data_a_pins[] = {
3726 	/* SDATA */
3727 	RCAR_GP_PIN(6, 4),
3728 };
3729 static const unsigned int ssi2_data_a_mux[] = {
3730 	SSI_SDATA2_A_MARK,
3731 };
3732 static const unsigned int ssi2_data_b_pins[] = {
3733 	/* SDATA */
3734 	RCAR_GP_PIN(5, 13),
3735 };
3736 static const unsigned int ssi2_data_b_mux[] = {
3737 	SSI_SDATA2_B_MARK,
3738 };
3739 static const unsigned int ssi2_ctrl_a_pins[] = {
3740 	/* SCK, WS */
3741 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3742 };
3743 static const unsigned int ssi2_ctrl_a_mux[] = {
3744 	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3745 };
3746 static const unsigned int ssi2_ctrl_b_pins[] = {
3747 	/* SCK, WS */
3748 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3749 };
3750 static const unsigned int ssi2_ctrl_b_mux[] = {
3751 	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3752 };
3753 static const unsigned int ssi3_data_pins[] = {
3754 	/* SDATA */
3755 	RCAR_GP_PIN(6, 7),
3756 };
3757 static const unsigned int ssi3_data_mux[] = {
3758 	SSI_SDATA3_MARK,
3759 };
3760 static const unsigned int ssi349_ctrl_pins[] = {
3761 	/* SCK, WS */
3762 	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3763 };
3764 static const unsigned int ssi349_ctrl_mux[] = {
3765 	SSI_SCK349_MARK, SSI_WS349_MARK,
3766 };
3767 static const unsigned int ssi4_data_pins[] = {
3768 	/* SDATA */
3769 	RCAR_GP_PIN(6, 10),
3770 };
3771 static const unsigned int ssi4_data_mux[] = {
3772 	SSI_SDATA4_MARK,
3773 };
3774 static const unsigned int ssi4_ctrl_pins[] = {
3775 	/* SCK, WS */
3776 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3777 };
3778 static const unsigned int ssi4_ctrl_mux[] = {
3779 	SSI_SCK4_MARK, SSI_WS4_MARK,
3780 };
3781 static const unsigned int ssi5_data_pins[] = {
3782 	/* SDATA */
3783 	RCAR_GP_PIN(6, 13),
3784 };
3785 static const unsigned int ssi5_data_mux[] = {
3786 	SSI_SDATA5_MARK,
3787 };
3788 static const unsigned int ssi5_ctrl_pins[] = {
3789 	/* SCK, WS */
3790 	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3791 };
3792 static const unsigned int ssi5_ctrl_mux[] = {
3793 	SSI_SCK5_MARK, SSI_WS5_MARK,
3794 };
3795 static const unsigned int ssi6_data_pins[] = {
3796 	/* SDATA */
3797 	RCAR_GP_PIN(6, 16),
3798 };
3799 static const unsigned int ssi6_data_mux[] = {
3800 	SSI_SDATA6_MARK,
3801 };
3802 static const unsigned int ssi6_ctrl_pins[] = {
3803 	/* SCK, WS */
3804 	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3805 };
3806 static const unsigned int ssi6_ctrl_mux[] = {
3807 	SSI_SCK6_MARK, SSI_WS6_MARK,
3808 };
3809 static const unsigned int ssi7_data_pins[] = {
3810 	/* SDATA */
3811 	RCAR_GP_PIN(6, 19),
3812 };
3813 static const unsigned int ssi7_data_mux[] = {
3814 	SSI_SDATA7_MARK,
3815 };
3816 static const unsigned int ssi78_ctrl_pins[] = {
3817 	/* SCK, WS */
3818 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3819 };
3820 static const unsigned int ssi78_ctrl_mux[] = {
3821 	SSI_SCK78_MARK, SSI_WS78_MARK,
3822 };
3823 static const unsigned int ssi8_data_pins[] = {
3824 	/* SDATA */
3825 	RCAR_GP_PIN(6, 20),
3826 };
3827 static const unsigned int ssi8_data_mux[] = {
3828 	SSI_SDATA8_MARK,
3829 };
3830 static const unsigned int ssi9_data_a_pins[] = {
3831 	/* SDATA */
3832 	RCAR_GP_PIN(6, 21),
3833 };
3834 static const unsigned int ssi9_data_a_mux[] = {
3835 	SSI_SDATA9_A_MARK,
3836 };
3837 static const unsigned int ssi9_data_b_pins[] = {
3838 	/* SDATA */
3839 	RCAR_GP_PIN(5, 14),
3840 };
3841 static const unsigned int ssi9_data_b_mux[] = {
3842 	SSI_SDATA9_B_MARK,
3843 };
3844 static const unsigned int ssi9_ctrl_a_pins[] = {
3845 	/* SCK, WS */
3846 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3847 };
3848 static const unsigned int ssi9_ctrl_a_mux[] = {
3849 	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3850 };
3851 static const unsigned int ssi9_ctrl_b_pins[] = {
3852 	/* SCK, WS */
3853 	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3854 };
3855 static const unsigned int ssi9_ctrl_b_mux[] = {
3856 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3857 };
3858 
3859 /* - TMU -------------------------------------------------------------------- */
3860 static const unsigned int tmu_tclk1_a_pins[] = {
3861 	/* TCLK */
3862 	RCAR_GP_PIN(6, 23),
3863 };
3864 static const unsigned int tmu_tclk1_a_mux[] = {
3865 	TCLK1_A_MARK,
3866 };
3867 static const unsigned int tmu_tclk1_b_pins[] = {
3868 	/* TCLK */
3869 	RCAR_GP_PIN(5, 19),
3870 };
3871 static const unsigned int tmu_tclk1_b_mux[] = {
3872 	TCLK1_B_MARK,
3873 };
3874 static const unsigned int tmu_tclk2_a_pins[] = {
3875 	/* TCLK */
3876 	RCAR_GP_PIN(6, 19),
3877 };
3878 static const unsigned int tmu_tclk2_a_mux[] = {
3879 	TCLK2_A_MARK,
3880 };
3881 static const unsigned int tmu_tclk2_b_pins[] = {
3882 	/* TCLK */
3883 	RCAR_GP_PIN(6, 28),
3884 };
3885 static const unsigned int tmu_tclk2_b_mux[] = {
3886 	TCLK2_B_MARK,
3887 };
3888 
3889 /* - USB0 ------------------------------------------------------------------- */
3890 static const unsigned int usb0_pins[] = {
3891 	/* PWEN, OVC */
3892 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3893 };
3894 static const unsigned int usb0_mux[] = {
3895 	USB0_PWEN_MARK, USB0_OVC_MARK,
3896 };
3897 /* - USB1 ------------------------------------------------------------------- */
3898 static const unsigned int usb1_pins[] = {
3899 	/* PWEN, OVC */
3900 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3901 };
3902 static const unsigned int usb1_mux[] = {
3903 	USB1_PWEN_MARK, USB1_OVC_MARK,
3904 };
3905 /* - USB2 ------------------------------------------------------------------- */
3906 static const unsigned int usb2_pins[] = {
3907 	/* PWEN, OVC */
3908 	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3909 };
3910 static const unsigned int usb2_mux[] = {
3911 	USB2_PWEN_MARK, USB2_OVC_MARK,
3912 };
3913 /* - USB2_CH3 --------------------------------------------------------------- */
3914 static const unsigned int usb2_ch3_pins[] = {
3915 	/* PWEN, OVC */
3916 	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3917 };
3918 static const unsigned int usb2_ch3_mux[] = {
3919 	USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3920 };
3921 
3922 /* - USB30 ------------------------------------------------------------------ */
3923 static const unsigned int usb30_pins[] = {
3924 	/* PWEN, OVC */
3925 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3926 };
3927 static const unsigned int usb30_mux[] = {
3928 	USB30_PWEN_MARK, USB30_OVC_MARK,
3929 };
3930 
3931 /* - VIN4 ------------------------------------------------------------------- */
3932 static const unsigned int vin4_data18_a_pins[] = {
3933 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3934 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3935 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3936 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3937 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3938 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3939 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3940 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3941 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3942 };
3943 static const unsigned int vin4_data18_a_mux[] = {
3944 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3945 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3946 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3947 	VI4_DATA10_MARK, VI4_DATA11_MARK,
3948 	VI4_DATA12_MARK, VI4_DATA13_MARK,
3949 	VI4_DATA14_MARK, VI4_DATA15_MARK,
3950 	VI4_DATA18_MARK, VI4_DATA19_MARK,
3951 	VI4_DATA20_MARK, VI4_DATA21_MARK,
3952 	VI4_DATA22_MARK, VI4_DATA23_MARK,
3953 };
3954 static const unsigned int vin4_data18_b_pins[] = {
3955 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3956 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3957 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3958 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3959 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3960 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3961 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3962 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3963 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3964 };
3965 static const unsigned int vin4_data18_b_mux[] = {
3966 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3967 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3968 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3969 	VI4_DATA10_MARK, VI4_DATA11_MARK,
3970 	VI4_DATA12_MARK, VI4_DATA13_MARK,
3971 	VI4_DATA14_MARK, VI4_DATA15_MARK,
3972 	VI4_DATA18_MARK, VI4_DATA19_MARK,
3973 	VI4_DATA20_MARK, VI4_DATA21_MARK,
3974 	VI4_DATA22_MARK, VI4_DATA23_MARK,
3975 };
3976 static const union vin_data vin4_data_a_pins = {
3977 	.data24 = {
3978 		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3979 		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3980 		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3981 		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3982 		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3983 		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3984 		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3985 		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3986 		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3987 		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3988 		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3989 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3990 	},
3991 };
3992 static const union vin_data vin4_data_a_mux = {
3993 	.data24 = {
3994 		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3995 		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3996 		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3997 		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3998 		VI4_DATA8_MARK,  VI4_DATA9_MARK,
3999 		VI4_DATA10_MARK, VI4_DATA11_MARK,
4000 		VI4_DATA12_MARK, VI4_DATA13_MARK,
4001 		VI4_DATA14_MARK, VI4_DATA15_MARK,
4002 		VI4_DATA16_MARK, VI4_DATA17_MARK,
4003 		VI4_DATA18_MARK, VI4_DATA19_MARK,
4004 		VI4_DATA20_MARK, VI4_DATA21_MARK,
4005 		VI4_DATA22_MARK, VI4_DATA23_MARK,
4006 	},
4007 };
4008 static const union vin_data vin4_data_b_pins = {
4009 	.data24 = {
4010 		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4011 		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4012 		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4013 		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4014 		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4015 		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4016 		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4017 		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4018 		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4019 		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4020 		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4021 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4022 	},
4023 };
4024 static const union vin_data vin4_data_b_mux = {
4025 	.data24 = {
4026 		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4027 		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4028 		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4029 		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4030 		VI4_DATA8_MARK,  VI4_DATA9_MARK,
4031 		VI4_DATA10_MARK, VI4_DATA11_MARK,
4032 		VI4_DATA12_MARK, VI4_DATA13_MARK,
4033 		VI4_DATA14_MARK, VI4_DATA15_MARK,
4034 		VI4_DATA16_MARK, VI4_DATA17_MARK,
4035 		VI4_DATA18_MARK, VI4_DATA19_MARK,
4036 		VI4_DATA20_MARK, VI4_DATA21_MARK,
4037 		VI4_DATA22_MARK, VI4_DATA23_MARK,
4038 	},
4039 };
4040 static const unsigned int vin4_sync_pins[] = {
4041 	/* HSYNC#, VSYNC# */
4042 	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4043 };
4044 static const unsigned int vin4_sync_mux[] = {
4045 	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4046 };
4047 static const unsigned int vin4_field_pins[] = {
4048 	/* FIELD */
4049 	RCAR_GP_PIN(1, 16),
4050 };
4051 static const unsigned int vin4_field_mux[] = {
4052 	VI4_FIELD_MARK,
4053 };
4054 static const unsigned int vin4_clkenb_pins[] = {
4055 	/* CLKENB */
4056 	RCAR_GP_PIN(1, 19),
4057 };
4058 static const unsigned int vin4_clkenb_mux[] = {
4059 	VI4_CLKENB_MARK,
4060 };
4061 static const unsigned int vin4_clk_pins[] = {
4062 	/* CLK */
4063 	RCAR_GP_PIN(1, 27),
4064 };
4065 static const unsigned int vin4_clk_mux[] = {
4066 	VI4_CLK_MARK,
4067 };
4068 
4069 /* - VIN5 ------------------------------------------------------------------- */
4070 static const unsigned int vin5_data8_pins[] = {
4071 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4072 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4073 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4074 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4075 };
4076 static const unsigned int vin5_data8_mux[] = {
4077 	VI5_DATA0_MARK, VI5_DATA1_MARK,
4078 	VI5_DATA2_MARK, VI5_DATA3_MARK,
4079 	VI5_DATA4_MARK, VI5_DATA5_MARK,
4080 	VI5_DATA6_MARK, VI5_DATA7_MARK,
4081 };
4082 static const unsigned int vin5_data10_pins[] = {
4083 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4084 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4085 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4086 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4087 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4088 };
4089 static const unsigned int vin5_data10_mux[] = {
4090 	VI5_DATA0_MARK, VI5_DATA1_MARK,
4091 	VI5_DATA2_MARK, VI5_DATA3_MARK,
4092 	VI5_DATA4_MARK, VI5_DATA5_MARK,
4093 	VI5_DATA6_MARK, VI5_DATA7_MARK,
4094 	VI5_DATA8_MARK,  VI5_DATA9_MARK,
4095 };
4096 static const unsigned int vin5_data12_pins[] = {
4097 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4098 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4099 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4100 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4101 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4102 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4103 };
4104 static const unsigned int vin5_data12_mux[] = {
4105 	VI5_DATA0_MARK, VI5_DATA1_MARK,
4106 	VI5_DATA2_MARK, VI5_DATA3_MARK,
4107 	VI5_DATA4_MARK, VI5_DATA5_MARK,
4108 	VI5_DATA6_MARK, VI5_DATA7_MARK,
4109 	VI5_DATA8_MARK,  VI5_DATA9_MARK,
4110 	VI5_DATA10_MARK, VI5_DATA11_MARK,
4111 };
4112 static const unsigned int vin5_data16_pins[] = {
4113 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4114 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4115 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4116 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4117 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4118 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4119 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4120 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4121 };
4122 static const unsigned int vin5_data16_mux[] = {
4123 	VI5_DATA0_MARK, VI5_DATA1_MARK,
4124 	VI5_DATA2_MARK, VI5_DATA3_MARK,
4125 	VI5_DATA4_MARK, VI5_DATA5_MARK,
4126 	VI5_DATA6_MARK, VI5_DATA7_MARK,
4127 	VI5_DATA8_MARK,  VI5_DATA9_MARK,
4128 	VI5_DATA10_MARK, VI5_DATA11_MARK,
4129 	VI5_DATA12_MARK, VI5_DATA13_MARK,
4130 	VI5_DATA14_MARK, VI5_DATA15_MARK,
4131 };
4132 static const unsigned int vin5_sync_pins[] = {
4133 	/* HSYNC#, VSYNC# */
4134 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4135 };
4136 static const unsigned int vin5_sync_mux[] = {
4137 	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4138 };
4139 static const unsigned int vin5_field_pins[] = {
4140 	RCAR_GP_PIN(1, 11),
4141 };
4142 static const unsigned int vin5_field_mux[] = {
4143 	/* FIELD */
4144 	VI5_FIELD_MARK,
4145 };
4146 static const unsigned int vin5_clkenb_pins[] = {
4147 	RCAR_GP_PIN(1, 20),
4148 };
4149 static const unsigned int vin5_clkenb_mux[] = {
4150 	/* CLKENB */
4151 	VI5_CLKENB_MARK,
4152 };
4153 static const unsigned int vin5_clk_pins[] = {
4154 	RCAR_GP_PIN(1, 21),
4155 };
4156 static const unsigned int vin5_clk_mux[] = {
4157 	/* CLK */
4158 	VI5_CLK_MARK,
4159 };
4160 
4161 static const struct sh_pfc_pin_group pinmux_groups[] = {
4162 	SH_PFC_PIN_GROUP(audio_clk_a_a),
4163 	SH_PFC_PIN_GROUP(audio_clk_a_b),
4164 	SH_PFC_PIN_GROUP(audio_clk_a_c),
4165 	SH_PFC_PIN_GROUP(audio_clk_b_a),
4166 	SH_PFC_PIN_GROUP(audio_clk_b_b),
4167 	SH_PFC_PIN_GROUP(audio_clk_c_a),
4168 	SH_PFC_PIN_GROUP(audio_clk_c_b),
4169 	SH_PFC_PIN_GROUP(audio_clkout_a),
4170 	SH_PFC_PIN_GROUP(audio_clkout_b),
4171 	SH_PFC_PIN_GROUP(audio_clkout_c),
4172 	SH_PFC_PIN_GROUP(audio_clkout_d),
4173 	SH_PFC_PIN_GROUP(audio_clkout1_a),
4174 	SH_PFC_PIN_GROUP(audio_clkout1_b),
4175 	SH_PFC_PIN_GROUP(audio_clkout2_a),
4176 	SH_PFC_PIN_GROUP(audio_clkout2_b),
4177 	SH_PFC_PIN_GROUP(audio_clkout3_a),
4178 	SH_PFC_PIN_GROUP(audio_clkout3_b),
4179 	SH_PFC_PIN_GROUP(avb_link),
4180 	SH_PFC_PIN_GROUP(avb_magic),
4181 	SH_PFC_PIN_GROUP(avb_phy_int),
4182 	SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
4183 	SH_PFC_PIN_GROUP(avb_mdio),
4184 	SH_PFC_PIN_GROUP(avb_mii),
4185 	SH_PFC_PIN_GROUP(avb_avtp_pps),
4186 	SH_PFC_PIN_GROUP(avb_avtp_match_a),
4187 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4188 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
4189 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4190 	SH_PFC_PIN_GROUP(can0_data_a),
4191 	SH_PFC_PIN_GROUP(can0_data_b),
4192 	SH_PFC_PIN_GROUP(can1_data),
4193 	SH_PFC_PIN_GROUP(can_clk),
4194 	SH_PFC_PIN_GROUP(canfd0_data_a),
4195 	SH_PFC_PIN_GROUP(canfd0_data_b),
4196 	SH_PFC_PIN_GROUP(canfd1_data),
4197 	SH_PFC_PIN_GROUP(drif0_ctrl_a),
4198 	SH_PFC_PIN_GROUP(drif0_data0_a),
4199 	SH_PFC_PIN_GROUP(drif0_data1_a),
4200 	SH_PFC_PIN_GROUP(drif0_ctrl_b),
4201 	SH_PFC_PIN_GROUP(drif0_data0_b),
4202 	SH_PFC_PIN_GROUP(drif0_data1_b),
4203 	SH_PFC_PIN_GROUP(drif0_ctrl_c),
4204 	SH_PFC_PIN_GROUP(drif0_data0_c),
4205 	SH_PFC_PIN_GROUP(drif0_data1_c),
4206 	SH_PFC_PIN_GROUP(drif1_ctrl_a),
4207 	SH_PFC_PIN_GROUP(drif1_data0_a),
4208 	SH_PFC_PIN_GROUP(drif1_data1_a),
4209 	SH_PFC_PIN_GROUP(drif1_ctrl_b),
4210 	SH_PFC_PIN_GROUP(drif1_data0_b),
4211 	SH_PFC_PIN_GROUP(drif1_data1_b),
4212 	SH_PFC_PIN_GROUP(drif1_ctrl_c),
4213 	SH_PFC_PIN_GROUP(drif1_data0_c),
4214 	SH_PFC_PIN_GROUP(drif1_data1_c),
4215 	SH_PFC_PIN_GROUP(drif2_ctrl_a),
4216 	SH_PFC_PIN_GROUP(drif2_data0_a),
4217 	SH_PFC_PIN_GROUP(drif2_data1_a),
4218 	SH_PFC_PIN_GROUP(drif2_ctrl_b),
4219 	SH_PFC_PIN_GROUP(drif2_data0_b),
4220 	SH_PFC_PIN_GROUP(drif2_data1_b),
4221 	SH_PFC_PIN_GROUP(drif3_ctrl_a),
4222 	SH_PFC_PIN_GROUP(drif3_data0_a),
4223 	SH_PFC_PIN_GROUP(drif3_data1_a),
4224 	SH_PFC_PIN_GROUP(drif3_ctrl_b),
4225 	SH_PFC_PIN_GROUP(drif3_data0_b),
4226 	SH_PFC_PIN_GROUP(drif3_data1_b),
4227 	SH_PFC_PIN_GROUP(du_rgb666),
4228 	SH_PFC_PIN_GROUP(du_rgb888),
4229 	SH_PFC_PIN_GROUP(du_clk_out_0),
4230 	SH_PFC_PIN_GROUP(du_clk_out_1),
4231 	SH_PFC_PIN_GROUP(du_sync),
4232 	SH_PFC_PIN_GROUP(du_oddf),
4233 	SH_PFC_PIN_GROUP(du_cde),
4234 	SH_PFC_PIN_GROUP(du_disp),
4235 	SH_PFC_PIN_GROUP(gp7_02),
4236 	SH_PFC_PIN_GROUP(gp7_03),
4237 	SH_PFC_PIN_GROUP(hscif0_data),
4238 	SH_PFC_PIN_GROUP(hscif0_clk),
4239 	SH_PFC_PIN_GROUP(hscif0_ctrl),
4240 	SH_PFC_PIN_GROUP(hscif1_data_a),
4241 	SH_PFC_PIN_GROUP(hscif1_clk_a),
4242 	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4243 	SH_PFC_PIN_GROUP(hscif1_data_b),
4244 	SH_PFC_PIN_GROUP(hscif1_clk_b),
4245 	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4246 	SH_PFC_PIN_GROUP(hscif2_data_a),
4247 	SH_PFC_PIN_GROUP(hscif2_clk_a),
4248 	SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4249 	SH_PFC_PIN_GROUP(hscif2_data_b),
4250 	SH_PFC_PIN_GROUP(hscif2_clk_b),
4251 	SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4252 	SH_PFC_PIN_GROUP(hscif2_data_c),
4253 	SH_PFC_PIN_GROUP(hscif2_clk_c),
4254 	SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4255 	SH_PFC_PIN_GROUP(hscif3_data_a),
4256 	SH_PFC_PIN_GROUP(hscif3_clk),
4257 	SH_PFC_PIN_GROUP(hscif3_ctrl),
4258 	SH_PFC_PIN_GROUP(hscif3_data_b),
4259 	SH_PFC_PIN_GROUP(hscif3_data_c),
4260 	SH_PFC_PIN_GROUP(hscif3_data_d),
4261 	SH_PFC_PIN_GROUP(hscif4_data_a),
4262 	SH_PFC_PIN_GROUP(hscif4_clk),
4263 	SH_PFC_PIN_GROUP(hscif4_ctrl),
4264 	SH_PFC_PIN_GROUP(hscif4_data_b),
4265 	SH_PFC_PIN_GROUP(i2c1_a),
4266 	SH_PFC_PIN_GROUP(i2c1_b),
4267 	SH_PFC_PIN_GROUP(i2c2_a),
4268 	SH_PFC_PIN_GROUP(i2c2_b),
4269 	SH_PFC_PIN_GROUP(i2c6_a),
4270 	SH_PFC_PIN_GROUP(i2c6_b),
4271 	SH_PFC_PIN_GROUP(i2c6_c),
4272 	SH_PFC_PIN_GROUP(intc_ex_irq0),
4273 	SH_PFC_PIN_GROUP(intc_ex_irq1),
4274 	SH_PFC_PIN_GROUP(intc_ex_irq2),
4275 	SH_PFC_PIN_GROUP(intc_ex_irq3),
4276 	SH_PFC_PIN_GROUP(intc_ex_irq4),
4277 	SH_PFC_PIN_GROUP(intc_ex_irq5),
4278 	SH_PFC_PIN_GROUP(msiof0_clk),
4279 	SH_PFC_PIN_GROUP(msiof0_sync),
4280 	SH_PFC_PIN_GROUP(msiof0_ss1),
4281 	SH_PFC_PIN_GROUP(msiof0_ss2),
4282 	SH_PFC_PIN_GROUP(msiof0_txd),
4283 	SH_PFC_PIN_GROUP(msiof0_rxd),
4284 	SH_PFC_PIN_GROUP(msiof1_clk_a),
4285 	SH_PFC_PIN_GROUP(msiof1_sync_a),
4286 	SH_PFC_PIN_GROUP(msiof1_ss1_a),
4287 	SH_PFC_PIN_GROUP(msiof1_ss2_a),
4288 	SH_PFC_PIN_GROUP(msiof1_txd_a),
4289 	SH_PFC_PIN_GROUP(msiof1_rxd_a),
4290 	SH_PFC_PIN_GROUP(msiof1_clk_b),
4291 	SH_PFC_PIN_GROUP(msiof1_sync_b),
4292 	SH_PFC_PIN_GROUP(msiof1_ss1_b),
4293 	SH_PFC_PIN_GROUP(msiof1_ss2_b),
4294 	SH_PFC_PIN_GROUP(msiof1_txd_b),
4295 	SH_PFC_PIN_GROUP(msiof1_rxd_b),
4296 	SH_PFC_PIN_GROUP(msiof1_clk_c),
4297 	SH_PFC_PIN_GROUP(msiof1_sync_c),
4298 	SH_PFC_PIN_GROUP(msiof1_ss1_c),
4299 	SH_PFC_PIN_GROUP(msiof1_ss2_c),
4300 	SH_PFC_PIN_GROUP(msiof1_txd_c),
4301 	SH_PFC_PIN_GROUP(msiof1_rxd_c),
4302 	SH_PFC_PIN_GROUP(msiof1_clk_d),
4303 	SH_PFC_PIN_GROUP(msiof1_sync_d),
4304 	SH_PFC_PIN_GROUP(msiof1_ss1_d),
4305 	SH_PFC_PIN_GROUP(msiof1_ss2_d),
4306 	SH_PFC_PIN_GROUP(msiof1_txd_d),
4307 	SH_PFC_PIN_GROUP(msiof1_rxd_d),
4308 	SH_PFC_PIN_GROUP(msiof1_clk_e),
4309 	SH_PFC_PIN_GROUP(msiof1_sync_e),
4310 	SH_PFC_PIN_GROUP(msiof1_ss1_e),
4311 	SH_PFC_PIN_GROUP(msiof1_ss2_e),
4312 	SH_PFC_PIN_GROUP(msiof1_txd_e),
4313 	SH_PFC_PIN_GROUP(msiof1_rxd_e),
4314 	SH_PFC_PIN_GROUP(msiof1_clk_f),
4315 	SH_PFC_PIN_GROUP(msiof1_sync_f),
4316 	SH_PFC_PIN_GROUP(msiof1_ss1_f),
4317 	SH_PFC_PIN_GROUP(msiof1_ss2_f),
4318 	SH_PFC_PIN_GROUP(msiof1_txd_f),
4319 	SH_PFC_PIN_GROUP(msiof1_rxd_f),
4320 	SH_PFC_PIN_GROUP(msiof1_clk_g),
4321 	SH_PFC_PIN_GROUP(msiof1_sync_g),
4322 	SH_PFC_PIN_GROUP(msiof1_ss1_g),
4323 	SH_PFC_PIN_GROUP(msiof1_ss2_g),
4324 	SH_PFC_PIN_GROUP(msiof1_txd_g),
4325 	SH_PFC_PIN_GROUP(msiof1_rxd_g),
4326 	SH_PFC_PIN_GROUP(msiof2_clk_a),
4327 	SH_PFC_PIN_GROUP(msiof2_sync_a),
4328 	SH_PFC_PIN_GROUP(msiof2_ss1_a),
4329 	SH_PFC_PIN_GROUP(msiof2_ss2_a),
4330 	SH_PFC_PIN_GROUP(msiof2_txd_a),
4331 	SH_PFC_PIN_GROUP(msiof2_rxd_a),
4332 	SH_PFC_PIN_GROUP(msiof2_clk_b),
4333 	SH_PFC_PIN_GROUP(msiof2_sync_b),
4334 	SH_PFC_PIN_GROUP(msiof2_ss1_b),
4335 	SH_PFC_PIN_GROUP(msiof2_ss2_b),
4336 	SH_PFC_PIN_GROUP(msiof2_txd_b),
4337 	SH_PFC_PIN_GROUP(msiof2_rxd_b),
4338 	SH_PFC_PIN_GROUP(msiof2_clk_c),
4339 	SH_PFC_PIN_GROUP(msiof2_sync_c),
4340 	SH_PFC_PIN_GROUP(msiof2_ss1_c),
4341 	SH_PFC_PIN_GROUP(msiof2_ss2_c),
4342 	SH_PFC_PIN_GROUP(msiof2_txd_c),
4343 	SH_PFC_PIN_GROUP(msiof2_rxd_c),
4344 	SH_PFC_PIN_GROUP(msiof2_clk_d),
4345 	SH_PFC_PIN_GROUP(msiof2_sync_d),
4346 	SH_PFC_PIN_GROUP(msiof2_ss1_d),
4347 	SH_PFC_PIN_GROUP(msiof2_ss2_d),
4348 	SH_PFC_PIN_GROUP(msiof2_txd_d),
4349 	SH_PFC_PIN_GROUP(msiof2_rxd_d),
4350 	SH_PFC_PIN_GROUP(msiof3_clk_a),
4351 	SH_PFC_PIN_GROUP(msiof3_sync_a),
4352 	SH_PFC_PIN_GROUP(msiof3_ss1_a),
4353 	SH_PFC_PIN_GROUP(msiof3_ss2_a),
4354 	SH_PFC_PIN_GROUP(msiof3_txd_a),
4355 	SH_PFC_PIN_GROUP(msiof3_rxd_a),
4356 	SH_PFC_PIN_GROUP(msiof3_clk_b),
4357 	SH_PFC_PIN_GROUP(msiof3_sync_b),
4358 	SH_PFC_PIN_GROUP(msiof3_ss1_b),
4359 	SH_PFC_PIN_GROUP(msiof3_ss2_b),
4360 	SH_PFC_PIN_GROUP(msiof3_txd_b),
4361 	SH_PFC_PIN_GROUP(msiof3_rxd_b),
4362 	SH_PFC_PIN_GROUP(msiof3_clk_c),
4363 	SH_PFC_PIN_GROUP(msiof3_sync_c),
4364 	SH_PFC_PIN_GROUP(msiof3_txd_c),
4365 	SH_PFC_PIN_GROUP(msiof3_rxd_c),
4366 	SH_PFC_PIN_GROUP(msiof3_clk_d),
4367 	SH_PFC_PIN_GROUP(msiof3_sync_d),
4368 	SH_PFC_PIN_GROUP(msiof3_ss1_d),
4369 	SH_PFC_PIN_GROUP(msiof3_txd_d),
4370 	SH_PFC_PIN_GROUP(msiof3_rxd_d),
4371 	SH_PFC_PIN_GROUP(msiof3_clk_e),
4372 	SH_PFC_PIN_GROUP(msiof3_sync_e),
4373 	SH_PFC_PIN_GROUP(msiof3_ss1_e),
4374 	SH_PFC_PIN_GROUP(msiof3_ss2_e),
4375 	SH_PFC_PIN_GROUP(msiof3_txd_e),
4376 	SH_PFC_PIN_GROUP(msiof3_rxd_e),
4377 	SH_PFC_PIN_GROUP(pwm0),
4378 	SH_PFC_PIN_GROUP(pwm1_a),
4379 	SH_PFC_PIN_GROUP(pwm1_b),
4380 	SH_PFC_PIN_GROUP(pwm2_a),
4381 	SH_PFC_PIN_GROUP(pwm2_b),
4382 	SH_PFC_PIN_GROUP(pwm3_a),
4383 	SH_PFC_PIN_GROUP(pwm3_b),
4384 	SH_PFC_PIN_GROUP(pwm4_a),
4385 	SH_PFC_PIN_GROUP(pwm4_b),
4386 	SH_PFC_PIN_GROUP(pwm5_a),
4387 	SH_PFC_PIN_GROUP(pwm5_b),
4388 	SH_PFC_PIN_GROUP(pwm6_a),
4389 	SH_PFC_PIN_GROUP(pwm6_b),
4390 	SH_PFC_PIN_GROUP(sata0_devslp_a),
4391 	SH_PFC_PIN_GROUP(sata0_devslp_b),
4392 	SH_PFC_PIN_GROUP(scif0_data),
4393 	SH_PFC_PIN_GROUP(scif0_clk),
4394 	SH_PFC_PIN_GROUP(scif0_ctrl),
4395 	SH_PFC_PIN_GROUP(scif1_data_a),
4396 	SH_PFC_PIN_GROUP(scif1_clk),
4397 	SH_PFC_PIN_GROUP(scif1_ctrl),
4398 	SH_PFC_PIN_GROUP(scif1_data_b),
4399 	SH_PFC_PIN_GROUP(scif2_data_a),
4400 	SH_PFC_PIN_GROUP(scif2_clk),
4401 	SH_PFC_PIN_GROUP(scif2_data_b),
4402 	SH_PFC_PIN_GROUP(scif3_data_a),
4403 	SH_PFC_PIN_GROUP(scif3_clk),
4404 	SH_PFC_PIN_GROUP(scif3_ctrl),
4405 	SH_PFC_PIN_GROUP(scif3_data_b),
4406 	SH_PFC_PIN_GROUP(scif4_data_a),
4407 	SH_PFC_PIN_GROUP(scif4_clk_a),
4408 	SH_PFC_PIN_GROUP(scif4_ctrl_a),
4409 	SH_PFC_PIN_GROUP(scif4_data_b),
4410 	SH_PFC_PIN_GROUP(scif4_clk_b),
4411 	SH_PFC_PIN_GROUP(scif4_ctrl_b),
4412 	SH_PFC_PIN_GROUP(scif4_data_c),
4413 	SH_PFC_PIN_GROUP(scif4_clk_c),
4414 	SH_PFC_PIN_GROUP(scif4_ctrl_c),
4415 	SH_PFC_PIN_GROUP(scif5_data_a),
4416 	SH_PFC_PIN_GROUP(scif5_clk_a),
4417 	SH_PFC_PIN_GROUP(scif5_data_b),
4418 	SH_PFC_PIN_GROUP(scif5_clk_b),
4419 	SH_PFC_PIN_GROUP(scif_clk_a),
4420 	SH_PFC_PIN_GROUP(scif_clk_b),
4421 	SH_PFC_PIN_GROUP(sdhi0_data1),
4422 	SH_PFC_PIN_GROUP(sdhi0_data4),
4423 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
4424 	SH_PFC_PIN_GROUP(sdhi0_cd),
4425 	SH_PFC_PIN_GROUP(sdhi0_wp),
4426 	SH_PFC_PIN_GROUP(sdhi1_data1),
4427 	SH_PFC_PIN_GROUP(sdhi1_data4),
4428 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
4429 	SH_PFC_PIN_GROUP(sdhi1_cd),
4430 	SH_PFC_PIN_GROUP(sdhi1_wp),
4431 	SH_PFC_PIN_GROUP(sdhi2_data1),
4432 	SH_PFC_PIN_GROUP(sdhi2_data4),
4433 	SH_PFC_PIN_GROUP(sdhi2_data8),
4434 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
4435 	SH_PFC_PIN_GROUP(sdhi2_cd_a),
4436 	SH_PFC_PIN_GROUP(sdhi2_wp_a),
4437 	SH_PFC_PIN_GROUP(sdhi2_cd_b),
4438 	SH_PFC_PIN_GROUP(sdhi2_wp_b),
4439 	SH_PFC_PIN_GROUP(sdhi2_ds),
4440 	SH_PFC_PIN_GROUP(sdhi3_data1),
4441 	SH_PFC_PIN_GROUP(sdhi3_data4),
4442 	SH_PFC_PIN_GROUP(sdhi3_data8),
4443 	SH_PFC_PIN_GROUP(sdhi3_ctrl),
4444 	SH_PFC_PIN_GROUP(sdhi3_cd),
4445 	SH_PFC_PIN_GROUP(sdhi3_wp),
4446 	SH_PFC_PIN_GROUP(sdhi3_ds),
4447 	SH_PFC_PIN_GROUP(ssi0_data),
4448 	SH_PFC_PIN_GROUP(ssi01239_ctrl),
4449 	SH_PFC_PIN_GROUP(ssi1_data_a),
4450 	SH_PFC_PIN_GROUP(ssi1_data_b),
4451 	SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4452 	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4453 	SH_PFC_PIN_GROUP(ssi2_data_a),
4454 	SH_PFC_PIN_GROUP(ssi2_data_b),
4455 	SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4456 	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4457 	SH_PFC_PIN_GROUP(ssi3_data),
4458 	SH_PFC_PIN_GROUP(ssi349_ctrl),
4459 	SH_PFC_PIN_GROUP(ssi4_data),
4460 	SH_PFC_PIN_GROUP(ssi4_ctrl),
4461 	SH_PFC_PIN_GROUP(ssi5_data),
4462 	SH_PFC_PIN_GROUP(ssi5_ctrl),
4463 	SH_PFC_PIN_GROUP(ssi6_data),
4464 	SH_PFC_PIN_GROUP(ssi6_ctrl),
4465 	SH_PFC_PIN_GROUP(ssi7_data),
4466 	SH_PFC_PIN_GROUP(ssi78_ctrl),
4467 	SH_PFC_PIN_GROUP(ssi8_data),
4468 	SH_PFC_PIN_GROUP(ssi9_data_a),
4469 	SH_PFC_PIN_GROUP(ssi9_data_b),
4470 	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4471 	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4472 	SH_PFC_PIN_GROUP(tmu_tclk1_a),
4473 	SH_PFC_PIN_GROUP(tmu_tclk1_b),
4474 	SH_PFC_PIN_GROUP(tmu_tclk2_a),
4475 	SH_PFC_PIN_GROUP(tmu_tclk2_b),
4476 	SH_PFC_PIN_GROUP(usb0),
4477 	SH_PFC_PIN_GROUP(usb1),
4478 	SH_PFC_PIN_GROUP(usb2),
4479 	SH_PFC_PIN_GROUP(usb2_ch3),
4480 	SH_PFC_PIN_GROUP(usb30),
4481 	VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4482 	VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4483 	VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4484 	VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4485 	SH_PFC_PIN_GROUP(vin4_data18_a),
4486 	VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4487 	VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4488 	VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4489 	VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4490 	VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4491 	VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4492 	SH_PFC_PIN_GROUP(vin4_data18_b),
4493 	VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4494 	VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4495 	SH_PFC_PIN_GROUP(vin4_sync),
4496 	SH_PFC_PIN_GROUP(vin4_field),
4497 	SH_PFC_PIN_GROUP(vin4_clkenb),
4498 	SH_PFC_PIN_GROUP(vin4_clk),
4499 	SH_PFC_PIN_GROUP(vin5_data8),
4500 	SH_PFC_PIN_GROUP(vin5_data10),
4501 	SH_PFC_PIN_GROUP(vin5_data12),
4502 	SH_PFC_PIN_GROUP(vin5_data16),
4503 	SH_PFC_PIN_GROUP(vin5_sync),
4504 	SH_PFC_PIN_GROUP(vin5_field),
4505 	SH_PFC_PIN_GROUP(vin5_clkenb),
4506 	SH_PFC_PIN_GROUP(vin5_clk),
4507 };
4508 
4509 static const char * const audio_clk_groups[] = {
4510 	"audio_clk_a_a",
4511 	"audio_clk_a_b",
4512 	"audio_clk_a_c",
4513 	"audio_clk_b_a",
4514 	"audio_clk_b_b",
4515 	"audio_clk_c_a",
4516 	"audio_clk_c_b",
4517 	"audio_clkout_a",
4518 	"audio_clkout_b",
4519 	"audio_clkout_c",
4520 	"audio_clkout_d",
4521 	"audio_clkout1_a",
4522 	"audio_clkout1_b",
4523 	"audio_clkout2_a",
4524 	"audio_clkout2_b",
4525 	"audio_clkout3_a",
4526 	"audio_clkout3_b",
4527 };
4528 
4529 static const char * const avb_groups[] = {
4530 	"avb_link",
4531 	"avb_magic",
4532 	"avb_phy_int",
4533 	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
4534 	"avb_mdio",
4535 	"avb_mii",
4536 	"avb_avtp_pps",
4537 	"avb_avtp_match_a",
4538 	"avb_avtp_capture_a",
4539 	"avb_avtp_match_b",
4540 	"avb_avtp_capture_b",
4541 };
4542 
4543 static const char * const can0_groups[] = {
4544 	"can0_data_a",
4545 	"can0_data_b",
4546 };
4547 
4548 static const char * const can1_groups[] = {
4549 	"can1_data",
4550 };
4551 
4552 static const char * const can_clk_groups[] = {
4553 	"can_clk",
4554 };
4555 
4556 static const char * const canfd0_groups[] = {
4557 	"canfd0_data_a",
4558 	"canfd0_data_b",
4559 };
4560 
4561 static const char * const canfd1_groups[] = {
4562 	"canfd1_data",
4563 };
4564 
4565 static const char * const drif0_groups[] = {
4566 	"drif0_ctrl_a",
4567 	"drif0_data0_a",
4568 	"drif0_data1_a",
4569 	"drif0_ctrl_b",
4570 	"drif0_data0_b",
4571 	"drif0_data1_b",
4572 	"drif0_ctrl_c",
4573 	"drif0_data0_c",
4574 	"drif0_data1_c",
4575 };
4576 
4577 static const char * const drif1_groups[] = {
4578 	"drif1_ctrl_a",
4579 	"drif1_data0_a",
4580 	"drif1_data1_a",
4581 	"drif1_ctrl_b",
4582 	"drif1_data0_b",
4583 	"drif1_data1_b",
4584 	"drif1_ctrl_c",
4585 	"drif1_data0_c",
4586 	"drif1_data1_c",
4587 };
4588 
4589 static const char * const drif2_groups[] = {
4590 	"drif2_ctrl_a",
4591 	"drif2_data0_a",
4592 	"drif2_data1_a",
4593 	"drif2_ctrl_b",
4594 	"drif2_data0_b",
4595 	"drif2_data1_b",
4596 };
4597 
4598 static const char * const drif3_groups[] = {
4599 	"drif3_ctrl_a",
4600 	"drif3_data0_a",
4601 	"drif3_data1_a",
4602 	"drif3_ctrl_b",
4603 	"drif3_data0_b",
4604 	"drif3_data1_b",
4605 };
4606 
4607 static const char * const du_groups[] = {
4608 	"du_rgb666",
4609 	"du_rgb888",
4610 	"du_clk_out_0",
4611 	"du_clk_out_1",
4612 	"du_sync",
4613 	"du_oddf",
4614 	"du_cde",
4615 	"du_disp",
4616 };
4617 
4618 static const char * const gp7_02_groups[] = {
4619 	"gp7_02",
4620 };
4621 
4622 static const char * const gp7_03_groups[] = {
4623 	"gp7_03",
4624 };
4625 
4626 static const char * const hscif0_groups[] = {
4627 	"hscif0_data",
4628 	"hscif0_clk",
4629 	"hscif0_ctrl",
4630 };
4631 
4632 static const char * const hscif1_groups[] = {
4633 	"hscif1_data_a",
4634 	"hscif1_clk_a",
4635 	"hscif1_ctrl_a",
4636 	"hscif1_data_b",
4637 	"hscif1_clk_b",
4638 	"hscif1_ctrl_b",
4639 };
4640 
4641 static const char * const hscif2_groups[] = {
4642 	"hscif2_data_a",
4643 	"hscif2_clk_a",
4644 	"hscif2_ctrl_a",
4645 	"hscif2_data_b",
4646 	"hscif2_clk_b",
4647 	"hscif2_ctrl_b",
4648 	"hscif2_data_c",
4649 	"hscif2_clk_c",
4650 	"hscif2_ctrl_c",
4651 };
4652 
4653 static const char * const hscif3_groups[] = {
4654 	"hscif3_data_a",
4655 	"hscif3_clk",
4656 	"hscif3_ctrl",
4657 	"hscif3_data_b",
4658 	"hscif3_data_c",
4659 	"hscif3_data_d",
4660 };
4661 
4662 static const char * const hscif4_groups[] = {
4663 	"hscif4_data_a",
4664 	"hscif4_clk",
4665 	"hscif4_ctrl",
4666 	"hscif4_data_b",
4667 };
4668 
4669 static const char * const i2c1_groups[] = {
4670 	"i2c1_a",
4671 	"i2c1_b",
4672 };
4673 
4674 static const char * const i2c2_groups[] = {
4675 	"i2c2_a",
4676 	"i2c2_b",
4677 };
4678 
4679 static const char * const i2c6_groups[] = {
4680 	"i2c6_a",
4681 	"i2c6_b",
4682 	"i2c6_c",
4683 };
4684 
4685 static const char * const intc_ex_groups[] = {
4686 	"intc_ex_irq0",
4687 	"intc_ex_irq1",
4688 	"intc_ex_irq2",
4689 	"intc_ex_irq3",
4690 	"intc_ex_irq4",
4691 	"intc_ex_irq5",
4692 };
4693 
4694 static const char * const msiof0_groups[] = {
4695 	"msiof0_clk",
4696 	"msiof0_sync",
4697 	"msiof0_ss1",
4698 	"msiof0_ss2",
4699 	"msiof0_txd",
4700 	"msiof0_rxd",
4701 };
4702 
4703 static const char * const msiof1_groups[] = {
4704 	"msiof1_clk_a",
4705 	"msiof1_sync_a",
4706 	"msiof1_ss1_a",
4707 	"msiof1_ss2_a",
4708 	"msiof1_txd_a",
4709 	"msiof1_rxd_a",
4710 	"msiof1_clk_b",
4711 	"msiof1_sync_b",
4712 	"msiof1_ss1_b",
4713 	"msiof1_ss2_b",
4714 	"msiof1_txd_b",
4715 	"msiof1_rxd_b",
4716 	"msiof1_clk_c",
4717 	"msiof1_sync_c",
4718 	"msiof1_ss1_c",
4719 	"msiof1_ss2_c",
4720 	"msiof1_txd_c",
4721 	"msiof1_rxd_c",
4722 	"msiof1_clk_d",
4723 	"msiof1_sync_d",
4724 	"msiof1_ss1_d",
4725 	"msiof1_ss2_d",
4726 	"msiof1_txd_d",
4727 	"msiof1_rxd_d",
4728 	"msiof1_clk_e",
4729 	"msiof1_sync_e",
4730 	"msiof1_ss1_e",
4731 	"msiof1_ss2_e",
4732 	"msiof1_txd_e",
4733 	"msiof1_rxd_e",
4734 	"msiof1_clk_f",
4735 	"msiof1_sync_f",
4736 	"msiof1_ss1_f",
4737 	"msiof1_ss2_f",
4738 	"msiof1_txd_f",
4739 	"msiof1_rxd_f",
4740 	"msiof1_clk_g",
4741 	"msiof1_sync_g",
4742 	"msiof1_ss1_g",
4743 	"msiof1_ss2_g",
4744 	"msiof1_txd_g",
4745 	"msiof1_rxd_g",
4746 };
4747 
4748 static const char * const msiof2_groups[] = {
4749 	"msiof2_clk_a",
4750 	"msiof2_sync_a",
4751 	"msiof2_ss1_a",
4752 	"msiof2_ss2_a",
4753 	"msiof2_txd_a",
4754 	"msiof2_rxd_a",
4755 	"msiof2_clk_b",
4756 	"msiof2_sync_b",
4757 	"msiof2_ss1_b",
4758 	"msiof2_ss2_b",
4759 	"msiof2_txd_b",
4760 	"msiof2_rxd_b",
4761 	"msiof2_clk_c",
4762 	"msiof2_sync_c",
4763 	"msiof2_ss1_c",
4764 	"msiof2_ss2_c",
4765 	"msiof2_txd_c",
4766 	"msiof2_rxd_c",
4767 	"msiof2_clk_d",
4768 	"msiof2_sync_d",
4769 	"msiof2_ss1_d",
4770 	"msiof2_ss2_d",
4771 	"msiof2_txd_d",
4772 	"msiof2_rxd_d",
4773 };
4774 
4775 static const char * const msiof3_groups[] = {
4776 	"msiof3_clk_a",
4777 	"msiof3_sync_a",
4778 	"msiof3_ss1_a",
4779 	"msiof3_ss2_a",
4780 	"msiof3_txd_a",
4781 	"msiof3_rxd_a",
4782 	"msiof3_clk_b",
4783 	"msiof3_sync_b",
4784 	"msiof3_ss1_b",
4785 	"msiof3_ss2_b",
4786 	"msiof3_txd_b",
4787 	"msiof3_rxd_b",
4788 	"msiof3_clk_c",
4789 	"msiof3_sync_c",
4790 	"msiof3_txd_c",
4791 	"msiof3_rxd_c",
4792 	"msiof3_clk_d",
4793 	"msiof3_sync_d",
4794 	"msiof3_ss1_d",
4795 	"msiof3_txd_d",
4796 	"msiof3_rxd_d",
4797 	"msiof3_clk_e",
4798 	"msiof3_sync_e",
4799 	"msiof3_ss1_e",
4800 	"msiof3_ss2_e",
4801 	"msiof3_txd_e",
4802 	"msiof3_rxd_e",
4803 };
4804 
4805 static const char * const pwm0_groups[] = {
4806 	"pwm0",
4807 };
4808 
4809 static const char * const pwm1_groups[] = {
4810 	"pwm1_a",
4811 	"pwm1_b",
4812 };
4813 
4814 static const char * const pwm2_groups[] = {
4815 	"pwm2_a",
4816 	"pwm2_b",
4817 };
4818 
4819 static const char * const pwm3_groups[] = {
4820 	"pwm3_a",
4821 	"pwm3_b",
4822 };
4823 
4824 static const char * const pwm4_groups[] = {
4825 	"pwm4_a",
4826 	"pwm4_b",
4827 };
4828 
4829 static const char * const pwm5_groups[] = {
4830 	"pwm5_a",
4831 	"pwm5_b",
4832 };
4833 
4834 static const char * const pwm6_groups[] = {
4835 	"pwm6_a",
4836 	"pwm6_b",
4837 };
4838 
4839 static const char * const sata0_groups[] = {
4840 	"sata0_devslp_a",
4841 	"sata0_devslp_b",
4842 };
4843 
4844 static const char * const scif0_groups[] = {
4845 	"scif0_data",
4846 	"scif0_clk",
4847 	"scif0_ctrl",
4848 };
4849 
4850 static const char * const scif1_groups[] = {
4851 	"scif1_data_a",
4852 	"scif1_clk",
4853 	"scif1_ctrl",
4854 	"scif1_data_b",
4855 };
4856 
4857 static const char * const scif2_groups[] = {
4858 	"scif2_data_a",
4859 	"scif2_clk",
4860 	"scif2_data_b",
4861 };
4862 
4863 static const char * const scif3_groups[] = {
4864 	"scif3_data_a",
4865 	"scif3_clk",
4866 	"scif3_ctrl",
4867 	"scif3_data_b",
4868 };
4869 
4870 static const char * const scif4_groups[] = {
4871 	"scif4_data_a",
4872 	"scif4_clk_a",
4873 	"scif4_ctrl_a",
4874 	"scif4_data_b",
4875 	"scif4_clk_b",
4876 	"scif4_ctrl_b",
4877 	"scif4_data_c",
4878 	"scif4_clk_c",
4879 	"scif4_ctrl_c",
4880 };
4881 
4882 static const char * const scif5_groups[] = {
4883 	"scif5_data_a",
4884 	"scif5_clk_a",
4885 	"scif5_data_b",
4886 	"scif5_clk_b",
4887 };
4888 
4889 static const char * const scif_clk_groups[] = {
4890 	"scif_clk_a",
4891 	"scif_clk_b",
4892 };
4893 
4894 static const char * const sdhi0_groups[] = {
4895 	"sdhi0_data1",
4896 	"sdhi0_data4",
4897 	"sdhi0_ctrl",
4898 	"sdhi0_cd",
4899 	"sdhi0_wp",
4900 };
4901 
4902 static const char * const sdhi1_groups[] = {
4903 	"sdhi1_data1",
4904 	"sdhi1_data4",
4905 	"sdhi1_ctrl",
4906 	"sdhi1_cd",
4907 	"sdhi1_wp",
4908 };
4909 
4910 static const char * const sdhi2_groups[] = {
4911 	"sdhi2_data1",
4912 	"sdhi2_data4",
4913 	"sdhi2_data8",
4914 	"sdhi2_ctrl",
4915 	"sdhi2_cd_a",
4916 	"sdhi2_wp_a",
4917 	"sdhi2_cd_b",
4918 	"sdhi2_wp_b",
4919 	"sdhi2_ds",
4920 };
4921 
4922 static const char * const sdhi3_groups[] = {
4923 	"sdhi3_data1",
4924 	"sdhi3_data4",
4925 	"sdhi3_data8",
4926 	"sdhi3_ctrl",
4927 	"sdhi3_cd",
4928 	"sdhi3_wp",
4929 	"sdhi3_ds",
4930 };
4931 
4932 static const char * const ssi_groups[] = {
4933 	"ssi0_data",
4934 	"ssi01239_ctrl",
4935 	"ssi1_data_a",
4936 	"ssi1_data_b",
4937 	"ssi1_ctrl_a",
4938 	"ssi1_ctrl_b",
4939 	"ssi2_data_a",
4940 	"ssi2_data_b",
4941 	"ssi2_ctrl_a",
4942 	"ssi2_ctrl_b",
4943 	"ssi3_data",
4944 	"ssi349_ctrl",
4945 	"ssi4_data",
4946 	"ssi4_ctrl",
4947 	"ssi5_data",
4948 	"ssi5_ctrl",
4949 	"ssi6_data",
4950 	"ssi6_ctrl",
4951 	"ssi7_data",
4952 	"ssi78_ctrl",
4953 	"ssi8_data",
4954 	"ssi9_data_a",
4955 	"ssi9_data_b",
4956 	"ssi9_ctrl_a",
4957 	"ssi9_ctrl_b",
4958 };
4959 
4960 static const char * const tmu_groups[] = {
4961 	"tmu_tclk1_a",
4962 	"tmu_tclk1_b",
4963 	"tmu_tclk2_a",
4964 	"tmu_tclk2_b",
4965 };
4966 
4967 static const char * const usb0_groups[] = {
4968 	"usb0",
4969 };
4970 
4971 static const char * const usb1_groups[] = {
4972 	"usb1",
4973 };
4974 
4975 static const char * const usb2_groups[] = {
4976 	"usb2",
4977 };
4978 
4979 static const char * const usb2_ch3_groups[] = {
4980 	"usb2_ch3",
4981 };
4982 
4983 static const char * const usb30_groups[] = {
4984 	"usb30",
4985 };
4986 
4987 static const char * const vin4_groups[] = {
4988 	"vin4_data8_a",
4989 	"vin4_data10_a",
4990 	"vin4_data12_a",
4991 	"vin4_data16_a",
4992 	"vin4_data18_a",
4993 	"vin4_data20_a",
4994 	"vin4_data24_a",
4995 	"vin4_data8_b",
4996 	"vin4_data10_b",
4997 	"vin4_data12_b",
4998 	"vin4_data16_b",
4999 	"vin4_data18_b",
5000 	"vin4_data20_b",
5001 	"vin4_data24_b",
5002 	"vin4_sync",
5003 	"vin4_field",
5004 	"vin4_clkenb",
5005 	"vin4_clk",
5006 };
5007 
5008 static const char * const vin5_groups[] = {
5009 	"vin5_data8",
5010 	"vin5_data10",
5011 	"vin5_data12",
5012 	"vin5_data16",
5013 	"vin5_sync",
5014 	"vin5_field",
5015 	"vin5_clkenb",
5016 	"vin5_clk",
5017 };
5018 
5019 static const struct sh_pfc_function pinmux_functions[] = {
5020 	SH_PFC_FUNCTION(audio_clk),
5021 	SH_PFC_FUNCTION(avb),
5022 	SH_PFC_FUNCTION(can0),
5023 	SH_PFC_FUNCTION(can1),
5024 	SH_PFC_FUNCTION(can_clk),
5025 	SH_PFC_FUNCTION(canfd0),
5026 	SH_PFC_FUNCTION(canfd1),
5027 	SH_PFC_FUNCTION(drif0),
5028 	SH_PFC_FUNCTION(drif1),
5029 	SH_PFC_FUNCTION(drif2),
5030 	SH_PFC_FUNCTION(drif3),
5031 	SH_PFC_FUNCTION(du),
5032 	SH_PFC_FUNCTION(gp7_02),
5033 	SH_PFC_FUNCTION(gp7_03),
5034 	SH_PFC_FUNCTION(hscif0),
5035 	SH_PFC_FUNCTION(hscif1),
5036 	SH_PFC_FUNCTION(hscif2),
5037 	SH_PFC_FUNCTION(hscif3),
5038 	SH_PFC_FUNCTION(hscif4),
5039 	SH_PFC_FUNCTION(i2c1),
5040 	SH_PFC_FUNCTION(i2c2),
5041 	SH_PFC_FUNCTION(i2c6),
5042 	SH_PFC_FUNCTION(intc_ex),
5043 	SH_PFC_FUNCTION(msiof0),
5044 	SH_PFC_FUNCTION(msiof1),
5045 	SH_PFC_FUNCTION(msiof2),
5046 	SH_PFC_FUNCTION(msiof3),
5047 	SH_PFC_FUNCTION(pwm0),
5048 	SH_PFC_FUNCTION(pwm1),
5049 	SH_PFC_FUNCTION(pwm2),
5050 	SH_PFC_FUNCTION(pwm3),
5051 	SH_PFC_FUNCTION(pwm4),
5052 	SH_PFC_FUNCTION(pwm5),
5053 	SH_PFC_FUNCTION(pwm6),
5054 	SH_PFC_FUNCTION(sata0),
5055 	SH_PFC_FUNCTION(scif0),
5056 	SH_PFC_FUNCTION(scif1),
5057 	SH_PFC_FUNCTION(scif2),
5058 	SH_PFC_FUNCTION(scif3),
5059 	SH_PFC_FUNCTION(scif4),
5060 	SH_PFC_FUNCTION(scif5),
5061 	SH_PFC_FUNCTION(scif_clk),
5062 	SH_PFC_FUNCTION(sdhi0),
5063 	SH_PFC_FUNCTION(sdhi1),
5064 	SH_PFC_FUNCTION(sdhi2),
5065 	SH_PFC_FUNCTION(sdhi3),
5066 	SH_PFC_FUNCTION(ssi),
5067 	SH_PFC_FUNCTION(tmu),
5068 	SH_PFC_FUNCTION(usb0),
5069 	SH_PFC_FUNCTION(usb1),
5070 	SH_PFC_FUNCTION(usb2),
5071 	SH_PFC_FUNCTION(usb2_ch3),
5072 	SH_PFC_FUNCTION(usb30),
5073 	SH_PFC_FUNCTION(vin4),
5074 	SH_PFC_FUNCTION(vin5),
5075 };
5076 
5077 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5078 #define F_(x, y)	FN_##y
5079 #define FM(x)		FN_##x
5080 	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5081 		0, 0,
5082 		0, 0,
5083 		0, 0,
5084 		0, 0,
5085 		0, 0,
5086 		0, 0,
5087 		0, 0,
5088 		0, 0,
5089 		0, 0,
5090 		0, 0,
5091 		0, 0,
5092 		0, 0,
5093 		0, 0,
5094 		0, 0,
5095 		0, 0,
5096 		0, 0,
5097 		GP_0_15_FN,	GPSR0_15,
5098 		GP_0_14_FN,	GPSR0_14,
5099 		GP_0_13_FN,	GPSR0_13,
5100 		GP_0_12_FN,	GPSR0_12,
5101 		GP_0_11_FN,	GPSR0_11,
5102 		GP_0_10_FN,	GPSR0_10,
5103 		GP_0_9_FN,	GPSR0_9,
5104 		GP_0_8_FN,	GPSR0_8,
5105 		GP_0_7_FN,	GPSR0_7,
5106 		GP_0_6_FN,	GPSR0_6,
5107 		GP_0_5_FN,	GPSR0_5,
5108 		GP_0_4_FN,	GPSR0_4,
5109 		GP_0_3_FN,	GPSR0_3,
5110 		GP_0_2_FN,	GPSR0_2,
5111 		GP_0_1_FN,	GPSR0_1,
5112 		GP_0_0_FN,	GPSR0_0, }
5113 	},
5114 	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5115 		0, 0,
5116 		0, 0,
5117 		0, 0,
5118 		GP_1_28_FN,	GPSR1_28,
5119 		GP_1_27_FN,	GPSR1_27,
5120 		GP_1_26_FN,	GPSR1_26,
5121 		GP_1_25_FN,	GPSR1_25,
5122 		GP_1_24_FN,	GPSR1_24,
5123 		GP_1_23_FN,	GPSR1_23,
5124 		GP_1_22_FN,	GPSR1_22,
5125 		GP_1_21_FN,	GPSR1_21,
5126 		GP_1_20_FN,	GPSR1_20,
5127 		GP_1_19_FN,	GPSR1_19,
5128 		GP_1_18_FN,	GPSR1_18,
5129 		GP_1_17_FN,	GPSR1_17,
5130 		GP_1_16_FN,	GPSR1_16,
5131 		GP_1_15_FN,	GPSR1_15,
5132 		GP_1_14_FN,	GPSR1_14,
5133 		GP_1_13_FN,	GPSR1_13,
5134 		GP_1_12_FN,	GPSR1_12,
5135 		GP_1_11_FN,	GPSR1_11,
5136 		GP_1_10_FN,	GPSR1_10,
5137 		GP_1_9_FN,	GPSR1_9,
5138 		GP_1_8_FN,	GPSR1_8,
5139 		GP_1_7_FN,	GPSR1_7,
5140 		GP_1_6_FN,	GPSR1_6,
5141 		GP_1_5_FN,	GPSR1_5,
5142 		GP_1_4_FN,	GPSR1_4,
5143 		GP_1_3_FN,	GPSR1_3,
5144 		GP_1_2_FN,	GPSR1_2,
5145 		GP_1_1_FN,	GPSR1_1,
5146 		GP_1_0_FN,	GPSR1_0, }
5147 	},
5148 	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5149 		0, 0,
5150 		0, 0,
5151 		0, 0,
5152 		0, 0,
5153 		0, 0,
5154 		0, 0,
5155 		0, 0,
5156 		0, 0,
5157 		0, 0,
5158 		0, 0,
5159 		0, 0,
5160 		0, 0,
5161 		0, 0,
5162 		0, 0,
5163 		0, 0,
5164 		0, 0,
5165 		0, 0,
5166 		GP_2_14_FN,	GPSR2_14,
5167 		GP_2_13_FN,	GPSR2_13,
5168 		GP_2_12_FN,	GPSR2_12,
5169 		GP_2_11_FN,	GPSR2_11,
5170 		GP_2_10_FN,	GPSR2_10,
5171 		GP_2_9_FN,	GPSR2_9,
5172 		GP_2_8_FN,	GPSR2_8,
5173 		GP_2_7_FN,	GPSR2_7,
5174 		GP_2_6_FN,	GPSR2_6,
5175 		GP_2_5_FN,	GPSR2_5,
5176 		GP_2_4_FN,	GPSR2_4,
5177 		GP_2_3_FN,	GPSR2_3,
5178 		GP_2_2_FN,	GPSR2_2,
5179 		GP_2_1_FN,	GPSR2_1,
5180 		GP_2_0_FN,	GPSR2_0, }
5181 	},
5182 	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5183 		0, 0,
5184 		0, 0,
5185 		0, 0,
5186 		0, 0,
5187 		0, 0,
5188 		0, 0,
5189 		0, 0,
5190 		0, 0,
5191 		0, 0,
5192 		0, 0,
5193 		0, 0,
5194 		0, 0,
5195 		0, 0,
5196 		0, 0,
5197 		0, 0,
5198 		0, 0,
5199 		GP_3_15_FN,	GPSR3_15,
5200 		GP_3_14_FN,	GPSR3_14,
5201 		GP_3_13_FN,	GPSR3_13,
5202 		GP_3_12_FN,	GPSR3_12,
5203 		GP_3_11_FN,	GPSR3_11,
5204 		GP_3_10_FN,	GPSR3_10,
5205 		GP_3_9_FN,	GPSR3_9,
5206 		GP_3_8_FN,	GPSR3_8,
5207 		GP_3_7_FN,	GPSR3_7,
5208 		GP_3_6_FN,	GPSR3_6,
5209 		GP_3_5_FN,	GPSR3_5,
5210 		GP_3_4_FN,	GPSR3_4,
5211 		GP_3_3_FN,	GPSR3_3,
5212 		GP_3_2_FN,	GPSR3_2,
5213 		GP_3_1_FN,	GPSR3_1,
5214 		GP_3_0_FN,	GPSR3_0, }
5215 	},
5216 	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5217 		0, 0,
5218 		0, 0,
5219 		0, 0,
5220 		0, 0,
5221 		0, 0,
5222 		0, 0,
5223 		0, 0,
5224 		0, 0,
5225 		0, 0,
5226 		0, 0,
5227 		0, 0,
5228 		0, 0,
5229 		0, 0,
5230 		0, 0,
5231 		GP_4_17_FN,	GPSR4_17,
5232 		GP_4_16_FN,	GPSR4_16,
5233 		GP_4_15_FN,	GPSR4_15,
5234 		GP_4_14_FN,	GPSR4_14,
5235 		GP_4_13_FN,	GPSR4_13,
5236 		GP_4_12_FN,	GPSR4_12,
5237 		GP_4_11_FN,	GPSR4_11,
5238 		GP_4_10_FN,	GPSR4_10,
5239 		GP_4_9_FN,	GPSR4_9,
5240 		GP_4_8_FN,	GPSR4_8,
5241 		GP_4_7_FN,	GPSR4_7,
5242 		GP_4_6_FN,	GPSR4_6,
5243 		GP_4_5_FN,	GPSR4_5,
5244 		GP_4_4_FN,	GPSR4_4,
5245 		GP_4_3_FN,	GPSR4_3,
5246 		GP_4_2_FN,	GPSR4_2,
5247 		GP_4_1_FN,	GPSR4_1,
5248 		GP_4_0_FN,	GPSR4_0, }
5249 	},
5250 	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5251 		0, 0,
5252 		0, 0,
5253 		0, 0,
5254 		0, 0,
5255 		0, 0,
5256 		0, 0,
5257 		GP_5_25_FN,	GPSR5_25,
5258 		GP_5_24_FN,	GPSR5_24,
5259 		GP_5_23_FN,	GPSR5_23,
5260 		GP_5_22_FN,	GPSR5_22,
5261 		GP_5_21_FN,	GPSR5_21,
5262 		GP_5_20_FN,	GPSR5_20,
5263 		GP_5_19_FN,	GPSR5_19,
5264 		GP_5_18_FN,	GPSR5_18,
5265 		GP_5_17_FN,	GPSR5_17,
5266 		GP_5_16_FN,	GPSR5_16,
5267 		GP_5_15_FN,	GPSR5_15,
5268 		GP_5_14_FN,	GPSR5_14,
5269 		GP_5_13_FN,	GPSR5_13,
5270 		GP_5_12_FN,	GPSR5_12,
5271 		GP_5_11_FN,	GPSR5_11,
5272 		GP_5_10_FN,	GPSR5_10,
5273 		GP_5_9_FN,	GPSR5_9,
5274 		GP_5_8_FN,	GPSR5_8,
5275 		GP_5_7_FN,	GPSR5_7,
5276 		GP_5_6_FN,	GPSR5_6,
5277 		GP_5_5_FN,	GPSR5_5,
5278 		GP_5_4_FN,	GPSR5_4,
5279 		GP_5_3_FN,	GPSR5_3,
5280 		GP_5_2_FN,	GPSR5_2,
5281 		GP_5_1_FN,	GPSR5_1,
5282 		GP_5_0_FN,	GPSR5_0, }
5283 	},
5284 	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5285 		GP_6_31_FN,	GPSR6_31,
5286 		GP_6_30_FN,	GPSR6_30,
5287 		GP_6_29_FN,	GPSR6_29,
5288 		GP_6_28_FN,	GPSR6_28,
5289 		GP_6_27_FN,	GPSR6_27,
5290 		GP_6_26_FN,	GPSR6_26,
5291 		GP_6_25_FN,	GPSR6_25,
5292 		GP_6_24_FN,	GPSR6_24,
5293 		GP_6_23_FN,	GPSR6_23,
5294 		GP_6_22_FN,	GPSR6_22,
5295 		GP_6_21_FN,	GPSR6_21,
5296 		GP_6_20_FN,	GPSR6_20,
5297 		GP_6_19_FN,	GPSR6_19,
5298 		GP_6_18_FN,	GPSR6_18,
5299 		GP_6_17_FN,	GPSR6_17,
5300 		GP_6_16_FN,	GPSR6_16,
5301 		GP_6_15_FN,	GPSR6_15,
5302 		GP_6_14_FN,	GPSR6_14,
5303 		GP_6_13_FN,	GPSR6_13,
5304 		GP_6_12_FN,	GPSR6_12,
5305 		GP_6_11_FN,	GPSR6_11,
5306 		GP_6_10_FN,	GPSR6_10,
5307 		GP_6_9_FN,	GPSR6_9,
5308 		GP_6_8_FN,	GPSR6_8,
5309 		GP_6_7_FN,	GPSR6_7,
5310 		GP_6_6_FN,	GPSR6_6,
5311 		GP_6_5_FN,	GPSR6_5,
5312 		GP_6_4_FN,	GPSR6_4,
5313 		GP_6_3_FN,	GPSR6_3,
5314 		GP_6_2_FN,	GPSR6_2,
5315 		GP_6_1_FN,	GPSR6_1,
5316 		GP_6_0_FN,	GPSR6_0, }
5317 	},
5318 	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5319 		0, 0,
5320 		0, 0,
5321 		0, 0,
5322 		0, 0,
5323 		0, 0,
5324 		0, 0,
5325 		0, 0,
5326 		0, 0,
5327 		0, 0,
5328 		0, 0,
5329 		0, 0,
5330 		0, 0,
5331 		0, 0,
5332 		0, 0,
5333 		0, 0,
5334 		0, 0,
5335 		0, 0,
5336 		0, 0,
5337 		0, 0,
5338 		0, 0,
5339 		0, 0,
5340 		0, 0,
5341 		0, 0,
5342 		0, 0,
5343 		0, 0,
5344 		0, 0,
5345 		0, 0,
5346 		0, 0,
5347 		GP_7_3_FN, GPSR7_3,
5348 		GP_7_2_FN, GPSR7_2,
5349 		GP_7_1_FN, GPSR7_1,
5350 		GP_7_0_FN, GPSR7_0, }
5351 	},
5352 #undef F_
5353 #undef FM
5354 
5355 #define F_(x, y)	x,
5356 #define FM(x)		FN_##x,
5357 	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5358 		IP0_31_28
5359 		IP0_27_24
5360 		IP0_23_20
5361 		IP0_19_16
5362 		IP0_15_12
5363 		IP0_11_8
5364 		IP0_7_4
5365 		IP0_3_0 }
5366 	},
5367 	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5368 		IP1_31_28
5369 		IP1_27_24
5370 		IP1_23_20
5371 		IP1_19_16
5372 		IP1_15_12
5373 		IP1_11_8
5374 		IP1_7_4
5375 		IP1_3_0 }
5376 	},
5377 	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5378 		IP2_31_28
5379 		IP2_27_24
5380 		IP2_23_20
5381 		IP2_19_16
5382 		IP2_15_12
5383 		IP2_11_8
5384 		IP2_7_4
5385 		IP2_3_0 }
5386 	},
5387 	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5388 		IP3_31_28
5389 		IP3_27_24
5390 		IP3_23_20
5391 		IP3_19_16
5392 		IP3_15_12
5393 		IP3_11_8
5394 		IP3_7_4
5395 		IP3_3_0 }
5396 	},
5397 	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5398 		IP4_31_28
5399 		IP4_27_24
5400 		IP4_23_20
5401 		IP4_19_16
5402 		IP4_15_12
5403 		IP4_11_8
5404 		IP4_7_4
5405 		IP4_3_0 }
5406 	},
5407 	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5408 		IP5_31_28
5409 		IP5_27_24
5410 		IP5_23_20
5411 		IP5_19_16
5412 		IP5_15_12
5413 		IP5_11_8
5414 		IP5_7_4
5415 		IP5_3_0 }
5416 	},
5417 	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5418 		IP6_31_28
5419 		IP6_27_24
5420 		IP6_23_20
5421 		IP6_19_16
5422 		IP6_15_12
5423 		IP6_11_8
5424 		IP6_7_4
5425 		IP6_3_0 }
5426 	},
5427 	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5428 		IP7_31_28
5429 		IP7_27_24
5430 		IP7_23_20
5431 		IP7_19_16
5432 		/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5433 		IP7_11_8
5434 		IP7_7_4
5435 		IP7_3_0 }
5436 	},
5437 	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5438 		IP8_31_28
5439 		IP8_27_24
5440 		IP8_23_20
5441 		IP8_19_16
5442 		IP8_15_12
5443 		IP8_11_8
5444 		IP8_7_4
5445 		IP8_3_0 }
5446 	},
5447 	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5448 		IP9_31_28
5449 		IP9_27_24
5450 		IP9_23_20
5451 		IP9_19_16
5452 		IP9_15_12
5453 		IP9_11_8
5454 		IP9_7_4
5455 		IP9_3_0 }
5456 	},
5457 	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5458 		IP10_31_28
5459 		IP10_27_24
5460 		IP10_23_20
5461 		IP10_19_16
5462 		IP10_15_12
5463 		IP10_11_8
5464 		IP10_7_4
5465 		IP10_3_0 }
5466 	},
5467 	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5468 		IP11_31_28
5469 		IP11_27_24
5470 		IP11_23_20
5471 		IP11_19_16
5472 		IP11_15_12
5473 		IP11_11_8
5474 		IP11_7_4
5475 		IP11_3_0 }
5476 	},
5477 	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5478 		IP12_31_28
5479 		IP12_27_24
5480 		IP12_23_20
5481 		IP12_19_16
5482 		IP12_15_12
5483 		IP12_11_8
5484 		IP12_7_4
5485 		IP12_3_0 }
5486 	},
5487 	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5488 		IP13_31_28
5489 		IP13_27_24
5490 		IP13_23_20
5491 		IP13_19_16
5492 		IP13_15_12
5493 		IP13_11_8
5494 		IP13_7_4
5495 		IP13_3_0 }
5496 	},
5497 	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5498 		IP14_31_28
5499 		IP14_27_24
5500 		IP14_23_20
5501 		IP14_19_16
5502 		IP14_15_12
5503 		IP14_11_8
5504 		IP14_7_4
5505 		IP14_3_0 }
5506 	},
5507 	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5508 		IP15_31_28
5509 		IP15_27_24
5510 		IP15_23_20
5511 		IP15_19_16
5512 		IP15_15_12
5513 		IP15_11_8
5514 		IP15_7_4
5515 		IP15_3_0 }
5516 	},
5517 	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5518 		IP16_31_28
5519 		IP16_27_24
5520 		IP16_23_20
5521 		IP16_19_16
5522 		IP16_15_12
5523 		IP16_11_8
5524 		IP16_7_4
5525 		IP16_3_0 }
5526 	},
5527 	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5528 		IP17_31_28
5529 		IP17_27_24
5530 		IP17_23_20
5531 		IP17_19_16
5532 		IP17_15_12
5533 		IP17_11_8
5534 		IP17_7_4
5535 		IP17_3_0 }
5536 	},
5537 	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5538 		/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5539 		/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5540 		/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5541 		/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5542 		/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5543 		/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5544 		IP18_7_4
5545 		IP18_3_0 }
5546 	},
5547 #undef F_
5548 #undef FM
5549 
5550 #define F_(x, y)	x,
5551 #define FM(x)		FN_##x,
5552 	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5553 			     3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5554 			     1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5555 		MOD_SEL0_31_30_29
5556 		MOD_SEL0_28_27
5557 		MOD_SEL0_26_25_24
5558 		MOD_SEL0_23
5559 		MOD_SEL0_22
5560 		MOD_SEL0_21
5561 		MOD_SEL0_20
5562 		MOD_SEL0_19
5563 		MOD_SEL0_18_17
5564 		MOD_SEL0_16
5565 		0, 0, /* RESERVED 15 */
5566 		MOD_SEL0_14_13
5567 		MOD_SEL0_12
5568 		MOD_SEL0_11
5569 		MOD_SEL0_10
5570 		MOD_SEL0_9_8
5571 		MOD_SEL0_7_6
5572 		MOD_SEL0_5
5573 		MOD_SEL0_4_3
5574 		/* RESERVED 2, 1, 0 */
5575 		0, 0, 0, 0, 0, 0, 0, 0 }
5576 	},
5577 	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5578 			     2, 3, 1, 2, 3, 1, 1, 2, 1,
5579 			     2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5580 		MOD_SEL1_31_30
5581 		MOD_SEL1_29_28_27
5582 		MOD_SEL1_26
5583 		MOD_SEL1_25_24
5584 		MOD_SEL1_23_22_21
5585 		MOD_SEL1_20
5586 		MOD_SEL1_19
5587 		MOD_SEL1_18_17
5588 		MOD_SEL1_16
5589 		MOD_SEL1_15_14
5590 		MOD_SEL1_13
5591 		MOD_SEL1_12
5592 		MOD_SEL1_11
5593 		MOD_SEL1_10
5594 		MOD_SEL1_9
5595 		0, 0, 0, 0, /* RESERVED 8, 7 */
5596 		MOD_SEL1_6
5597 		MOD_SEL1_5
5598 		MOD_SEL1_4
5599 		MOD_SEL1_3
5600 		MOD_SEL1_2
5601 		MOD_SEL1_1
5602 		MOD_SEL1_0 }
5603 	},
5604 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5605 			     1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5606 			     4, 4, 4, 3, 1) {
5607 		MOD_SEL2_31
5608 		MOD_SEL2_30
5609 		MOD_SEL2_29
5610 		MOD_SEL2_28_27
5611 		MOD_SEL2_26
5612 		MOD_SEL2_25_24_23
5613 		/* RESERVED 22 */
5614 		0, 0,
5615 		MOD_SEL2_21
5616 		MOD_SEL2_20
5617 		MOD_SEL2_19
5618 		MOD_SEL2_18
5619 		MOD_SEL2_17
5620 		/* RESERVED 16 */
5621 		0, 0,
5622 		/* RESERVED 15, 14, 13, 12 */
5623 		0, 0, 0, 0, 0, 0, 0, 0,
5624 		0, 0, 0, 0, 0, 0, 0, 0,
5625 		/* RESERVED 11, 10, 9, 8 */
5626 		0, 0, 0, 0, 0, 0, 0, 0,
5627 		0, 0, 0, 0, 0, 0, 0, 0,
5628 		/* RESERVED 7, 6, 5, 4 */
5629 		0, 0, 0, 0, 0, 0, 0, 0,
5630 		0, 0, 0, 0, 0, 0, 0, 0,
5631 		/* RESERVED 3, 2, 1 */
5632 		0, 0, 0, 0, 0, 0, 0, 0,
5633 		MOD_SEL2_0 }
5634 	},
5635 	{ },
5636 };
5637 
5638 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5639 	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5640 		{ PIN_NUMBER('W', 3),   28, 2 },	/* QSPI0_SPCLK */
5641 		{ PIN_A_NUMBER('C', 5), 24, 2 },	/* QSPI0_MOSI_IO0 */
5642 		{ PIN_A_NUMBER('B', 4), 20, 2 },	/* QSPI0_MISO_IO1 */
5643 		{ PIN_NUMBER('Y', 6),   16, 2 },	/* QSPI0_IO2 */
5644 		{ PIN_A_NUMBER('B', 6), 12, 2 },	/* QSPI0_IO3 */
5645 		{ PIN_NUMBER('Y', 3),    8, 2 },	/* QSPI0_SSL */
5646 		{ PIN_NUMBER('V', 3),    4, 2 },	/* QSPI1_SPCLK */
5647 		{ PIN_A_NUMBER('C', 7),  0, 2 },	/* QSPI1_MOSI_IO0 */
5648 	} },
5649 	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5650 		{ PIN_A_NUMBER('E', 5), 28, 2 },	/* QSPI1_MISO_IO1 */
5651 		{ PIN_A_NUMBER('E', 4), 24, 2 },	/* QSPI1_IO2 */
5652 		{ PIN_A_NUMBER('C', 3), 20, 2 },	/* QSPI1_IO3 */
5653 		{ PIN_NUMBER('V', 5),   16, 2 },	/* QSPI1_SSL */
5654 		{ PIN_NUMBER('Y', 7),   12, 2 },	/* RPC_INT# */
5655 		{ PIN_NUMBER('V', 6),    8, 2 },	/* RPC_WP# */
5656 		{ PIN_NUMBER('V', 7),    4, 2 },	/* RPC_RESET# */
5657 		{ PIN_NUMBER('A', 16),   0, 3 },	/* AVB_RX_CTL */
5658 	} },
5659 	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5660 		{ PIN_NUMBER('B', 19),  28, 3 },	/* AVB_RXC */
5661 		{ PIN_NUMBER('A', 13),  24, 3 },	/* AVB_RD0 */
5662 		{ PIN_NUMBER('B', 13),  20, 3 },	/* AVB_RD1 */
5663 		{ PIN_NUMBER('A', 14),  16, 3 },	/* AVB_RD2 */
5664 		{ PIN_NUMBER('B', 14),  12, 3 },	/* AVB_RD3 */
5665 		{ PIN_NUMBER('A', 8),    8, 3 },	/* AVB_TX_CTL */
5666 		{ PIN_NUMBER('A', 19),   4, 3 },	/* AVB_TXC */
5667 		{ PIN_NUMBER('A', 18),   0, 3 },	/* AVB_TD0 */
5668 	} },
5669 	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5670 		{ PIN_NUMBER('B', 18),  28, 3 },	/* AVB_TD1 */
5671 		{ PIN_NUMBER('A', 17),  24, 3 },	/* AVB_TD2 */
5672 		{ PIN_NUMBER('B', 17),  20, 3 },	/* AVB_TD3 */
5673 		{ PIN_NUMBER('A', 12),  16, 3 },	/* AVB_TXCREFCLK */
5674 		{ PIN_NUMBER('A', 9),   12, 3 },	/* AVB_MDIO */
5675 		{ RCAR_GP_PIN(2,  9),    8, 3 },	/* AVB_MDC */
5676 		{ RCAR_GP_PIN(2, 10),    4, 3 },	/* AVB_MAGIC */
5677 		{ RCAR_GP_PIN(2, 11),    0, 3 },	/* AVB_PHY_INT */
5678 	} },
5679 	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5680 		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
5681 		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
5682 		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
5683 		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
5684 		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
5685 		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
5686 		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
5687 		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
5688 	} },
5689 	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5690 		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
5691 		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
5692 		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
5693 		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
5694 		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
5695 		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
5696 		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
5697 		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
5698 	} },
5699 	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5700 		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
5701 		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
5702 		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
5703 		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
5704 		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
5705 		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
5706 		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
5707 		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
5708 	} },
5709 	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5710 		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
5711 		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
5712 		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
5713 		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
5714 		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
5715 		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
5716 		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
5717 		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
5718 	} },
5719 	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5720 		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
5721 		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
5722 		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
5723 		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
5724 		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
5725 		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
5726 		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
5727 		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
5728 	} },
5729 	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5730 		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
5731 		{ PIN_NUMBER('C', 1), 24, 3 },	/* PRESETOUT# */
5732 		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
5733 		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
5734 		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
5735 		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
5736 		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
5737 		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
5738 	} },
5739 	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5740 		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
5741 		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
5742 		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
5743 		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
5744 		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
5745 		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
5746 		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
5747 		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
5748 	} },
5749 	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5750 		{ RCAR_GP_PIN(0, 14),   28, 3 },	/* D14 */
5751 		{ RCAR_GP_PIN(0, 15),   24, 3 },	/* D15 */
5752 		{ RCAR_GP_PIN(7,  0),   20, 3 },	/* AVS1 */
5753 		{ RCAR_GP_PIN(7,  1),   16, 3 },	/* AVS2 */
5754 		{ RCAR_GP_PIN(7,  2),   12, 3 },	/* GP7_02 */
5755 		{ RCAR_GP_PIN(7,  3),    8, 3 },	/* GP7_03 */
5756 		{ PIN_A_NUMBER('P', 7),  4, 2 },	/* DU_DOTCLKIN0 */
5757 		{ PIN_A_NUMBER('P', 8),  0, 2 },	/* DU_DOTCLKIN1 */
5758 	} },
5759 	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5760 		{ PIN_A_NUMBER('R', 7),  28, 2 },	/* DU_DOTCLKIN2 */
5761 		{ PIN_A_NUMBER('R', 8),  24, 2 },	/* DU_DOTCLKIN3 */
5762 		{ PIN_A_NUMBER('D', 38), 20, 2 },	/* FSCLKST# */
5763 		{ PIN_A_NUMBER('R', 30),  4, 2 },	/* TMS */
5764 	} },
5765 	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5766 		{ PIN_A_NUMBER('T', 28), 28, 2 },	/* TDO */
5767 		{ PIN_A_NUMBER('T', 30), 24, 2 },	/* ASEBRK */
5768 		{ RCAR_GP_PIN(3,  0),    20, 3 },	/* SD0_CLK */
5769 		{ RCAR_GP_PIN(3,  1),    16, 3 },	/* SD0_CMD */
5770 		{ RCAR_GP_PIN(3,  2),    12, 3 },	/* SD0_DAT0 */
5771 		{ RCAR_GP_PIN(3,  3),     8, 3 },	/* SD0_DAT1 */
5772 		{ RCAR_GP_PIN(3,  4),     4, 3 },	/* SD0_DAT2 */
5773 		{ RCAR_GP_PIN(3,  5),     0, 3 },	/* SD0_DAT3 */
5774 	} },
5775 	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5776 		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
5777 		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
5778 		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
5779 		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
5780 		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
5781 		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
5782 		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
5783 		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
5784 	} },
5785 	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5786 		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
5787 		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
5788 		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
5789 		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
5790 		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
5791 		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
5792 		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
5793 		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
5794 	} },
5795 	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5796 		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
5797 		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
5798 		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
5799 		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
5800 		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
5801 		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
5802 		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
5803 		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
5804 	} },
5805 	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5806 		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
5807 		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
5808 		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
5809 		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
5810 		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
5811 		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
5812 		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
5813 		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
5814 	} },
5815 	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5816 		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
5817 		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
5818 		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
5819 		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
5820 		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
5821 		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
5822 		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
5823 		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
5824 	} },
5825 	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5826 		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
5827 		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
5828 		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
5829 		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
5830 		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
5831 		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
5832 		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
5833 		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
5834 	} },
5835 	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5836 		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
5837 		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
5838 		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
5839 		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
5840 		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
5841 		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
5842 		{ PIN_NUMBER('H', 37),  4, 3 },	/* MLB_REF */
5843 		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
5844 	} },
5845 	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5846 		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
5847 		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
5848 		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
5849 		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
5850 		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
5851 		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
5852 		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
5853 		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
5854 	} },
5855 	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5856 		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
5857 		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
5858 		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
5859 		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
5860 		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
5861 		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
5862 		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
5863 		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
5864 	} },
5865 	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5866 		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
5867 		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
5868 		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
5869 		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
5870 		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
5871 		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
5872 		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
5873 		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
5874 	} },
5875 	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5876 		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
5877 		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
5878 		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
5879 		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
5880 		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
5881 		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* USB2_CH3_PWEN */
5882 		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* USB2_CH3_OVC */
5883 	} },
5884 	{ },
5885 };
5886 
5887 enum ioctrl_regs {
5888 	POCCTRL,
5889 };
5890 
5891 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5892 	[POCCTRL] = { 0xe6060380, },
5893 	{ /* sentinel */ },
5894 };
5895 
r8a7795_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)5896 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5897 {
5898 	int bit = -EINVAL;
5899 
5900 	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5901 
5902 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5903 		bit = pin & 0x1f;
5904 
5905 	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5906 		bit = (pin & 0x1f) + 12;
5907 
5908 	return bit;
5909 }
5910 
5911 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5912 	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5913 		[ 0] = PIN_NUMBER('W', 3),	/* QSPI0_SPCLK */
5914 		[ 1] = PIN_A_NUMBER('C', 5),	/* QSPI0_MOSI_IO0 */
5915 		[ 2] = PIN_A_NUMBER('B', 4),	/* QSPI0_MISO_IO1 */
5916 		[ 3] = PIN_NUMBER('Y', 6),	/* QSPI0_IO2 */
5917 		[ 4] = PIN_A_NUMBER('B', 6),	/* QSPI0_IO3 */
5918 		[ 5] = PIN_NUMBER('Y', 3),	/* QSPI0_SSL */
5919 		[ 6] = PIN_NUMBER('V', 3),	/* QSPI1_SPCLK */
5920 		[ 7] = PIN_A_NUMBER('C', 7),	/* QSPI1_MOSI_IO0 */
5921 		[ 8] = PIN_A_NUMBER('E', 5),	/* QSPI1_MISO_IO1 */
5922 		[ 9] = PIN_A_NUMBER('E', 4),	/* QSPI1_IO2 */
5923 		[10] = PIN_A_NUMBER('C', 3),	/* QSPI1_IO3 */
5924 		[11] = PIN_NUMBER('V', 5),	/* QSPI1_SSL */
5925 		[12] = PIN_NUMBER('Y', 7),	/* RPC_INT# */
5926 		[13] = PIN_NUMBER('V', 6),	/* RPC_WP# */
5927 		[14] = PIN_NUMBER('V', 7),	/* RPC_RESET# */
5928 		[15] = PIN_NUMBER('A', 16),	/* AVB_RX_CTL */
5929 		[16] = PIN_NUMBER('B', 19),	/* AVB_RXC */
5930 		[17] = PIN_NUMBER('A', 13),	/* AVB_RD0 */
5931 		[18] = PIN_NUMBER('B', 13),	/* AVB_RD1 */
5932 		[19] = PIN_NUMBER('A', 14),	/* AVB_RD2 */
5933 		[20] = PIN_NUMBER('B', 14),	/* AVB_RD3 */
5934 		[21] = PIN_NUMBER('A', 8),	/* AVB_TX_CTL */
5935 		[22] = PIN_NUMBER('A', 19),	/* AVB_TXC */
5936 		[23] = PIN_NUMBER('A', 18),	/* AVB_TD0 */
5937 		[24] = PIN_NUMBER('B', 18),	/* AVB_TD1 */
5938 		[25] = PIN_NUMBER('A', 17),	/* AVB_TD2 */
5939 		[26] = PIN_NUMBER('B', 17),	/* AVB_TD3 */
5940 		[27] = PIN_NUMBER('A', 12),	/* AVB_TXCREFCLK */
5941 		[28] = PIN_NUMBER('A', 9),	/* AVB_MDIO */
5942 		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
5943 		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
5944 		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
5945 	} },
5946 	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5947 		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
5948 		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
5949 		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
5950 		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
5951 		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
5952 		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
5953 		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
5954 		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
5955 		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
5956 		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
5957 		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
5958 		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
5959 		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
5960 		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
5961 		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
5962 		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
5963 		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
5964 		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
5965 		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
5966 		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
5967 		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
5968 		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
5969 		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
5970 		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
5971 		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
5972 		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
5973 		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
5974 		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
5975 		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
5976 		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
5977 		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
5978 		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
5979 	} },
5980 	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5981 		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
5982 		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
5983 		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
5984 		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
5985 		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
5986 		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
5987 		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
5988 		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
5989 		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
5990 		[ 9] = PIN_NUMBER('C', 1),	/* PRESETOUT# */
5991 		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
5992 		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
5993 		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
5994 		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
5995 		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
5996 		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
5997 		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
5998 		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
5999 		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
6000 		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
6001 		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
6002 		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
6003 		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
6004 		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
6005 		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
6006 		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
6007 		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
6008 		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
6009 		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
6010 		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
6011 		[30] = PIN_A_NUMBER('P', 7),	/* DU_DOTCLKIN0 */
6012 		[31] = PIN_A_NUMBER('P', 8),	/* DU_DOTCLKIN1 */
6013 	} },
6014 	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6015 		[ 0] = PIN_A_NUMBER('R', 7),	/* DU_DOTCLKIN2 */
6016 		[ 1] = PIN_A_NUMBER('R', 8),	/* DU_DOTCLKIN3 */
6017 		[ 2] = PIN_A_NUMBER('D', 38),	/* FSCLKST# */
6018 		[ 3] = PIN_A_NUMBER('D', 39),	/* EXTALR*/
6019 		[ 4] = PIN_A_NUMBER('R', 26),	/* TRST# */
6020 		[ 5] = PIN_A_NUMBER('T', 27),	/* TCK */
6021 		[ 6] = PIN_A_NUMBER('R', 30),	/* TMS */
6022 		[ 7] = PIN_A_NUMBER('R', 29),	/* TDI */
6023 		[ 8] = PIN_NONE,
6024 		[ 9] = PIN_A_NUMBER('T', 30),	/* ASEBRK */
6025 		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
6026 		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
6027 		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
6028 		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
6029 		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
6030 		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
6031 		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
6032 		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
6033 		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
6034 		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
6035 		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
6036 		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
6037 		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
6038 		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
6039 		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
6040 		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
6041 		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
6042 		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
6043 		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
6044 		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
6045 		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
6046 		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
6047 	} },
6048 	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6049 		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
6050 		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
6051 		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
6052 		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
6053 		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
6054 		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
6055 		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
6056 		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
6057 		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
6058 		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
6059 		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
6060 		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
6061 		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
6062 		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
6063 		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
6064 		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
6065 		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
6066 		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
6067 		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
6068 		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
6069 		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
6070 		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
6071 		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
6072 		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
6073 		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
6074 		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
6075 		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
6076 		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
6077 		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
6078 		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
6079 		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
6080 		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
6081 	} },
6082 	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6083 		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
6084 		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
6085 		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
6086 		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
6087 		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
6088 		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
6089 		[ 6] = PIN_NUMBER('H', 37),	/* MLB_REF */
6090 		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
6091 		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
6092 		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
6093 		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
6094 		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
6095 		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
6096 		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
6097 		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
6098 		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
6099 		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
6100 		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
6101 		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
6102 		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
6103 		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
6104 		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
6105 		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
6106 		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
6107 		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
6108 		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
6109 		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
6110 		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
6111 		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
6112 		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
6113 		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
6114 		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
6115 	} },
6116 	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6117 		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
6118 		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
6119 		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
6120 		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
6121 		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
6122 		[ 5] = RCAR_GP_PIN(6, 30),	/* USB2_CH3_PWEN */
6123 		[ 6] = RCAR_GP_PIN(6, 31),	/* USB2_CH3_OVC */
6124 		[ 7] = PIN_NONE,
6125 		[ 8] = PIN_NONE,
6126 		[ 9] = PIN_NONE,
6127 		[10] = PIN_NONE,
6128 		[11] = PIN_NONE,
6129 		[12] = PIN_NONE,
6130 		[13] = PIN_NONE,
6131 		[14] = PIN_NONE,
6132 		[15] = PIN_NONE,
6133 		[16] = PIN_NONE,
6134 		[17] = PIN_NONE,
6135 		[18] = PIN_NONE,
6136 		[19] = PIN_NONE,
6137 		[20] = PIN_NONE,
6138 		[21] = PIN_NONE,
6139 		[22] = PIN_NONE,
6140 		[23] = PIN_NONE,
6141 		[24] = PIN_NONE,
6142 		[25] = PIN_NONE,
6143 		[26] = PIN_NONE,
6144 		[27] = PIN_NONE,
6145 		[28] = PIN_NONE,
6146 		[29] = PIN_NONE,
6147 		[30] = PIN_NONE,
6148 		[31] = PIN_NONE,
6149 	} },
6150 	{ /* sentinel */ },
6151 };
6152 
r8a7795_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)6153 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6154 					    unsigned int pin)
6155 {
6156 	const struct pinmux_bias_reg *reg;
6157 	unsigned int bit;
6158 
6159 	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6160 	if (!reg)
6161 		return PIN_CONFIG_BIAS_DISABLE;
6162 
6163 	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6164 		return PIN_CONFIG_BIAS_DISABLE;
6165 	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6166 		return PIN_CONFIG_BIAS_PULL_UP;
6167 	else
6168 		return PIN_CONFIG_BIAS_PULL_DOWN;
6169 }
6170 
r8a7795_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)6171 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6172 				   unsigned int bias)
6173 {
6174 	const struct pinmux_bias_reg *reg;
6175 	u32 enable, updown;
6176 	unsigned int bit;
6177 
6178 	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6179 	if (!reg)
6180 		return;
6181 
6182 	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6183 	if (bias != PIN_CONFIG_BIAS_DISABLE)
6184 		enable |= BIT(bit);
6185 
6186 	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6187 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
6188 		updown |= BIT(bit);
6189 
6190 	sh_pfc_write(pfc, reg->pud, updown);
6191 	sh_pfc_write(pfc, reg->puen, enable);
6192 }
6193 
6194 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6195 	.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6196 	.get_bias = r8a7795_pinmux_get_bias,
6197 	.set_bias = r8a7795_pinmux_set_bias,
6198 };
6199 
6200 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6201 	.name = "r8a77951_pfc",
6202 	.ops = &r8a7795_pinmux_ops,
6203 	.unlock_reg = 0xe6060000, /* PMMR */
6204 
6205 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6206 
6207 	.pins = pinmux_pins,
6208 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6209 	.groups = pinmux_groups,
6210 	.nr_groups = ARRAY_SIZE(pinmux_groups),
6211 	.functions = pinmux_functions,
6212 	.nr_functions = ARRAY_SIZE(pinmux_functions),
6213 
6214 	.cfg_regs = pinmux_config_regs,
6215 	.drive_regs = pinmux_drive_regs,
6216 	.bias_regs = pinmux_bias_regs,
6217 	.ioctrl_regs = pinmux_ioctrl_regs,
6218 
6219 	.pinmux_data = pinmux_data,
6220 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6221 };
6222