xref: /openbmc/u-boot/drivers/clk/sunxi/clk_r40.c (revision 821aa191)
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (C) 2018 Amarula Solutions.
4  * Author: Jagan Teki <jagan@amarulasolutions.com>
5  */
6 
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <asm/arch/ccu.h>
12 #include <dt-bindings/clock/sun8i-r40-ccu.h>
13 #include <dt-bindings/reset/sun8i-r40-ccu.h>
14 
15 static struct ccu_clk_gate r40_gates[] = {
16 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
17 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
18 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
19 	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
20 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
21 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
22 	[CLK_BUS_SPI2]		= GATE(0x060, BIT(22)),
23 	[CLK_BUS_SPI3]		= GATE(0x060, BIT(23)),
24 	[CLK_BUS_OTG]		= GATE(0x060, BIT(25)),
25 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
26 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
27 	[CLK_BUS_EHCI2]		= GATE(0x060, BIT(28)),
28 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
29 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
30 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
31 
32 	[CLK_BUS_GMAC]		= GATE(0x064, BIT(17)),
33 
34 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
35 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
36 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
37 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
38 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
39 	[CLK_BUS_UART5]		= GATE(0x06c, BIT(21)),
40 	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
41 	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
42 
43 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
44 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
45 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
46 	[CLK_SPI3]		= GATE(0x0ac, BIT(31)),
47 
48 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
49 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
50 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
51 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
52 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
53 	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
54 };
55 
56 static struct ccu_reset r40_resets[] = {
57 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
58 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
59 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
60 
61 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
62 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
63 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
64 	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
65 	[RST_BUS_GMAC]		= RESET(0x2c0, BIT(17)),
66 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
67 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
68 	[RST_BUS_SPI2]		= RESET(0x2c0, BIT(22)),
69 	[RST_BUS_SPI3]		= RESET(0x2c0, BIT(23)),
70 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(25)),
71 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
72 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
73 	[RST_BUS_EHCI2]		= RESET(0x2c0, BIT(28)),
74 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
75 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
76 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
77 
78 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
79 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
80 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
81 	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
82 	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
83 	[RST_BUS_UART5]		= RESET(0x2d8, BIT(21)),
84 	[RST_BUS_UART6]		= RESET(0x2d8, BIT(22)),
85 	[RST_BUS_UART7]		= RESET(0x2d8, BIT(23)),
86 };
87 
88 static const struct ccu_desc r40_ccu_desc = {
89 	.gates = r40_gates,
90 	.resets = r40_resets,
91 };
92 
r40_clk_bind(struct udevice * dev)93 static int r40_clk_bind(struct udevice *dev)
94 {
95 	return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
96 }
97 
98 static const struct udevice_id r40_clk_ids[] = {
99 	{ .compatible = "allwinner,sun8i-r40-ccu",
100 	  .data = (ulong)&r40_ccu_desc },
101 	{ }
102 };
103 
104 U_BOOT_DRIVER(clk_sun8i_r40) = {
105 	.name		= "sun8i_r40_ccu",
106 	.id		= UCLASS_CLK,
107 	.of_match	= r40_clk_ids,
108 	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
109 	.ops		= &sunxi_clk_ops,
110 	.probe		= sunxi_clk_probe,
111 	.bind		= r40_clk_bind,
112 };
113