xref: /openbmc/u-boot/board/udoo/neo/neo.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4  * Copyright (C) Jasbir Matharu
5  * Copyright (C) UDOO Team
6  *
7  * Author: Breno Lima <breno.lima@nxp.com>
8  * Author: Francesco Montefoschi <francesco.monte@gmail.com>
9  */
10 
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <mmc.h>
19 #include <fsl_esdhc.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/io.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/arch/sys_proto.h>
24 #include <spl.h>
25 #include <linux/sizes.h>
26 #include <common.h>
27 #include <i2c.h>
28 #include <miiphy.h>
29 #include <netdev.h>
30 #include <power/pmic.h>
31 #include <power/pfuze3000_pmic.h>
32 #include <malloc.h>
33 
34 DECLARE_GLOBAL_DATA_PTR;
35 
36 enum {
37 	UDOO_NEO_TYPE_BASIC,
38 	UDOO_NEO_TYPE_BASIC_KS,
39 	UDOO_NEO_TYPE_FULL,
40 	UDOO_NEO_TYPE_EXTENDED,
41 };
42 
43 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
44 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
45 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
46 
47 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
48 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
49 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
50 
51 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
52 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
53 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
54 	PAD_CTL_ODE)
55 
56 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
57 	PAD_CTL_SPEED_MED   |                                   \
58 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
59 
60 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
61 	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
62 
63 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
64 	PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
65 
66 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
67 	PAD_CTL_DSE_40ohm)
68 
69 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
70 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
71 	PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
72 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |	\
73 	MUX_MODE_SION)
74 
dram_init(void)75 int dram_init(void)
76 {
77 	gd->ram_size = imx_ddr_size();
78 	return 0;
79 }
80 
81 #ifdef CONFIG_SYS_I2C_MXC
82 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
83 /* I2C1 for PMIC */
84 static struct i2c_pads_info i2c_pad_info1 = {
85 	.scl = {
86 		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
87 		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
88 		.gp = IMX_GPIO_NR(1, 0),
89 	},
90 	.sda = {
91 		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
92 		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
93 		.gp = IMX_GPIO_NR(1, 1),
94 	},
95 };
96 #endif
97 
98 #ifdef CONFIG_POWER
power_init_board(void)99 int power_init_board(void)
100 {
101 	struct pmic *p;
102 	int ret;
103 	unsigned int reg, rev_id;
104 
105 	ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
106 	if (ret)
107 		return ret;
108 
109 	p = pmic_get("PFUZE3000");
110 	ret = pmic_probe(p);
111 	if (ret)
112 		return ret;
113 
114 	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
115 	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
116 	printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
117 
118 	/* disable Low Power Mode during standby mode */
119 	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
120 	reg |= 0x1;
121 	ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
122 	if (ret)
123 		return ret;
124 
125 	ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
126 	if (ret)
127 		return ret;
128 
129 	ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
130 	if (ret)
131 		return ret;
132 
133 	ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
134 	if (ret)
135 		return ret;
136 
137 	ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
138 	if (ret)
139 		return ret;
140 
141 	/* set SW1A standby voltage 0.975V */
142 	pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
143 	reg &= ~0x3f;
144 	reg |= PFUZE3000_SW1AB_SETP(9750);
145 	ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
146 	if (ret)
147 		return ret;
148 
149 	/* set SW1B standby voltage 0.975V */
150 	pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
151 	reg &= ~0x3f;
152 	reg |= PFUZE3000_SW1AB_SETP(9750);
153 	ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
154 	if (ret)
155 		return ret;
156 
157 	/* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
158 	pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
159 	reg &= ~0xc0;
160 	reg |= 0x40;
161 	ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
162 	if (ret)
163 		return ret;
164 
165 	/* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
166 	pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
167 	reg &= ~0xc0;
168 	reg |= 0x40;
169 	ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
170 	if (ret)
171 		return ret;
172 
173 	/* set VDD_ARM_IN to 1.350V */
174 	pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
175 	reg &= ~0x3f;
176 	reg |= PFUZE3000_SW1AB_SETP(13500);
177 	ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
178 	if (ret)
179 		return ret;
180 
181 	/* set VDD_SOC_IN to 1.350V */
182 	pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
183 	reg &= ~0x3f;
184 	reg |= PFUZE3000_SW1AB_SETP(13500);
185 	ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
186 	if (ret)
187 		return ret;
188 
189 	/* set DDR_1_5V to 1.350V */
190 	pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
191 	reg &= ~0x0f;
192 	reg |= PFUZE3000_SW3_SETP(13500);
193 	ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
194 	if (ret)
195 		return ret;
196 
197 	/* set VGEN2_1V5 to 1.5V */
198 	pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
199 	reg &= ~0x0f;
200 	reg |= PFUZE3000_VLDO_SETP(15000);
201 	/*  enable  */
202 	reg |= 0x10;
203 	ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
204 	if (ret)
205 		return ret;
206 
207 	return 0;
208 }
209 #endif
210 
211 static iomux_v3_cfg_t const uart1_pads[] = {
212 	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
213 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
214 };
215 
216 static iomux_v3_cfg_t const usdhc2_pads[] = {
217 	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
218 	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
219 	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
220 	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
221 	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
222 	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
223 	/* CD pin */
224 	MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
225 	/* Power */
226 	MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
227 };
228 
229 static iomux_v3_cfg_t const fec1_pads[] = {
230 	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
233 	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
234 	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
235 	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 	MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
237 	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
239 	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
240 	MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
241 	MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
242 };
243 
244 static iomux_v3_cfg_t const phy_control_pads[] = {
245 	/* 25MHz Ethernet PHY Clock */
246 	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
247 	MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
248 };
249 
250 static iomux_v3_cfg_t const board_recognition_pads[] = {
251 	/*Connected to R184*/
252 	MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
253 	/*Connected to R185*/
254 	MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
255 };
256 
257 static iomux_v3_cfg_t const wdog_b_pad = {
258 	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
259 };
260 
261 static iomux_v3_cfg_t const peri_3v3_pads[] = {
262 	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
263 };
264 
setup_iomux_uart(void)265 static void setup_iomux_uart(void)
266 {
267 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
268 }
269 
setup_fec(int fec_id)270 static int setup_fec(int fec_id)
271 {
272 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
273 	int reg;
274 
275 	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
276 					 ARRAY_SIZE(phy_control_pads));
277 
278 	/* Reset PHY */
279 	gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
280 	udelay(10000);
281 	gpio_set_value(IMX_GPIO_NR(2, 1), 1);
282 	udelay(100);
283 
284 	reg = readl(&anatop->pll_enet);
285 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
286 	writel(reg, &anatop->pll_enet);
287 
288 	return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
289 }
290 
board_eth_init(bd_t * bis)291 int board_eth_init(bd_t *bis)
292 {
293 	uint32_t base = IMX_FEC_BASE;
294 	struct mii_dev *bus = NULL;
295 	struct phy_device *phydev = NULL;
296 	int ret;
297 
298 	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
299 
300 	setup_fec(CONFIG_FEC_ENET_DEV);
301 
302 	bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
303 	if (!bus)
304 		return -EINVAL;
305 
306 	phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
307 					PHY_INTERFACE_MODE_RMII);
308 	if (!phydev) {
309 		free(bus);
310 		return -EINVAL;
311 	}
312 
313 	ret  = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
314 	if (ret) {
315 		free(bus);
316 		free(phydev);
317 		return ret;
318 	}
319 	return 0;
320 }
321 
board_phy_config(struct phy_device * phydev)322 int board_phy_config(struct phy_device *phydev)
323 {
324 	if (phydev->drv->config)
325 		phydev->drv->config(phydev);
326 
327 	return 0;
328 }
329 
board_init(void)330 int board_init(void)
331 {
332 	/* Address of boot parameters */
333 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
334 
335 	/*
336 	 * Because kernel set WDOG_B mux before pad with the commone pinctrl
337 	 * framwork now and wdog reset will be triggered once set WDOG_B mux
338 	 * with default pad setting, we set pad setting here to workaround this.
339 	 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
340 	 * as GPIO mux firstly here to workaround it.
341 	 */
342 	imx_iomux_v3_setup_pad(wdog_b_pad);
343 
344 	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
345 	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
346 					 ARRAY_SIZE(peri_3v3_pads));
347 
348 	/* Active high for ncp692 */
349 	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
350 
351 #ifdef CONFIG_SYS_I2C_MXC
352 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
353 #endif
354 
355 	return 0;
356 }
357 
get_board_value(void)358 static int get_board_value(void)
359 {
360 	int r184, r185;
361 
362 	imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
363 					 ARRAY_SIZE(board_recognition_pads));
364 
365 	gpio_direction_input(IMX_GPIO_NR(4, 13));
366 	gpio_direction_input(IMX_GPIO_NR(4, 0));
367 
368 	r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
369 	r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
370 
371 	/*
372 	 * Machine selection -
373 	 * Machine          r184,    r185
374 	 * ---------------------------------
375 	 * Basic              0        0
376 	 * Basic Ks           0        1
377 	 * Full               1        0
378 	 * Extended           1        1
379 	 */
380 
381 	return (r184 << 1) + r185;
382 }
383 
board_early_init_f(void)384 int board_early_init_f(void)
385 {
386 	setup_iomux_uart();
387 
388 	return 0;
389 }
390 
391 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
392 	{USDHC2_BASE_ADDR, 0, 4},
393 };
394 
395 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
396 #define USDHC2_CD_GPIO	IMX_GPIO_NR(6, 2)
397 
board_mmc_getcd(struct mmc * mmc)398 int board_mmc_getcd(struct mmc *mmc)
399 {
400 	return !gpio_get_value(USDHC2_CD_GPIO);
401 }
402 
board_mmc_init(bd_t * bis)403 int board_mmc_init(bd_t *bis)
404 {
405 	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
406 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
407 	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
408 	gpio_direction_input(USDHC2_CD_GPIO);
409 	gpio_direction_output(USDHC2_PWR_GPIO, 1);
410 
411 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
412 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
413 }
414 
board_string(void)415 static char *board_string(void)
416 {
417 	switch (get_board_value()) {
418 	case UDOO_NEO_TYPE_BASIC:
419 		return "BASIC";
420 	case UDOO_NEO_TYPE_BASIC_KS:
421 		return "BASICKS";
422 	case UDOO_NEO_TYPE_FULL:
423 		return "FULL";
424 	case UDOO_NEO_TYPE_EXTENDED:
425 		return "EXTENDED";
426 	}
427 	return "UNDEFINED";
428 }
429 
checkboard(void)430 int checkboard(void)
431 {
432 	printf("Board: UDOO Neo %s\n", board_string());
433 	return 0;
434 }
435 
board_late_init(void)436 int board_late_init(void)
437 {
438 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
439 	env_set("board_name", board_string());
440 #endif
441 
442 	return 0;
443 }
444 
445 #ifdef CONFIG_SPL_BUILD
446 
447 #include <linux/libfdt.h>
448 #include <asm/arch/mx6-ddr.h>
449 
450 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
451 	.dram_dqm0 = 0x00000028,
452 	.dram_dqm1 = 0x00000028,
453 	.dram_dqm2 = 0x00000028,
454 	.dram_dqm3 = 0x00000028,
455 	.dram_ras = 0x00000020,
456 	.dram_cas = 0x00000020,
457 	.dram_odt0 = 0x00000020,
458 	.dram_odt1 = 0x00000020,
459 	.dram_sdba2 = 0x00000000,
460 	.dram_sdcke0 = 0x00003000,
461 	.dram_sdcke1 = 0x00003000,
462 	.dram_sdclk_0 = 0x00000030,
463 	.dram_sdqs0 = 0x00000028,
464 	.dram_sdqs1 = 0x00000028,
465 	.dram_sdqs2 = 0x00000028,
466 	.dram_sdqs3 = 0x00000028,
467 	.dram_reset = 0x00000020,
468 };
469 
470 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
471 	.grp_addds = 0x00000020,
472 	.grp_ddrmode_ctl = 0x00020000,
473 	.grp_ddrpke = 0x00000000,
474 	.grp_ddrmode = 0x00020000,
475 	.grp_b0ds = 0x00000028,
476 	.grp_b1ds = 0x00000028,
477 	.grp_ctlds = 0x00000020,
478 	.grp_ddr_type = 0x000c0000,
479 	.grp_b2ds = 0x00000028,
480 	.grp_b3ds = 0x00000028,
481 };
482 
483 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
484 	.p0_mpwldectrl0 = 0x000E000B,
485 	.p0_mpwldectrl1 = 0x000E0010,
486 	.p0_mpdgctrl0 = 0x41600158,
487 	.p0_mpdgctrl1 = 0x01500140,
488 	.p0_mprddlctl = 0x3A383E3E,
489 	.p0_mpwrdlctl = 0x3A383C38,
490 };
491 
492 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
493 	.p0_mpwldectrl0 = 0x001E0022,
494 	.p0_mpwldectrl1 = 0x001C0019,
495 	.p0_mpdgctrl0 = 0x41540150,
496 	.p0_mpdgctrl1 = 0x01440138,
497 	.p0_mprddlctl = 0x403E4644,
498 	.p0_mpwrdlctl = 0x3C3A4038,
499 };
500 
501 /* MT41K256M16 */
502 static struct mx6_ddr3_cfg neo_mem_ddr = {
503 	.mem_speed = 1600,
504 	.density = 4,
505 	.width = 16,
506 	.banks = 8,
507 	.rowaddr = 15,
508 	.coladdr = 10,
509 	.pagesz = 2,
510 	.trcd = 1375,
511 	.trcmin = 4875,
512 	.trasmin = 3500,
513 };
514 
515 /* MT41K128M16 */
516 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
517 	.mem_speed = 1600,
518 	.density = 2,
519 	.width = 16,
520 	.banks = 8,
521 	.rowaddr = 14,
522 	.coladdr = 10,
523 	.pagesz = 2,
524 	.trcd = 1375,
525 	.trcmin = 4875,
526 	.trasmin = 3500,
527 };
528 
ccgr_init(void)529 static void ccgr_init(void)
530 {
531 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
532 
533 	writel(0xFFFFFFFF, &ccm->CCGR0);
534 	writel(0xFFFFFFFF, &ccm->CCGR1);
535 	writel(0xFFFFFFFF, &ccm->CCGR2);
536 	writel(0xFFFFFFFF, &ccm->CCGR3);
537 	writel(0xFFFFFFFF, &ccm->CCGR4);
538 	writel(0xFFFFFFFF, &ccm->CCGR5);
539 	writel(0xFFFFFFFF, &ccm->CCGR6);
540 	writel(0xFFFFFFFF, &ccm->CCGR7);
541 }
542 
spl_dram_init(void)543 static void spl_dram_init(void)
544 {
545 	int board = get_board_value();
546 
547 	struct mx6_ddr_sysinfo sysinfo = {
548 		.dsize = 1, /* width of data bus: 1 = 32 bits */
549 		.cs_density = 24,
550 		.ncs = 1,
551 		.cs1_mirror = 0,
552 		.rtt_wr = 2,
553 		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
554 		.walat = 1,		/* Write additional latency */
555 		.ralat = 5,		/* Read additional latency */
556 		.mif3_mode = 3,		/* Command prediction working mode */
557 		.bi_on = 1,		/* Bank interleaving enabled */
558 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
559 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
560 	};
561 
562 	mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
563 	if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
564 		mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
565 			     &neo_basic_mem_ddr);
566 	else
567 		mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
568 }
569 
board_init_f(ulong dummy)570 void board_init_f(ulong dummy)
571 {
572 	ccgr_init();
573 
574 	/* setup AIPS and disable watchdog */
575 	arch_cpu_init();
576 
577 	board_early_init_f();
578 
579 	/* setup GP timer */
580 	timer_init();
581 
582 	/* UART clocks enabled and gd valid - init serial console */
583 	preloader_console_init();
584 
585 	/* DDR initialization */
586 	spl_dram_init();
587 
588 	/* Clear the BSS. */
589 	memset(__bss_start, 0, __bss_end - __bss_start);
590 
591 	/* load/boot image from boot device */
592 	board_init_r(NULL, 0);
593 }
594 
595 #endif
596