1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8280xp.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6afe.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board_clk: xo-board-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a78c"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <602>; 53 next-level-cache = <&L2_0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78c"; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <602>; 80 next-level-cache = <&L2_100>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a78c"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <602>; 102 next-level-cache = <&L2_200>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 108 #cooling-cells = <2>; 109 L2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a78c"; 120 reg = <0x0 0x300>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <602>; 124 next-level-cache = <&L2_300>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 operating-points-v2 = <&cpu0_opp_table>; 129 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 130 #cooling-cells = <2>; 131 L2_300: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU4: cpu@400 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-x1c"; 142 reg = <0x0 0x400>; 143 clocks = <&cpufreq_hw 1>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 next-level-cache = <&L2_400>; 147 power-domains = <&CPU_PD4>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 operating-points-v2 = <&cpu4_opp_table>; 151 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 152 #cooling-cells = <2>; 153 L2_400: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU5: cpu@500 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-x1c"; 164 reg = <0x0 0x500>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1024>; 168 next-level-cache = <&L2_500>; 169 power-domains = <&CPU_PD5>; 170 power-domain-names = "psci"; 171 qcom,freq-domain = <&cpufreq_hw 1>; 172 operating-points-v2 = <&cpu4_opp_table>; 173 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 174 #cooling-cells = <2>; 175 L2_500: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-x1c"; 186 reg = <0x0 0x600>; 187 clocks = <&cpufreq_hw 1>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1024>; 190 next-level-cache = <&L2_600>; 191 power-domains = <&CPU_PD6>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 operating-points-v2 = <&cpu4_opp_table>; 195 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 196 #cooling-cells = <2>; 197 L2_600: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU7: cpu@700 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-x1c"; 208 reg = <0x0 0x700>; 209 clocks = <&cpufreq_hw 1>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 next-level-cache = <&L2_700>; 213 power-domains = <&CPU_PD7>; 214 power-domain-names = "psci"; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu4_opp_table>; 217 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 cpu-map { 228 cluster0 { 229 core0 { 230 cpu = <&CPU0>; 231 }; 232 233 core1 { 234 cpu = <&CPU1>; 235 }; 236 237 core2 { 238 cpu = <&CPU2>; 239 }; 240 241 core3 { 242 cpu = <&CPU3>; 243 }; 244 245 core4 { 246 cpu = <&CPU4>; 247 }; 248 249 core5 { 250 cpu = <&CPU5>; 251 }; 252 253 core6 { 254 cpu = <&CPU6>; 255 }; 256 257 core7 { 258 cpu = <&CPU7>; 259 }; 260 }; 261 }; 262 263 idle-states { 264 entry-method = "psci"; 265 266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "little-rail-power-collapse"; 269 arm,psci-suspend-param = <0x40000004>; 270 entry-latency-us = <355>; 271 exit-latency-us = <909>; 272 min-residency-us = <3934>; 273 local-timer-stop; 274 }; 275 276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "big-rail-power-collapse"; 279 arm,psci-suspend-param = <0x40000004>; 280 entry-latency-us = <241>; 281 exit-latency-us = <1461>; 282 min-residency-us = <4488>; 283 local-timer-stop; 284 }; 285 }; 286 287 domain-idle-states { 288 CLUSTER_SLEEP_0: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 arm,psci-suspend-param = <0x4100c344>; 291 entry-latency-us = <3263>; 292 exit-latency-us = <6562>; 293 min-residency-us = <9987>; 294 }; 295 }; 296 }; 297 298 firmware { 299 scm: scm { 300 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 301 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 302 }; 303 }; 304 305 aggre1_noc: interconnect-aggre1-noc { 306 compatible = "qcom,sc8280xp-aggre1-noc"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 aggre2_noc: interconnect-aggre2-noc { 312 compatible = "qcom,sc8280xp-aggre2-noc"; 313 #interconnect-cells = <2>; 314 qcom,bcm-voters = <&apps_bcm_voter>; 315 }; 316 317 clk_virt: interconnect-clk-virt { 318 compatible = "qcom,sc8280xp-clk-virt"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 config_noc: interconnect-config-noc { 324 compatible = "qcom,sc8280xp-config-noc"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 dc_noc: interconnect-dc-noc { 330 compatible = "qcom,sc8280xp-dc-noc"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 gem_noc: interconnect-gem-noc { 336 compatible = "qcom,sc8280xp-gem-noc"; 337 #interconnect-cells = <2>; 338 qcom,bcm-voters = <&apps_bcm_voter>; 339 }; 340 341 lpass_noc: interconnect-lpass-ag-noc { 342 compatible = "qcom,sc8280xp-lpass-ag-noc"; 343 #interconnect-cells = <2>; 344 qcom,bcm-voters = <&apps_bcm_voter>; 345 }; 346 347 mc_virt: interconnect-mc-virt { 348 compatible = "qcom,sc8280xp-mc-virt"; 349 #interconnect-cells = <2>; 350 qcom,bcm-voters = <&apps_bcm_voter>; 351 }; 352 353 mmss_noc: interconnect-mmss-noc { 354 compatible = "qcom,sc8280xp-mmss-noc"; 355 #interconnect-cells = <2>; 356 qcom,bcm-voters = <&apps_bcm_voter>; 357 }; 358 359 nspa_noc: interconnect-nspa-noc { 360 compatible = "qcom,sc8280xp-nspa-noc"; 361 #interconnect-cells = <2>; 362 qcom,bcm-voters = <&apps_bcm_voter>; 363 }; 364 365 nspb_noc: interconnect-nspb-noc { 366 compatible = "qcom,sc8280xp-nspb-noc"; 367 #interconnect-cells = <2>; 368 qcom,bcm-voters = <&apps_bcm_voter>; 369 }; 370 371 system_noc: interconnect-system-noc { 372 compatible = "qcom,sc8280xp-system-noc"; 373 #interconnect-cells = <2>; 374 qcom,bcm-voters = <&apps_bcm_voter>; 375 }; 376 377 memory@80000000 { 378 device_type = "memory"; 379 /* We expect the bootloader to fill in the size */ 380 reg = <0x0 0x80000000 0x0 0x0>; 381 }; 382 383 cpu0_opp_table: opp-table-cpu0 { 384 compatible = "operating-points-v2"; 385 opp-shared; 386 387 opp-300000000 { 388 opp-hz = /bits/ 64 <300000000>; 389 opp-peak-kBps = <(300000 * 32)>; 390 }; 391 opp-403200000 { 392 opp-hz = /bits/ 64 <403200000>; 393 opp-peak-kBps = <(384000 * 32)>; 394 }; 395 opp-499200000 { 396 opp-hz = /bits/ 64 <499200000>; 397 opp-peak-kBps = <(480000 * 32)>; 398 }; 399 opp-595200000 { 400 opp-hz = /bits/ 64 <595200000>; 401 opp-peak-kBps = <(576000 * 32)>; 402 }; 403 opp-691200000 { 404 opp-hz = /bits/ 64 <691200000>; 405 opp-peak-kBps = <(672000 * 32)>; 406 }; 407 opp-806400000 { 408 opp-hz = /bits/ 64 <806400000>; 409 opp-peak-kBps = <(768000 * 32)>; 410 }; 411 opp-902400000 { 412 opp-hz = /bits/ 64 <902400000>; 413 opp-peak-kBps = <(864000 * 32)>; 414 }; 415 opp-1017600000 { 416 opp-hz = /bits/ 64 <1017600000>; 417 opp-peak-kBps = <(960000 * 32)>; 418 }; 419 opp-1113600000 { 420 opp-hz = /bits/ 64 <1113600000>; 421 opp-peak-kBps = <(1075200 * 32)>; 422 }; 423 opp-1209600000 { 424 opp-hz = /bits/ 64 <1209600000>; 425 opp-peak-kBps = <(1171200 * 32)>; 426 }; 427 opp-1324800000 { 428 opp-hz = /bits/ 64 <1324800000>; 429 opp-peak-kBps = <(1267200 * 32)>; 430 }; 431 opp-1440000000 { 432 opp-hz = /bits/ 64 <1440000000>; 433 opp-peak-kBps = <(1363200 * 32)>; 434 }; 435 opp-1555200000 { 436 opp-hz = /bits/ 64 <1555200000>; 437 opp-peak-kBps = <(1536000 * 32)>; 438 }; 439 opp-1670400000 { 440 opp-hz = /bits/ 64 <1670400000>; 441 opp-peak-kBps = <(1612800 * 32)>; 442 }; 443 opp-1785600000 { 444 opp-hz = /bits/ 64 <1785600000>; 445 opp-peak-kBps = <(1689600 * 32)>; 446 }; 447 opp-1881600000 { 448 opp-hz = /bits/ 64 <1881600000>; 449 opp-peak-kBps = <(1689600 * 32)>; 450 }; 451 opp-1996800000 { 452 opp-hz = /bits/ 64 <1996800000>; 453 opp-peak-kBps = <(1689600 * 32)>; 454 }; 455 opp-2112000000 { 456 opp-hz = /bits/ 64 <2112000000>; 457 opp-peak-kBps = <(1689600 * 32)>; 458 }; 459 opp-2227200000 { 460 opp-hz = /bits/ 64 <2227200000>; 461 opp-peak-kBps = <(1689600 * 32)>; 462 }; 463 opp-2342400000 { 464 opp-hz = /bits/ 64 <2342400000>; 465 opp-peak-kBps = <(1689600 * 32)>; 466 }; 467 opp-2438400000 { 468 opp-hz = /bits/ 64 <2438400000>; 469 opp-peak-kBps = <(1689600 * 32)>; 470 }; 471 }; 472 473 cpu4_opp_table: opp-table-cpu4 { 474 compatible = "operating-points-v2"; 475 opp-shared; 476 477 opp-825600000 { 478 opp-hz = /bits/ 64 <825600000>; 479 opp-peak-kBps = <(768000 * 32)>; 480 }; 481 opp-940800000 { 482 opp-hz = /bits/ 64 <940800000>; 483 opp-peak-kBps = <(864000 * 32)>; 484 }; 485 opp-1056000000 { 486 opp-hz = /bits/ 64 <1056000000>; 487 opp-peak-kBps = <(960000 * 32)>; 488 }; 489 opp-1171200000 { 490 opp-hz = /bits/ 64 <1171200000>; 491 opp-peak-kBps = <(1171200 * 32)>; 492 }; 493 opp-1286400000 { 494 opp-hz = /bits/ 64 <1286400000>; 495 opp-peak-kBps = <(1267200 * 32)>; 496 }; 497 opp-1401600000 { 498 opp-hz = /bits/ 64 <1401600000>; 499 opp-peak-kBps = <(1363200 * 32)>; 500 }; 501 opp-1516800000 { 502 opp-hz = /bits/ 64 <1516800000>; 503 opp-peak-kBps = <(1459200 * 32)>; 504 }; 505 opp-1632000000 { 506 opp-hz = /bits/ 64 <1632000000>; 507 opp-peak-kBps = <(1612800 * 32)>; 508 }; 509 opp-1747200000 { 510 opp-hz = /bits/ 64 <1747200000>; 511 opp-peak-kBps = <(1689600 * 32)>; 512 }; 513 opp-1862400000 { 514 opp-hz = /bits/ 64 <1862400000>; 515 opp-peak-kBps = <(1689600 * 32)>; 516 }; 517 opp-1977600000 { 518 opp-hz = /bits/ 64 <1977600000>; 519 opp-peak-kBps = <(1689600 * 32)>; 520 }; 521 opp-2073600000 { 522 opp-hz = /bits/ 64 <2073600000>; 523 opp-peak-kBps = <(1689600 * 32)>; 524 }; 525 opp-2169600000 { 526 opp-hz = /bits/ 64 <2169600000>; 527 opp-peak-kBps = <(1689600 * 32)>; 528 }; 529 opp-2284800000 { 530 opp-hz = /bits/ 64 <2284800000>; 531 opp-peak-kBps = <(1689600 * 32)>; 532 }; 533 opp-2400000000 { 534 opp-hz = /bits/ 64 <2400000000>; 535 opp-peak-kBps = <(1689600 * 32)>; 536 }; 537 opp-2496000000 { 538 opp-hz = /bits/ 64 <2496000000>; 539 opp-peak-kBps = <(1689600 * 32)>; 540 }; 541 opp-2592000000 { 542 opp-hz = /bits/ 64 <2592000000>; 543 opp-peak-kBps = <(1689600 * 32)>; 544 }; 545 opp-2688000000 { 546 opp-hz = /bits/ 64 <2688000000>; 547 opp-peak-kBps = <(1689600 * 32)>; 548 }; 549 opp-2803200000 { 550 opp-hz = /bits/ 64 <2803200000>; 551 opp-peak-kBps = <(1689600 * 32)>; 552 }; 553 opp-2899200000 { 554 opp-hz = /bits/ 64 <2899200000>; 555 opp-peak-kBps = <(1689600 * 32)>; 556 }; 557 opp-2995200000 { 558 opp-hz = /bits/ 64 <2995200000>; 559 opp-peak-kBps = <(1689600 * 32)>; 560 }; 561 }; 562 563 qup_opp_table_100mhz: opp-table-qup100mhz { 564 compatible = "operating-points-v2"; 565 566 opp-75000000 { 567 opp-hz = /bits/ 64 <75000000>; 568 required-opps = <&rpmhpd_opp_low_svs>; 569 }; 570 571 opp-100000000 { 572 opp-hz = /bits/ 64 <100000000>; 573 required-opps = <&rpmhpd_opp_svs>; 574 }; 575 }; 576 577 pmu { 578 compatible = "arm,armv8-pmuv3"; 579 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 580 }; 581 582 psci { 583 compatible = "arm,psci-1.0"; 584 method = "smc"; 585 586 CPU_PD0: power-domain-cpu0 { 587 #power-domain-cells = <0>; 588 power-domains = <&CLUSTER_PD>; 589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 590 }; 591 592 CPU_PD1: power-domain-cpu1 { 593 #power-domain-cells = <0>; 594 power-domains = <&CLUSTER_PD>; 595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 596 }; 597 598 CPU_PD2: power-domain-cpu2 { 599 #power-domain-cells = <0>; 600 power-domains = <&CLUSTER_PD>; 601 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 602 }; 603 604 CPU_PD3: power-domain-cpu3 { 605 #power-domain-cells = <0>; 606 power-domains = <&CLUSTER_PD>; 607 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 608 }; 609 610 CPU_PD4: power-domain-cpu4 { 611 #power-domain-cells = <0>; 612 power-domains = <&CLUSTER_PD>; 613 domain-idle-states = <&BIG_CPU_SLEEP_0>; 614 }; 615 616 CPU_PD5: power-domain-cpu5 { 617 #power-domain-cells = <0>; 618 power-domains = <&CLUSTER_PD>; 619 domain-idle-states = <&BIG_CPU_SLEEP_0>; 620 }; 621 622 CPU_PD6: power-domain-cpu6 { 623 #power-domain-cells = <0>; 624 power-domains = <&CLUSTER_PD>; 625 domain-idle-states = <&BIG_CPU_SLEEP_0>; 626 }; 627 628 CPU_PD7: power-domain-cpu7 { 629 #power-domain-cells = <0>; 630 power-domains = <&CLUSTER_PD>; 631 domain-idle-states = <&BIG_CPU_SLEEP_0>; 632 }; 633 634 CLUSTER_PD: power-domain-cpu-cluster0 { 635 #power-domain-cells = <0>; 636 domain-idle-states = <&CLUSTER_SLEEP_0>; 637 }; 638 }; 639 640 reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 reserved-region@80000000 { 646 reg = <0 0x80000000 0 0x860000>; 647 no-map; 648 }; 649 650 cmd_db: cmd-db-region@80860000 { 651 compatible = "qcom,cmd-db"; 652 reg = <0 0x80860000 0 0x20000>; 653 no-map; 654 }; 655 656 reserved-region@80880000 { 657 reg = <0 0x80880000 0 0x80000>; 658 no-map; 659 }; 660 661 smem_mem: smem-region@80900000 { 662 compatible = "qcom,smem"; 663 reg = <0 0x80900000 0 0x200000>; 664 no-map; 665 hwlocks = <&tcsr_mutex 3>; 666 }; 667 668 reserved-region@80b00000 { 669 reg = <0 0x80b00000 0 0x100000>; 670 no-map; 671 }; 672 673 reserved-region@83b00000 { 674 reg = <0 0x83b00000 0 0x1700000>; 675 no-map; 676 }; 677 678 reserved-region@85b00000 { 679 reg = <0 0x85b00000 0 0xc00000>; 680 no-map; 681 }; 682 683 pil_adsp_mem: adsp-region@86c00000 { 684 reg = <0 0x86c00000 0 0x2000000>; 685 no-map; 686 }; 687 688 pil_nsp0_mem: cdsp0-region@8a100000 { 689 reg = <0 0x8a100000 0 0x1e00000>; 690 no-map; 691 }; 692 693 pil_nsp1_mem: cdsp1-region@8c600000 { 694 reg = <0 0x8c600000 0 0x1e00000>; 695 no-map; 696 }; 697 698 reserved-region@aeb00000 { 699 reg = <0 0xaeb00000 0 0x16600000>; 700 no-map; 701 }; 702 }; 703 704 smp2p-adsp { 705 compatible = "qcom,smp2p"; 706 qcom,smem = <443>, <429>; 707 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 708 IPCC_MPROC_SIGNAL_SMP2P 709 IRQ_TYPE_EDGE_RISING>; 710 mboxes = <&ipcc IPCC_CLIENT_LPASS 711 IPCC_MPROC_SIGNAL_SMP2P>; 712 713 qcom,local-pid = <0>; 714 qcom,remote-pid = <2>; 715 716 smp2p_adsp_out: master-kernel { 717 qcom,entry-name = "master-kernel"; 718 #qcom,smem-state-cells = <1>; 719 }; 720 721 smp2p_adsp_in: slave-kernel { 722 qcom,entry-name = "slave-kernel"; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 }; 727 728 smp2p-nsp0 { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <94>, <432>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_CDSP 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <5>; 739 740 smp2p_nsp0_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 smp2p_nsp0_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 }; 751 752 smp2p-nsp1 { 753 compatible = "qcom,smp2p"; 754 qcom,smem = <617>, <616>; 755 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 756 IPCC_MPROC_SIGNAL_SMP2P 757 IRQ_TYPE_EDGE_RISING>; 758 mboxes = <&ipcc IPCC_CLIENT_NSP1 759 IPCC_MPROC_SIGNAL_SMP2P>; 760 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <12>; 763 764 smp2p_nsp1_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 smp2p_nsp1_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 }; 775 776 soc: soc@0 { 777 compatible = "simple-bus"; 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges = <0 0 0 0 0x10 0>; 781 dma-ranges = <0 0 0 0 0x10 0>; 782 783 ethernet0: ethernet@20000 { 784 compatible = "qcom,sc8280xp-ethqos"; 785 reg = <0x0 0x00020000 0x0 0x10000>, 786 <0x0 0x00036000 0x0 0x100>; 787 reg-names = "stmmaceth", "rgmii"; 788 789 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 790 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 791 <&gcc GCC_EMAC0_PTP_CLK>, 792 <&gcc GCC_EMAC0_RGMII_CLK>; 793 clock-names = "stmmaceth", 794 "pclk", 795 "ptp_ref", 796 "rgmii"; 797 798 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 800 interrupt-names = "macirq", "eth_lpi"; 801 802 iommus = <&apps_smmu 0x4c0 0xf>; 803 power-domains = <&gcc EMAC_0_GDSC>; 804 805 snps,tso; 806 snps,pbl = <32>; 807 rx-fifo-depth = <4096>; 808 tx-fifo-depth = <4096>; 809 810 status = "disabled"; 811 }; 812 813 gcc: clock-controller@100000 { 814 compatible = "qcom,gcc-sc8280xp"; 815 reg = <0x0 0x00100000 0x0 0x1f0000>; 816 #clock-cells = <1>; 817 #reset-cells = <1>; 818 #power-domain-cells = <1>; 819 clocks = <&rpmhcc RPMH_CXO_CLK>, 820 <&sleep_clk>, 821 <0>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <0>, 845 <&pcie2a_phy>, 846 <&pcie2b_phy>, 847 <&pcie3a_phy>, 848 <&pcie3b_phy>, 849 <&pcie4_phy>, 850 <0>, 851 <0>; 852 power-domains = <&rpmhpd SC8280XP_CX>; 853 }; 854 855 ipcc: mailbox@408000 { 856 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 857 reg = <0 0x00408000 0 0x1000>; 858 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-controller; 860 #interrupt-cells = <3>; 861 #mbox-cells = <2>; 862 }; 863 864 qup2: geniqup@8c0000 { 865 compatible = "qcom,geni-se-qup"; 866 reg = <0 0x008c0000 0 0x2000>; 867 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 868 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 869 clock-names = "m-ahb", "s-ahb"; 870 iommus = <&apps_smmu 0xa3 0>; 871 872 #address-cells = <2>; 873 #size-cells = <2>; 874 ranges; 875 876 status = "disabled"; 877 878 i2c16: i2c@880000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00880000 0 0x4000>; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 884 clock-names = "se"; 885 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&rpmhpd SC8280XP_CX>; 887 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 889 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 891 status = "disabled"; 892 }; 893 894 spi16: spi@880000 { 895 compatible = "qcom,geni-spi"; 896 reg = <0 0x00880000 0 0x4000>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 900 clock-names = "se"; 901 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 902 power-domains = <&rpmhpd SC8280XP_CX>; 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 905 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 906 interconnect-names = "qup-core", "qup-config", "qup-memory"; 907 status = "disabled"; 908 }; 909 910 i2c17: i2c@884000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0 0x00884000 0 0x4000>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 916 clock-names = "se"; 917 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 918 power-domains = <&rpmhpd SC8280XP_CX>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 921 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 922 interconnect-names = "qup-core", "qup-config", "qup-memory"; 923 status = "disabled"; 924 }; 925 926 spi17: spi@884000 { 927 compatible = "qcom,geni-spi"; 928 reg = <0 0x00884000 0 0x4000>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 932 clock-names = "se"; 933 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 934 power-domains = <&rpmhpd SC8280XP_CX>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 937 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 status = "disabled"; 940 }; 941 942 uart17: serial@884000 { 943 compatible = "qcom,geni-uart"; 944 reg = <0 0x00884000 0 0x4000>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 946 clock-names = "se"; 947 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 948 operating-points-v2 = <&qup_opp_table_100mhz>; 949 power-domains = <&rpmhpd SC8280XP_CX>; 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 952 interconnect-names = "qup-core", "qup-config"; 953 status = "disabled"; 954 }; 955 956 i2c18: i2c@888000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0 0x00888000 0 0x4000>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 962 clock-names = "se"; 963 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 964 power-domains = <&rpmhpd SC8280XP_CX>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 967 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", "qup-memory"; 969 status = "disabled"; 970 }; 971 972 spi18: spi@888000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x00888000 0 0x4000>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 978 clock-names = "se"; 979 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 980 power-domains = <&rpmhpd SC8280XP_CX>; 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 983 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 984 interconnect-names = "qup-core", "qup-config", "qup-memory"; 985 status = "disabled"; 986 }; 987 988 i2c19: i2c@88c000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x0088c000 0 0x4000>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 994 clock-names = "se"; 995 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 996 power-domains = <&rpmhpd SC8280XP_CX>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 999 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1000 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1001 status = "disabled"; 1002 }; 1003 1004 spi19: spi@88c000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x0088c000 0 0x4000>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1010 clock-names = "se"; 1011 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1012 power-domains = <&rpmhpd SC8280XP_CX>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1015 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c20: i2c@890000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00890000 0 0x4000>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1026 clock-names = "se"; 1027 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1028 power-domains = <&rpmhpd SC8280XP_CX>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1031 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1032 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1033 status = "disabled"; 1034 }; 1035 1036 spi20: spi@890000 { 1037 compatible = "qcom,geni-spi"; 1038 reg = <0 0x00890000 0 0x4000>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1042 clock-names = "se"; 1043 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SC8280XP_CX>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1047 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1049 status = "disabled"; 1050 }; 1051 1052 i2c21: i2c@894000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x00894000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1057 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 power-domains = <&rpmhpd SC8280XP_CX>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1063 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1064 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1065 status = "disabled"; 1066 }; 1067 1068 spi21: spi@894000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x00894000 0 0x4000>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1074 clock-names = "se"; 1075 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1076 power-domains = <&rpmhpd SC8280XP_CX>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1079 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1080 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c22: i2c@898000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00898000 0 0x4000>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 clock-names = "se"; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1091 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1092 power-domains = <&rpmhpd SC8280XP_CX>; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1095 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1096 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1097 status = "disabled"; 1098 }; 1099 1100 spi22: spi@898000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00898000 0 0x4000>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1106 clock-names = "se"; 1107 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1108 power-domains = <&rpmhpd SC8280XP_CX>; 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1111 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1112 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1113 status = "disabled"; 1114 }; 1115 1116 i2c23: i2c@89c000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0 0x0089c000 0 0x4000>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1123 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1124 power-domains = <&rpmhpd SC8280XP_CX>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1126 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1128 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1129 status = "disabled"; 1130 }; 1131 1132 spi23: spi@89c000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x0089c000 0 0x4000>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1138 clock-names = "se"; 1139 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1140 power-domains = <&rpmhpd SC8280XP_CX>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1143 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1144 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1145 status = "disabled"; 1146 }; 1147 }; 1148 1149 qup0: geniqup@9c0000 { 1150 compatible = "qcom,geni-se-qup"; 1151 reg = <0 0x009c0000 0 0x6000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1153 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1154 clock-names = "m-ahb", "s-ahb"; 1155 iommus = <&apps_smmu 0x563 0>; 1156 1157 #address-cells = <2>; 1158 #size-cells = <2>; 1159 ranges; 1160 1161 status = "disabled"; 1162 1163 i2c0: i2c@980000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x00980000 0 0x4000>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1170 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1171 power-domains = <&rpmhpd SC8280XP_CX>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1173 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1175 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1176 status = "disabled"; 1177 }; 1178 1179 spi0: spi@980000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x00980000 0 0x4000>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1185 clock-names = "se"; 1186 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1187 power-domains = <&rpmhpd SC8280XP_CX>; 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1189 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1190 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1191 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1192 status = "disabled"; 1193 }; 1194 1195 i2c1: i2c@984000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0 0x00984000 0 0x4000>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1203 power-domains = <&rpmhpd SC8280XP_CX>; 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1206 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1207 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1208 status = "disabled"; 1209 }; 1210 1211 spi1: spi@984000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00984000 0 0x4000>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1217 clock-names = "se"; 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1219 power-domains = <&rpmhpd SC8280XP_CX>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1222 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1223 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1224 status = "disabled"; 1225 }; 1226 1227 i2c2: i2c@988000 { 1228 compatible = "qcom,geni-i2c"; 1229 reg = <0 0x00988000 0 0x4000>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1234 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC8280XP_CX>; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1238 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1239 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1240 status = "disabled"; 1241 }; 1242 1243 spi2: spi@988000 { 1244 compatible = "qcom,geni-spi"; 1245 reg = <0 0x00988000 0 0x4000>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1249 clock-names = "se"; 1250 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1251 power-domains = <&rpmhpd SC8280XP_CX>; 1252 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1254 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1255 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1256 status = "disabled"; 1257 }; 1258 1259 uart2: serial@988000 { 1260 compatible = "qcom,geni-uart"; 1261 reg = <0 0x00988000 0 0x4000>; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1263 clock-names = "se"; 1264 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1265 operating-points-v2 = <&qup_opp_table_100mhz>; 1266 power-domains = <&rpmhpd SC8280XP_CX>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 status = "disabled"; 1271 }; 1272 1273 i2c3: i2c@98c000 { 1274 compatible = "qcom,geni-i2c"; 1275 reg = <0 0x0098c000 0 0x4000>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1281 power-domains = <&rpmhpd SC8280XP_CX>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1284 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1285 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1286 status = "disabled"; 1287 }; 1288 1289 spi3: spi@98c000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x0098c000 0 0x4000>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1295 clock-names = "se"; 1296 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1297 power-domains = <&rpmhpd SC8280XP_CX>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1299 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1301 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1302 status = "disabled"; 1303 }; 1304 1305 i2c4: i2c@990000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0 0x00990000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1310 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&rpmhpd SC8280XP_CX>; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1316 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1317 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1318 status = "disabled"; 1319 }; 1320 1321 spi4: spi@990000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0 0x00990000 0 0x4000>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1327 clock-names = "se"; 1328 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1329 power-domains = <&rpmhpd SC8280XP_CX>; 1330 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1332 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1333 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1334 status = "disabled"; 1335 }; 1336 1337 i2c5: i2c@994000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0 0x00994000 0 0x4000>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC8280XP_CX>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1348 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 status = "disabled"; 1351 }; 1352 1353 spi5: spi@994000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00994000 0 0x4000>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1359 clock-names = "se"; 1360 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1361 power-domains = <&rpmhpd SC8280XP_CX>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1366 status = "disabled"; 1367 }; 1368 1369 i2c6: i2c@998000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0 0x00998000 0 0x4000>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 clock-names = "se"; 1375 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1376 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1377 power-domains = <&rpmhpd SC8280XP_CX>; 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1381 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1382 status = "disabled"; 1383 }; 1384 1385 spi6: spi@998000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00998000 0 0x4000>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1391 clock-names = "se"; 1392 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1393 power-domains = <&rpmhpd SC8280XP_CX>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1395 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1396 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1397 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1398 status = "disabled"; 1399 }; 1400 1401 i2c7: i2c@99c000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x0099c000 0 0x4000>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC8280XP_CX>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1412 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1413 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1414 status = "disabled"; 1415 }; 1416 1417 spi7: spi@99c000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x0099c000 0 0x4000>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1423 clock-names = "se"; 1424 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1425 power-domains = <&rpmhpd SC8280XP_CX>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1428 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1429 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1430 status = "disabled"; 1431 }; 1432 }; 1433 1434 qup1: geniqup@ac0000 { 1435 compatible = "qcom,geni-se-qup"; 1436 reg = <0 0x00ac0000 0 0x6000>; 1437 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1438 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1439 clock-names = "m-ahb", "s-ahb"; 1440 iommus = <&apps_smmu 0x83 0>; 1441 1442 #address-cells = <2>; 1443 #size-cells = <2>; 1444 ranges; 1445 1446 status = "disabled"; 1447 1448 i2c8: i2c@a80000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x00a80000 0 0x4000>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1454 clock-names = "se"; 1455 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1456 power-domains = <&rpmhpd SC8280XP_CX>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1459 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1460 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1461 status = "disabled"; 1462 }; 1463 1464 spi8: spi@a80000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0 0x00a80000 0 0x4000>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1470 clock-names = "se"; 1471 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1472 power-domains = <&rpmhpd SC8280XP_CX>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 status = "disabled"; 1478 }; 1479 1480 i2c9: i2c@a84000 { 1481 compatible = "qcom,geni-i2c"; 1482 reg = <0 0x00a84000 0 0x4000>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1486 clock-names = "se"; 1487 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1488 power-domains = <&rpmhpd SC8280XP_CX>; 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1491 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1492 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1493 status = "disabled"; 1494 }; 1495 1496 spi9: spi@a84000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00a84000 0 0x4000>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1502 clock-names = "se"; 1503 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd SC8280XP_CX>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1508 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1509 status = "disabled"; 1510 }; 1511 1512 i2c10: i2c@a88000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0 0x00a88000 0 0x4000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1518 clock-names = "se"; 1519 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1520 power-domains = <&rpmhpd SC8280XP_CX>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1523 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1524 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1525 status = "disabled"; 1526 }; 1527 1528 spi10: spi@a88000 { 1529 compatible = "qcom,geni-spi"; 1530 reg = <0 0x00a88000 0 0x4000>; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1534 clock-names = "se"; 1535 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1536 power-domains = <&rpmhpd SC8280XP_CX>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1538 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1539 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 status = "disabled"; 1542 }; 1543 1544 i2c11: i2c@a8c000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0 0x00a8c000 0 0x4000>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1550 clock-names = "se"; 1551 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1552 power-domains = <&rpmhpd SC8280XP_CX>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1556 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1557 status = "disabled"; 1558 }; 1559 1560 spi11: spi@a8c000 { 1561 compatible = "qcom,geni-spi"; 1562 reg = <0 0x00a8c000 0 0x4000>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1566 clock-names = "se"; 1567 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1568 power-domains = <&rpmhpd SC8280XP_CX>; 1569 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1570 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1571 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1572 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1573 status = "disabled"; 1574 }; 1575 1576 i2c12: i2c@a90000 { 1577 compatible = "qcom,geni-i2c"; 1578 reg = <0 0x00a90000 0 0x4000>; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1582 clock-names = "se"; 1583 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1584 power-domains = <&rpmhpd SC8280XP_CX>; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1588 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1589 status = "disabled"; 1590 }; 1591 1592 spi12: spi@a90000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0 0x00a90000 0 0x4000>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1598 clock-names = "se"; 1599 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1600 power-domains = <&rpmhpd SC8280XP_CX>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1603 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1604 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1605 status = "disabled"; 1606 }; 1607 1608 i2c13: i2c@a94000 { 1609 compatible = "qcom,geni-i2c"; 1610 reg = <0 0x00a94000 0 0x4000>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1614 clock-names = "se"; 1615 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1616 power-domains = <&rpmhpd SC8280XP_CX>; 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1618 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1619 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1620 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1621 status = "disabled"; 1622 }; 1623 1624 spi13: spi@a94000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a94000 0 0x4000>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1630 clock-names = "se"; 1631 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1632 power-domains = <&rpmhpd SC8280XP_CX>; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1634 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1635 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1636 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1637 status = "disabled"; 1638 }; 1639 1640 i2c14: i2c@a98000 { 1641 compatible = "qcom,geni-i2c"; 1642 reg = <0 0x00a98000 0 0x4000>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1646 clock-names = "se"; 1647 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1648 power-domains = <&rpmhpd SC8280XP_CX>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1651 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1652 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1653 status = "disabled"; 1654 }; 1655 1656 spi14: spi@a98000 { 1657 compatible = "qcom,geni-spi"; 1658 reg = <0 0x00a98000 0 0x4000>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1662 clock-names = "se"; 1663 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1664 power-domains = <&rpmhpd SC8280XP_CX>; 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1667 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1668 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1669 status = "disabled"; 1670 }; 1671 1672 i2c15: i2c@a9c000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a9c000 0 0x4000>; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1678 clock-names = "se"; 1679 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1680 power-domains = <&rpmhpd SC8280XP_CX>; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1682 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1683 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1684 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1685 status = "disabled"; 1686 }; 1687 1688 spi15: spi@a9c000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x00a9c000 0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1694 clock-names = "se"; 1695 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1696 power-domains = <&rpmhpd SC8280XP_CX>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1699 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1701 status = "disabled"; 1702 }; 1703 }; 1704 1705 rng: rng@10d3000 { 1706 compatible = "qcom,prng-ee"; 1707 reg = <0 0x010d3000 0 0x1000>; 1708 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1709 clock-names = "core"; 1710 }; 1711 1712 pcie4: pcie@1c00000 { 1713 device_type = "pci"; 1714 compatible = "qcom,pcie-sc8280xp"; 1715 reg = <0x0 0x01c00000 0x0 0x3000>, 1716 <0x0 0x30000000 0x0 0xf1d>, 1717 <0x0 0x30000f20 0x0 0xa8>, 1718 <0x0 0x30001000 0x0 0x1000>, 1719 <0x0 0x30100000 0x0 0x100000>, 1720 <0x0 0x01c03000 0x0 0x1000>; 1721 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1722 #address-cells = <3>; 1723 #size-cells = <2>; 1724 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1725 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1726 bus-range = <0x00 0xff>; 1727 1728 dma-coherent; 1729 1730 linux,pci-domain = <6>; 1731 num-lanes = <1>; 1732 1733 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1737 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1738 1739 #interrupt-cells = <1>; 1740 interrupt-map-mask = <0 0 0 0x7>; 1741 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1742 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1743 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1744 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1745 1746 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1747 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1748 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1749 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1750 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1751 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1752 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1753 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1754 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1755 clock-names = "aux", 1756 "cfg", 1757 "bus_master", 1758 "bus_slave", 1759 "slave_q2a", 1760 "ddrss_sf_tbu", 1761 "noc_aggr_4", 1762 "noc_aggr_south_sf", 1763 "cnoc_qx"; 1764 1765 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1766 assigned-clock-rates = <19200000>; 1767 1768 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1769 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1770 interconnect-names = "pcie-mem", "cpu-pcie"; 1771 1772 resets = <&gcc GCC_PCIE_4_BCR>; 1773 reset-names = "pci"; 1774 1775 power-domains = <&gcc PCIE_4_GDSC>; 1776 required-opps = <&rpmhpd_opp_nom>; 1777 1778 phys = <&pcie4_phy>; 1779 phy-names = "pciephy"; 1780 1781 status = "disabled"; 1782 }; 1783 1784 pcie4_phy: phy@1c06000 { 1785 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1786 reg = <0x0 0x01c06000 0x0 0x2000>; 1787 1788 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1789 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1790 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1791 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1792 <&gcc GCC_PCIE_4_PIPE_CLK>, 1793 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1794 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1795 "pipe", "pipediv2"; 1796 1797 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1798 assigned-clock-rates = <100000000>; 1799 1800 power-domains = <&gcc PCIE_4_GDSC>; 1801 required-opps = <&rpmhpd_opp_nom>; 1802 1803 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1804 reset-names = "phy"; 1805 1806 #clock-cells = <0>; 1807 clock-output-names = "pcie_4_pipe_clk"; 1808 1809 #phy-cells = <0>; 1810 1811 status = "disabled"; 1812 }; 1813 1814 pcie3b: pcie@1c08000 { 1815 device_type = "pci"; 1816 compatible = "qcom,pcie-sc8280xp"; 1817 reg = <0x0 0x01c08000 0x0 0x3000>, 1818 <0x0 0x32000000 0x0 0xf1d>, 1819 <0x0 0x32000f20 0x0 0xa8>, 1820 <0x0 0x32001000 0x0 0x1000>, 1821 <0x0 0x32100000 0x0 0x100000>, 1822 <0x0 0x01c0b000 0x0 0x1000>; 1823 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1824 #address-cells = <3>; 1825 #size-cells = <2>; 1826 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1827 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1828 bus-range = <0x00 0xff>; 1829 1830 dma-coherent; 1831 1832 linux,pci-domain = <5>; 1833 num-lanes = <2>; 1834 1835 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1839 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1840 1841 #interrupt-cells = <1>; 1842 interrupt-map-mask = <0 0 0 0x7>; 1843 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1844 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1845 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1846 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1847 1848 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1849 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1850 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1851 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1852 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1853 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1854 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1855 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1856 clock-names = "aux", 1857 "cfg", 1858 "bus_master", 1859 "bus_slave", 1860 "slave_q2a", 1861 "ddrss_sf_tbu", 1862 "noc_aggr_4", 1863 "noc_aggr_south_sf"; 1864 1865 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1866 assigned-clock-rates = <19200000>; 1867 1868 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1870 interconnect-names = "pcie-mem", "cpu-pcie"; 1871 1872 resets = <&gcc GCC_PCIE_3B_BCR>; 1873 reset-names = "pci"; 1874 1875 power-domains = <&gcc PCIE_3B_GDSC>; 1876 required-opps = <&rpmhpd_opp_nom>; 1877 1878 phys = <&pcie3b_phy>; 1879 phy-names = "pciephy"; 1880 1881 status = "disabled"; 1882 }; 1883 1884 pcie3b_phy: phy@1c0e000 { 1885 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1886 reg = <0x0 0x01c0e000 0x0 0x2000>; 1887 1888 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1889 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1890 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1891 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1892 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1893 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1894 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1895 "pipe", "pipediv2"; 1896 1897 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1898 assigned-clock-rates = <100000000>; 1899 1900 power-domains = <&gcc PCIE_3B_GDSC>; 1901 required-opps = <&rpmhpd_opp_nom>; 1902 1903 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1904 reset-names = "phy"; 1905 1906 #clock-cells = <0>; 1907 clock-output-names = "pcie_3b_pipe_clk"; 1908 1909 #phy-cells = <0>; 1910 1911 status = "disabled"; 1912 }; 1913 1914 pcie3a: pcie@1c10000 { 1915 device_type = "pci"; 1916 compatible = "qcom,pcie-sc8280xp"; 1917 reg = <0x0 0x01c10000 0x0 0x3000>, 1918 <0x0 0x34000000 0x0 0xf1d>, 1919 <0x0 0x34000f20 0x0 0xa8>, 1920 <0x0 0x34001000 0x0 0x1000>, 1921 <0x0 0x34100000 0x0 0x100000>, 1922 <0x0 0x01c13000 0x0 0x1000>; 1923 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1924 #address-cells = <3>; 1925 #size-cells = <2>; 1926 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1927 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1928 bus-range = <0x00 0xff>; 1929 1930 dma-coherent; 1931 1932 linux,pci-domain = <4>; 1933 num-lanes = <4>; 1934 1935 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1939 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1940 1941 #interrupt-cells = <1>; 1942 interrupt-map-mask = <0 0 0 0x7>; 1943 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1944 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1945 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1946 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1947 1948 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1949 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1950 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1951 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1952 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1953 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1954 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1955 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1956 clock-names = "aux", 1957 "cfg", 1958 "bus_master", 1959 "bus_slave", 1960 "slave_q2a", 1961 "ddrss_sf_tbu", 1962 "noc_aggr_4", 1963 "noc_aggr_south_sf"; 1964 1965 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1966 assigned-clock-rates = <19200000>; 1967 1968 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1969 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1970 interconnect-names = "pcie-mem", "cpu-pcie"; 1971 1972 resets = <&gcc GCC_PCIE_3A_BCR>; 1973 reset-names = "pci"; 1974 1975 power-domains = <&gcc PCIE_3A_GDSC>; 1976 required-opps = <&rpmhpd_opp_nom>; 1977 1978 phys = <&pcie3a_phy>; 1979 phy-names = "pciephy"; 1980 1981 status = "disabled"; 1982 }; 1983 1984 pcie3a_phy: phy@1c14000 { 1985 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1986 reg = <0x0 0x01c14000 0x0 0x2000>, 1987 <0x0 0x01c16000 0x0 0x2000>; 1988 1989 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1990 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1991 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1992 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1993 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1994 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1995 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1996 "pipe", "pipediv2"; 1997 1998 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1999 assigned-clock-rates = <100000000>; 2000 2001 power-domains = <&gcc PCIE_3A_GDSC>; 2002 required-opps = <&rpmhpd_opp_nom>; 2003 2004 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2005 reset-names = "phy"; 2006 2007 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2008 2009 #clock-cells = <0>; 2010 clock-output-names = "pcie_3a_pipe_clk"; 2011 2012 #phy-cells = <0>; 2013 2014 status = "disabled"; 2015 }; 2016 2017 pcie2b: pcie@1c18000 { 2018 device_type = "pci"; 2019 compatible = "qcom,pcie-sc8280xp"; 2020 reg = <0x0 0x01c18000 0x0 0x3000>, 2021 <0x0 0x38000000 0x0 0xf1d>, 2022 <0x0 0x38000f20 0x0 0xa8>, 2023 <0x0 0x38001000 0x0 0x1000>, 2024 <0x0 0x38100000 0x0 0x100000>, 2025 <0x0 0x01c1b000 0x0 0x1000>; 2026 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2027 #address-cells = <3>; 2028 #size-cells = <2>; 2029 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2030 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2031 bus-range = <0x00 0xff>; 2032 2033 dma-coherent; 2034 2035 linux,pci-domain = <3>; 2036 num-lanes = <2>; 2037 2038 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2042 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2043 2044 #interrupt-cells = <1>; 2045 interrupt-map-mask = <0 0 0 0x7>; 2046 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2047 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2048 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2049 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2050 2051 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2052 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2053 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2054 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2055 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2056 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2057 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2058 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2059 clock-names = "aux", 2060 "cfg", 2061 "bus_master", 2062 "bus_slave", 2063 "slave_q2a", 2064 "ddrss_sf_tbu", 2065 "noc_aggr_4", 2066 "noc_aggr_south_sf"; 2067 2068 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2069 assigned-clock-rates = <19200000>; 2070 2071 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2073 interconnect-names = "pcie-mem", "cpu-pcie"; 2074 2075 resets = <&gcc GCC_PCIE_2B_BCR>; 2076 reset-names = "pci"; 2077 2078 power-domains = <&gcc PCIE_2B_GDSC>; 2079 required-opps = <&rpmhpd_opp_nom>; 2080 2081 phys = <&pcie2b_phy>; 2082 phy-names = "pciephy"; 2083 2084 status = "disabled"; 2085 }; 2086 2087 pcie2b_phy: phy@1c1e000 { 2088 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2089 reg = <0x0 0x01c1e000 0x0 0x2000>; 2090 2091 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2092 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2093 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2094 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2095 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2096 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2097 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2098 "pipe", "pipediv2"; 2099 2100 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2101 assigned-clock-rates = <100000000>; 2102 2103 power-domains = <&gcc PCIE_2B_GDSC>; 2104 required-opps = <&rpmhpd_opp_nom>; 2105 2106 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2107 reset-names = "phy"; 2108 2109 #clock-cells = <0>; 2110 clock-output-names = "pcie_2b_pipe_clk"; 2111 2112 #phy-cells = <0>; 2113 2114 status = "disabled"; 2115 }; 2116 2117 pcie2a: pcie@1c20000 { 2118 device_type = "pci"; 2119 compatible = "qcom,pcie-sc8280xp"; 2120 reg = <0x0 0x01c20000 0x0 0x3000>, 2121 <0x0 0x3c000000 0x0 0xf1d>, 2122 <0x0 0x3c000f20 0x0 0xa8>, 2123 <0x0 0x3c001000 0x0 0x1000>, 2124 <0x0 0x3c100000 0x0 0x100000>, 2125 <0x0 0x01c23000 0x0 0x1000>; 2126 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2127 #address-cells = <3>; 2128 #size-cells = <2>; 2129 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2130 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2131 bus-range = <0x00 0xff>; 2132 2133 dma-coherent; 2134 2135 linux,pci-domain = <2>; 2136 num-lanes = <4>; 2137 2138 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2142 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2143 2144 #interrupt-cells = <1>; 2145 interrupt-map-mask = <0 0 0 0x7>; 2146 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2147 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2148 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2149 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2150 2151 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2152 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2153 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2154 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2155 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2156 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2157 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2158 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2159 clock-names = "aux", 2160 "cfg", 2161 "bus_master", 2162 "bus_slave", 2163 "slave_q2a", 2164 "ddrss_sf_tbu", 2165 "noc_aggr_4", 2166 "noc_aggr_south_sf"; 2167 2168 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2169 assigned-clock-rates = <19200000>; 2170 2171 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2173 interconnect-names = "pcie-mem", "cpu-pcie"; 2174 2175 resets = <&gcc GCC_PCIE_2A_BCR>; 2176 reset-names = "pci"; 2177 2178 power-domains = <&gcc PCIE_2A_GDSC>; 2179 required-opps = <&rpmhpd_opp_nom>; 2180 2181 phys = <&pcie2a_phy>; 2182 phy-names = "pciephy"; 2183 2184 status = "disabled"; 2185 }; 2186 2187 pcie2a_phy: phy@1c24000 { 2188 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2189 reg = <0x0 0x01c24000 0x0 0x2000>, 2190 <0x0 0x01c26000 0x0 0x2000>; 2191 2192 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2193 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2194 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2195 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2196 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2197 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2198 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2199 "pipe", "pipediv2"; 2200 2201 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2202 assigned-clock-rates = <100000000>; 2203 2204 power-domains = <&gcc PCIE_2A_GDSC>; 2205 required-opps = <&rpmhpd_opp_nom>; 2206 2207 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2208 reset-names = "phy"; 2209 2210 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2211 2212 #clock-cells = <0>; 2213 clock-output-names = "pcie_2a_pipe_clk"; 2214 2215 #phy-cells = <0>; 2216 2217 status = "disabled"; 2218 }; 2219 2220 ufs_mem_hc: ufs@1d84000 { 2221 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2222 "jedec,ufs-2.0"; 2223 reg = <0 0x01d84000 0 0x3000>; 2224 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2225 phys = <&ufs_mem_phy>; 2226 phy-names = "ufsphy"; 2227 lanes-per-direction = <2>; 2228 #reset-cells = <1>; 2229 resets = <&gcc GCC_UFS_PHY_BCR>; 2230 reset-names = "rst"; 2231 2232 power-domains = <&gcc UFS_PHY_GDSC>; 2233 required-opps = <&rpmhpd_opp_nom>; 2234 2235 iommus = <&apps_smmu 0xe0 0x0>; 2236 dma-coherent; 2237 2238 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2239 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2240 <&gcc GCC_UFS_PHY_AHB_CLK>, 2241 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2242 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2243 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2244 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2245 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2246 clock-names = "core_clk", 2247 "bus_aggr_clk", 2248 "iface_clk", 2249 "core_clk_unipro", 2250 "ref_clk", 2251 "tx_lane0_sync_clk", 2252 "rx_lane0_sync_clk", 2253 "rx_lane1_sync_clk"; 2254 freq-table-hz = <75000000 300000000>, 2255 <0 0>, 2256 <0 0>, 2257 <75000000 300000000>, 2258 <0 0>, 2259 <0 0>, 2260 <0 0>, 2261 <0 0>; 2262 status = "disabled"; 2263 }; 2264 2265 ufs_mem_phy: phy@1d87000 { 2266 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2267 reg = <0 0x01d87000 0 0x1000>; 2268 2269 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2270 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2271 clock-names = "ref", "ref_aux"; 2272 2273 power-domains = <&gcc UFS_PHY_GDSC>; 2274 2275 resets = <&ufs_mem_hc 0>; 2276 reset-names = "ufsphy"; 2277 2278 #phy-cells = <0>; 2279 2280 status = "disabled"; 2281 }; 2282 2283 ufs_card_hc: ufs@1da4000 { 2284 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2285 "jedec,ufs-2.0"; 2286 reg = <0 0x01da4000 0 0x3000>; 2287 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2288 phys = <&ufs_card_phy>; 2289 phy-names = "ufsphy"; 2290 lanes-per-direction = <2>; 2291 #reset-cells = <1>; 2292 resets = <&gcc GCC_UFS_CARD_BCR>; 2293 reset-names = "rst"; 2294 2295 power-domains = <&gcc UFS_CARD_GDSC>; 2296 2297 iommus = <&apps_smmu 0x4a0 0x0>; 2298 dma-coherent; 2299 2300 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2301 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2302 <&gcc GCC_UFS_CARD_AHB_CLK>, 2303 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2304 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2305 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2306 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2307 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2308 clock-names = "core_clk", 2309 "bus_aggr_clk", 2310 "iface_clk", 2311 "core_clk_unipro", 2312 "ref_clk", 2313 "tx_lane0_sync_clk", 2314 "rx_lane0_sync_clk", 2315 "rx_lane1_sync_clk"; 2316 freq-table-hz = <75000000 300000000>, 2317 <0 0>, 2318 <0 0>, 2319 <75000000 300000000>, 2320 <0 0>, 2321 <0 0>, 2322 <0 0>, 2323 <0 0>; 2324 status = "disabled"; 2325 }; 2326 2327 ufs_card_phy: phy@1da7000 { 2328 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2329 reg = <0 0x01da7000 0 0x1000>; 2330 2331 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2332 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2333 clock-names = "ref", "ref_aux"; 2334 2335 power-domains = <&gcc UFS_CARD_GDSC>; 2336 2337 resets = <&ufs_card_hc 0>; 2338 reset-names = "ufsphy"; 2339 2340 #phy-cells = <0>; 2341 2342 status = "disabled"; 2343 }; 2344 2345 tcsr_mutex: hwlock@1f40000 { 2346 compatible = "qcom,tcsr-mutex"; 2347 reg = <0x0 0x01f40000 0x0 0x20000>; 2348 #hwlock-cells = <1>; 2349 }; 2350 2351 tcsr: syscon@1fc0000 { 2352 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2353 reg = <0x0 0x01fc0000 0x0 0x30000>; 2354 }; 2355 2356 gpu: gpu@3d00000 { 2357 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2358 2359 reg = <0 0x03d00000 0 0x40000>, 2360 <0 0x03d9e000 0 0x1000>, 2361 <0 0x03d61000 0 0x800>; 2362 reg-names = "kgsl_3d0_reg_memory", 2363 "cx_mem", 2364 "cx_dbgc"; 2365 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2366 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2367 operating-points-v2 = <&gpu_opp_table>; 2368 2369 qcom,gmu = <&gmu>; 2370 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2371 interconnect-names = "gfx-mem"; 2372 #cooling-cells = <2>; 2373 2374 status = "disabled"; 2375 2376 gpu_opp_table: opp-table { 2377 compatible = "operating-points-v2"; 2378 2379 opp-270000000 { 2380 opp-hz = /bits/ 64 <270000000>; 2381 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2382 opp-peak-kBps = <451000>; 2383 }; 2384 2385 opp-410000000 { 2386 opp-hz = /bits/ 64 <410000000>; 2387 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2388 opp-peak-kBps = <1555000>; 2389 }; 2390 2391 opp-500000000 { 2392 opp-hz = /bits/ 64 <500000000>; 2393 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2394 opp-peak-kBps = <1555000>; 2395 }; 2396 2397 opp-547000000 { 2398 opp-hz = /bits/ 64 <547000000>; 2399 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2400 opp-peak-kBps = <1555000>; 2401 }; 2402 2403 opp-606000000 { 2404 opp-hz = /bits/ 64 <606000000>; 2405 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2406 opp-peak-kBps = <2736000>; 2407 }; 2408 2409 opp-640000000 { 2410 opp-hz = /bits/ 64 <640000000>; 2411 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2412 opp-peak-kBps = <2736000>; 2413 }; 2414 2415 opp-655000000 { 2416 opp-hz = /bits/ 64 <655000000>; 2417 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2418 opp-peak-kBps = <2736000>; 2419 }; 2420 2421 opp-690000000 { 2422 opp-hz = /bits/ 64 <690000000>; 2423 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2424 opp-peak-kBps = <2736000>; 2425 }; 2426 }; 2427 }; 2428 2429 gmu: gmu@3d6a000 { 2430 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2431 reg = <0 0x03d6a000 0 0x34000>, 2432 <0 0x03de0000 0 0x10000>, 2433 <0 0x0b290000 0 0x10000>; 2434 reg-names = "gmu", "rscc", "gmu_pdc"; 2435 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2437 interrupt-names = "hfi", "gmu"; 2438 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2439 <&gpucc GPU_CC_CXO_CLK>, 2440 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2441 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2442 <&gpucc GPU_CC_AHB_CLK>, 2443 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2444 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2445 clock-names = "gmu", 2446 "cxo", 2447 "axi", 2448 "memnoc", 2449 "ahb", 2450 "hub", 2451 "smmu_vote"; 2452 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2453 <&gpucc GPU_CC_GX_GDSC>; 2454 power-domain-names = "cx", 2455 "gx"; 2456 iommus = <&gpu_smmu 5 0xc00>; 2457 operating-points-v2 = <&gmu_opp_table>; 2458 2459 gmu_opp_table: opp-table { 2460 compatible = "operating-points-v2"; 2461 2462 opp-200000000 { 2463 opp-hz = /bits/ 64 <200000000>; 2464 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2465 }; 2466 2467 opp-500000000 { 2468 opp-hz = /bits/ 64 <500000000>; 2469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2470 }; 2471 }; 2472 }; 2473 2474 gpucc: clock-controller@3d90000 { 2475 compatible = "qcom,sc8280xp-gpucc"; 2476 reg = <0 0x03d90000 0 0x9000>; 2477 clocks = <&rpmhcc RPMH_CXO_CLK>, 2478 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2479 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2480 clock-names = "bi_tcxo", 2481 "gcc_gpu_gpll0_clk_src", 2482 "gcc_gpu_gpll0_div_clk_src"; 2483 2484 power-domains = <&rpmhpd SC8280XP_GFX>; 2485 #clock-cells = <1>; 2486 #reset-cells = <1>; 2487 #power-domain-cells = <1>; 2488 }; 2489 2490 gpu_smmu: iommu@3da0000 { 2491 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2492 "qcom,smmu-500", "arm,mmu-500"; 2493 reg = <0 0x03da0000 0 0x20000>; 2494 #iommu-cells = <2>; 2495 #global-interrupts = <2>; 2496 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2510 2511 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2512 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2513 <&gpucc GPU_CC_AHB_CLK>, 2514 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2515 <&gpucc GPU_CC_CX_GMU_CLK>, 2516 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2517 <&gpucc GPU_CC_HUB_AON_CLK>; 2518 clock-names = "gcc_gpu_memnoc_gfx_clk", 2519 "gcc_gpu_snoc_dvm_gfx_clk", 2520 "gpu_cc_ahb_clk", 2521 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2522 "gpu_cc_cx_gmu_clk", 2523 "gpu_cc_hub_cx_int_clk", 2524 "gpu_cc_hub_aon_clk"; 2525 2526 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2527 dma-coherent; 2528 }; 2529 2530 usb_0_hsphy: phy@88e5000 { 2531 compatible = "qcom,sc8280xp-usb-hs-phy", 2532 "qcom,usb-snps-hs-5nm-phy"; 2533 reg = <0 0x088e5000 0 0x400>; 2534 clocks = <&rpmhcc RPMH_CXO_CLK>; 2535 clock-names = "ref"; 2536 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2537 2538 #phy-cells = <0>; 2539 2540 status = "disabled"; 2541 }; 2542 2543 usb_2_hsphy0: phy@88e7000 { 2544 compatible = "qcom,sc8280xp-usb-hs-phy", 2545 "qcom,usb-snps-hs-5nm-phy"; 2546 reg = <0 0x088e7000 0 0x400>; 2547 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2548 clock-names = "ref"; 2549 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2550 2551 #phy-cells = <0>; 2552 2553 status = "disabled"; 2554 }; 2555 2556 usb_2_hsphy1: phy@88e8000 { 2557 compatible = "qcom,sc8280xp-usb-hs-phy", 2558 "qcom,usb-snps-hs-5nm-phy"; 2559 reg = <0 0x088e8000 0 0x400>; 2560 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2561 clock-names = "ref"; 2562 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2563 2564 #phy-cells = <0>; 2565 2566 status = "disabled"; 2567 }; 2568 2569 usb_2_hsphy2: phy@88e9000 { 2570 compatible = "qcom,sc8280xp-usb-hs-phy", 2571 "qcom,usb-snps-hs-5nm-phy"; 2572 reg = <0 0x088e9000 0 0x400>; 2573 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2574 clock-names = "ref"; 2575 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2576 2577 #phy-cells = <0>; 2578 2579 status = "disabled"; 2580 }; 2581 2582 usb_2_hsphy3: phy@88ea000 { 2583 compatible = "qcom,sc8280xp-usb-hs-phy", 2584 "qcom,usb-snps-hs-5nm-phy"; 2585 reg = <0 0x088ea000 0 0x400>; 2586 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2587 clock-names = "ref"; 2588 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2589 2590 #phy-cells = <0>; 2591 2592 status = "disabled"; 2593 }; 2594 2595 usb_2_qmpphy0: phy@88ef000 { 2596 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2597 reg = <0 0x088ef000 0 0x2000>; 2598 2599 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2600 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2601 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2602 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2603 clock-names = "aux", "ref", "com_aux", "pipe"; 2604 2605 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2606 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2607 reset-names = "phy", "phy_phy"; 2608 2609 power-domains = <&gcc USB30_MP_GDSC>; 2610 2611 #clock-cells = <0>; 2612 clock-output-names = "usb2_phy0_pipe_clk"; 2613 2614 #phy-cells = <0>; 2615 2616 status = "disabled"; 2617 }; 2618 2619 usb_2_qmpphy1: phy@88f1000 { 2620 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2621 reg = <0 0x088f1000 0 0x2000>; 2622 2623 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2624 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2625 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2626 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2627 clock-names = "aux", "ref", "com_aux", "pipe"; 2628 2629 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2630 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2631 reset-names = "phy", "phy_phy"; 2632 2633 power-domains = <&gcc USB30_MP_GDSC>; 2634 2635 #clock-cells = <0>; 2636 clock-output-names = "usb2_phy1_pipe_clk"; 2637 2638 #phy-cells = <0>; 2639 2640 status = "disabled"; 2641 }; 2642 2643 remoteproc_adsp: remoteproc@3000000 { 2644 compatible = "qcom,sc8280xp-adsp-pas"; 2645 reg = <0 0x03000000 0 0x100>; 2646 2647 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2648 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2649 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2650 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2651 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2652 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2653 interrupt-names = "wdog", "fatal", "ready", 2654 "handover", "stop-ack", "shutdown-ack"; 2655 2656 clocks = <&rpmhcc RPMH_CXO_CLK>; 2657 clock-names = "xo"; 2658 2659 power-domains = <&rpmhpd SC8280XP_LCX>, 2660 <&rpmhpd SC8280XP_LMX>; 2661 power-domain-names = "lcx", "lmx"; 2662 2663 memory-region = <&pil_adsp_mem>; 2664 2665 qcom,qmp = <&aoss_qmp>; 2666 2667 qcom,smem-states = <&smp2p_adsp_out 0>; 2668 qcom,smem-state-names = "stop"; 2669 2670 status = "disabled"; 2671 2672 remoteproc_adsp_glink: glink-edge { 2673 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2674 IPCC_MPROC_SIGNAL_GLINK_QMP 2675 IRQ_TYPE_EDGE_RISING>; 2676 mboxes = <&ipcc IPCC_CLIENT_LPASS 2677 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2678 2679 label = "lpass"; 2680 qcom,remote-pid = <2>; 2681 2682 gpr { 2683 compatible = "qcom,gpr"; 2684 qcom,glink-channels = "adsp_apps"; 2685 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2686 qcom,intents = <512 20>; 2687 #address-cells = <1>; 2688 #size-cells = <0>; 2689 2690 q6apm: service@1 { 2691 compatible = "qcom,q6apm"; 2692 reg = <GPR_APM_MODULE_IID>; 2693 #sound-dai-cells = <0>; 2694 qcom,protection-domain = "avs/audio", 2695 "msm/adsp/audio_pd"; 2696 q6apmdai: dais { 2697 compatible = "qcom,q6apm-dais"; 2698 iommus = <&apps_smmu 0x0c01 0x0>; 2699 }; 2700 2701 q6apmbedai: bedais { 2702 compatible = "qcom,q6apm-lpass-dais"; 2703 #sound-dai-cells = <1>; 2704 }; 2705 }; 2706 2707 q6prm: service@2 { 2708 compatible = "qcom,q6prm"; 2709 reg = <GPR_PRM_MODULE_IID>; 2710 qcom,protection-domain = "avs/audio", 2711 "msm/adsp/audio_pd"; 2712 q6prmcc: clock-controller { 2713 compatible = "qcom,q6prm-lpass-clocks"; 2714 #clock-cells = <2>; 2715 }; 2716 }; 2717 }; 2718 }; 2719 }; 2720 2721 rxmacro: rxmacro@3200000 { 2722 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2723 reg = <0 0x03200000 0 0x1000>; 2724 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2725 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2726 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2727 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2728 <&vamacro>; 2729 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2730 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2731 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2732 assigned-clock-rates = <19200000>, <19200000>; 2733 2734 clock-output-names = "mclk"; 2735 #clock-cells = <0>; 2736 #sound-dai-cells = <1>; 2737 2738 pinctrl-names = "default"; 2739 pinctrl-0 = <&rx_swr_default>; 2740 2741 status = "disabled"; 2742 }; 2743 2744 swr1: soundwire-controller@3210000 { 2745 compatible = "qcom,soundwire-v1.6.0"; 2746 reg = <0 0x03210000 0 0x2000>; 2747 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2748 clocks = <&rxmacro>; 2749 clock-names = "iface"; 2750 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2751 reset-names = "swr_audio_cgcr"; 2752 label = "RX"; 2753 2754 qcom,din-ports = <0>; 2755 qcom,dout-ports = <5>; 2756 2757 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2758 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2759 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2760 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2761 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2762 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2763 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2764 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2765 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2766 2767 #sound-dai-cells = <1>; 2768 #address-cells = <2>; 2769 #size-cells = <0>; 2770 2771 status = "disabled"; 2772 }; 2773 2774 txmacro: txmacro@3220000 { 2775 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2776 reg = <0 0x03220000 0 0x1000>; 2777 pinctrl-names = "default"; 2778 pinctrl-0 = <&tx_swr_default>; 2779 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2780 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2781 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2782 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2783 <&vamacro>; 2784 2785 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2786 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2787 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2788 assigned-clock-rates = <19200000>, <19200000>; 2789 clock-output-names = "mclk"; 2790 2791 #clock-cells = <0>; 2792 #sound-dai-cells = <1>; 2793 2794 status = "disabled"; 2795 }; 2796 2797 wsamacro: codec@3240000 { 2798 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2799 reg = <0 0x03240000 0 0x1000>; 2800 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2801 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2802 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2803 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2804 <&vamacro>; 2805 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2806 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2807 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2808 assigned-clock-rates = <19200000>, <19200000>; 2809 2810 #clock-cells = <0>; 2811 clock-output-names = "mclk"; 2812 #sound-dai-cells = <1>; 2813 2814 pinctrl-names = "default"; 2815 pinctrl-0 = <&wsa_swr_default>; 2816 2817 status = "disabled"; 2818 }; 2819 2820 swr0: soundwire-controller@3250000 { 2821 reg = <0 0x03250000 0 0x2000>; 2822 compatible = "qcom,soundwire-v1.6.0"; 2823 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2824 clocks = <&wsamacro>; 2825 clock-names = "iface"; 2826 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2827 reset-names = "swr_audio_cgcr"; 2828 label = "WSA"; 2829 2830 qcom,din-ports = <2>; 2831 qcom,dout-ports = <6>; 2832 2833 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2834 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2835 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2836 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2837 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2838 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2839 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2840 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2841 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2842 2843 #sound-dai-cells = <1>; 2844 #address-cells = <2>; 2845 #size-cells = <0>; 2846 2847 status = "disabled"; 2848 }; 2849 2850 lpass_audiocc: clock-controller@32a9000 { 2851 compatible = "qcom,sc8280xp-lpassaudiocc"; 2852 reg = <0 0x032a9000 0 0x1000>; 2853 #clock-cells = <1>; 2854 #reset-cells = <1>; 2855 }; 2856 2857 swr2: soundwire-controller@3330000 { 2858 compatible = "qcom,soundwire-v1.6.0"; 2859 reg = <0 0x03330000 0 0x2000>; 2860 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2861 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2862 interrupt-names = "core", "wakeup"; 2863 2864 clocks = <&txmacro>; 2865 clock-names = "iface"; 2866 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2867 reset-names = "swr_audio_cgcr"; 2868 label = "TX"; 2869 #sound-dai-cells = <1>; 2870 #address-cells = <2>; 2871 #size-cells = <0>; 2872 2873 qcom,din-ports = <4>; 2874 qcom,dout-ports = <0>; 2875 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2876 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2877 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2878 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2879 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2880 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2881 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2882 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2883 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2884 2885 status = "disabled"; 2886 }; 2887 2888 vamacro: codec@3370000 { 2889 compatible = "qcom,sc8280xp-lpass-va-macro"; 2890 reg = <0 0x03370000 0 0x1000>; 2891 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2892 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2893 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2894 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2895 clock-names = "mclk", "macro", "dcodec", "npl"; 2896 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2897 assigned-clock-rates = <19200000>; 2898 2899 #clock-cells = <0>; 2900 clock-output-names = "fsgen"; 2901 #sound-dai-cells = <1>; 2902 2903 status = "disabled"; 2904 }; 2905 2906 lpass_tlmm: pinctrl@33c0000 { 2907 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2908 reg = <0 0x33c0000 0x0 0x20000>, 2909 <0 0x3550000 0x0 0x10000>; 2910 gpio-controller; 2911 #gpio-cells = <2>; 2912 gpio-ranges = <&lpass_tlmm 0 0 19>; 2913 2914 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2915 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2916 clock-names = "core", "audio"; 2917 2918 status = "disabled"; 2919 2920 tx_swr_default: tx-swr-default-state { 2921 clk-pins { 2922 pins = "gpio0"; 2923 function = "swr_tx_clk"; 2924 drive-strength = <2>; 2925 slew-rate = <1>; 2926 bias-disable; 2927 }; 2928 2929 data-pins { 2930 pins = "gpio1", "gpio2"; 2931 function = "swr_tx_data"; 2932 drive-strength = <2>; 2933 slew-rate = <1>; 2934 bias-bus-hold; 2935 }; 2936 }; 2937 2938 rx_swr_default: rx-swr-default-state { 2939 clk-pins { 2940 pins = "gpio3"; 2941 function = "swr_rx_clk"; 2942 drive-strength = <2>; 2943 slew-rate = <1>; 2944 bias-disable; 2945 }; 2946 2947 data-pins { 2948 pins = "gpio4", "gpio5"; 2949 function = "swr_rx_data"; 2950 drive-strength = <2>; 2951 slew-rate = <1>; 2952 bias-bus-hold; 2953 }; 2954 }; 2955 2956 dmic01_default: dmic01-default-state { 2957 clk-pins { 2958 pins = "gpio6"; 2959 function = "dmic1_clk"; 2960 drive-strength = <8>; 2961 output-high; 2962 }; 2963 2964 data-pins { 2965 pins = "gpio7"; 2966 function = "dmic1_data"; 2967 drive-strength = <8>; 2968 input-enable; 2969 }; 2970 }; 2971 2972 dmic01_sleep: dmic01-sleep-state { 2973 clk-pins { 2974 pins = "gpio6"; 2975 function = "dmic1_clk"; 2976 drive-strength = <2>; 2977 bias-disable; 2978 output-low; 2979 }; 2980 2981 data-pins { 2982 pins = "gpio7"; 2983 function = "dmic1_data"; 2984 drive-strength = <2>; 2985 bias-pull-down; 2986 input-enable; 2987 }; 2988 }; 2989 2990 dmic02_default: dmic02-default-state { 2991 clk-pins { 2992 pins = "gpio8"; 2993 function = "dmic2_clk"; 2994 drive-strength = <8>; 2995 output-high; 2996 }; 2997 2998 data-pins { 2999 pins = "gpio9"; 3000 function = "dmic2_data"; 3001 drive-strength = <8>; 3002 input-enable; 3003 }; 3004 }; 3005 3006 dmic02_sleep: dmic02-sleep-state { 3007 clk-pins { 3008 pins = "gpio8"; 3009 function = "dmic2_clk"; 3010 drive-strength = <2>; 3011 bias-disable; 3012 output-low; 3013 }; 3014 3015 data-pins { 3016 pins = "gpio9"; 3017 function = "dmic2_data"; 3018 drive-strength = <2>; 3019 bias-pull-down; 3020 input-enable; 3021 }; 3022 }; 3023 3024 wsa_swr_default: wsa-swr-default-state { 3025 clk-pins { 3026 pins = "gpio10"; 3027 function = "wsa_swr_clk"; 3028 drive-strength = <2>; 3029 slew-rate = <1>; 3030 bias-disable; 3031 }; 3032 3033 data-pins { 3034 pins = "gpio11"; 3035 function = "wsa_swr_data"; 3036 drive-strength = <2>; 3037 slew-rate = <1>; 3038 bias-bus-hold; 3039 }; 3040 }; 3041 3042 wsa2_swr_default: wsa2-swr-default-state { 3043 clk-pins { 3044 pins = "gpio15"; 3045 function = "wsa2_swr_clk"; 3046 drive-strength = <2>; 3047 slew-rate = <1>; 3048 bias-disable; 3049 }; 3050 3051 data-pins { 3052 pins = "gpio16"; 3053 function = "wsa2_swr_data"; 3054 drive-strength = <2>; 3055 slew-rate = <1>; 3056 bias-bus-hold; 3057 }; 3058 }; 3059 }; 3060 3061 lpasscc: clock-controller@33e0000 { 3062 compatible = "qcom,sc8280xp-lpasscc"; 3063 reg = <0 0x033e0000 0 0x12000>; 3064 #clock-cells = <1>; 3065 #reset-cells = <1>; 3066 }; 3067 3068 sdc2: mmc@8804000 { 3069 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3070 reg = <0 0x08804000 0 0x1000>; 3071 3072 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3074 interrupt-names = "hc_irq", "pwr_irq"; 3075 3076 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3077 <&gcc GCC_SDCC2_APPS_CLK>, 3078 <&rpmhcc RPMH_CXO_CLK>; 3079 clock-names = "iface", "core", "xo"; 3080 resets = <&gcc GCC_SDCC2_BCR>; 3081 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3082 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3083 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3084 iommus = <&apps_smmu 0x4e0 0x0>; 3085 power-domains = <&rpmhpd SC8280XP_CX>; 3086 operating-points-v2 = <&sdc2_opp_table>; 3087 bus-width = <4>; 3088 dma-coherent; 3089 3090 status = "disabled"; 3091 3092 sdc2_opp_table: opp-table { 3093 compatible = "operating-points-v2"; 3094 3095 opp-100000000 { 3096 opp-hz = /bits/ 64 <100000000>; 3097 required-opps = <&rpmhpd_opp_low_svs>; 3098 opp-peak-kBps = <1800000 400000>; 3099 opp-avg-kBps = <100000 0>; 3100 }; 3101 3102 opp-202000000 { 3103 opp-hz = /bits/ 64 <202000000>; 3104 required-opps = <&rpmhpd_opp_svs_l1>; 3105 opp-peak-kBps = <5400000 1600000>; 3106 opp-avg-kBps = <200000 0>; 3107 }; 3108 }; 3109 }; 3110 3111 usb_0_qmpphy: phy@88eb000 { 3112 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3113 reg = <0 0x088eb000 0 0x4000>; 3114 3115 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3116 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3117 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3118 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3119 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3120 3121 power-domains = <&gcc USB30_PRIM_GDSC>; 3122 3123 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3124 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3125 reset-names = "phy", "common"; 3126 3127 #clock-cells = <1>; 3128 #phy-cells = <1>; 3129 3130 status = "disabled"; 3131 3132 ports { 3133 #address-cells = <1>; 3134 #size-cells = <0>; 3135 3136 port@0 { 3137 reg = <0>; 3138 3139 usb_0_qmpphy_out: endpoint {}; 3140 }; 3141 3142 port@2 { 3143 reg = <2>; 3144 3145 usb_0_qmpphy_dp_in: endpoint {}; 3146 }; 3147 }; 3148 }; 3149 3150 usb_1_hsphy: phy@8902000 { 3151 compatible = "qcom,sc8280xp-usb-hs-phy", 3152 "qcom,usb-snps-hs-5nm-phy"; 3153 reg = <0 0x08902000 0 0x400>; 3154 #phy-cells = <0>; 3155 3156 clocks = <&rpmhcc RPMH_CXO_CLK>; 3157 clock-names = "ref"; 3158 3159 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3160 3161 status = "disabled"; 3162 }; 3163 3164 usb_1_qmpphy: phy@8903000 { 3165 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3166 reg = <0 0x08903000 0 0x4000>; 3167 3168 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3169 <&gcc GCC_USB4_CLKREF_CLK>, 3170 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3171 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3172 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3173 3174 power-domains = <&gcc USB30_SEC_GDSC>; 3175 3176 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3177 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3178 reset-names = "phy", "common"; 3179 3180 #clock-cells = <1>; 3181 #phy-cells = <1>; 3182 3183 status = "disabled"; 3184 3185 ports { 3186 #address-cells = <1>; 3187 #size-cells = <0>; 3188 3189 port@0 { 3190 reg = <0>; 3191 3192 usb_1_qmpphy_out: endpoint {}; 3193 }; 3194 3195 port@2 { 3196 reg = <2>; 3197 3198 usb_1_qmpphy_dp_in: endpoint {}; 3199 }; 3200 }; 3201 }; 3202 3203 mdss1_dp0_phy: phy@8909a00 { 3204 compatible = "qcom,sc8280xp-dp-phy"; 3205 reg = <0 0x08909a00 0 0x19c>, 3206 <0 0x08909200 0 0xec>, 3207 <0 0x08909600 0 0xec>, 3208 <0 0x08909000 0 0x1c8>; 3209 3210 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3211 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3212 clock-names = "aux", "cfg_ahb"; 3213 power-domains = <&rpmhpd SC8280XP_MX>; 3214 3215 #clock-cells = <1>; 3216 #phy-cells = <0>; 3217 3218 status = "disabled"; 3219 }; 3220 3221 mdss1_dp1_phy: phy@890ca00 { 3222 compatible = "qcom,sc8280xp-dp-phy"; 3223 reg = <0 0x0890ca00 0 0x19c>, 3224 <0 0x0890c200 0 0xec>, 3225 <0 0x0890c600 0 0xec>, 3226 <0 0x0890c000 0 0x1c8>; 3227 3228 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3229 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3230 clock-names = "aux", "cfg_ahb"; 3231 power-domains = <&rpmhpd SC8280XP_MX>; 3232 3233 #clock-cells = <1>; 3234 #phy-cells = <0>; 3235 3236 status = "disabled"; 3237 }; 3238 3239 pmu@9091000 { 3240 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3241 reg = <0 0x09091000 0 0x1000>; 3242 3243 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3244 3245 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3246 3247 operating-points-v2 = <&llcc_bwmon_opp_table>; 3248 3249 llcc_bwmon_opp_table: opp-table { 3250 compatible = "operating-points-v2"; 3251 3252 opp-0 { 3253 opp-peak-kBps = <762000>; 3254 }; 3255 opp-1 { 3256 opp-peak-kBps = <1720000>; 3257 }; 3258 opp-2 { 3259 opp-peak-kBps = <2086000>; 3260 }; 3261 opp-3 { 3262 opp-peak-kBps = <2597000>; 3263 }; 3264 opp-4 { 3265 opp-peak-kBps = <2929000>; 3266 }; 3267 opp-5 { 3268 opp-peak-kBps = <3879000>; 3269 }; 3270 opp-6 { 3271 opp-peak-kBps = <5161000>; 3272 }; 3273 opp-7 { 3274 opp-peak-kBps = <5931000>; 3275 }; 3276 opp-8 { 3277 opp-peak-kBps = <6515000>; 3278 }; 3279 opp-9 { 3280 opp-peak-kBps = <7980000>; 3281 }; 3282 opp-10 { 3283 opp-peak-kBps = <8136000>; 3284 }; 3285 opp-11 { 3286 opp-peak-kBps = <10437000>; 3287 }; 3288 opp-12 { 3289 opp-peak-kBps = <12191000>; 3290 }; 3291 }; 3292 }; 3293 3294 pmu@90b6400 { 3295 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3296 reg = <0 0x090b6400 0 0x600>; 3297 3298 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3299 3300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3301 operating-points-v2 = <&cpu_bwmon_opp_table>; 3302 3303 cpu_bwmon_opp_table: opp-table { 3304 compatible = "operating-points-v2"; 3305 3306 opp-0 { 3307 opp-peak-kBps = <2288000>; 3308 }; 3309 opp-1 { 3310 opp-peak-kBps = <4577000>; 3311 }; 3312 opp-2 { 3313 opp-peak-kBps = <7110000>; 3314 }; 3315 opp-3 { 3316 opp-peak-kBps = <9155000>; 3317 }; 3318 opp-4 { 3319 opp-peak-kBps = <12298000>; 3320 }; 3321 opp-5 { 3322 opp-peak-kBps = <14236000>; 3323 }; 3324 opp-6 { 3325 opp-peak-kBps = <15258001>; 3326 }; 3327 }; 3328 }; 3329 3330 system-cache-controller@9200000 { 3331 compatible = "qcom,sc8280xp-llcc"; 3332 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3333 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3334 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3335 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3336 <0 0x09600000 0 0x58000>; 3337 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3338 "llcc3_base", "llcc4_base", "llcc5_base", 3339 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3340 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3341 }; 3342 3343 usb_0: usb@a6f8800 { 3344 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3345 reg = <0 0x0a6f8800 0 0x400>; 3346 #address-cells = <2>; 3347 #size-cells = <2>; 3348 ranges; 3349 3350 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3351 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3352 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3353 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3354 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3355 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3356 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3357 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3358 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3359 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3360 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3361 3362 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3363 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3364 assigned-clock-rates = <19200000>, <200000000>; 3365 3366 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3367 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3368 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3369 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3370 interrupt-names = "pwr_event", 3371 "dp_hs_phy_irq", 3372 "dm_hs_phy_irq", 3373 "ss_phy_irq"; 3374 3375 power-domains = <&gcc USB30_PRIM_GDSC>; 3376 required-opps = <&rpmhpd_opp_nom>; 3377 3378 resets = <&gcc GCC_USB30_PRIM_BCR>; 3379 3380 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3381 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3382 interconnect-names = "usb-ddr", "apps-usb"; 3383 3384 wakeup-source; 3385 3386 status = "disabled"; 3387 3388 usb_0_dwc3: usb@a600000 { 3389 compatible = "snps,dwc3"; 3390 reg = <0 0x0a600000 0 0xcd00>; 3391 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3392 iommus = <&apps_smmu 0x820 0x0>; 3393 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3394 phy-names = "usb2-phy", "usb3-phy"; 3395 3396 port { 3397 usb_0_role_switch: endpoint { 3398 }; 3399 }; 3400 }; 3401 }; 3402 3403 usb_1: usb@a8f8800 { 3404 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3405 reg = <0 0x0a8f8800 0 0x400>; 3406 #address-cells = <2>; 3407 #size-cells = <2>; 3408 ranges; 3409 3410 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3411 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3412 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3413 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3414 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3415 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3416 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3417 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3418 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3419 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3420 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3421 3422 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3423 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3424 assigned-clock-rates = <19200000>, <200000000>; 3425 3426 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3427 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3428 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3429 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3430 interrupt-names = "pwr_event", 3431 "dp_hs_phy_irq", 3432 "dm_hs_phy_irq", 3433 "ss_phy_irq"; 3434 3435 power-domains = <&gcc USB30_SEC_GDSC>; 3436 required-opps = <&rpmhpd_opp_nom>; 3437 3438 resets = <&gcc GCC_USB30_SEC_BCR>; 3439 3440 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3441 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3442 interconnect-names = "usb-ddr", "apps-usb"; 3443 3444 wakeup-source; 3445 3446 status = "disabled"; 3447 3448 usb_1_dwc3: usb@a800000 { 3449 compatible = "snps,dwc3"; 3450 reg = <0 0x0a800000 0 0xcd00>; 3451 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3452 iommus = <&apps_smmu 0x860 0x0>; 3453 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3454 phy-names = "usb2-phy", "usb3-phy"; 3455 3456 port { 3457 usb_1_role_switch: endpoint { 3458 }; 3459 }; 3460 }; 3461 }; 3462 3463 mdss0: display-subsystem@ae00000 { 3464 compatible = "qcom,sc8280xp-mdss"; 3465 reg = <0 0x0ae00000 0 0x1000>; 3466 reg-names = "mdss"; 3467 3468 clocks = <&gcc GCC_DISP_AHB_CLK>, 3469 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3470 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3471 clock-names = "iface", 3472 "ahb", 3473 "core"; 3474 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3475 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3476 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3477 interconnect-names = "mdp0-mem", "mdp1-mem"; 3478 iommus = <&apps_smmu 0x1000 0x402>; 3479 power-domains = <&dispcc0 MDSS_GDSC>; 3480 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3481 3482 interrupt-controller; 3483 #interrupt-cells = <1>; 3484 #address-cells = <2>; 3485 #size-cells = <2>; 3486 ranges; 3487 3488 status = "disabled"; 3489 3490 mdss0_mdp: display-controller@ae01000 { 3491 compatible = "qcom,sc8280xp-dpu"; 3492 reg = <0 0x0ae01000 0 0x8f000>, 3493 <0 0x0aeb0000 0 0x2008>; 3494 reg-names = "mdp", "vbif"; 3495 3496 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3497 <&gcc GCC_DISP_SF_AXI_CLK>, 3498 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3499 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3500 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3501 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3502 clock-names = "bus", 3503 "nrt_bus", 3504 "iface", 3505 "lut", 3506 "core", 3507 "vsync"; 3508 interrupt-parent = <&mdss0>; 3509 interrupts = <0>; 3510 power-domains = <&rpmhpd SC8280XP_MMCX>; 3511 3512 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3513 assigned-clock-rates = <19200000>; 3514 operating-points-v2 = <&mdss0_mdp_opp_table>; 3515 3516 ports { 3517 #address-cells = <1>; 3518 #size-cells = <0>; 3519 3520 port@0 { 3521 reg = <0>; 3522 mdss0_intf0_out: endpoint { 3523 remote-endpoint = <&mdss0_dp0_in>; 3524 }; 3525 }; 3526 3527 port@4 { 3528 reg = <4>; 3529 mdss0_intf4_out: endpoint { 3530 remote-endpoint = <&mdss0_dp1_in>; 3531 }; 3532 }; 3533 3534 port@5 { 3535 reg = <5>; 3536 mdss0_intf5_out: endpoint { 3537 remote-endpoint = <&mdss0_dp3_in>; 3538 }; 3539 }; 3540 3541 port@6 { 3542 reg = <6>; 3543 mdss0_intf6_out: endpoint { 3544 remote-endpoint = <&mdss0_dp2_in>; 3545 }; 3546 }; 3547 }; 3548 3549 mdss0_mdp_opp_table: opp-table { 3550 compatible = "operating-points-v2"; 3551 3552 opp-200000000 { 3553 opp-hz = /bits/ 64 <200000000>; 3554 required-opps = <&rpmhpd_opp_low_svs>; 3555 }; 3556 3557 opp-300000000 { 3558 opp-hz = /bits/ 64 <300000000>; 3559 required-opps = <&rpmhpd_opp_svs>; 3560 }; 3561 3562 opp-375000000 { 3563 opp-hz = /bits/ 64 <375000000>; 3564 required-opps = <&rpmhpd_opp_svs_l1>; 3565 }; 3566 3567 opp-500000000 { 3568 opp-hz = /bits/ 64 <500000000>; 3569 required-opps = <&rpmhpd_opp_nom>; 3570 }; 3571 opp-600000000 { 3572 opp-hz = /bits/ 64 <600000000>; 3573 required-opps = <&rpmhpd_opp_turbo_l1>; 3574 }; 3575 }; 3576 }; 3577 3578 mdss0_dp0: displayport-controller@ae90000 { 3579 compatible = "qcom,sc8280xp-dp"; 3580 reg = <0 0xae90000 0 0x200>, 3581 <0 0xae90200 0 0x200>, 3582 <0 0xae90400 0 0x600>, 3583 <0 0xae91000 0 0x400>, 3584 <0 0xae91400 0 0x400>; 3585 interrupt-parent = <&mdss0>; 3586 interrupts = <12>; 3587 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3588 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3589 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3590 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3591 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3592 clock-names = "core_iface", "core_aux", 3593 "ctrl_link", 3594 "ctrl_link_iface", 3595 "stream_pixel"; 3596 3597 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3598 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3599 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3600 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3601 3602 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3603 phy-names = "dp"; 3604 3605 #sound-dai-cells = <0>; 3606 3607 operating-points-v2 = <&mdss0_dp0_opp_table>; 3608 power-domains = <&rpmhpd SC8280XP_MMCX>; 3609 3610 status = "disabled"; 3611 3612 ports { 3613 #address-cells = <1>; 3614 #size-cells = <0>; 3615 3616 port@0 { 3617 reg = <0>; 3618 3619 mdss0_dp0_in: endpoint { 3620 remote-endpoint = <&mdss0_intf0_out>; 3621 }; 3622 }; 3623 3624 port@1 { 3625 reg = <1>; 3626 3627 mdss0_dp0_out: endpoint { 3628 }; 3629 }; 3630 }; 3631 3632 mdss0_dp0_opp_table: opp-table { 3633 compatible = "operating-points-v2"; 3634 3635 opp-160000000 { 3636 opp-hz = /bits/ 64 <160000000>; 3637 required-opps = <&rpmhpd_opp_low_svs>; 3638 }; 3639 3640 opp-270000000 { 3641 opp-hz = /bits/ 64 <270000000>; 3642 required-opps = <&rpmhpd_opp_svs>; 3643 }; 3644 3645 opp-540000000 { 3646 opp-hz = /bits/ 64 <540000000>; 3647 required-opps = <&rpmhpd_opp_svs_l1>; 3648 }; 3649 3650 opp-810000000 { 3651 opp-hz = /bits/ 64 <810000000>; 3652 required-opps = <&rpmhpd_opp_nom>; 3653 }; 3654 }; 3655 }; 3656 3657 mdss0_dp1: displayport-controller@ae98000 { 3658 compatible = "qcom,sc8280xp-dp"; 3659 reg = <0 0xae98000 0 0x200>, 3660 <0 0xae98200 0 0x200>, 3661 <0 0xae98400 0 0x600>, 3662 <0 0xae99000 0 0x400>, 3663 <0 0xae99400 0 0x400>; 3664 interrupt-parent = <&mdss0>; 3665 interrupts = <13>; 3666 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3667 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3668 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3669 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3670 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3671 clock-names = "core_iface", "core_aux", 3672 "ctrl_link", 3673 "ctrl_link_iface", "stream_pixel"; 3674 3675 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3676 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3677 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3678 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3679 3680 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3681 phy-names = "dp"; 3682 3683 #sound-dai-cells = <0>; 3684 3685 operating-points-v2 = <&mdss0_dp1_opp_table>; 3686 power-domains = <&rpmhpd SC8280XP_MMCX>; 3687 3688 status = "disabled"; 3689 3690 ports { 3691 #address-cells = <1>; 3692 #size-cells = <0>; 3693 3694 port@0 { 3695 reg = <0>; 3696 3697 mdss0_dp1_in: endpoint { 3698 remote-endpoint = <&mdss0_intf4_out>; 3699 }; 3700 }; 3701 3702 port@1 { 3703 reg = <1>; 3704 3705 mdss0_dp1_out: endpoint { 3706 }; 3707 }; 3708 }; 3709 3710 mdss0_dp1_opp_table: opp-table { 3711 compatible = "operating-points-v2"; 3712 3713 opp-160000000 { 3714 opp-hz = /bits/ 64 <160000000>; 3715 required-opps = <&rpmhpd_opp_low_svs>; 3716 }; 3717 3718 opp-270000000 { 3719 opp-hz = /bits/ 64 <270000000>; 3720 required-opps = <&rpmhpd_opp_svs>; 3721 }; 3722 3723 opp-540000000 { 3724 opp-hz = /bits/ 64 <540000000>; 3725 required-opps = <&rpmhpd_opp_svs_l1>; 3726 }; 3727 3728 opp-810000000 { 3729 opp-hz = /bits/ 64 <810000000>; 3730 required-opps = <&rpmhpd_opp_nom>; 3731 }; 3732 }; 3733 }; 3734 3735 mdss0_dp2: displayport-controller@ae9a000 { 3736 compatible = "qcom,sc8280xp-dp"; 3737 reg = <0 0xae9a000 0 0x200>, 3738 <0 0xae9a200 0 0x200>, 3739 <0 0xae9a400 0 0x600>, 3740 <0 0xae9b000 0 0x400>, 3741 <0 0xae9b400 0 0x400>; 3742 3743 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3744 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3745 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3746 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3747 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3748 clock-names = "core_iface", "core_aux", 3749 "ctrl_link", 3750 "ctrl_link_iface", "stream_pixel"; 3751 interrupt-parent = <&mdss0>; 3752 interrupts = <14>; 3753 phys = <&mdss0_dp2_phy>; 3754 phy-names = "dp"; 3755 power-domains = <&rpmhpd SC8280XP_MMCX>; 3756 3757 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3758 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3759 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3760 operating-points-v2 = <&mdss0_dp2_opp_table>; 3761 3762 #sound-dai-cells = <0>; 3763 3764 status = "disabled"; 3765 3766 ports { 3767 #address-cells = <1>; 3768 #size-cells = <0>; 3769 3770 port@0 { 3771 reg = <0>; 3772 mdss0_dp2_in: endpoint { 3773 remote-endpoint = <&mdss0_intf6_out>; 3774 }; 3775 }; 3776 3777 port@1 { 3778 reg = <1>; 3779 }; 3780 }; 3781 3782 mdss0_dp2_opp_table: opp-table { 3783 compatible = "operating-points-v2"; 3784 3785 opp-160000000 { 3786 opp-hz = /bits/ 64 <160000000>; 3787 required-opps = <&rpmhpd_opp_low_svs>; 3788 }; 3789 3790 opp-270000000 { 3791 opp-hz = /bits/ 64 <270000000>; 3792 required-opps = <&rpmhpd_opp_svs>; 3793 }; 3794 3795 opp-540000000 { 3796 opp-hz = /bits/ 64 <540000000>; 3797 required-opps = <&rpmhpd_opp_svs_l1>; 3798 }; 3799 3800 opp-810000000 { 3801 opp-hz = /bits/ 64 <810000000>; 3802 required-opps = <&rpmhpd_opp_nom>; 3803 }; 3804 }; 3805 }; 3806 3807 mdss0_dp3: displayport-controller@aea0000 { 3808 compatible = "qcom,sc8280xp-dp"; 3809 reg = <0 0xaea0000 0 0x200>, 3810 <0 0xaea0200 0 0x200>, 3811 <0 0xaea0400 0 0x600>, 3812 <0 0xaea1000 0 0x400>, 3813 <0 0xaea1400 0 0x400>; 3814 3815 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3816 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3817 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3818 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3819 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3820 clock-names = "core_iface", "core_aux", 3821 "ctrl_link", 3822 "ctrl_link_iface", "stream_pixel"; 3823 interrupt-parent = <&mdss0>; 3824 interrupts = <15>; 3825 phys = <&mdss0_dp3_phy>; 3826 phy-names = "dp"; 3827 power-domains = <&rpmhpd SC8280XP_MMCX>; 3828 3829 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3830 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3831 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3832 operating-points-v2 = <&mdss0_dp3_opp_table>; 3833 3834 #sound-dai-cells = <0>; 3835 3836 status = "disabled"; 3837 3838 ports { 3839 #address-cells = <1>; 3840 #size-cells = <0>; 3841 3842 port@0 { 3843 reg = <0>; 3844 mdss0_dp3_in: endpoint { 3845 remote-endpoint = <&mdss0_intf5_out>; 3846 }; 3847 }; 3848 3849 port@1 { 3850 reg = <1>; 3851 }; 3852 }; 3853 3854 mdss0_dp3_opp_table: opp-table { 3855 compatible = "operating-points-v2"; 3856 3857 opp-160000000 { 3858 opp-hz = /bits/ 64 <160000000>; 3859 required-opps = <&rpmhpd_opp_low_svs>; 3860 }; 3861 3862 opp-270000000 { 3863 opp-hz = /bits/ 64 <270000000>; 3864 required-opps = <&rpmhpd_opp_svs>; 3865 }; 3866 3867 opp-540000000 { 3868 opp-hz = /bits/ 64 <540000000>; 3869 required-opps = <&rpmhpd_opp_svs_l1>; 3870 }; 3871 3872 opp-810000000 { 3873 opp-hz = /bits/ 64 <810000000>; 3874 required-opps = <&rpmhpd_opp_nom>; 3875 }; 3876 }; 3877 }; 3878 }; 3879 3880 mdss0_dp2_phy: phy@aec2a00 { 3881 compatible = "qcom,sc8280xp-dp-phy"; 3882 reg = <0 0x0aec2a00 0 0x19c>, 3883 <0 0x0aec2200 0 0xec>, 3884 <0 0x0aec2600 0 0xec>, 3885 <0 0x0aec2000 0 0x1c8>; 3886 3887 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3888 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3889 clock-names = "aux", "cfg_ahb"; 3890 power-domains = <&rpmhpd SC8280XP_MX>; 3891 3892 #clock-cells = <1>; 3893 #phy-cells = <0>; 3894 3895 status = "disabled"; 3896 }; 3897 3898 mdss0_dp3_phy: phy@aec5a00 { 3899 compatible = "qcom,sc8280xp-dp-phy"; 3900 reg = <0 0x0aec5a00 0 0x19c>, 3901 <0 0x0aec5200 0 0xec>, 3902 <0 0x0aec5600 0 0xec>, 3903 <0 0x0aec5000 0 0x1c8>; 3904 3905 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3906 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3907 clock-names = "aux", "cfg_ahb"; 3908 power-domains = <&rpmhpd SC8280XP_MX>; 3909 3910 #clock-cells = <1>; 3911 #phy-cells = <0>; 3912 3913 status = "disabled"; 3914 }; 3915 3916 dispcc0: clock-controller@af00000 { 3917 compatible = "qcom,sc8280xp-dispcc0"; 3918 reg = <0 0x0af00000 0 0x20000>; 3919 3920 clocks = <&gcc GCC_DISP_AHB_CLK>, 3921 <&rpmhcc RPMH_CXO_CLK>, 3922 <&sleep_clk>, 3923 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3924 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3925 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3926 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3927 <&mdss0_dp2_phy 0>, 3928 <&mdss0_dp2_phy 1>, 3929 <&mdss0_dp3_phy 0>, 3930 <&mdss0_dp3_phy 1>, 3931 <0>, 3932 <0>, 3933 <0>, 3934 <0>; 3935 power-domains = <&rpmhpd SC8280XP_MMCX>; 3936 3937 #clock-cells = <1>; 3938 #power-domain-cells = <1>; 3939 #reset-cells = <1>; 3940 3941 status = "disabled"; 3942 }; 3943 3944 pdc: interrupt-controller@b220000 { 3945 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3946 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3947 qcom,pdc-ranges = <0 480 40>, 3948 <40 140 14>, 3949 <54 263 1>, 3950 <55 306 4>, 3951 <59 312 3>, 3952 <62 374 2>, 3953 <64 434 2>, 3954 <66 438 3>, 3955 <69 86 1>, 3956 <70 520 54>, 3957 <124 609 28>, 3958 <159 638 1>, 3959 <160 720 8>, 3960 <168 801 1>, 3961 <169 728 30>, 3962 <199 416 2>, 3963 <201 449 1>, 3964 <202 89 1>, 3965 <203 451 1>, 3966 <204 462 1>, 3967 <205 264 1>, 3968 <206 579 1>, 3969 <207 653 1>, 3970 <208 656 1>, 3971 <209 659 1>, 3972 <210 122 1>, 3973 <211 699 1>, 3974 <212 705 1>, 3975 <213 450 1>, 3976 <214 643 1>, 3977 <216 646 5>, 3978 <221 390 5>, 3979 <226 700 3>, 3980 <229 240 3>, 3981 <232 269 1>, 3982 <233 377 1>, 3983 <234 372 1>, 3984 <235 138 1>, 3985 <236 857 1>, 3986 <237 860 1>, 3987 <238 137 1>, 3988 <239 668 1>, 3989 <240 366 1>, 3990 <241 949 1>, 3991 <242 815 5>, 3992 <247 769 1>, 3993 <248 768 1>, 3994 <249 663 1>, 3995 <250 799 2>, 3996 <252 798 1>, 3997 <253 765 1>, 3998 <254 763 1>, 3999 <255 454 1>, 4000 <258 139 1>, 4001 <259 786 2>, 4002 <261 370 2>, 4003 <263 158 2>; 4004 #interrupt-cells = <2>; 4005 interrupt-parent = <&intc>; 4006 interrupt-controller; 4007 }; 4008 4009 tsens0: thermal-sensor@c263000 { 4010 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4011 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4012 <0 0x0c222000 0 0x8>; /* SROT */ 4013 #qcom,sensors = <14>; 4014 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4015 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4016 interrupt-names = "uplow", "critical"; 4017 #thermal-sensor-cells = <1>; 4018 }; 4019 4020 tsens1: thermal-sensor@c265000 { 4021 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4022 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4023 <0 0x0c223000 0 0x8>; /* SROT */ 4024 #qcom,sensors = <16>; 4025 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4026 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4027 interrupt-names = "uplow", "critical"; 4028 #thermal-sensor-cells = <1>; 4029 }; 4030 4031 aoss_qmp: power-management@c300000 { 4032 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4033 reg = <0 0x0c300000 0 0x400>; 4034 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4035 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4036 4037 #clock-cells = <0>; 4038 }; 4039 4040 sram@c3f0000 { 4041 compatible = "qcom,rpmh-stats"; 4042 reg = <0 0x0c3f0000 0 0x400>; 4043 }; 4044 4045 spmi_bus: spmi@c440000 { 4046 compatible = "qcom,spmi-pmic-arb"; 4047 reg = <0 0x0c440000 0 0x1100>, 4048 <0 0x0c600000 0 0x2000000>, 4049 <0 0x0e600000 0 0x100000>, 4050 <0 0x0e700000 0 0xa0000>, 4051 <0 0x0c40a000 0 0x26000>; 4052 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4053 interrupt-names = "periph_irq"; 4054 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4055 qcom,ee = <0>; 4056 qcom,channel = <0>; 4057 #address-cells = <2>; 4058 #size-cells = <0>; 4059 interrupt-controller; 4060 #interrupt-cells = <4>; 4061 }; 4062 4063 tlmm: pinctrl@f100000 { 4064 compatible = "qcom,sc8280xp-tlmm"; 4065 reg = <0 0x0f100000 0 0x300000>; 4066 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4067 gpio-controller; 4068 #gpio-cells = <2>; 4069 interrupt-controller; 4070 #interrupt-cells = <2>; 4071 gpio-ranges = <&tlmm 0 0 230>; 4072 wakeup-parent = <&pdc>; 4073 }; 4074 4075 apps_smmu: iommu@15000000 { 4076 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4077 reg = <0 0x15000000 0 0x100000>; 4078 #iommu-cells = <2>; 4079 #global-interrupts = <2>; 4080 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 4210 }; 4211 4212 intc: interrupt-controller@17a00000 { 4213 compatible = "arm,gic-v3"; 4214 interrupt-controller; 4215 #interrupt-cells = <3>; 4216 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4217 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4218 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4219 #redistributor-regions = <1>; 4220 redistributor-stride = <0 0x20000>; 4221 4222 #address-cells = <2>; 4223 #size-cells = <2>; 4224 ranges; 4225 4226 msi-controller@17a40000 { 4227 compatible = "arm,gic-v3-its"; 4228 reg = <0 0x17a40000 0 0x20000>; 4229 msi-controller; 4230 #msi-cells = <1>; 4231 }; 4232 }; 4233 4234 watchdog@17c10000 { 4235 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4236 reg = <0 0x17c10000 0 0x1000>; 4237 clocks = <&sleep_clk>; 4238 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4239 }; 4240 4241 timer@17c20000 { 4242 compatible = "arm,armv7-timer-mem"; 4243 reg = <0x0 0x17c20000 0x0 0x1000>; 4244 #address-cells = <1>; 4245 #size-cells = <1>; 4246 ranges = <0x0 0x0 0x0 0x20000000>; 4247 4248 frame@17c21000 { 4249 frame-number = <0>; 4250 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4252 reg = <0x17c21000 0x1000>, 4253 <0x17c22000 0x1000>; 4254 }; 4255 4256 frame@17c23000 { 4257 frame-number = <1>; 4258 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4259 reg = <0x17c23000 0x1000>; 4260 status = "disabled"; 4261 }; 4262 4263 frame@17c25000 { 4264 frame-number = <2>; 4265 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4266 reg = <0x17c25000 0x1000>; 4267 status = "disabled"; 4268 }; 4269 4270 frame@17c27000 { 4271 frame-number = <3>; 4272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4273 reg = <0x17c26000 0x1000>; 4274 status = "disabled"; 4275 }; 4276 4277 frame@17c29000 { 4278 frame-number = <4>; 4279 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4280 reg = <0x17c29000 0x1000>; 4281 status = "disabled"; 4282 }; 4283 4284 frame@17c2b000 { 4285 frame-number = <5>; 4286 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4287 reg = <0x17c2b000 0x1000>; 4288 status = "disabled"; 4289 }; 4290 4291 frame@17c2d000 { 4292 frame-number = <6>; 4293 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4294 reg = <0x17c2d000 0x1000>; 4295 status = "disabled"; 4296 }; 4297 }; 4298 4299 apps_rsc: rsc@18200000 { 4300 compatible = "qcom,rpmh-rsc"; 4301 reg = <0x0 0x18200000 0x0 0x10000>, 4302 <0x0 0x18210000 0x0 0x10000>, 4303 <0x0 0x18220000 0x0 0x10000>; 4304 reg-names = "drv-0", "drv-1", "drv-2"; 4305 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4308 qcom,tcs-offset = <0xd00>; 4309 qcom,drv-id = <2>; 4310 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4311 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4312 label = "apps_rsc"; 4313 power-domains = <&CLUSTER_PD>; 4314 4315 apps_bcm_voter: bcm-voter { 4316 compatible = "qcom,bcm-voter"; 4317 }; 4318 4319 rpmhcc: clock-controller { 4320 compatible = "qcom,sc8280xp-rpmh-clk"; 4321 #clock-cells = <1>; 4322 clock-names = "xo"; 4323 clocks = <&xo_board_clk>; 4324 }; 4325 4326 rpmhpd: power-controller { 4327 compatible = "qcom,sc8280xp-rpmhpd"; 4328 #power-domain-cells = <1>; 4329 operating-points-v2 = <&rpmhpd_opp_table>; 4330 4331 rpmhpd_opp_table: opp-table { 4332 compatible = "operating-points-v2"; 4333 4334 rpmhpd_opp_ret: opp1 { 4335 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4336 }; 4337 4338 rpmhpd_opp_min_svs: opp2 { 4339 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4340 }; 4341 4342 rpmhpd_opp_low_svs: opp3 { 4343 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4344 }; 4345 4346 rpmhpd_opp_svs: opp4 { 4347 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4348 }; 4349 4350 rpmhpd_opp_svs_l1: opp5 { 4351 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4352 }; 4353 4354 rpmhpd_opp_nom: opp6 { 4355 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4356 }; 4357 4358 rpmhpd_opp_nom_l1: opp7 { 4359 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4360 }; 4361 4362 rpmhpd_opp_nom_l2: opp8 { 4363 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4364 }; 4365 4366 rpmhpd_opp_turbo: opp9 { 4367 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4368 }; 4369 4370 rpmhpd_opp_turbo_l1: opp10 { 4371 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4372 }; 4373 }; 4374 }; 4375 }; 4376 4377 epss_l3: interconnect@18590000 { 4378 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4379 reg = <0 0x18590000 0 0x1000>; 4380 4381 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4382 clock-names = "xo", "alternate"; 4383 4384 #interconnect-cells = <1>; 4385 }; 4386 4387 cpufreq_hw: cpufreq@18591000 { 4388 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4389 reg = <0 0x18591000 0 0x1000>, 4390 <0 0x18592000 0 0x1000>; 4391 reg-names = "freq-domain0", "freq-domain1"; 4392 4393 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4394 clock-names = "xo", "alternate"; 4395 4396 #freq-domain-cells = <1>; 4397 #clock-cells = <1>; 4398 }; 4399 4400 remoteproc_nsp0: remoteproc@1b300000 { 4401 compatible = "qcom,sc8280xp-nsp0-pas"; 4402 reg = <0 0x1b300000 0 0x100>; 4403 4404 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4405 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4406 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4407 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4408 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4409 interrupt-names = "wdog", "fatal", "ready", 4410 "handover", "stop-ack"; 4411 4412 clocks = <&rpmhcc RPMH_CXO_CLK>; 4413 clock-names = "xo"; 4414 4415 power-domains = <&rpmhpd SC8280XP_NSP>; 4416 power-domain-names = "nsp"; 4417 4418 memory-region = <&pil_nsp0_mem>; 4419 4420 qcom,smem-states = <&smp2p_nsp0_out 0>; 4421 qcom,smem-state-names = "stop"; 4422 4423 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4424 4425 status = "disabled"; 4426 4427 glink-edge { 4428 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4429 IPCC_MPROC_SIGNAL_GLINK_QMP 4430 IRQ_TYPE_EDGE_RISING>; 4431 mboxes = <&ipcc IPCC_CLIENT_CDSP 4432 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4433 4434 label = "nsp0"; 4435 qcom,remote-pid = <5>; 4436 4437 fastrpc { 4438 compatible = "qcom,fastrpc"; 4439 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4440 label = "cdsp"; 4441 #address-cells = <1>; 4442 #size-cells = <0>; 4443 4444 compute-cb@1 { 4445 compatible = "qcom,fastrpc-compute-cb"; 4446 reg = <1>; 4447 iommus = <&apps_smmu 0x3181 0x0420>; 4448 }; 4449 4450 compute-cb@2 { 4451 compatible = "qcom,fastrpc-compute-cb"; 4452 reg = <2>; 4453 iommus = <&apps_smmu 0x3182 0x0420>; 4454 }; 4455 4456 compute-cb@3 { 4457 compatible = "qcom,fastrpc-compute-cb"; 4458 reg = <3>; 4459 iommus = <&apps_smmu 0x3183 0x0420>; 4460 }; 4461 4462 compute-cb@4 { 4463 compatible = "qcom,fastrpc-compute-cb"; 4464 reg = <4>; 4465 iommus = <&apps_smmu 0x3184 0x0420>; 4466 }; 4467 4468 compute-cb@5 { 4469 compatible = "qcom,fastrpc-compute-cb"; 4470 reg = <5>; 4471 iommus = <&apps_smmu 0x3185 0x0420>; 4472 }; 4473 4474 compute-cb@6 { 4475 compatible = "qcom,fastrpc-compute-cb"; 4476 reg = <6>; 4477 iommus = <&apps_smmu 0x3186 0x0420>; 4478 }; 4479 4480 compute-cb@7 { 4481 compatible = "qcom,fastrpc-compute-cb"; 4482 reg = <7>; 4483 iommus = <&apps_smmu 0x3187 0x0420>; 4484 }; 4485 4486 compute-cb@8 { 4487 compatible = "qcom,fastrpc-compute-cb"; 4488 reg = <8>; 4489 iommus = <&apps_smmu 0x3188 0x0420>; 4490 }; 4491 4492 compute-cb@9 { 4493 compatible = "qcom,fastrpc-compute-cb"; 4494 reg = <9>; 4495 iommus = <&apps_smmu 0x318b 0x0420>; 4496 }; 4497 4498 compute-cb@10 { 4499 compatible = "qcom,fastrpc-compute-cb"; 4500 reg = <10>; 4501 iommus = <&apps_smmu 0x318b 0x0420>; 4502 }; 4503 4504 compute-cb@11 { 4505 compatible = "qcom,fastrpc-compute-cb"; 4506 reg = <11>; 4507 iommus = <&apps_smmu 0x318c 0x0420>; 4508 }; 4509 4510 compute-cb@12 { 4511 compatible = "qcom,fastrpc-compute-cb"; 4512 reg = <12>; 4513 iommus = <&apps_smmu 0x318d 0x0420>; 4514 }; 4515 4516 compute-cb@13 { 4517 compatible = "qcom,fastrpc-compute-cb"; 4518 reg = <13>; 4519 iommus = <&apps_smmu 0x318e 0x0420>; 4520 }; 4521 4522 compute-cb@14 { 4523 compatible = "qcom,fastrpc-compute-cb"; 4524 reg = <14>; 4525 iommus = <&apps_smmu 0x318f 0x0420>; 4526 }; 4527 }; 4528 }; 4529 }; 4530 4531 remoteproc_nsp1: remoteproc@21300000 { 4532 compatible = "qcom,sc8280xp-nsp1-pas"; 4533 reg = <0 0x21300000 0 0x100>; 4534 4535 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4536 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4537 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4538 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4539 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4540 interrupt-names = "wdog", "fatal", "ready", 4541 "handover", "stop-ack"; 4542 4543 clocks = <&rpmhcc RPMH_CXO_CLK>; 4544 clock-names = "xo"; 4545 4546 power-domains = <&rpmhpd SC8280XP_NSP>; 4547 power-domain-names = "nsp"; 4548 4549 memory-region = <&pil_nsp1_mem>; 4550 4551 qcom,smem-states = <&smp2p_nsp1_out 0>; 4552 qcom,smem-state-names = "stop"; 4553 4554 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4555 4556 status = "disabled"; 4557 4558 glink-edge { 4559 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4560 IPCC_MPROC_SIGNAL_GLINK_QMP 4561 IRQ_TYPE_EDGE_RISING>; 4562 mboxes = <&ipcc IPCC_CLIENT_NSP1 4563 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4564 4565 label = "nsp1"; 4566 qcom,remote-pid = <12>; 4567 }; 4568 }; 4569 4570 mdss1: display-subsystem@22000000 { 4571 compatible = "qcom,sc8280xp-mdss"; 4572 reg = <0 0x22000000 0 0x1000>; 4573 reg-names = "mdss"; 4574 4575 clocks = <&gcc GCC_DISP_AHB_CLK>, 4576 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4577 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4578 clock-names = "iface", 4579 "ahb", 4580 "core"; 4581 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4582 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4583 interconnect-names = "mdp0-mem", "mdp1-mem"; 4584 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4585 4586 iommus = <&apps_smmu 0x1800 0x402>; 4587 power-domains = <&dispcc1 MDSS_GDSC>; 4588 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4589 4590 interrupt-controller; 4591 #interrupt-cells = <1>; 4592 #address-cells = <2>; 4593 #size-cells = <2>; 4594 ranges; 4595 4596 status = "disabled"; 4597 4598 mdss1_mdp: display-controller@22001000 { 4599 compatible = "qcom,sc8280xp-dpu"; 4600 reg = <0 0x22001000 0 0x8f000>, 4601 <0 0x220b0000 0 0x2008>; 4602 reg-names = "mdp", "vbif"; 4603 4604 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4605 <&gcc GCC_DISP_SF_AXI_CLK>, 4606 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4607 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4608 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4609 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4610 clock-names = "bus", 4611 "nrt_bus", 4612 "iface", 4613 "lut", 4614 "core", 4615 "vsync"; 4616 interrupt-parent = <&mdss1>; 4617 interrupts = <0>; 4618 power-domains = <&rpmhpd SC8280XP_MMCX>; 4619 4620 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4621 assigned-clock-rates = <19200000>; 4622 operating-points-v2 = <&mdss1_mdp_opp_table>; 4623 4624 ports { 4625 #address-cells = <1>; 4626 #size-cells = <0>; 4627 4628 port@0 { 4629 reg = <0>; 4630 mdss1_intf0_out: endpoint { 4631 remote-endpoint = <&mdss1_dp0_in>; 4632 }; 4633 }; 4634 4635 port@4 { 4636 reg = <4>; 4637 mdss1_intf4_out: endpoint { 4638 remote-endpoint = <&mdss1_dp1_in>; 4639 }; 4640 }; 4641 4642 port@5 { 4643 reg = <5>; 4644 mdss1_intf5_out: endpoint { 4645 remote-endpoint = <&mdss1_dp3_in>; 4646 }; 4647 }; 4648 4649 port@6 { 4650 reg = <6>; 4651 mdss1_intf6_out: endpoint { 4652 remote-endpoint = <&mdss1_dp2_in>; 4653 }; 4654 }; 4655 }; 4656 4657 mdss1_mdp_opp_table: opp-table { 4658 compatible = "operating-points-v2"; 4659 4660 opp-200000000 { 4661 opp-hz = /bits/ 64 <200000000>; 4662 required-opps = <&rpmhpd_opp_low_svs>; 4663 }; 4664 4665 opp-300000000 { 4666 opp-hz = /bits/ 64 <300000000>; 4667 required-opps = <&rpmhpd_opp_svs>; 4668 }; 4669 4670 opp-375000000 { 4671 opp-hz = /bits/ 64 <375000000>; 4672 required-opps = <&rpmhpd_opp_svs_l1>; 4673 }; 4674 4675 opp-500000000 { 4676 opp-hz = /bits/ 64 <500000000>; 4677 required-opps = <&rpmhpd_opp_nom>; 4678 }; 4679 opp-600000000 { 4680 opp-hz = /bits/ 64 <600000000>; 4681 required-opps = <&rpmhpd_opp_turbo_l1>; 4682 }; 4683 }; 4684 }; 4685 4686 mdss1_dp0: displayport-controller@22090000 { 4687 compatible = "qcom,sc8280xp-dp"; 4688 reg = <0 0x22090000 0 0x200>, 4689 <0 0x22090200 0 0x200>, 4690 <0 0x22090400 0 0x600>, 4691 <0 0x22091000 0 0x400>, 4692 <0 0x22091400 0 0x400>; 4693 4694 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4695 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4696 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4697 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4698 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4699 clock-names = "core_iface", "core_aux", 4700 "ctrl_link", 4701 "ctrl_link_iface", "stream_pixel"; 4702 interrupt-parent = <&mdss1>; 4703 interrupts = <12>; 4704 phys = <&mdss1_dp0_phy>; 4705 phy-names = "dp"; 4706 power-domains = <&rpmhpd SC8280XP_MMCX>; 4707 4708 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4709 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4710 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4711 operating-points-v2 = <&mdss1_dp0_opp_table>; 4712 4713 #sound-dai-cells = <0>; 4714 4715 status = "disabled"; 4716 4717 ports { 4718 #address-cells = <1>; 4719 #size-cells = <0>; 4720 4721 port@0 { 4722 reg = <0>; 4723 mdss1_dp0_in: endpoint { 4724 remote-endpoint = <&mdss1_intf0_out>; 4725 }; 4726 }; 4727 4728 port@1 { 4729 reg = <1>; 4730 }; 4731 }; 4732 4733 mdss1_dp0_opp_table: opp-table { 4734 compatible = "operating-points-v2"; 4735 4736 opp-160000000 { 4737 opp-hz = /bits/ 64 <160000000>; 4738 required-opps = <&rpmhpd_opp_low_svs>; 4739 }; 4740 4741 opp-270000000 { 4742 opp-hz = /bits/ 64 <270000000>; 4743 required-opps = <&rpmhpd_opp_svs>; 4744 }; 4745 4746 opp-540000000 { 4747 opp-hz = /bits/ 64 <540000000>; 4748 required-opps = <&rpmhpd_opp_svs_l1>; 4749 }; 4750 4751 opp-810000000 { 4752 opp-hz = /bits/ 64 <810000000>; 4753 required-opps = <&rpmhpd_opp_nom>; 4754 }; 4755 }; 4756 }; 4757 4758 mdss1_dp1: displayport-controller@22098000 { 4759 compatible = "qcom,sc8280xp-dp"; 4760 reg = <0 0x22098000 0 0x200>, 4761 <0 0x22098200 0 0x200>, 4762 <0 0x22098400 0 0x600>, 4763 <0 0x22099000 0 0x400>, 4764 <0 0x22099400 0 0x400>; 4765 4766 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4767 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4768 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4769 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4770 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4771 clock-names = "core_iface", "core_aux", 4772 "ctrl_link", 4773 "ctrl_link_iface", "stream_pixel"; 4774 interrupt-parent = <&mdss1>; 4775 interrupts = <13>; 4776 phys = <&mdss1_dp1_phy>; 4777 phy-names = "dp"; 4778 power-domains = <&rpmhpd SC8280XP_MMCX>; 4779 4780 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4781 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4782 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4783 operating-points-v2 = <&mdss1_dp1_opp_table>; 4784 4785 #sound-dai-cells = <0>; 4786 4787 status = "disabled"; 4788 4789 ports { 4790 #address-cells = <1>; 4791 #size-cells = <0>; 4792 4793 port@0 { 4794 reg = <0>; 4795 mdss1_dp1_in: endpoint { 4796 remote-endpoint = <&mdss1_intf4_out>; 4797 }; 4798 }; 4799 4800 port@1 { 4801 reg = <1>; 4802 }; 4803 }; 4804 4805 mdss1_dp1_opp_table: opp-table { 4806 compatible = "operating-points-v2"; 4807 4808 opp-160000000 { 4809 opp-hz = /bits/ 64 <160000000>; 4810 required-opps = <&rpmhpd_opp_low_svs>; 4811 }; 4812 4813 opp-270000000 { 4814 opp-hz = /bits/ 64 <270000000>; 4815 required-opps = <&rpmhpd_opp_svs>; 4816 }; 4817 4818 opp-540000000 { 4819 opp-hz = /bits/ 64 <540000000>; 4820 required-opps = <&rpmhpd_opp_svs_l1>; 4821 }; 4822 4823 opp-810000000 { 4824 opp-hz = /bits/ 64 <810000000>; 4825 required-opps = <&rpmhpd_opp_nom>; 4826 }; 4827 }; 4828 }; 4829 4830 mdss1_dp2: displayport-controller@2209a000 { 4831 compatible = "qcom,sc8280xp-dp"; 4832 reg = <0 0x2209a000 0 0x200>, 4833 <0 0x2209a200 0 0x200>, 4834 <0 0x2209a400 0 0x600>, 4835 <0 0x2209b000 0 0x400>, 4836 <0 0x2209b400 0 0x400>; 4837 4838 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4839 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4840 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4841 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4842 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4843 clock-names = "core_iface", "core_aux", 4844 "ctrl_link", 4845 "ctrl_link_iface", "stream_pixel"; 4846 interrupt-parent = <&mdss1>; 4847 interrupts = <14>; 4848 phys = <&mdss1_dp2_phy>; 4849 phy-names = "dp"; 4850 power-domains = <&rpmhpd SC8280XP_MMCX>; 4851 4852 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4853 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4854 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4855 operating-points-v2 = <&mdss1_dp2_opp_table>; 4856 4857 #sound-dai-cells = <0>; 4858 4859 status = "disabled"; 4860 4861 ports { 4862 #address-cells = <1>; 4863 #size-cells = <0>; 4864 4865 port@0 { 4866 reg = <0>; 4867 mdss1_dp2_in: endpoint { 4868 remote-endpoint = <&mdss1_intf6_out>; 4869 }; 4870 }; 4871 4872 port@1 { 4873 reg = <1>; 4874 }; 4875 }; 4876 4877 mdss1_dp2_opp_table: opp-table { 4878 compatible = "operating-points-v2"; 4879 4880 opp-160000000 { 4881 opp-hz = /bits/ 64 <160000000>; 4882 required-opps = <&rpmhpd_opp_low_svs>; 4883 }; 4884 4885 opp-270000000 { 4886 opp-hz = /bits/ 64 <270000000>; 4887 required-opps = <&rpmhpd_opp_svs>; 4888 }; 4889 4890 opp-540000000 { 4891 opp-hz = /bits/ 64 <540000000>; 4892 required-opps = <&rpmhpd_opp_svs_l1>; 4893 }; 4894 4895 opp-810000000 { 4896 opp-hz = /bits/ 64 <810000000>; 4897 required-opps = <&rpmhpd_opp_nom>; 4898 }; 4899 }; 4900 }; 4901 4902 mdss1_dp3: displayport-controller@220a0000 { 4903 compatible = "qcom,sc8280xp-dp"; 4904 reg = <0 0x220a0000 0 0x200>, 4905 <0 0x220a0200 0 0x200>, 4906 <0 0x220a0400 0 0x600>, 4907 <0 0x220a1000 0 0x400>, 4908 <0 0x220a1400 0 0x400>; 4909 4910 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4911 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4912 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4913 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4914 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4915 clock-names = "core_iface", "core_aux", 4916 "ctrl_link", 4917 "ctrl_link_iface", "stream_pixel"; 4918 interrupt-parent = <&mdss1>; 4919 interrupts = <15>; 4920 phys = <&mdss1_dp3_phy>; 4921 phy-names = "dp"; 4922 power-domains = <&rpmhpd SC8280XP_MMCX>; 4923 4924 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4925 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4926 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4927 operating-points-v2 = <&mdss1_dp3_opp_table>; 4928 4929 #sound-dai-cells = <0>; 4930 4931 status = "disabled"; 4932 4933 ports { 4934 #address-cells = <1>; 4935 #size-cells = <0>; 4936 4937 port@0 { 4938 reg = <0>; 4939 mdss1_dp3_in: endpoint { 4940 remote-endpoint = <&mdss1_intf5_out>; 4941 }; 4942 }; 4943 4944 port@1 { 4945 reg = <1>; 4946 }; 4947 }; 4948 4949 mdss1_dp3_opp_table: opp-table { 4950 compatible = "operating-points-v2"; 4951 4952 opp-160000000 { 4953 opp-hz = /bits/ 64 <160000000>; 4954 required-opps = <&rpmhpd_opp_low_svs>; 4955 }; 4956 4957 opp-270000000 { 4958 opp-hz = /bits/ 64 <270000000>; 4959 required-opps = <&rpmhpd_opp_svs>; 4960 }; 4961 4962 opp-540000000 { 4963 opp-hz = /bits/ 64 <540000000>; 4964 required-opps = <&rpmhpd_opp_svs_l1>; 4965 }; 4966 4967 opp-810000000 { 4968 opp-hz = /bits/ 64 <810000000>; 4969 required-opps = <&rpmhpd_opp_nom>; 4970 }; 4971 }; 4972 }; 4973 }; 4974 4975 mdss1_dp2_phy: phy@220c2a00 { 4976 compatible = "qcom,sc8280xp-dp-phy"; 4977 reg = <0 0x220c2a00 0 0x19c>, 4978 <0 0x220c2200 0 0xec>, 4979 <0 0x220c2600 0 0xec>, 4980 <0 0x220c2000 0 0x1c8>; 4981 4982 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4983 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4984 clock-names = "aux", "cfg_ahb"; 4985 power-domains = <&rpmhpd SC8280XP_MX>; 4986 4987 #clock-cells = <1>; 4988 #phy-cells = <0>; 4989 4990 status = "disabled"; 4991 }; 4992 4993 mdss1_dp3_phy: phy@220c5a00 { 4994 compatible = "qcom,sc8280xp-dp-phy"; 4995 reg = <0 0x220c5a00 0 0x19c>, 4996 <0 0x220c5200 0 0xec>, 4997 <0 0x220c5600 0 0xec>, 4998 <0 0x220c5000 0 0x1c8>; 4999 5000 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5001 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5002 clock-names = "aux", "cfg_ahb"; 5003 power-domains = <&rpmhpd SC8280XP_MX>; 5004 5005 #clock-cells = <1>; 5006 #phy-cells = <0>; 5007 5008 status = "disabled"; 5009 }; 5010 5011 dispcc1: clock-controller@22100000 { 5012 compatible = "qcom,sc8280xp-dispcc1"; 5013 reg = <0 0x22100000 0 0x20000>; 5014 5015 clocks = <&gcc GCC_DISP_AHB_CLK>, 5016 <&rpmhcc RPMH_CXO_CLK>, 5017 <0>, 5018 <&mdss1_dp0_phy 0>, 5019 <&mdss1_dp0_phy 1>, 5020 <&mdss1_dp1_phy 0>, 5021 <&mdss1_dp1_phy 1>, 5022 <&mdss1_dp2_phy 0>, 5023 <&mdss1_dp2_phy 1>, 5024 <&mdss1_dp3_phy 0>, 5025 <&mdss1_dp3_phy 1>, 5026 <0>, 5027 <0>, 5028 <0>, 5029 <0>; 5030 power-domains = <&rpmhpd SC8280XP_MMCX>; 5031 5032 #clock-cells = <1>; 5033 #power-domain-cells = <1>; 5034 #reset-cells = <1>; 5035 5036 status = "disabled"; 5037 }; 5038 5039 ethernet1: ethernet@23000000 { 5040 compatible = "qcom,sc8280xp-ethqos"; 5041 reg = <0x0 0x23000000 0x0 0x10000>, 5042 <0x0 0x23016000 0x0 0x100>; 5043 reg-names = "stmmaceth", "rgmii"; 5044 5045 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5046 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5047 <&gcc GCC_EMAC1_PTP_CLK>, 5048 <&gcc GCC_EMAC1_RGMII_CLK>; 5049 clock-names = "stmmaceth", 5050 "pclk", 5051 "ptp_ref", 5052 "rgmii"; 5053 5054 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5056 interrupt-names = "macirq", "eth_lpi"; 5057 5058 iommus = <&apps_smmu 0x40 0xf>; 5059 power-domains = <&gcc EMAC_1_GDSC>; 5060 5061 snps,tso; 5062 snps,pbl = <32>; 5063 rx-fifo-depth = <4096>; 5064 tx-fifo-depth = <4096>; 5065 5066 status = "disabled"; 5067 }; 5068 }; 5069 5070 sound: sound { 5071 }; 5072 5073 thermal-zones { 5074 cpu0-thermal { 5075 polling-delay-passive = <250>; 5076 polling-delay = <1000>; 5077 5078 thermal-sensors = <&tsens0 1>; 5079 5080 trips { 5081 cpu-crit { 5082 temperature = <110000>; 5083 hysteresis = <1000>; 5084 type = "critical"; 5085 }; 5086 }; 5087 }; 5088 5089 cpu1-thermal { 5090 polling-delay-passive = <250>; 5091 polling-delay = <1000>; 5092 5093 thermal-sensors = <&tsens0 2>; 5094 5095 trips { 5096 cpu-crit { 5097 temperature = <110000>; 5098 hysteresis = <1000>; 5099 type = "critical"; 5100 }; 5101 }; 5102 }; 5103 5104 cpu2-thermal { 5105 polling-delay-passive = <250>; 5106 polling-delay = <1000>; 5107 5108 thermal-sensors = <&tsens0 3>; 5109 5110 trips { 5111 cpu-crit { 5112 temperature = <110000>; 5113 hysteresis = <1000>; 5114 type = "critical"; 5115 }; 5116 }; 5117 }; 5118 5119 cpu3-thermal { 5120 polling-delay-passive = <250>; 5121 polling-delay = <1000>; 5122 5123 thermal-sensors = <&tsens0 4>; 5124 5125 trips { 5126 cpu-crit { 5127 temperature = <110000>; 5128 hysteresis = <1000>; 5129 type = "critical"; 5130 }; 5131 }; 5132 }; 5133 5134 cpu4-thermal { 5135 polling-delay-passive = <250>; 5136 polling-delay = <1000>; 5137 5138 thermal-sensors = <&tsens0 5>; 5139 5140 trips { 5141 cpu-crit { 5142 temperature = <110000>; 5143 hysteresis = <1000>; 5144 type = "critical"; 5145 }; 5146 }; 5147 }; 5148 5149 cpu5-thermal { 5150 polling-delay-passive = <250>; 5151 polling-delay = <1000>; 5152 5153 thermal-sensors = <&tsens0 6>; 5154 5155 trips { 5156 cpu-crit { 5157 temperature = <110000>; 5158 hysteresis = <1000>; 5159 type = "critical"; 5160 }; 5161 }; 5162 }; 5163 5164 cpu6-thermal { 5165 polling-delay-passive = <250>; 5166 polling-delay = <1000>; 5167 5168 thermal-sensors = <&tsens0 7>; 5169 5170 trips { 5171 cpu-crit { 5172 temperature = <110000>; 5173 hysteresis = <1000>; 5174 type = "critical"; 5175 }; 5176 }; 5177 }; 5178 5179 cpu7-thermal { 5180 polling-delay-passive = <250>; 5181 polling-delay = <1000>; 5182 5183 thermal-sensors = <&tsens0 8>; 5184 5185 trips { 5186 cpu-crit { 5187 temperature = <110000>; 5188 hysteresis = <1000>; 5189 type = "critical"; 5190 }; 5191 }; 5192 }; 5193 5194 cluster0-thermal { 5195 polling-delay-passive = <250>; 5196 polling-delay = <1000>; 5197 5198 thermal-sensors = <&tsens0 9>; 5199 5200 trips { 5201 cpu-crit { 5202 temperature = <110000>; 5203 hysteresis = <1000>; 5204 type = "critical"; 5205 }; 5206 }; 5207 }; 5208 5209 mem-thermal { 5210 polling-delay-passive = <250>; 5211 polling-delay = <1000>; 5212 5213 thermal-sensors = <&tsens1 15>; 5214 5215 trips { 5216 trip-point0 { 5217 temperature = <90000>; 5218 hysteresis = <2000>; 5219 type = "hot"; 5220 }; 5221 }; 5222 }; 5223 }; 5224 5225 timer { 5226 compatible = "arm,armv8-timer"; 5227 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5228 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5229 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5230 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5231 }; 5232}; 5233