xref: /openbmc/linux/arch/mips/pci/fixup-malta.c (revision b2441318)
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/init.h>
3 #include <linux/pci.h>
4 #include <asm/mips-boards/piix4.h>
5 
6 /* PCI interrupt pins */
7 #define PCIA		1
8 #define PCIB		2
9 #define PCIC		3
10 #define PCID		4
11 
12 /* This table is filled in by interrogating the PIIX4 chip */
13 static char pci_irq[5] = {
14 };
15 
16 static char irq_tab[][5] = {
17 	/*	INTA	INTB	INTC	INTD */
18 	{0,	0,	0,	0,	0 },	/*  0: GT64120 PCI bridge */
19 	{0,	0,	0,	0,	0 },	/*  1: Unused */
20 	{0,	0,	0,	0,	0 },	/*  2: Unused */
21 	{0,	0,	0,	0,	0 },	/*  3: Unused */
22 	{0,	0,	0,	0,	0 },	/*  4: Unused */
23 	{0,	0,	0,	0,	0 },	/*  5: Unused */
24 	{0,	0,	0,	0,	0 },	/*  6: Unused */
25 	{0,	0,	0,	0,	0 },	/*  7: Unused */
26 	{0,	0,	0,	0,	0 },	/*  8: Unused */
27 	{0,	0,	0,	0,	0 },	/*  9: Unused */
28 	{0,	0,	0,	0,	PCID }, /* 10: PIIX4 USB */
29 	{0,	PCIB,	0,	0,	0 },	/* 11: AMD 79C973 Ethernet */
30 	{0,	PCIC,	0,	0,	0 },	/* 12: Crystal 4281 Sound */
31 	{0,	0,	0,	0,	0 },	/* 13: Unused */
32 	{0,	0,	0,	0,	0 },	/* 14: Unused */
33 	{0,	0,	0,	0,	0 },	/* 15: Unused */
34 	{0,	0,	0,	0,	0 },	/* 16: Unused */
35 	{0,	0,	0,	0,	0 },	/* 17: Bonito/SOC-it PCI Bridge*/
36 	{0,	PCIA,	PCIB,	PCIC,	PCID }, /* 18: PCI Slot 1 */
37 	{0,	PCIB,	PCIC,	PCID,	PCIA }, /* 19: PCI Slot 2 */
38 	{0,	PCIC,	PCID,	PCIA,	PCIB }, /* 20: PCI Slot 3 */
39 	{0,	PCID,	PCIA,	PCIB,	PCIC }	/* 21: PCI Slot 4 */
40 };
41 
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)42 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
43 {
44 	int virq;
45 	virq = irq_tab[slot][pin];
46 	return pci_irq[virq];
47 }
48 
49 /* Do platform specific device initialization at pci_enable_device() time */
pcibios_plat_dev_init(struct pci_dev * dev)50 int pcibios_plat_dev_init(struct pci_dev *dev)
51 {
52 	return 0;
53 }
54 
malta_piix_func3_base_fixup(struct pci_dev * dev)55 static void malta_piix_func3_base_fixup(struct pci_dev *dev)
56 {
57 	/* Set a sane PM I/O base address */
58 	pci_write_config_word(dev, PIIX4_FUNC3_PMBA, 0x1000);
59 
60 	/* Enable access to the PM I/O region */
61 	pci_write_config_byte(dev, PIIX4_FUNC3_PMREGMISC,
62 			      PIIX4_FUNC3_PMREGMISC_EN);
63 }
64 
65 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
66 			malta_piix_func3_base_fixup);
67 
malta_piix_func0_fixup(struct pci_dev * pdev)68 static void malta_piix_func0_fixup(struct pci_dev *pdev)
69 {
70 	unsigned char reg_val;
71 	u32 reg_val32;
72 	u16 reg_val16;
73 	/* PIIX PIRQC[A:D] irq mappings */
74 	static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
75 		0,  0,	0,  3,
76 		4,  5,	6,  7,
77 		0,  9, 10, 11,
78 		12, 0, 14, 15
79 	};
80 	int i;
81 
82 	/* Interrogate PIIX4 to get PCI IRQ mapping */
83 	for (i = 0; i <= 3; i++) {
84 		pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);
85 		if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
86 			pci_irq[PCIA+i] = 0;	/* Disabled */
87 		else
88 			pci_irq[PCIA+i] = piixirqmap[reg_val &
89 				PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
90 	}
91 
92 	/* Done by YAMON 2.00 onwards */
93 	if (PCI_SLOT(pdev->devfn) == 10) {
94 		/*
95 		 * Set top of main memory accessible by ISA or DMA
96 		 * devices to 16 Mb.
97 		 */
98 		pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);
99 		pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
100 				PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
101 	}
102 
103 	/* Mux SERIRQ to its pin */
104 	pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
105 	pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
106 			       reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
107 
108 	/* Enable SERIRQ */
109 	pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
110 	reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
111 	pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
112 
113 	/* Enable response to special cycles */
114 	pci_read_config_word(pdev, PCI_COMMAND, &reg_val16);
115 	pci_write_config_word(pdev, PCI_COMMAND,
116 			      reg_val16 | PCI_COMMAND_SPECIAL);
117 }
118 
119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
120 	 malta_piix_func0_fixup);
121 
malta_piix_func1_fixup(struct pci_dev * pdev)122 static void malta_piix_func1_fixup(struct pci_dev *pdev)
123 {
124 	unsigned char reg_val;
125 
126 	/* Done by YAMON 2.02 onwards */
127 	if (PCI_SLOT(pdev->devfn) == 10) {
128 		/*
129 		 * IDE Decode enable.
130 		 */
131 		pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
132 			&reg_val);
133 		pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
134 			reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
135 		pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
136 			&reg_val);
137 		pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
138 			reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
139 	}
140 }
141 
142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
143 	 malta_piix_func1_fixup);
144 
145 /* Enable PCI 2.1 compatibility in PIIX4 */
quirk_dlcsetup(struct pci_dev * dev)146 static void quirk_dlcsetup(struct pci_dev *dev)
147 {
148 	u8 odlc, ndlc;
149 
150 	(void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
151 	/* Enable passive releases and delayed transaction */
152 	ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN |
153 		      PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN |
154 		      PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
155 	(void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
156 }
157 
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
159 	quirk_dlcsetup);
160