xref: /openbmc/u-boot/arch/x86/cpu/quark/quark.c (revision 2ae23a28)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4  */
5 
6 #include <common.h>
7 #include <mmc.h>
8 #include <asm/io.h>
9 #include <asm/ioapic.h>
10 #include <asm/irq.h>
11 #include <asm/mrccache.h>
12 #include <asm/mtrr.h>
13 #include <asm/pci.h>
14 #include <asm/post.h>
15 #include <asm/arch/device.h>
16 #include <asm/arch/msg_port.h>
17 #include <asm/arch/quark.h>
18 
quark_setup_mtrr(void)19 static void quark_setup_mtrr(void)
20 {
21 	u32 base, mask;
22 	int i;
23 
24 	disable_caches();
25 
26 	/* mark the VGA RAM area as uncacheable */
27 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
28 		       MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
29 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
30 		       MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
31 
32 	/* mark other fixed range areas as cacheable */
33 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
34 		       MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
35 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
36 		       MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
37 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
38 		       MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
39 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
40 		       MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
41 	for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
42 		msg_port_write(MSG_PORT_HOST_BRIDGE, i,
43 			       MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
44 
45 	/* variable range MTRR#0: ROM area */
46 	mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
47 	base = CONFIG_SYS_TEXT_BASE & mask;
48 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
49 		       base | MTRR_TYPE_WRBACK);
50 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
51 		       mask | MTRR_PHYS_MASK_VALID);
52 
53 	/* variable range MTRR#1: eSRAM area */
54 	mask = ~(ESRAM_SIZE - 1);
55 	base = CONFIG_ESRAM_BASE & mask;
56 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
57 		       base | MTRR_TYPE_WRBACK);
58 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
59 		       mask | MTRR_PHYS_MASK_VALID);
60 
61 	/* enable both variable and fixed range MTRRs */
62 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
63 		       MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
64 
65 	enable_caches();
66 }
67 
quark_setup_bars(void)68 static void quark_setup_bars(void)
69 {
70 	/* GPIO - D31:F0:R44h */
71 	qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
72 				   CONFIG_GPIO_BASE | IO_BAR_EN);
73 
74 	/* ACPI PM1 Block - D31:F0:R48h */
75 	qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
76 				   CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
77 
78 	/* GPE0 - D31:F0:R4Ch */
79 	qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
80 				   CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
81 
82 	/* WDT - D31:F0:R84h */
83 	qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
84 				   CONFIG_WDT_BASE | IO_BAR_EN);
85 
86 	/* RCBA - D31:F0:RF0h */
87 	qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
88 				   CONFIG_RCBA_BASE | MEM_BAR_EN);
89 
90 	/* ACPI P Block - Msg Port 04:R70h */
91 	msg_port_write(MSG_PORT_RMU, PBLK_BA,
92 		       CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
93 
94 	/* SPI DMA - Msg Port 04:R7Ah */
95 	msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
96 		       CONFIG_SPI_DMA_BASE | IO_BAR_EN);
97 
98 	/* PCIe ECAM */
99 	msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
100 		       CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
101 	msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
102 		       CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
103 }
104 
quark_pcie_early_init(void)105 static void quark_pcie_early_init(void)
106 {
107 	/*
108 	 * Step1: Assert PCIe signal PERST#
109 	 *
110 	 * The CPU interface to the PERST# signal is platform dependent.
111 	 * Call the board-specific codes to perform this task.
112 	 */
113 	board_assert_perst();
114 
115 	/* Step2: PHY common lane reset */
116 	msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
117 	/* wait 1 ms for PHY common lane reset */
118 	mdelay(1);
119 
120 	/* Step3: PHY sideband interface reset and controller main reset */
121 	msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
122 			     PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
123 	/* wait 80ms for PLL to lock */
124 	mdelay(80);
125 
126 	/* Step4: Controller sideband interface reset */
127 	msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
128 	/* wait 20ms for controller sideband interface reset */
129 	mdelay(20);
130 
131 	/* Step5: De-assert PERST# */
132 	board_deassert_perst();
133 
134 	/* Step6: Controller primary interface reset */
135 	msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
136 
137 	/* Mixer Load Lane 0 */
138 	msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
139 			    (1 << 6) | (1 << 7));
140 
141 	/* Mixer Load Lane 1 */
142 	msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
143 			    (1 << 6) | (1 << 7));
144 }
145 
quark_usb_early_init(void)146 static void quark_usb_early_init(void)
147 {
148 	/* The sequence below comes from Quark firmware writer guide */
149 
150 	msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
151 				1 << 1, (1 << 6) | (1 << 7));
152 
153 	msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
154 				(1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
155 
156 	msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
157 
158 	msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
159 
160 	msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
161 				(1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
162 
163 	msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
164 
165 	msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
166 }
167 
quark_thermal_early_init(void)168 static void quark_thermal_early_init(void)
169 {
170 	/* The sequence below comes from Quark firmware writer guide */
171 
172 	/* thermal sensor mode config */
173 	msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
174 				(1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
175 	msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
176 				(1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
177 				(1 << 12), 1 << 9);
178 	msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
179 	msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
180 	msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
181 	msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
182 	msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
183 	msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
184 				(1 << 8) | (1 << 9), 1 << 8);
185 	msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
186 	msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
187 				0x7ff800, 0xc8 << 11);
188 
189 	/* thermal monitor catastrophic trip set point (105 celsius) */
190 	msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
191 
192 	/* thermal monitor catastrophic trip clear point (0 celsius) */
193 	msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
194 
195 	/* take thermal sensor out of reset */
196 	msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
197 
198 	/* enable thermal monitor */
199 	msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
200 
201 	/* lock all thermal configuration */
202 	msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
203 }
204 
quark_enable_legacy_seg(void)205 static void quark_enable_legacy_seg(void)
206 {
207 	msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
208 			 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
209 }
210 
arch_cpu_init(void)211 int arch_cpu_init(void)
212 {
213 	int ret;
214 
215 	post_code(POST_CPU_INIT);
216 
217 	ret = x86_cpu_init_f();
218 	if (ret)
219 		return ret;
220 
221 	/*
222 	 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
223 	 * are accessed indirectly via the message port and not the traditional
224 	 * MSR mechanism. Only UC, WT and WB cache types are supported.
225 	 */
226 	quark_setup_mtrr();
227 
228 	/*
229 	 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
230 	 * which need be initialized with suggested values
231 	 */
232 	quark_setup_bars();
233 
234 	/* Initialize USB2 PHY */
235 	quark_usb_early_init();
236 
237 	/* Initialize thermal sensor */
238 	quark_thermal_early_init();
239 
240 	/* Turn on legacy segments (A/B/E/F) decode to system RAM */
241 	quark_enable_legacy_seg();
242 
243 	return 0;
244 }
245 
arch_cpu_init_dm(void)246 int arch_cpu_init_dm(void)
247 {
248 	/*
249 	 * Initialize PCIe controller
250 	 *
251 	 * Quark SoC holds the PCIe controller in reset following a power on.
252 	 * U-Boot needs to release the PCIe controller from reset. The PCIe
253 	 * controller (D23:F0/F1) will not be visible in PCI configuration
254 	 * space and any access to its PCI configuration registers will cause
255 	 * system hang while it is held in reset.
256 	 */
257 	quark_pcie_early_init();
258 
259 	return 0;
260 }
261 
checkcpu(void)262 int checkcpu(void)
263 {
264 	return 0;
265 }
266 
print_cpuinfo(void)267 int print_cpuinfo(void)
268 {
269 	post_code(POST_CPU_INFO);
270 	return default_print_cpuinfo();
271 }
272 
quark_pcie_init(void)273 static void quark_pcie_init(void)
274 {
275 	u32 val;
276 
277 	/* PCIe upstream non-posted & posted request size */
278 	qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
279 				   CCFG_UPRS | CCFG_UNRS);
280 	qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
281 				   CCFG_UPRS | CCFG_UNRS);
282 
283 	/* PCIe packet fast transmit mode (IPF) */
284 	qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
285 	qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
286 
287 	/* PCIe message bus idle counter (SBIC) */
288 	qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
289 	val |= MBC_SBIC;
290 	qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
291 	qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
292 	val |= MBC_SBIC;
293 	qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
294 }
295 
quark_usb_init(void)296 static void quark_usb_init(void)
297 {
298 	u32 bar;
299 
300 	/* Change USB EHCI packet buffer OUT/IN threshold */
301 	qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
302 	writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
303 
304 	/* Disable USB device interrupts */
305 	qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
306 	writel(0x7f, bar + USBD_INT_MASK);
307 	writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
308 	writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
309 }
310 
quark_irq_init(void)311 static void quark_irq_init(void)
312 {
313 	struct quark_rcba *rcba;
314 	u32 base;
315 
316 	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
317 	base &= ~MEM_BAR_EN;
318 	rcba = (struct quark_rcba *)base;
319 
320 	/*
321 	 * Route Quark PCI device interrupt pin to PIRQ
322 	 *
323 	 * Route device#23's INTA/B/C/D to PIRQA/B/C/D
324 	 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
325 	 */
326 	writew(PIRQC, &rcba->rmu_ir);
327 	writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
328 	       &rcba->d23_ir);
329 	writew(PIRQD, &rcba->core_ir);
330 	writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
331 	       &rcba->d20d21_ir);
332 }
333 
arch_early_init_r(void)334 int arch_early_init_r(void)
335 {
336 	quark_pcie_init();
337 
338 	quark_usb_init();
339 
340 	quark_irq_init();
341 
342 	return 0;
343 }
344 
arch_misc_init(void)345 int arch_misc_init(void)
346 {
347 #ifdef CONFIG_ENABLE_MRC_CACHE
348 	/*
349 	 * We intend not to check any return value here, as even MRC cache
350 	 * is not saved successfully, it is not a severe error that will
351 	 * prevent system from continuing to boot.
352 	 */
353 	mrccache_save();
354 #endif
355 
356 	/* Assign a unique I/O APIC ID */
357 	io_apic_set_id(1);
358 
359 	return 0;
360 }
361 
board_final_cleanup(void)362 void board_final_cleanup(void)
363 {
364 	struct quark_rcba *rcba;
365 	u32 base, val;
366 
367 	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
368 	base &= ~MEM_BAR_EN;
369 	rcba = (struct quark_rcba *)base;
370 
371 	/* Initialize 'Component ID' to zero */
372 	val = readl(&rcba->esd);
373 	val &= ~0xff0000;
374 	writel(val, &rcba->esd);
375 
376 	/* Lock HMBOUND for security */
377 	msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
378 
379 	return;
380 }
381