xref: /openbmc/linux/drivers/media/tuners/qt1010.c (revision 86495af1)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Driver for Quantek QT1010 silicon tuner
4  *
5  *  Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
6  *                     Aapo Tahkola <aet@rasterburn.org>
7  */
8 #include "qt1010.h"
9 #include "qt1010_priv.h"
10 
11 /* read single register */
qt1010_readreg(struct qt1010_priv * priv,u8 reg,u8 * val)12 static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
13 {
14 	struct i2c_msg msg[2] = {
15 		{ .addr = priv->cfg->i2c_address,
16 		  .flags = 0, .buf = &reg, .len = 1 },
17 		{ .addr = priv->cfg->i2c_address,
18 		  .flags = I2C_M_RD, .buf = val, .len = 1 },
19 	};
20 
21 	if (i2c_transfer(priv->i2c, msg, 2) != 2) {
22 		dev_warn(&priv->i2c->dev, "%s: i2c rd failed reg=%02x\n",
23 				KBUILD_MODNAME, reg);
24 		return -EREMOTEIO;
25 	}
26 	return 0;
27 }
28 
29 /* write single register */
qt1010_writereg(struct qt1010_priv * priv,u8 reg,u8 val)30 static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
31 {
32 	u8 buf[2] = { reg, val };
33 	struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
34 			       .flags = 0, .buf = buf, .len = 2 };
35 
36 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
37 		dev_warn(&priv->i2c->dev, "%s: i2c wr failed reg=%02x\n",
38 				KBUILD_MODNAME, reg);
39 		return -EREMOTEIO;
40 	}
41 	return 0;
42 }
43 
qt1010_set_params(struct dvb_frontend * fe)44 static int qt1010_set_params(struct dvb_frontend *fe)
45 {
46 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
47 	struct qt1010_priv *priv;
48 	int err;
49 	u32 freq, div, mod1, mod2;
50 	u8 i, tmpval, reg05;
51 	qt1010_i2c_oper_t rd[48] = {
52 		{ QT1010_WR, 0x01, 0x80 },
53 		{ QT1010_WR, 0x02, 0x3f },
54 		{ QT1010_WR, 0x05, 0xff }, /* 02 c write */
55 		{ QT1010_WR, 0x06, 0x44 },
56 		{ QT1010_WR, 0x07, 0xff }, /* 04 c write */
57 		{ QT1010_WR, 0x08, 0x08 },
58 		{ QT1010_WR, 0x09, 0xff }, /* 06 c write */
59 		{ QT1010_WR, 0x0a, 0xff }, /* 07 c write */
60 		{ QT1010_WR, 0x0b, 0xff }, /* 08 c write */
61 		{ QT1010_WR, 0x0c, 0xe1 },
62 		{ QT1010_WR, 0x1a, 0xff }, /* 10 c write */
63 		{ QT1010_WR, 0x1b, 0x00 },
64 		{ QT1010_WR, 0x1c, 0x89 },
65 		{ QT1010_WR, 0x11, 0xff }, /* 13 c write */
66 		{ QT1010_WR, 0x12, 0xff }, /* 14 c write */
67 		{ QT1010_WR, 0x22, 0xff }, /* 15 c write */
68 		{ QT1010_WR, 0x1e, 0x00 },
69 		{ QT1010_WR, 0x1e, 0xd0 },
70 		{ QT1010_RD, 0x22, 0xff }, /* 16 c read */
71 		{ QT1010_WR, 0x1e, 0x00 },
72 		{ QT1010_RD, 0x05, 0xff }, /* 20 c read */
73 		{ QT1010_RD, 0x22, 0xff }, /* 21 c read */
74 		{ QT1010_WR, 0x23, 0xd0 },
75 		{ QT1010_WR, 0x1e, 0x00 },
76 		{ QT1010_WR, 0x1e, 0xe0 },
77 		{ QT1010_RD, 0x23, 0xff }, /* 25 c read */
78 		{ QT1010_RD, 0x23, 0xff }, /* 26 c read */
79 		{ QT1010_WR, 0x1e, 0x00 },
80 		{ QT1010_WR, 0x24, 0xd0 },
81 		{ QT1010_WR, 0x1e, 0x00 },
82 		{ QT1010_WR, 0x1e, 0xf0 },
83 		{ QT1010_RD, 0x24, 0xff }, /* 31 c read */
84 		{ QT1010_WR, 0x1e, 0x00 },
85 		{ QT1010_WR, 0x14, 0x7f },
86 		{ QT1010_WR, 0x15, 0x7f },
87 		{ QT1010_WR, 0x05, 0xff }, /* 35 c write */
88 		{ QT1010_WR, 0x06, 0x00 },
89 		{ QT1010_WR, 0x15, 0x1f },
90 		{ QT1010_WR, 0x16, 0xff },
91 		{ QT1010_WR, 0x18, 0xff },
92 		{ QT1010_WR, 0x1f, 0xff }, /* 40 c write */
93 		{ QT1010_WR, 0x20, 0xff }, /* 41 c write */
94 		{ QT1010_WR, 0x21, 0x53 },
95 		{ QT1010_WR, 0x25, 0xff }, /* 43 c write */
96 		{ QT1010_WR, 0x26, 0x15 },
97 		{ QT1010_WR, 0x00, 0xff }, /* 45 c write */
98 		{ QT1010_WR, 0x02, 0x00 },
99 		{ QT1010_WR, 0x01, 0x00 }
100 	};
101 
102 #define FREQ1 32000000 /* 32 MHz */
103 #define FREQ2  4000000 /* 4 MHz Quartz oscillator in the stick? */
104 
105 	priv = fe->tuner_priv;
106 	freq = c->frequency;
107 	div = (freq + QT1010_OFFSET) / QT1010_STEP;
108 	freq = (div * QT1010_STEP) - QT1010_OFFSET;
109 	mod1 = (freq + QT1010_OFFSET) % FREQ1;
110 	mod2 = (freq + QT1010_OFFSET) % FREQ2;
111 	priv->frequency = freq;
112 
113 	if (fe->ops.i2c_gate_ctrl)
114 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
115 
116 	/* reg 05 base value */
117 	if      (freq < 290000000) reg05 = 0x14; /* 290 MHz */
118 	else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
119 	else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
120 	else                       reg05 = 0x74;
121 
122 	/* 0x5 */
123 	rd[2].val = reg05;
124 
125 	/* 07 - set frequency: 32 MHz scale */
126 	rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
127 
128 	/* 09 - changes every 8/24 MHz */
129 	if (mod1 < 8000000) rd[6].val = 0x1d;
130 	else                rd[6].val = 0x1c;
131 
132 	/* 0a - set frequency: 4 MHz scale (max 28 MHz) */
133 	if      (mod1 < 1*FREQ2) rd[7].val = 0x09; /*  +0 MHz */
134 	else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /*  +4 MHz */
135 	else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /*  +8 MHz */
136 	else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
137 	else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
138 	else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
139 	else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
140 	else                     rd[7].val = 0x0a; /* +28 MHz */
141 
142 	/* 0b - changes every 2/2 MHz */
143 	if (mod2 < 2000000) rd[8].val = 0x45;
144 	else                rd[8].val = 0x44;
145 
146 	/* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
147 	tmpval = 0x78; /* byte, overflows intentionally */
148 	rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
149 
150 	/* 11 */
151 	rd[13].val = 0xfd; /* TODO: correct value calculation */
152 
153 	/* 12 */
154 	rd[14].val = 0x91; /* TODO: correct value calculation */
155 
156 	/* 22 */
157 	if      (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
158 	else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
159 	else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
160 	else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
161 	else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
162 	else                       rd[15].val = 0xd0;
163 
164 	/* 05 */
165 	rd[35].val = (reg05 & 0xf0);
166 
167 	/* 1f */
168 	if      (mod1 <  8000000) tmpval = 0x00;
169 	else if (mod1 < 12000000) tmpval = 0x01;
170 	else if (mod1 < 16000000) tmpval = 0x02;
171 	else if (mod1 < 24000000) tmpval = 0x03;
172 	else if (mod1 < 28000000) tmpval = 0x04;
173 	else                      tmpval = 0x05;
174 	rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
175 
176 	/* 20 */
177 	if      (mod1 <  8000000) tmpval = 0x00;
178 	else if (mod1 < 12000000) tmpval = 0x01;
179 	else if (mod1 < 20000000) tmpval = 0x02;
180 	else if (mod1 < 24000000) tmpval = 0x03;
181 	else if (mod1 < 28000000) tmpval = 0x04;
182 	else                      tmpval = 0x05;
183 	rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
184 
185 	/* 25 */
186 	rd[43].val = priv->reg25_init_val;
187 
188 	/* 00 */
189 	rd[45].val = 0x92; /* TODO: correct value calculation */
190 
191 	dev_dbg(&priv->i2c->dev,
192 			"%s: freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \
193 			"1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \
194 			"20:%02x 25:%02x 00:%02x\n", __func__, \
195 			freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \
196 			rd[8].val, rd[10].val, rd[13].val, rd[14].val, \
197 			rd[15].val, rd[35].val, rd[40].val, rd[41].val, \
198 			rd[43].val, rd[45].val);
199 
200 	for (i = 0; i < ARRAY_SIZE(rd); i++) {
201 		if (rd[i].oper == QT1010_WR) {
202 			err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
203 		} else { /* read is required to proper locking */
204 			err = qt1010_readreg(priv, rd[i].reg, &tmpval);
205 		}
206 		if (err) return err;
207 	}
208 
209 	if (fe->ops.i2c_gate_ctrl)
210 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
211 
212 	return 0;
213 }
214 
qt1010_init_meas1(struct qt1010_priv * priv,u8 oper,u8 reg,u8 reg_init_val,u8 * retval)215 static int qt1010_init_meas1(struct qt1010_priv *priv,
216 			     u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
217 {
218 	u8 i, val1, val2;
219 	int err;
220 
221 	qt1010_i2c_oper_t i2c_data[] = {
222 		{ QT1010_WR, reg, reg_init_val },
223 		{ QT1010_WR, 0x1e, 0x00 },
224 		{ QT1010_WR, 0x1e, oper },
225 	};
226 
227 	for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
228 		err = qt1010_writereg(priv, i2c_data[i].reg,
229 				      i2c_data[i].val);
230 		if (err)
231 			return err;
232 	}
233 
234 	err = qt1010_readreg(priv, reg, &val2);
235 	if (err)
236 		return err;
237 	do {
238 		val1 = val2;
239 		err = qt1010_readreg(priv, reg, &val2);
240 		if (err)
241 			return err;
242 
243 		dev_dbg(&priv->i2c->dev, "%s: compare reg:%02x %02x %02x\n",
244 				__func__, reg, val1, val2);
245 	} while (val1 != val2);
246 	*retval = val1;
247 
248 	return qt1010_writereg(priv, 0x1e, 0x00);
249 }
250 
qt1010_init_meas2(struct qt1010_priv * priv,u8 reg_init_val,u8 * retval)251 static int qt1010_init_meas2(struct qt1010_priv *priv,
252 			    u8 reg_init_val, u8 *retval)
253 {
254 	u8 i, val = 0xff;
255 	int err;
256 	qt1010_i2c_oper_t i2c_data[] = {
257 		{ QT1010_WR, 0x07, reg_init_val },
258 		{ QT1010_WR, 0x22, 0xd0 },
259 		{ QT1010_WR, 0x1e, 0x00 },
260 		{ QT1010_WR, 0x1e, 0xd0 },
261 		{ QT1010_RD, 0x22, 0xff },
262 		{ QT1010_WR, 0x1e, 0x00 },
263 		{ QT1010_WR, 0x22, 0xff }
264 	};
265 
266 	for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
267 		if (i2c_data[i].oper == QT1010_WR) {
268 			err = qt1010_writereg(priv, i2c_data[i].reg,
269 					      i2c_data[i].val);
270 		} else {
271 			err = qt1010_readreg(priv, i2c_data[i].reg, &val);
272 		}
273 		if (err)
274 			return err;
275 	}
276 	*retval = val;
277 	return 0;
278 }
279 
qt1010_init(struct dvb_frontend * fe)280 static int qt1010_init(struct dvb_frontend *fe)
281 {
282 	struct qt1010_priv *priv = fe->tuner_priv;
283 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
284 	int err = 0;
285 	u8 i, tmpval, *valptr = NULL;
286 
287 	static const qt1010_i2c_oper_t i2c_data[] = {
288 		{ QT1010_WR, 0x01, 0x80 },
289 		{ QT1010_WR, 0x0d, 0x84 },
290 		{ QT1010_WR, 0x0e, 0xb7 },
291 		{ QT1010_WR, 0x2a, 0x23 },
292 		{ QT1010_WR, 0x2c, 0xdc },
293 		{ QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
294 		{ QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
295 		{ QT1010_WR, 0x2b, 0x70 },
296 		{ QT1010_WR, 0x2a, 0x23 },
297 		{ QT1010_M1, 0x26, 0x08 },
298 		{ QT1010_M1, 0x82, 0xff },
299 		{ QT1010_WR, 0x05, 0x14 },
300 		{ QT1010_WR, 0x06, 0x44 },
301 		{ QT1010_WR, 0x07, 0x28 },
302 		{ QT1010_WR, 0x08, 0x0b },
303 		{ QT1010_WR, 0x11, 0xfd },
304 		{ QT1010_M1, 0x22, 0x0d },
305 		{ QT1010_M1, 0xd0, 0xff },
306 		{ QT1010_WR, 0x06, 0x40 },
307 		{ QT1010_WR, 0x16, 0xf0 },
308 		{ QT1010_WR, 0x02, 0x38 },
309 		{ QT1010_WR, 0x03, 0x18 },
310 		{ QT1010_WR, 0x20, 0xe0 },
311 		{ QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
312 		{ QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
313 		{ QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
314 		{ QT1010_WR, 0x03, 0x19 },
315 		{ QT1010_WR, 0x02, 0x3f },
316 		{ QT1010_WR, 0x21, 0x53 },
317 		{ QT1010_RD, 0x21, 0xff },
318 		{ QT1010_WR, 0x11, 0xfd },
319 		{ QT1010_WR, 0x05, 0x34 },
320 		{ QT1010_WR, 0x06, 0x44 },
321 		{ QT1010_WR, 0x08, 0x08 }
322 	};
323 
324 	if (fe->ops.i2c_gate_ctrl)
325 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
326 
327 	for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
328 		switch (i2c_data[i].oper) {
329 		case QT1010_WR:
330 			err = qt1010_writereg(priv, i2c_data[i].reg,
331 					      i2c_data[i].val);
332 			break;
333 		case QT1010_RD:
334 			if (i2c_data[i].val == 0x20)
335 				valptr = &priv->reg20_init_val;
336 			else
337 				valptr = &tmpval;
338 			err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
339 			break;
340 		case QT1010_M1:
341 			if (i2c_data[i].val == 0x25)
342 				valptr = &priv->reg25_init_val;
343 			else if (i2c_data[i].val == 0x1f)
344 				valptr = &priv->reg1f_init_val;
345 			else
346 				valptr = &tmpval;
347 
348 			if (i >= ARRAY_SIZE(i2c_data) - 1)
349 				err = -EIO;
350 			else
351 				err = qt1010_init_meas1(priv, i2c_data[i + 1].reg,
352 							i2c_data[i].reg,
353 							i2c_data[i].val, valptr);
354 			i++;
355 			break;
356 		}
357 		if (err)
358 			return err;
359 	}
360 
361 	for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
362 		if ((err = qt1010_init_meas2(priv, i, &tmpval)))
363 			return err;
364 
365 	if (!c->frequency)
366 		c->frequency = 545000000; /* Sigmatek DVB-110 545000000 */
367 				      /* MSI Megasky 580 GL861 533000000 */
368 	return qt1010_set_params(fe);
369 }
370 
qt1010_release(struct dvb_frontend * fe)371 static void qt1010_release(struct dvb_frontend *fe)
372 {
373 	kfree(fe->tuner_priv);
374 	fe->tuner_priv = NULL;
375 }
376 
qt1010_get_frequency(struct dvb_frontend * fe,u32 * frequency)377 static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
378 {
379 	struct qt1010_priv *priv = fe->tuner_priv;
380 	*frequency = priv->frequency;
381 	return 0;
382 }
383 
qt1010_get_if_frequency(struct dvb_frontend * fe,u32 * frequency)384 static int qt1010_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
385 {
386 	*frequency = 36125000;
387 	return 0;
388 }
389 
390 static const struct dvb_tuner_ops qt1010_tuner_ops = {
391 	.info = {
392 		.name              = "Quantek QT1010",
393 		.frequency_min_hz  = QT1010_MIN_FREQ,
394 		.frequency_max_hz  = QT1010_MAX_FREQ,
395 		.frequency_step_hz = QT1010_STEP,
396 	},
397 
398 	.release       = qt1010_release,
399 	.init          = qt1010_init,
400 	/* TODO: implement sleep */
401 
402 	.set_params    = qt1010_set_params,
403 	.get_frequency = qt1010_get_frequency,
404 	.get_if_frequency = qt1010_get_if_frequency,
405 };
406 
qt1010_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,struct qt1010_config * cfg)407 struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
408 				    struct i2c_adapter *i2c,
409 				    struct qt1010_config *cfg)
410 {
411 	struct qt1010_priv *priv = NULL;
412 	u8 id;
413 
414 	priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
415 	if (priv == NULL)
416 		return NULL;
417 
418 	priv->cfg = cfg;
419 	priv->i2c = i2c;
420 
421 	if (fe->ops.i2c_gate_ctrl)
422 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
423 
424 
425 	/* Try to detect tuner chip. Probably this is not correct register. */
426 	if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
427 		kfree(priv);
428 		return NULL;
429 	}
430 
431 	if (fe->ops.i2c_gate_ctrl)
432 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
433 
434 	dev_info(&priv->i2c->dev,
435 			"%s: Quantek QT1010 successfully identified\n",
436 			KBUILD_MODNAME);
437 
438 	memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops,
439 	       sizeof(struct dvb_tuner_ops));
440 
441 	fe->tuner_priv = priv;
442 	return fe;
443 }
444 EXPORT_SYMBOL_GPL(qt1010_attach);
445 
446 MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
447 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
448 MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
449 MODULE_VERSION("0.1");
450 MODULE_LICENSE("GPL");
451