1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: QPLib resource manager (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RES_H__ 40 #define __BNXT_QPLIB_RES_H__ 41 42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; 43 44 #define CHIP_NUM_57508 0x1750 45 #define CHIP_NUM_57504 0x1751 46 #define CHIP_NUM_57502 0x1752 47 #define CHIP_NUM_58818 0xd818 48 #define CHIP_NUM_57608 0x1760 49 50 51 struct bnxt_qplib_drv_modes { 52 u8 wqe_mode; 53 bool db_push; 54 bool dbr_pacing; 55 }; 56 57 struct bnxt_qplib_chip_ctx { 58 u16 chip_num; 59 u8 chip_rev; 60 u8 chip_metal; 61 u16 hw_stats_size; 62 u16 hwrm_cmd_max_timeout; 63 struct bnxt_qplib_drv_modes modes; 64 u64 hwrm_intf_ver; 65 u32 dbr_stat_db_fifo; 66 }; 67 68 struct bnxt_qplib_db_pacing_data { 69 u32 do_pacing; 70 u32 pacing_th; 71 u32 alarm_th; 72 u32 fifo_max_depth; 73 u32 fifo_room_mask; 74 u32 fifo_room_shift; 75 u32 grc_reg_offset; 76 }; 77 78 #define BNXT_QPLIB_DBR_PF_DB_OFFSET 0x10000 79 #define BNXT_QPLIB_DBR_VF_DB_OFFSET 0x4000 80 81 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 82 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 83 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) 84 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG) 85 86 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1)) 87 88 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \ 89 ((HWQ_CMP(hwq->prod, hwq)\ 90 - HWQ_CMP(hwq->cons, hwq))\ 91 & (hwq->max_elements - 1))) 92 enum bnxt_qplib_hwq_type { 93 HWQ_TYPE_CTX, 94 HWQ_TYPE_QUEUE, 95 HWQ_TYPE_L2_CMPL, 96 HWQ_TYPE_MR 97 }; 98 99 #define MAX_PBL_LVL_0_PGS 1 100 #define MAX_PBL_LVL_1_PGS 512 101 #define MAX_PBL_LVL_1_PGS_SHIFT 9 102 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256 103 #define MAX_PBL_LVL_2_PGS (256 * 512) 104 #define MAX_PDL_LVL_SHIFT 9 105 106 enum bnxt_qplib_pbl_lvl { 107 PBL_LVL_0, 108 PBL_LVL_1, 109 PBL_LVL_2, 110 PBL_LVL_MAX 111 }; 112 113 #define ROCE_PG_SIZE_4K (4 * 1024) 114 #define ROCE_PG_SIZE_8K (8 * 1024) 115 #define ROCE_PG_SIZE_64K (64 * 1024) 116 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024) 117 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024) 118 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024) 119 120 enum bnxt_qplib_hwrm_pg_size { 121 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0, 122 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1, 123 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2, 124 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3, 125 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4, 126 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5, 127 }; 128 129 struct bnxt_qplib_reg_desc { 130 u8 bar_id; 131 resource_size_t bar_base; 132 unsigned long offset; 133 void __iomem *bar_reg; 134 size_t len; 135 }; 136 137 struct bnxt_qplib_pbl { 138 u32 pg_count; 139 u32 pg_size; 140 void **pg_arr; 141 dma_addr_t *pg_map_arr; 142 }; 143 144 struct bnxt_qplib_sg_info { 145 struct ib_umem *umem; 146 u32 npages; 147 u32 pgshft; 148 u32 pgsize; 149 bool nopte; 150 }; 151 152 struct bnxt_qplib_hwq_attr { 153 struct bnxt_qplib_res *res; 154 struct bnxt_qplib_sg_info *sginfo; 155 enum bnxt_qplib_hwq_type type; 156 u32 depth; 157 u32 stride; 158 u32 aux_stride; 159 u32 aux_depth; 160 }; 161 162 struct bnxt_qplib_hwq { 163 struct pci_dev *pdev; 164 /* lock to protect qplib_hwq */ 165 spinlock_t lock; 166 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1]; 167 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */ 168 /* ptr for easy access to the PBL entries */ 169 void **pbl_ptr; 170 /* ptr for easy access to the dma_addr */ 171 dma_addr_t *pbl_dma_ptr; 172 u32 max_elements; 173 u32 depth; 174 u16 element_size; /* Size of each entry */ 175 u16 qe_ppg; /* queue entry per page */ 176 177 u32 prod; /* raw */ 178 u32 cons; /* raw */ 179 u8 cp_bit; 180 u8 is_user; 181 u64 *pad_pg; 182 u32 pad_stride; 183 u32 pad_pgofft; 184 }; 185 186 struct bnxt_qplib_db_info { 187 void __iomem *db; 188 void __iomem *priv_db; 189 struct bnxt_qplib_hwq *hwq; 190 u32 xid; 191 u32 max_slot; 192 u32 flags; 193 }; 194 195 enum bnxt_qplib_db_info_flags_mask { 196 BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT = 0x0UL, 197 BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT = 0x1UL, 198 BNXT_QPLIB_FLAG_EPOCH_CONS_MASK = 0x1UL, 199 BNXT_QPLIB_FLAG_EPOCH_PROD_MASK = 0x2UL, 200 }; 201 202 /* Tables */ 203 struct bnxt_qplib_pd_tbl { 204 unsigned long *tbl; 205 u32 max; 206 }; 207 208 struct bnxt_qplib_sgid_tbl { 209 struct bnxt_qplib_gid_info *tbl; 210 u16 *hw_id; 211 u16 max; 212 u16 active; 213 void *ctx; 214 u8 *vlan; 215 }; 216 217 enum { 218 BNXT_QPLIB_DPI_TYPE_KERNEL = 0, 219 BNXT_QPLIB_DPI_TYPE_UC = 1, 220 BNXT_QPLIB_DPI_TYPE_WC = 2 221 }; 222 223 struct bnxt_qplib_dpi { 224 u32 dpi; 225 u32 bit; 226 void __iomem *dbr; 227 u64 umdbr; 228 u8 type; 229 }; 230 231 struct bnxt_qplib_dpi_tbl { 232 void **app_tbl; 233 unsigned long *tbl; 234 u16 max; 235 struct bnxt_qplib_reg_desc ucreg; /* Hold entire DB bar. */ 236 struct bnxt_qplib_reg_desc wcreg; 237 void __iomem *priv_db; 238 }; 239 240 struct bnxt_qplib_stats { 241 dma_addr_t dma_map; 242 void *dma; 243 u32 size; 244 u32 fw_id; 245 }; 246 247 struct bnxt_qplib_vf_res { 248 u32 max_qp_per_vf; 249 u32 max_mrw_per_vf; 250 u32 max_srq_per_vf; 251 u32 max_cq_per_vf; 252 u32 max_gid_per_vf; 253 }; 254 255 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448 256 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64 257 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64 258 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128 259 260 #define MAX_TQM_ALLOC_REQ 48 261 #define MAX_TQM_ALLOC_BLK_SIZE 8 262 struct bnxt_qplib_tqm_ctx { 263 struct bnxt_qplib_hwq pde; 264 u8 pde_level; /* Original level */ 265 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ]; 266 u8 qcount[MAX_TQM_ALLOC_REQ]; 267 }; 268 269 struct bnxt_qplib_ctx { 270 u32 qpc_count; 271 struct bnxt_qplib_hwq qpc_tbl; 272 u32 mrw_count; 273 struct bnxt_qplib_hwq mrw_tbl; 274 u32 srqc_count; 275 struct bnxt_qplib_hwq srqc_tbl; 276 u32 cq_count; 277 struct bnxt_qplib_hwq cq_tbl; 278 struct bnxt_qplib_hwq tim_tbl; 279 struct bnxt_qplib_tqm_ctx tqm_ctx; 280 struct bnxt_qplib_stats stats; 281 struct bnxt_qplib_vf_res vf_res; 282 }; 283 284 struct bnxt_qplib_res { 285 struct pci_dev *pdev; 286 struct bnxt_qplib_chip_ctx *cctx; 287 struct bnxt_qplib_dev_attr *dattr; 288 struct net_device *netdev; 289 struct bnxt_qplib_rcfw *rcfw; 290 struct bnxt_qplib_pd_tbl pd_tbl; 291 /* To protect the pd table bit map */ 292 struct mutex pd_tbl_lock; 293 struct bnxt_qplib_sgid_tbl sgid_tbl; 294 struct bnxt_qplib_dpi_tbl dpi_tbl; 295 /* To protect the dpi table bit map */ 296 struct mutex dpi_tbl_lock; 297 bool prio; 298 bool is_vf; 299 struct bnxt_qplib_db_pacing_data *pacing_data; 300 }; 301 bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx * cctx)302 static inline bool bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx *cctx) 303 { 304 return (cctx->chip_num == CHIP_NUM_58818 || 305 cctx->chip_num == CHIP_NUM_57608); 306 } 307 bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx * cctx)308 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx) 309 { 310 return (cctx->chip_num == CHIP_NUM_57508 || 311 cctx->chip_num == CHIP_NUM_57504 || 312 cctx->chip_num == CHIP_NUM_57502); 313 } 314 bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx * cctx)315 static inline bool bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx *cctx) 316 { 317 return bnxt_qplib_is_chip_gen_p5(cctx) || bnxt_qplib_is_chip_gen_p7(cctx); 318 } 319 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res * res)320 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res) 321 { 322 return bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? 323 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL; 324 } 325 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx * cctx)326 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx) 327 { 328 return bnxt_qplib_is_chip_gen_p5_p7(cctx) ? 329 RING_ALLOC_REQ_RING_TYPE_NQ : 330 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL; 331 } 332 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq * hwq)333 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq) 334 { 335 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 336 struct bnxt_qplib_pbl *pbl; 337 338 pbl = &hwq->pbl[PBL_LVL_0]; 339 switch (pbl->pg_size) { 340 case ROCE_PG_SIZE_4K: 341 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 342 break; 343 case ROCE_PG_SIZE_8K: 344 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K; 345 break; 346 case ROCE_PG_SIZE_64K: 347 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K; 348 break; 349 case ROCE_PG_SIZE_2M: 350 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M; 351 break; 352 case ROCE_PG_SIZE_8M: 353 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M; 354 break; 355 case ROCE_PG_SIZE_1G: 356 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G; 357 break; 358 default: 359 break; 360 } 361 362 return pg_size; 363 } 364 bnxt_qplib_get_qe(struct bnxt_qplib_hwq * hwq,u32 indx,u64 * pg)365 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq, 366 u32 indx, u64 *pg) 367 { 368 u32 pg_num, pg_idx; 369 370 pg_num = (indx / hwq->qe_ppg); 371 pg_idx = (indx % hwq->qe_ppg); 372 if (pg) 373 *pg = (u64)&hwq->pbl_ptr[pg_num]; 374 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx); 375 } 376 bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq * hwq,u32 idx)377 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx) 378 { 379 idx += hwq->prod; 380 if (idx >= hwq->depth) 381 idx -= hwq->depth; 382 return bnxt_qplib_get_qe(hwq, idx, NULL); 383 } 384 385 #define to_bnxt_qplib(ptr, type, member) \ 386 container_of(ptr, type, member) 387 388 struct bnxt_qplib_pd; 389 struct bnxt_qplib_dev_attr; 390 391 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, 392 struct bnxt_qplib_hwq *hwq); 393 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, 394 struct bnxt_qplib_hwq_attr *hwq_attr); 395 int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res, 396 struct bnxt_qplib_pd *pd); 397 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, 398 struct bnxt_qplib_pd_tbl *pd_tbl, 399 struct bnxt_qplib_pd *pd); 400 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res, 401 struct bnxt_qplib_dpi *dpi, 402 void *app, u8 type); 403 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, 404 struct bnxt_qplib_dpi *dpi); 405 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); 406 int bnxt_qplib_init_res(struct bnxt_qplib_res *res); 407 void bnxt_qplib_free_res(struct bnxt_qplib_res *res); 408 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 409 struct net_device *netdev, 410 struct bnxt_qplib_dev_attr *dev_attr); 411 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 412 struct bnxt_qplib_ctx *ctx); 413 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, 414 struct bnxt_qplib_ctx *ctx, 415 bool virt_fn, bool is_p5); 416 int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res); 417 void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res); 418 419 int bnxt_qplib_determine_atomics(struct pci_dev *dev); 420 bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info * dbinfo,struct bnxt_qplib_hwq * hwq,u32 cnt)421 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info *dbinfo, 422 struct bnxt_qplib_hwq *hwq, u32 cnt) 423 { 424 /* move prod and update toggle/epoch if wrap around */ 425 hwq->prod += cnt; 426 if (hwq->prod >= hwq->depth) { 427 hwq->prod %= hwq->depth; 428 dbinfo->flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT; 429 } 430 } 431 bnxt_qplib_hwq_incr_cons(u32 max_elements,u32 * cons,u32 cnt,u32 * dbinfo_flags)432 static inline void bnxt_qplib_hwq_incr_cons(u32 max_elements, u32 *cons, u32 cnt, 433 u32 *dbinfo_flags) 434 { 435 /* move cons and update toggle/epoch if wrap around */ 436 *cons += cnt; 437 if (*cons >= max_elements) { 438 *cons %= max_elements; 439 *dbinfo_flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT; 440 } 441 } 442 bnxt_qplib_ring_db32(struct bnxt_qplib_db_info * info,bool arm)443 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info, 444 bool arm) 445 { 446 u32 key = 0; 447 448 key |= info->hwq->cons | (CMPL_DOORBELL_IDX_VALID | 449 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK)); 450 if (!arm) 451 key |= CMPL_DOORBELL_MASK; 452 writel(key, info->db); 453 } 454 bnxt_qplib_ring_db(struct bnxt_qplib_db_info * info,u32 type)455 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info, 456 u32 type) 457 { 458 u64 key = 0; 459 460 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 461 key <<= 32; 462 key |= (info->hwq->cons & DBC_DBC_INDEX_MASK); 463 writeq(key, info->db); 464 } 465 bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info * info,u32 type)466 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info, 467 u32 type) 468 { 469 u64 key = 0; 470 471 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 472 key <<= 32; 473 key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK; 474 writeq(key, info->db); 475 } 476 bnxt_qplib_armen_db(struct bnxt_qplib_db_info * info,u32 type)477 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info, 478 u32 type) 479 { 480 u64 key = 0; 481 482 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 483 key <<= 32; 484 writeq(key, info->priv_db); 485 } 486 bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info * info,u32 th)487 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info, 488 u32 th) 489 { 490 u64 key = 0; 491 492 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th; 493 key <<= 32; 494 key |= th & DBC_DBC_INDEX_MASK; 495 writeq(key, info->priv_db); 496 } 497 bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info * info,struct bnxt_qplib_chip_ctx * cctx,bool arm)498 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info, 499 struct bnxt_qplib_chip_ctx *cctx, 500 bool arm) 501 { 502 u32 type; 503 504 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; 505 if (bnxt_qplib_is_chip_gen_p5_p7(cctx)) 506 bnxt_qplib_ring_db(info, type); 507 else 508 bnxt_qplib_ring_db32(info, arm); 509 } 510 _is_ext_stats_supported(u16 dev_cap_flags)511 static inline bool _is_ext_stats_supported(u16 dev_cap_flags) 512 { 513 return dev_cap_flags & 514 CREQ_QUERY_FUNC_RESP_SB_EXT_STATS; 515 } 516 _is_hw_retx_supported(u16 dev_cap_flags)517 static inline bool _is_hw_retx_supported(u16 dev_cap_flags) 518 { 519 return dev_cap_flags & 520 (CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED | 521 CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED); 522 } 523 524 #define BNXT_RE_HW_RETX(a) _is_hw_retx_supported((a)) 525 _is_host_msn_table(u16 dev_cap_ext_flags2)526 static inline bool _is_host_msn_table(u16 dev_cap_ext_flags2) 527 { 528 return (dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK) == 529 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE; 530 } 531 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx * cctx)532 static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx) 533 { 534 return cctx->modes.dbr_pacing; 535 } 536 537 #endif /* __BNXT_QPLIB_RES_H__ */ 538