1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4  *
5  */
6 
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sm8250.h>
14 
15 #include "bcm-voter.h"
16 #include "icc-rpmh.h"
17 #include "sm8250.h"
18 
19 static struct qcom_icc_node qhm_a1noc_cfg = {
20 	.name = "qhm_a1noc_cfg",
21 	.id = SM8250_MASTER_A1NOC_CFG,
22 	.channels = 1,
23 	.buswidth = 4,
24 	.num_links = 1,
25 	.links = { SM8250_SLAVE_SERVICE_A1NOC },
26 };
27 
28 static struct qcom_icc_node qhm_qspi = {
29 	.name = "qhm_qspi",
30 	.id = SM8250_MASTER_QSPI_0,
31 	.channels = 1,
32 	.buswidth = 4,
33 	.num_links = 1,
34 	.links = { SM8250_A1NOC_SNOC_SLV },
35 };
36 
37 static struct qcom_icc_node qhm_qup1 = {
38 	.name = "qhm_qup1",
39 	.id = SM8250_MASTER_QUP_1,
40 	.channels = 1,
41 	.buswidth = 4,
42 	.num_links = 1,
43 	.links = { SM8250_A1NOC_SNOC_SLV },
44 };
45 
46 static struct qcom_icc_node qhm_qup2 = {
47 	.name = "qhm_qup2",
48 	.id = SM8250_MASTER_QUP_2,
49 	.channels = 1,
50 	.buswidth = 4,
51 	.num_links = 1,
52 	.links = { SM8250_A1NOC_SNOC_SLV },
53 };
54 
55 static struct qcom_icc_node qhm_tsif = {
56 	.name = "qhm_tsif",
57 	.id = SM8250_MASTER_TSIF,
58 	.channels = 1,
59 	.buswidth = 4,
60 	.num_links = 1,
61 	.links = { SM8250_A1NOC_SNOC_SLV },
62 };
63 
64 static struct qcom_icc_node xm_pcie3_modem = {
65 	.name = "xm_pcie3_modem",
66 	.id = SM8250_MASTER_PCIE_2,
67 	.channels = 1,
68 	.buswidth = 8,
69 	.num_links = 1,
70 	.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 },
71 };
72 
73 static struct qcom_icc_node xm_sdc4 = {
74 	.name = "xm_sdc4",
75 	.id = SM8250_MASTER_SDCC_4,
76 	.channels = 1,
77 	.buswidth = 8,
78 	.num_links = 1,
79 	.links = { SM8250_A1NOC_SNOC_SLV },
80 };
81 
82 static struct qcom_icc_node xm_ufs_mem = {
83 	.name = "xm_ufs_mem",
84 	.id = SM8250_MASTER_UFS_MEM,
85 	.channels = 1,
86 	.buswidth = 8,
87 	.num_links = 1,
88 	.links = { SM8250_A1NOC_SNOC_SLV },
89 };
90 
91 static struct qcom_icc_node xm_usb3_0 = {
92 	.name = "xm_usb3_0",
93 	.id = SM8250_MASTER_USB3,
94 	.channels = 1,
95 	.buswidth = 8,
96 	.num_links = 1,
97 	.links = { SM8250_A1NOC_SNOC_SLV },
98 };
99 
100 static struct qcom_icc_node xm_usb3_1 = {
101 	.name = "xm_usb3_1",
102 	.id = SM8250_MASTER_USB3_1,
103 	.channels = 1,
104 	.buswidth = 8,
105 	.num_links = 1,
106 	.links = { SM8250_A1NOC_SNOC_SLV },
107 };
108 
109 static struct qcom_icc_node qhm_a2noc_cfg = {
110 	.name = "qhm_a2noc_cfg",
111 	.id = SM8250_MASTER_A2NOC_CFG,
112 	.channels = 1,
113 	.buswidth = 4,
114 	.num_links = 1,
115 	.links = { SM8250_SLAVE_SERVICE_A2NOC },
116 };
117 
118 static struct qcom_icc_node qhm_qdss_bam = {
119 	.name = "qhm_qdss_bam",
120 	.id = SM8250_MASTER_QDSS_BAM,
121 	.channels = 1,
122 	.buswidth = 4,
123 	.num_links = 1,
124 	.links = { SM8250_A2NOC_SNOC_SLV },
125 };
126 
127 static struct qcom_icc_node qhm_qup0 = {
128 	.name = "qhm_qup0",
129 	.id = SM8250_MASTER_QUP_0,
130 	.channels = 1,
131 	.buswidth = 4,
132 	.num_links = 1,
133 	.links = { SM8250_A2NOC_SNOC_SLV },
134 };
135 
136 static struct qcom_icc_node qnm_cnoc = {
137 	.name = "qnm_cnoc",
138 	.id = SM8250_MASTER_CNOC_A2NOC,
139 	.channels = 1,
140 	.buswidth = 8,
141 	.num_links = 1,
142 	.links = { SM8250_A2NOC_SNOC_SLV },
143 };
144 
145 static struct qcom_icc_node qxm_crypto = {
146 	.name = "qxm_crypto",
147 	.id = SM8250_MASTER_CRYPTO_CORE_0,
148 	.channels = 1,
149 	.buswidth = 8,
150 	.num_links = 1,
151 	.links = { SM8250_A2NOC_SNOC_SLV },
152 };
153 
154 static struct qcom_icc_node qxm_ipa = {
155 	.name = "qxm_ipa",
156 	.id = SM8250_MASTER_IPA,
157 	.channels = 1,
158 	.buswidth = 8,
159 	.num_links = 1,
160 	.links = { SM8250_A2NOC_SNOC_SLV },
161 };
162 
163 static struct qcom_icc_node xm_pcie3_0 = {
164 	.name = "xm_pcie3_0",
165 	.id = SM8250_MASTER_PCIE,
166 	.channels = 1,
167 	.buswidth = 8,
168 	.num_links = 1,
169 	.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
170 };
171 
172 static struct qcom_icc_node xm_pcie3_1 = {
173 	.name = "xm_pcie3_1",
174 	.id = SM8250_MASTER_PCIE_1,
175 	.channels = 1,
176 	.buswidth = 8,
177 	.num_links = 1,
178 	.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
179 };
180 
181 static struct qcom_icc_node xm_qdss_etr = {
182 	.name = "xm_qdss_etr",
183 	.id = SM8250_MASTER_QDSS_ETR,
184 	.channels = 1,
185 	.buswidth = 8,
186 	.num_links = 1,
187 	.links = { SM8250_A2NOC_SNOC_SLV },
188 };
189 
190 static struct qcom_icc_node xm_sdc2 = {
191 	.name = "xm_sdc2",
192 	.id = SM8250_MASTER_SDCC_2,
193 	.channels = 1,
194 	.buswidth = 8,
195 	.num_links = 1,
196 	.links = { SM8250_A2NOC_SNOC_SLV },
197 };
198 
199 static struct qcom_icc_node xm_ufs_card = {
200 	.name = "xm_ufs_card",
201 	.id = SM8250_MASTER_UFS_CARD,
202 	.channels = 1,
203 	.buswidth = 8,
204 	.num_links = 1,
205 	.links = { SM8250_A2NOC_SNOC_SLV },
206 };
207 
208 static struct qcom_icc_node qnm_npu = {
209 	.name = "qnm_npu",
210 	.id = SM8250_MASTER_NPU,
211 	.channels = 2,
212 	.buswidth = 32,
213 	.num_links = 1,
214 	.links = { SM8250_SLAVE_CDSP_MEM_NOC },
215 };
216 
217 static struct qcom_icc_node qnm_snoc = {
218 	.name = "qnm_snoc",
219 	.id = SM8250_SNOC_CNOC_MAS,
220 	.channels = 1,
221 	.buswidth = 8,
222 	.num_links = 49,
223 	.links = { SM8250_SLAVE_CDSP_CFG,
224 		   SM8250_SLAVE_CAMERA_CFG,
225 		   SM8250_SLAVE_TLMM_SOUTH,
226 		   SM8250_SLAVE_TLMM_NORTH,
227 		   SM8250_SLAVE_SDCC_4,
228 		   SM8250_SLAVE_TLMM_WEST,
229 		   SM8250_SLAVE_SDCC_2,
230 		   SM8250_SLAVE_CNOC_MNOC_CFG,
231 		   SM8250_SLAVE_UFS_MEM_CFG,
232 		   SM8250_SLAVE_SNOC_CFG,
233 		   SM8250_SLAVE_PDM,
234 		   SM8250_SLAVE_CX_RDPM,
235 		   SM8250_SLAVE_PCIE_1_CFG,
236 		   SM8250_SLAVE_A2NOC_CFG,
237 		   SM8250_SLAVE_QDSS_CFG,
238 		   SM8250_SLAVE_DISPLAY_CFG,
239 		   SM8250_SLAVE_PCIE_2_CFG,
240 		   SM8250_SLAVE_TCSR,
241 		   SM8250_SLAVE_DCC_CFG,
242 		   SM8250_SLAVE_CNOC_DDRSS,
243 		   SM8250_SLAVE_IPC_ROUTER_CFG,
244 		   SM8250_SLAVE_PCIE_0_CFG,
245 		   SM8250_SLAVE_RBCPR_MMCX_CFG,
246 		   SM8250_SLAVE_NPU_CFG,
247 		   SM8250_SLAVE_AHB2PHY_SOUTH,
248 		   SM8250_SLAVE_AHB2PHY_NORTH,
249 		   SM8250_SLAVE_GRAPHICS_3D_CFG,
250 		   SM8250_SLAVE_VENUS_CFG,
251 		   SM8250_SLAVE_TSIF,
252 		   SM8250_SLAVE_IPA_CFG,
253 		   SM8250_SLAVE_IMEM_CFG,
254 		   SM8250_SLAVE_USB3,
255 		   SM8250_SLAVE_SERVICE_CNOC,
256 		   SM8250_SLAVE_UFS_CARD_CFG,
257 		   SM8250_SLAVE_USB3_1,
258 		   SM8250_SLAVE_LPASS,
259 		   SM8250_SLAVE_RBCPR_CX_CFG,
260 		   SM8250_SLAVE_A1NOC_CFG,
261 		   SM8250_SLAVE_AOSS,
262 		   SM8250_SLAVE_PRNG,
263 		   SM8250_SLAVE_VSENSE_CTRL_CFG,
264 		   SM8250_SLAVE_QSPI_0,
265 		   SM8250_SLAVE_CRYPTO_0_CFG,
266 		   SM8250_SLAVE_PIMEM_CFG,
267 		   SM8250_SLAVE_RBCPR_MX_CFG,
268 		   SM8250_SLAVE_QUP_0,
269 		   SM8250_SLAVE_QUP_1,
270 		   SM8250_SLAVE_QUP_2,
271 		   SM8250_SLAVE_CLK_CTL
272 	},
273 };
274 
275 static struct qcom_icc_node xm_qdss_dap = {
276 	.name = "xm_qdss_dap",
277 	.id = SM8250_MASTER_QDSS_DAP,
278 	.channels = 1,
279 	.buswidth = 8,
280 	.num_links = 50,
281 	.links = { SM8250_SLAVE_CDSP_CFG,
282 		   SM8250_SLAVE_CAMERA_CFG,
283 		   SM8250_SLAVE_TLMM_SOUTH,
284 		   SM8250_SLAVE_TLMM_NORTH,
285 		   SM8250_SLAVE_SDCC_4,
286 		   SM8250_SLAVE_TLMM_WEST,
287 		   SM8250_SLAVE_SDCC_2,
288 		   SM8250_SLAVE_CNOC_MNOC_CFG,
289 		   SM8250_SLAVE_UFS_MEM_CFG,
290 		   SM8250_SLAVE_SNOC_CFG,
291 		   SM8250_SLAVE_PDM,
292 		   SM8250_SLAVE_CX_RDPM,
293 		   SM8250_SLAVE_PCIE_1_CFG,
294 		   SM8250_SLAVE_A2NOC_CFG,
295 		   SM8250_SLAVE_QDSS_CFG,
296 		   SM8250_SLAVE_DISPLAY_CFG,
297 		   SM8250_SLAVE_PCIE_2_CFG,
298 		   SM8250_SLAVE_TCSR,
299 		   SM8250_SLAVE_DCC_CFG,
300 		   SM8250_SLAVE_CNOC_DDRSS,
301 		   SM8250_SLAVE_IPC_ROUTER_CFG,
302 		   SM8250_SLAVE_CNOC_A2NOC,
303 		   SM8250_SLAVE_PCIE_0_CFG,
304 		   SM8250_SLAVE_RBCPR_MMCX_CFG,
305 		   SM8250_SLAVE_NPU_CFG,
306 		   SM8250_SLAVE_AHB2PHY_SOUTH,
307 		   SM8250_SLAVE_AHB2PHY_NORTH,
308 		   SM8250_SLAVE_GRAPHICS_3D_CFG,
309 		   SM8250_SLAVE_VENUS_CFG,
310 		   SM8250_SLAVE_TSIF,
311 		   SM8250_SLAVE_IPA_CFG,
312 		   SM8250_SLAVE_IMEM_CFG,
313 		   SM8250_SLAVE_USB3,
314 		   SM8250_SLAVE_SERVICE_CNOC,
315 		   SM8250_SLAVE_UFS_CARD_CFG,
316 		   SM8250_SLAVE_USB3_1,
317 		   SM8250_SLAVE_LPASS,
318 		   SM8250_SLAVE_RBCPR_CX_CFG,
319 		   SM8250_SLAVE_A1NOC_CFG,
320 		   SM8250_SLAVE_AOSS,
321 		   SM8250_SLAVE_PRNG,
322 		   SM8250_SLAVE_VSENSE_CTRL_CFG,
323 		   SM8250_SLAVE_QSPI_0,
324 		   SM8250_SLAVE_CRYPTO_0_CFG,
325 		   SM8250_SLAVE_PIMEM_CFG,
326 		   SM8250_SLAVE_RBCPR_MX_CFG,
327 		   SM8250_SLAVE_QUP_0,
328 		   SM8250_SLAVE_QUP_1,
329 		   SM8250_SLAVE_QUP_2,
330 		   SM8250_SLAVE_CLK_CTL
331 	},
332 };
333 
334 static struct qcom_icc_node qhm_cnoc_dc_noc = {
335 	.name = "qhm_cnoc_dc_noc",
336 	.id = SM8250_MASTER_CNOC_DC_NOC,
337 	.channels = 1,
338 	.buswidth = 4,
339 	.num_links = 2,
340 	.links = { SM8250_SLAVE_GEM_NOC_CFG,
341 		   SM8250_SLAVE_LLCC_CFG
342 	},
343 };
344 
345 static struct qcom_icc_node alm_gpu_tcu = {
346 	.name = "alm_gpu_tcu",
347 	.id = SM8250_MASTER_GPU_TCU,
348 	.channels = 1,
349 	.buswidth = 8,
350 	.num_links = 2,
351 	.links = { SM8250_SLAVE_LLCC,
352 		   SM8250_SLAVE_GEM_NOC_SNOC
353 	},
354 };
355 
356 static struct qcom_icc_node alm_sys_tcu = {
357 	.name = "alm_sys_tcu",
358 	.id = SM8250_MASTER_SYS_TCU,
359 	.channels = 1,
360 	.buswidth = 8,
361 	.num_links = 2,
362 	.links = { SM8250_SLAVE_LLCC,
363 		   SM8250_SLAVE_GEM_NOC_SNOC
364 	},
365 };
366 
367 static struct qcom_icc_node chm_apps = {
368 	.name = "chm_apps",
369 	.id = SM8250_MASTER_AMPSS_M0,
370 	.channels = 2,
371 	.buswidth = 32,
372 	.num_links = 3,
373 	.links = { SM8250_SLAVE_LLCC,
374 		   SM8250_SLAVE_GEM_NOC_SNOC,
375 		   SM8250_SLAVE_MEM_NOC_PCIE_SNOC
376 	},
377 };
378 
379 static struct qcom_icc_node qhm_gemnoc_cfg = {
380 	.name = "qhm_gemnoc_cfg",
381 	.id = SM8250_MASTER_GEM_NOC_CFG,
382 	.channels = 1,
383 	.buswidth = 4,
384 	.num_links = 3,
385 	.links = { SM8250_SLAVE_SERVICE_GEM_NOC_2,
386 		   SM8250_SLAVE_SERVICE_GEM_NOC_1,
387 		   SM8250_SLAVE_SERVICE_GEM_NOC
388 	},
389 };
390 
391 static struct qcom_icc_node qnm_cmpnoc = {
392 	.name = "qnm_cmpnoc",
393 	.id = SM8250_MASTER_COMPUTE_NOC,
394 	.channels = 2,
395 	.buswidth = 32,
396 	.num_links = 2,
397 	.links = { SM8250_SLAVE_LLCC,
398 		   SM8250_SLAVE_GEM_NOC_SNOC
399 	},
400 };
401 
402 static struct qcom_icc_node qnm_gpu = {
403 	.name = "qnm_gpu",
404 	.id = SM8250_MASTER_GRAPHICS_3D,
405 	.channels = 2,
406 	.buswidth = 32,
407 	.num_links = 2,
408 	.links = { SM8250_SLAVE_LLCC,
409 		   SM8250_SLAVE_GEM_NOC_SNOC },
410 };
411 
412 static struct qcom_icc_node qnm_mnoc_hf = {
413 	.name = "qnm_mnoc_hf",
414 	.id = SM8250_MASTER_MNOC_HF_MEM_NOC,
415 	.channels = 2,
416 	.buswidth = 32,
417 	.num_links = 1,
418 	.links = { SM8250_SLAVE_LLCC },
419 };
420 
421 static struct qcom_icc_node qnm_mnoc_sf = {
422 	.name = "qnm_mnoc_sf",
423 	.id = SM8250_MASTER_MNOC_SF_MEM_NOC,
424 	.channels = 2,
425 	.buswidth = 32,
426 	.num_links = 2,
427 	.links = { SM8250_SLAVE_LLCC,
428 		   SM8250_SLAVE_GEM_NOC_SNOC
429 	},
430 };
431 
432 static struct qcom_icc_node qnm_pcie = {
433 	.name = "qnm_pcie",
434 	.id = SM8250_MASTER_ANOC_PCIE_GEM_NOC,
435 	.channels = 1,
436 	.buswidth = 16,
437 	.num_links = 2,
438 	.links = { SM8250_SLAVE_LLCC,
439 		   SM8250_SLAVE_GEM_NOC_SNOC
440 	},
441 };
442 
443 static struct qcom_icc_node qnm_snoc_gc = {
444 	.name = "qnm_snoc_gc",
445 	.id = SM8250_MASTER_SNOC_GC_MEM_NOC,
446 	.channels = 1,
447 	.buswidth = 8,
448 	.num_links = 1,
449 	.links = { SM8250_SLAVE_LLCC },
450 };
451 
452 static struct qcom_icc_node qnm_snoc_sf = {
453 	.name = "qnm_snoc_sf",
454 	.id = SM8250_MASTER_SNOC_SF_MEM_NOC,
455 	.channels = 1,
456 	.buswidth = 16,
457 	.num_links = 3,
458 	.links = { SM8250_SLAVE_LLCC,
459 		   SM8250_SLAVE_GEM_NOC_SNOC,
460 		   SM8250_SLAVE_MEM_NOC_PCIE_SNOC
461 	},
462 };
463 
464 static struct qcom_icc_node llcc_mc = {
465 	.name = "llcc_mc",
466 	.id = SM8250_MASTER_LLCC,
467 	.channels = 4,
468 	.buswidth = 4,
469 	.num_links = 1,
470 	.links = { SM8250_SLAVE_EBI_CH0 },
471 };
472 
473 static struct qcom_icc_node qhm_mnoc_cfg = {
474 	.name = "qhm_mnoc_cfg",
475 	.id = SM8250_MASTER_CNOC_MNOC_CFG,
476 	.channels = 1,
477 	.buswidth = 4,
478 	.num_links = 1,
479 	.links = { SM8250_SLAVE_SERVICE_MNOC },
480 };
481 
482 static struct qcom_icc_node qnm_camnoc_hf = {
483 	.name = "qnm_camnoc_hf",
484 	.id = SM8250_MASTER_CAMNOC_HF,
485 	.channels = 2,
486 	.buswidth = 32,
487 	.num_links = 1,
488 	.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
489 };
490 
491 static struct qcom_icc_node qnm_camnoc_icp = {
492 	.name = "qnm_camnoc_icp",
493 	.id = SM8250_MASTER_CAMNOC_ICP,
494 	.channels = 1,
495 	.buswidth = 8,
496 	.num_links = 1,
497 	.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
498 };
499 
500 static struct qcom_icc_node qnm_camnoc_sf = {
501 	.name = "qnm_camnoc_sf",
502 	.id = SM8250_MASTER_CAMNOC_SF,
503 	.channels = 2,
504 	.buswidth = 32,
505 	.num_links = 1,
506 	.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
507 };
508 
509 static struct qcom_icc_node qnm_video0 = {
510 	.name = "qnm_video0",
511 	.id = SM8250_MASTER_VIDEO_P0,
512 	.channels = 1,
513 	.buswidth = 32,
514 	.num_links = 1,
515 	.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
516 };
517 
518 static struct qcom_icc_node qnm_video1 = {
519 	.name = "qnm_video1",
520 	.id = SM8250_MASTER_VIDEO_P1,
521 	.channels = 1,
522 	.buswidth = 32,
523 	.num_links = 1,
524 	.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
525 };
526 
527 static struct qcom_icc_node qnm_video_cvp = {
528 	.name = "qnm_video_cvp",
529 	.id = SM8250_MASTER_VIDEO_PROC,
530 	.channels = 1,
531 	.buswidth = 32,
532 	.num_links = 1,
533 	.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
534 };
535 
536 static struct qcom_icc_node qxm_mdp0 = {
537 	.name = "qxm_mdp0",
538 	.id = SM8250_MASTER_MDP_PORT0,
539 	.channels = 1,
540 	.buswidth = 32,
541 	.num_links = 1,
542 	.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
543 };
544 
545 static struct qcom_icc_node qxm_mdp1 = {
546 	.name = "qxm_mdp1",
547 	.id = SM8250_MASTER_MDP_PORT1,
548 	.channels = 1,
549 	.buswidth = 32,
550 	.num_links = 1,
551 	.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
552 };
553 
554 static struct qcom_icc_node qxm_rot = {
555 	.name = "qxm_rot",
556 	.id = SM8250_MASTER_ROTATOR,
557 	.channels = 1,
558 	.buswidth = 32,
559 	.num_links = 1,
560 	.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
561 };
562 
563 static struct qcom_icc_node amm_npu_sys = {
564 	.name = "amm_npu_sys",
565 	.id = SM8250_MASTER_NPU_SYS,
566 	.channels = 4,
567 	.buswidth = 32,
568 	.num_links = 1,
569 	.links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
570 };
571 
572 static struct qcom_icc_node amm_npu_sys_cdp_w = {
573 	.name = "amm_npu_sys_cdp_w",
574 	.id = SM8250_MASTER_NPU_CDP,
575 	.channels = 2,
576 	.buswidth = 16,
577 	.num_links = 1,
578 	.links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
579 };
580 
581 static struct qcom_icc_node qhm_cfg = {
582 	.name = "qhm_cfg",
583 	.id = SM8250_MASTER_NPU_NOC_CFG,
584 	.channels = 1,
585 	.buswidth = 4,
586 	.num_links = 9,
587 	.links = { SM8250_SLAVE_SERVICE_NPU_NOC,
588 		   SM8250_SLAVE_ISENSE_CFG,
589 		   SM8250_SLAVE_NPU_LLM_CFG,
590 		   SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
591 		   SM8250_SLAVE_NPU_CP,
592 		   SM8250_SLAVE_NPU_TCM,
593 		   SM8250_SLAVE_NPU_CAL_DP0,
594 		   SM8250_SLAVE_NPU_CAL_DP1,
595 		   SM8250_SLAVE_NPU_DPM
596 	},
597 };
598 
599 static struct qcom_icc_node qhm_snoc_cfg = {
600 	.name = "qhm_snoc_cfg",
601 	.id = SM8250_MASTER_SNOC_CFG,
602 	.channels = 1,
603 	.buswidth = 4,
604 	.num_links = 1,
605 	.links = { SM8250_SLAVE_SERVICE_SNOC },
606 };
607 
608 static struct qcom_icc_node qnm_aggre1_noc = {
609 	.name = "qnm_aggre1_noc",
610 	.id = SM8250_A1NOC_SNOC_MAS,
611 	.channels = 1,
612 	.buswidth = 16,
613 	.num_links = 1,
614 	.links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
615 };
616 
617 static struct qcom_icc_node qnm_aggre2_noc = {
618 	.name = "qnm_aggre2_noc",
619 	.id = SM8250_A2NOC_SNOC_MAS,
620 	.channels = 1,
621 	.buswidth = 16,
622 	.num_links = 1,
623 	.links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
624 };
625 
626 static struct qcom_icc_node qnm_gemnoc = {
627 	.name = "qnm_gemnoc",
628 	.id = SM8250_MASTER_GEM_NOC_SNOC,
629 	.channels = 1,
630 	.buswidth = 16,
631 	.num_links = 6,
632 	.links = { SM8250_SLAVE_PIMEM,
633 		   SM8250_SLAVE_OCIMEM,
634 		   SM8250_SLAVE_APPSS,
635 		   SM8250_SNOC_CNOC_SLV,
636 		   SM8250_SLAVE_TCU,
637 		   SM8250_SLAVE_QDSS_STM
638 	},
639 };
640 
641 static struct qcom_icc_node qnm_gemnoc_pcie = {
642 	.name = "qnm_gemnoc_pcie",
643 	.id = SM8250_MASTER_GEM_NOC_PCIE_SNOC,
644 	.channels = 1,
645 	.buswidth = 8,
646 	.num_links = 3,
647 	.links = { SM8250_SLAVE_PCIE_2,
648 		   SM8250_SLAVE_PCIE_0,
649 		   SM8250_SLAVE_PCIE_1
650 	},
651 };
652 
653 static struct qcom_icc_node qxm_pimem = {
654 	.name = "qxm_pimem",
655 	.id = SM8250_MASTER_PIMEM,
656 	.channels = 1,
657 	.buswidth = 8,
658 	.num_links = 1,
659 	.links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
660 };
661 
662 static struct qcom_icc_node xm_gic = {
663 	.name = "xm_gic",
664 	.id = SM8250_MASTER_GIC,
665 	.channels = 1,
666 	.buswidth = 8,
667 	.num_links = 1,
668 	.links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
669 };
670 
671 static struct qcom_icc_node qns_a1noc_snoc = {
672 	.name = "qns_a1noc_snoc",
673 	.id = SM8250_A1NOC_SNOC_SLV,
674 	.channels = 1,
675 	.buswidth = 16,
676 	.num_links = 1,
677 	.links = { SM8250_A1NOC_SNOC_MAS },
678 };
679 
680 static struct qcom_icc_node qns_pcie_modem_mem_noc = {
681 	.name = "qns_pcie_modem_mem_noc",
682 	.id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1,
683 	.channels = 1,
684 	.buswidth = 16,
685 	.num_links = 1,
686 	.links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
687 };
688 
689 static struct qcom_icc_node srvc_aggre1_noc = {
690 	.name = "srvc_aggre1_noc",
691 	.id = SM8250_SLAVE_SERVICE_A1NOC,
692 	.channels = 1,
693 	.buswidth = 4,
694 };
695 
696 static struct qcom_icc_node qns_a2noc_snoc = {
697 	.name = "qns_a2noc_snoc",
698 	.id = SM8250_A2NOC_SNOC_SLV,
699 	.channels = 1,
700 	.buswidth = 16,
701 	.num_links = 1,
702 	.links = { SM8250_A2NOC_SNOC_MAS },
703 };
704 
705 static struct qcom_icc_node qns_pcie_mem_noc = {
706 	.name = "qns_pcie_mem_noc",
707 	.id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC,
708 	.channels = 1,
709 	.buswidth = 16,
710 	.num_links = 1,
711 	.links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
712 };
713 
714 static struct qcom_icc_node srvc_aggre2_noc = {
715 	.name = "srvc_aggre2_noc",
716 	.id = SM8250_SLAVE_SERVICE_A2NOC,
717 	.channels = 1,
718 	.buswidth = 4,
719 };
720 
721 static struct qcom_icc_node qns_cdsp_mem_noc = {
722 	.name = "qns_cdsp_mem_noc",
723 	.id = SM8250_SLAVE_CDSP_MEM_NOC,
724 	.channels = 2,
725 	.buswidth = 32,
726 	.num_links = 1,
727 	.links = { SM8250_MASTER_COMPUTE_NOC },
728 };
729 
730 static struct qcom_icc_node qhs_a1_noc_cfg = {
731 	.name = "qhs_a1_noc_cfg",
732 	.id = SM8250_SLAVE_A1NOC_CFG,
733 	.channels = 1,
734 	.buswidth = 4,
735 	.num_links = 1,
736 	.links = { SM8250_MASTER_A1NOC_CFG },
737 };
738 
739 static struct qcom_icc_node qhs_a2_noc_cfg = {
740 	.name = "qhs_a2_noc_cfg",
741 	.id = SM8250_SLAVE_A2NOC_CFG,
742 	.channels = 1,
743 	.buswidth = 4,
744 	.num_links = 1,
745 	.links = { SM8250_MASTER_A2NOC_CFG },
746 };
747 
748 static struct qcom_icc_node qhs_ahb2phy0 = {
749 	.name = "qhs_ahb2phy0",
750 	.id = SM8250_SLAVE_AHB2PHY_SOUTH,
751 	.channels = 1,
752 	.buswidth = 4,
753 };
754 
755 static struct qcom_icc_node qhs_ahb2phy1 = {
756 	.name = "qhs_ahb2phy1",
757 	.id = SM8250_SLAVE_AHB2PHY_NORTH,
758 	.channels = 1,
759 	.buswidth = 4,
760 };
761 
762 static struct qcom_icc_node qhs_aoss = {
763 	.name = "qhs_aoss",
764 	.id = SM8250_SLAVE_AOSS,
765 	.channels = 1,
766 	.buswidth = 4,
767 };
768 
769 static struct qcom_icc_node qhs_camera_cfg = {
770 	.name = "qhs_camera_cfg",
771 	.id = SM8250_SLAVE_CAMERA_CFG,
772 	.channels = 1,
773 	.buswidth = 4,
774 };
775 
776 static struct qcom_icc_node qhs_clk_ctl = {
777 	.name = "qhs_clk_ctl",
778 	.id = SM8250_SLAVE_CLK_CTL,
779 	.channels = 1,
780 	.buswidth = 4,
781 };
782 
783 static struct qcom_icc_node qhs_compute_dsp = {
784 	.name = "qhs_compute_dsp",
785 	.id = SM8250_SLAVE_CDSP_CFG,
786 	.channels = 1,
787 	.buswidth = 4,
788 };
789 
790 static struct qcom_icc_node qhs_cpr_cx = {
791 	.name = "qhs_cpr_cx",
792 	.id = SM8250_SLAVE_RBCPR_CX_CFG,
793 	.channels = 1,
794 	.buswidth = 4,
795 };
796 
797 static struct qcom_icc_node qhs_cpr_mmcx = {
798 	.name = "qhs_cpr_mmcx",
799 	.id = SM8250_SLAVE_RBCPR_MMCX_CFG,
800 	.channels = 1,
801 	.buswidth = 4,
802 };
803 
804 static struct qcom_icc_node qhs_cpr_mx = {
805 	.name = "qhs_cpr_mx",
806 	.id = SM8250_SLAVE_RBCPR_MX_CFG,
807 	.channels = 1,
808 	.buswidth = 4,
809 };
810 
811 static struct qcom_icc_node qhs_crypto0_cfg = {
812 	.name = "qhs_crypto0_cfg",
813 	.id = SM8250_SLAVE_CRYPTO_0_CFG,
814 	.channels = 1,
815 	.buswidth = 4,
816 };
817 
818 static struct qcom_icc_node qhs_cx_rdpm = {
819 	.name = "qhs_cx_rdpm",
820 	.id = SM8250_SLAVE_CX_RDPM,
821 	.channels = 1,
822 	.buswidth = 4,
823 };
824 
825 static struct qcom_icc_node qhs_dcc_cfg = {
826 	.name = "qhs_dcc_cfg",
827 	.id = SM8250_SLAVE_DCC_CFG,
828 	.channels = 1,
829 	.buswidth = 4,
830 };
831 
832 static struct qcom_icc_node qhs_ddrss_cfg = {
833 	.name = "qhs_ddrss_cfg",
834 	.id = SM8250_SLAVE_CNOC_DDRSS,
835 	.channels = 1,
836 	.buswidth = 4,
837 	.num_links = 1,
838 	.links = { SM8250_MASTER_CNOC_DC_NOC },
839 };
840 
841 static struct qcom_icc_node qhs_display_cfg = {
842 	.name = "qhs_display_cfg",
843 	.id = SM8250_SLAVE_DISPLAY_CFG,
844 	.channels = 1,
845 	.buswidth = 4,
846 };
847 
848 static struct qcom_icc_node qhs_gpuss_cfg = {
849 	.name = "qhs_gpuss_cfg",
850 	.id = SM8250_SLAVE_GRAPHICS_3D_CFG,
851 	.channels = 1,
852 	.buswidth = 8,
853 };
854 
855 static struct qcom_icc_node qhs_imem_cfg = {
856 	.name = "qhs_imem_cfg",
857 	.id = SM8250_SLAVE_IMEM_CFG,
858 	.channels = 1,
859 	.buswidth = 4,
860 };
861 
862 static struct qcom_icc_node qhs_ipa = {
863 	.name = "qhs_ipa",
864 	.id = SM8250_SLAVE_IPA_CFG,
865 	.channels = 1,
866 	.buswidth = 4,
867 };
868 
869 static struct qcom_icc_node qhs_ipc_router = {
870 	.name = "qhs_ipc_router",
871 	.id = SM8250_SLAVE_IPC_ROUTER_CFG,
872 	.channels = 1,
873 	.buswidth = 4,
874 };
875 
876 static struct qcom_icc_node qhs_lpass_cfg = {
877 	.name = "qhs_lpass_cfg",
878 	.id = SM8250_SLAVE_LPASS,
879 	.channels = 1,
880 	.buswidth = 4,
881 };
882 
883 static struct qcom_icc_node qhs_mnoc_cfg = {
884 	.name = "qhs_mnoc_cfg",
885 	.id = SM8250_SLAVE_CNOC_MNOC_CFG,
886 	.channels = 1,
887 	.buswidth = 4,
888 	.num_links = 1,
889 	.links = { SM8250_MASTER_CNOC_MNOC_CFG },
890 };
891 
892 static struct qcom_icc_node qhs_npu_cfg = {
893 	.name = "qhs_npu_cfg",
894 	.id = SM8250_SLAVE_NPU_CFG,
895 	.channels = 1,
896 	.buswidth = 4,
897 	.num_links = 1,
898 	.links = { SM8250_MASTER_NPU_NOC_CFG },
899 };
900 
901 static struct qcom_icc_node qhs_pcie0_cfg = {
902 	.name = "qhs_pcie0_cfg",
903 	.id = SM8250_SLAVE_PCIE_0_CFG,
904 	.channels = 1,
905 	.buswidth = 4,
906 };
907 
908 static struct qcom_icc_node qhs_pcie1_cfg = {
909 	.name = "qhs_pcie1_cfg",
910 	.id = SM8250_SLAVE_PCIE_1_CFG,
911 	.channels = 1,
912 	.buswidth = 4,
913 };
914 
915 static struct qcom_icc_node qhs_pcie_modem_cfg = {
916 	.name = "qhs_pcie_modem_cfg",
917 	.id = SM8250_SLAVE_PCIE_2_CFG,
918 	.channels = 1,
919 	.buswidth = 4,
920 };
921 
922 static struct qcom_icc_node qhs_pdm = {
923 	.name = "qhs_pdm",
924 	.id = SM8250_SLAVE_PDM,
925 	.channels = 1,
926 	.buswidth = 4,
927 };
928 
929 static struct qcom_icc_node qhs_pimem_cfg = {
930 	.name = "qhs_pimem_cfg",
931 	.id = SM8250_SLAVE_PIMEM_CFG,
932 	.channels = 1,
933 	.buswidth = 4,
934 };
935 
936 static struct qcom_icc_node qhs_prng = {
937 	.name = "qhs_prng",
938 	.id = SM8250_SLAVE_PRNG,
939 	.channels = 1,
940 	.buswidth = 4,
941 };
942 
943 static struct qcom_icc_node qhs_qdss_cfg = {
944 	.name = "qhs_qdss_cfg",
945 	.id = SM8250_SLAVE_QDSS_CFG,
946 	.channels = 1,
947 	.buswidth = 4,
948 };
949 
950 static struct qcom_icc_node qhs_qspi = {
951 	.name = "qhs_qspi",
952 	.id = SM8250_SLAVE_QSPI_0,
953 	.channels = 1,
954 	.buswidth = 4,
955 };
956 
957 static struct qcom_icc_node qhs_qup0 = {
958 	.name = "qhs_qup0",
959 	.id = SM8250_SLAVE_QUP_0,
960 	.channels = 1,
961 	.buswidth = 4,
962 };
963 
964 static struct qcom_icc_node qhs_qup1 = {
965 	.name = "qhs_qup1",
966 	.id = SM8250_SLAVE_QUP_1,
967 	.channels = 1,
968 	.buswidth = 4,
969 };
970 
971 static struct qcom_icc_node qhs_qup2 = {
972 	.name = "qhs_qup2",
973 	.id = SM8250_SLAVE_QUP_2,
974 	.channels = 1,
975 	.buswidth = 4,
976 };
977 
978 static struct qcom_icc_node qhs_sdc2 = {
979 	.name = "qhs_sdc2",
980 	.id = SM8250_SLAVE_SDCC_2,
981 	.channels = 1,
982 	.buswidth = 4,
983 };
984 
985 static struct qcom_icc_node qhs_sdc4 = {
986 	.name = "qhs_sdc4",
987 	.id = SM8250_SLAVE_SDCC_4,
988 	.channels = 1,
989 	.buswidth = 4,
990 };
991 
992 static struct qcom_icc_node qhs_snoc_cfg = {
993 	.name = "qhs_snoc_cfg",
994 	.id = SM8250_SLAVE_SNOC_CFG,
995 	.channels = 1,
996 	.buswidth = 4,
997 	.num_links = 1,
998 	.links = { SM8250_MASTER_SNOC_CFG },
999 };
1000 
1001 static struct qcom_icc_node qhs_tcsr = {
1002 	.name = "qhs_tcsr",
1003 	.id = SM8250_SLAVE_TCSR,
1004 	.channels = 1,
1005 	.buswidth = 4,
1006 };
1007 
1008 static struct qcom_icc_node qhs_tlmm0 = {
1009 	.name = "qhs_tlmm0",
1010 	.id = SM8250_SLAVE_TLMM_NORTH,
1011 	.channels = 1,
1012 	.buswidth = 4,
1013 };
1014 
1015 static struct qcom_icc_node qhs_tlmm1 = {
1016 	.name = "qhs_tlmm1",
1017 	.id = SM8250_SLAVE_TLMM_SOUTH,
1018 	.channels = 1,
1019 	.buswidth = 4,
1020 };
1021 
1022 static struct qcom_icc_node qhs_tlmm2 = {
1023 	.name = "qhs_tlmm2",
1024 	.id = SM8250_SLAVE_TLMM_WEST,
1025 	.channels = 1,
1026 	.buswidth = 4,
1027 };
1028 
1029 static struct qcom_icc_node qhs_tsif = {
1030 	.name = "qhs_tsif",
1031 	.id = SM8250_SLAVE_TSIF,
1032 	.channels = 1,
1033 	.buswidth = 4,
1034 };
1035 
1036 static struct qcom_icc_node qhs_ufs_card_cfg = {
1037 	.name = "qhs_ufs_card_cfg",
1038 	.id = SM8250_SLAVE_UFS_CARD_CFG,
1039 	.channels = 1,
1040 	.buswidth = 4,
1041 };
1042 
1043 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1044 	.name = "qhs_ufs_mem_cfg",
1045 	.id = SM8250_SLAVE_UFS_MEM_CFG,
1046 	.channels = 1,
1047 	.buswidth = 4,
1048 };
1049 
1050 static struct qcom_icc_node qhs_usb3_0 = {
1051 	.name = "qhs_usb3_0",
1052 	.id = SM8250_SLAVE_USB3,
1053 	.channels = 1,
1054 	.buswidth = 4,
1055 };
1056 
1057 static struct qcom_icc_node qhs_usb3_1 = {
1058 	.name = "qhs_usb3_1",
1059 	.id = SM8250_SLAVE_USB3_1,
1060 	.channels = 1,
1061 	.buswidth = 4,
1062 };
1063 
1064 static struct qcom_icc_node qhs_venus_cfg = {
1065 	.name = "qhs_venus_cfg",
1066 	.id = SM8250_SLAVE_VENUS_CFG,
1067 	.channels = 1,
1068 	.buswidth = 4,
1069 };
1070 
1071 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1072 	.name = "qhs_vsense_ctrl_cfg",
1073 	.id = SM8250_SLAVE_VSENSE_CTRL_CFG,
1074 	.channels = 1,
1075 	.buswidth = 4,
1076 };
1077 
1078 static struct qcom_icc_node qns_cnoc_a2noc = {
1079 	.name = "qns_cnoc_a2noc",
1080 	.id = SM8250_SLAVE_CNOC_A2NOC,
1081 	.channels = 1,
1082 	.buswidth = 8,
1083 	.num_links = 1,
1084 	.links = { SM8250_MASTER_CNOC_A2NOC },
1085 };
1086 
1087 static struct qcom_icc_node srvc_cnoc = {
1088 	.name = "srvc_cnoc",
1089 	.id = SM8250_SLAVE_SERVICE_CNOC,
1090 	.channels = 1,
1091 	.buswidth = 4,
1092 };
1093 
1094 static struct qcom_icc_node qhs_llcc = {
1095 	.name = "qhs_llcc",
1096 	.id = SM8250_SLAVE_LLCC_CFG,
1097 	.channels = 1,
1098 	.buswidth = 4,
1099 };
1100 
1101 static struct qcom_icc_node qhs_memnoc = {
1102 	.name = "qhs_memnoc",
1103 	.id = SM8250_SLAVE_GEM_NOC_CFG,
1104 	.channels = 1,
1105 	.buswidth = 4,
1106 	.num_links = 1,
1107 	.links = { SM8250_MASTER_GEM_NOC_CFG },
1108 };
1109 
1110 static struct qcom_icc_node qns_gem_noc_snoc = {
1111 	.name = "qns_gem_noc_snoc",
1112 	.id = SM8250_SLAVE_GEM_NOC_SNOC,
1113 	.channels = 1,
1114 	.buswidth = 16,
1115 	.num_links = 1,
1116 	.links = { SM8250_MASTER_GEM_NOC_SNOC },
1117 };
1118 
1119 static struct qcom_icc_node qns_llcc = {
1120 	.name = "qns_llcc",
1121 	.id = SM8250_SLAVE_LLCC,
1122 	.channels = 4,
1123 	.buswidth = 16,
1124 	.num_links = 1,
1125 	.links = { SM8250_MASTER_LLCC },
1126 };
1127 
1128 static struct qcom_icc_node qns_sys_pcie = {
1129 	.name = "qns_sys_pcie",
1130 	.id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC,
1131 	.channels = 1,
1132 	.buswidth = 8,
1133 	.num_links = 1,
1134 	.links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC },
1135 };
1136 
1137 static struct qcom_icc_node srvc_even_gemnoc = {
1138 	.name = "srvc_even_gemnoc",
1139 	.id = SM8250_SLAVE_SERVICE_GEM_NOC_1,
1140 	.channels = 1,
1141 	.buswidth = 4,
1142 };
1143 
1144 static struct qcom_icc_node srvc_odd_gemnoc = {
1145 	.name = "srvc_odd_gemnoc",
1146 	.id = SM8250_SLAVE_SERVICE_GEM_NOC_2,
1147 	.channels = 1,
1148 	.buswidth = 4,
1149 };
1150 
1151 static struct qcom_icc_node srvc_sys_gemnoc = {
1152 	.name = "srvc_sys_gemnoc",
1153 	.id = SM8250_SLAVE_SERVICE_GEM_NOC,
1154 	.channels = 1,
1155 	.buswidth = 4,
1156 };
1157 
1158 static struct qcom_icc_node ebi = {
1159 	.name = "ebi",
1160 	.id = SM8250_SLAVE_EBI_CH0,
1161 	.channels = 4,
1162 	.buswidth = 4,
1163 };
1164 
1165 static struct qcom_icc_node qns_mem_noc_hf = {
1166 	.name = "qns_mem_noc_hf",
1167 	.id = SM8250_SLAVE_MNOC_HF_MEM_NOC,
1168 	.channels = 2,
1169 	.buswidth = 32,
1170 	.num_links = 1,
1171 	.links = { SM8250_MASTER_MNOC_HF_MEM_NOC },
1172 };
1173 
1174 static struct qcom_icc_node qns_mem_noc_sf = {
1175 	.name = "qns_mem_noc_sf",
1176 	.id = SM8250_SLAVE_MNOC_SF_MEM_NOC,
1177 	.channels = 2,
1178 	.buswidth = 32,
1179 	.num_links = 1,
1180 	.links = { SM8250_MASTER_MNOC_SF_MEM_NOC },
1181 };
1182 
1183 static struct qcom_icc_node srvc_mnoc = {
1184 	.name = "srvc_mnoc",
1185 	.id = SM8250_SLAVE_SERVICE_MNOC,
1186 	.channels = 1,
1187 	.buswidth = 4,
1188 };
1189 
1190 static struct qcom_icc_node qhs_cal_dp0 = {
1191 	.name = "qhs_cal_dp0",
1192 	.id = SM8250_SLAVE_NPU_CAL_DP0,
1193 	.channels = 1,
1194 	.buswidth = 4,
1195 };
1196 
1197 static struct qcom_icc_node qhs_cal_dp1 = {
1198 	.name = "qhs_cal_dp1",
1199 	.id = SM8250_SLAVE_NPU_CAL_DP1,
1200 	.channels = 1,
1201 	.buswidth = 4,
1202 };
1203 
1204 static struct qcom_icc_node qhs_cp = {
1205 	.name = "qhs_cp",
1206 	.id = SM8250_SLAVE_NPU_CP,
1207 	.channels = 1,
1208 	.buswidth = 4,
1209 };
1210 
1211 static struct qcom_icc_node qhs_dma_bwmon = {
1212 	.name = "qhs_dma_bwmon",
1213 	.id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
1214 	.channels = 1,
1215 	.buswidth = 4,
1216 };
1217 
1218 static struct qcom_icc_node qhs_dpm = {
1219 	.name = "qhs_dpm",
1220 	.id = SM8250_SLAVE_NPU_DPM,
1221 	.channels = 1,
1222 	.buswidth = 4,
1223 };
1224 
1225 static struct qcom_icc_node qhs_isense = {
1226 	.name = "qhs_isense",
1227 	.id = SM8250_SLAVE_ISENSE_CFG,
1228 	.channels = 1,
1229 	.buswidth = 4,
1230 };
1231 
1232 static struct qcom_icc_node qhs_llm = {
1233 	.name = "qhs_llm",
1234 	.id = SM8250_SLAVE_NPU_LLM_CFG,
1235 	.channels = 1,
1236 	.buswidth = 4,
1237 };
1238 
1239 static struct qcom_icc_node qhs_tcm = {
1240 	.name = "qhs_tcm",
1241 	.id = SM8250_SLAVE_NPU_TCM,
1242 	.channels = 1,
1243 	.buswidth = 4,
1244 };
1245 
1246 static struct qcom_icc_node qns_npu_sys = {
1247 	.name = "qns_npu_sys",
1248 	.id = SM8250_SLAVE_NPU_COMPUTE_NOC,
1249 	.channels = 2,
1250 	.buswidth = 32,
1251 };
1252 
1253 static struct qcom_icc_node srvc_noc = {
1254 	.name = "srvc_noc",
1255 	.id = SM8250_SLAVE_SERVICE_NPU_NOC,
1256 	.channels = 1,
1257 	.buswidth = 4,
1258 };
1259 
1260 static struct qcom_icc_node qhs_apss = {
1261 	.name = "qhs_apss",
1262 	.id = SM8250_SLAVE_APPSS,
1263 	.channels = 1,
1264 	.buswidth = 8,
1265 };
1266 
1267 static struct qcom_icc_node qns_cnoc = {
1268 	.name = "qns_cnoc",
1269 	.id = SM8250_SNOC_CNOC_SLV,
1270 	.channels = 1,
1271 	.buswidth = 8,
1272 	.num_links = 1,
1273 	.links = { SM8250_SNOC_CNOC_MAS },
1274 };
1275 
1276 static struct qcom_icc_node qns_gemnoc_gc = {
1277 	.name = "qns_gemnoc_gc",
1278 	.id = SM8250_SLAVE_SNOC_GEM_NOC_GC,
1279 	.channels = 1,
1280 	.buswidth = 8,
1281 	.num_links = 1,
1282 	.links = { SM8250_MASTER_SNOC_GC_MEM_NOC },
1283 };
1284 
1285 static struct qcom_icc_node qns_gemnoc_sf = {
1286 	.name = "qns_gemnoc_sf",
1287 	.id = SM8250_SLAVE_SNOC_GEM_NOC_SF,
1288 	.channels = 1,
1289 	.buswidth = 16,
1290 	.num_links = 1,
1291 	.links = { SM8250_MASTER_SNOC_SF_MEM_NOC },
1292 };
1293 
1294 static struct qcom_icc_node qxs_imem = {
1295 	.name = "qxs_imem",
1296 	.id = SM8250_SLAVE_OCIMEM,
1297 	.channels = 1,
1298 	.buswidth = 8,
1299 };
1300 
1301 static struct qcom_icc_node qxs_pimem = {
1302 	.name = "qxs_pimem",
1303 	.id = SM8250_SLAVE_PIMEM,
1304 	.channels = 1,
1305 	.buswidth = 8,
1306 };
1307 
1308 static struct qcom_icc_node srvc_snoc = {
1309 	.name = "srvc_snoc",
1310 	.id = SM8250_SLAVE_SERVICE_SNOC,
1311 	.channels = 1,
1312 	.buswidth = 4,
1313 };
1314 
1315 static struct qcom_icc_node xs_pcie_0 = {
1316 	.name = "xs_pcie_0",
1317 	.id = SM8250_SLAVE_PCIE_0,
1318 	.channels = 1,
1319 	.buswidth = 8,
1320 };
1321 
1322 static struct qcom_icc_node xs_pcie_1 = {
1323 	.name = "xs_pcie_1",
1324 	.id = SM8250_SLAVE_PCIE_1,
1325 	.channels = 1,
1326 	.buswidth = 8,
1327 };
1328 
1329 static struct qcom_icc_node xs_pcie_modem = {
1330 	.name = "xs_pcie_modem",
1331 	.id = SM8250_SLAVE_PCIE_2,
1332 	.channels = 1,
1333 	.buswidth = 8,
1334 };
1335 
1336 static struct qcom_icc_node xs_qdss_stm = {
1337 	.name = "xs_qdss_stm",
1338 	.id = SM8250_SLAVE_QDSS_STM,
1339 	.channels = 1,
1340 	.buswidth = 4,
1341 };
1342 
1343 static struct qcom_icc_node xs_sys_tcu_cfg = {
1344 	.name = "xs_sys_tcu_cfg",
1345 	.id = SM8250_SLAVE_TCU,
1346 	.channels = 1,
1347 	.buswidth = 8,
1348 };
1349 
1350 static struct qcom_icc_node qup0_core_master = {
1351 	.name = "qup0_core_master",
1352 	.id = SM8250_MASTER_QUP_CORE_0,
1353 	.channels = 1,
1354 	.buswidth = 4,
1355 	.num_links = 1,
1356 	.links = { SM8250_SLAVE_QUP_CORE_0 },
1357 };
1358 
1359 static struct qcom_icc_node qup1_core_master = {
1360 	.name = "qup1_core_master",
1361 	.id = SM8250_MASTER_QUP_CORE_1,
1362 	.channels = 1,
1363 	.buswidth = 4,
1364 	.num_links = 1,
1365 	.links = { SM8250_SLAVE_QUP_CORE_1 },
1366 };
1367 
1368 static struct qcom_icc_node qup2_core_master = {
1369 	.name = "qup2_core_master",
1370 	.id = SM8250_MASTER_QUP_CORE_2,
1371 	.channels = 1,
1372 	.buswidth = 4,
1373 	.num_links = 1,
1374 	.links = { SM8250_SLAVE_QUP_CORE_2 },
1375 };
1376 
1377 static struct qcom_icc_node qup0_core_slave = {
1378 	.name = "qup0_core_slave",
1379 	.id = SM8250_SLAVE_QUP_CORE_0,
1380 	.channels = 1,
1381 	.buswidth = 4,
1382 };
1383 
1384 static struct qcom_icc_node qup1_core_slave = {
1385 	.name = "qup1_core_slave",
1386 	.id = SM8250_SLAVE_QUP_CORE_1,
1387 	.channels = 1,
1388 	.buswidth = 4,
1389 };
1390 
1391 static struct qcom_icc_node qup2_core_slave = {
1392 	.name = "qup2_core_slave",
1393 	.id = SM8250_SLAVE_QUP_CORE_2,
1394 	.channels = 1,
1395 	.buswidth = 4,
1396 };
1397 
1398 static struct qcom_icc_bcm bcm_acv = {
1399 	.name = "ACV",
1400 	.enable_mask = BIT(3),
1401 	.keepalive = false,
1402 	.num_nodes = 1,
1403 	.nodes = { &ebi },
1404 };
1405 
1406 static struct qcom_icc_bcm bcm_mc0 = {
1407 	.name = "MC0",
1408 	.keepalive = true,
1409 	.num_nodes = 1,
1410 	.nodes = { &ebi },
1411 };
1412 
1413 static struct qcom_icc_bcm bcm_sh0 = {
1414 	.name = "SH0",
1415 	.keepalive = true,
1416 	.num_nodes = 1,
1417 	.nodes = { &qns_llcc },
1418 };
1419 
1420 static struct qcom_icc_bcm bcm_mm0 = {
1421 	.name = "MM0",
1422 	.keepalive = true,
1423 	.num_nodes = 1,
1424 	.nodes = { &qns_mem_noc_hf },
1425 };
1426 
1427 static struct qcom_icc_bcm bcm_ce0 = {
1428 	.name = "CE0",
1429 	.keepalive = false,
1430 	.num_nodes = 1,
1431 	.nodes = { &qxm_crypto },
1432 };
1433 
1434 static struct qcom_icc_bcm bcm_mm1 = {
1435 	.name = "MM1",
1436 	.keepalive = false,
1437 	.num_nodes = 3,
1438 	.nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
1439 };
1440 
1441 static struct qcom_icc_bcm bcm_sh2 = {
1442 	.name = "SH2",
1443 	.keepalive = false,
1444 	.num_nodes = 2,
1445 	.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1446 };
1447 
1448 static struct qcom_icc_bcm bcm_mm2 = {
1449 	.name = "MM2",
1450 	.keepalive = false,
1451 	.num_nodes = 1,
1452 	.nodes = { &qns_mem_noc_sf },
1453 };
1454 
1455 static struct qcom_icc_bcm bcm_qup0 = {
1456 	.name = "QUP0",
1457 	.keepalive = false,
1458 	.num_nodes = 3,
1459 	.nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master },
1460 };
1461 
1462 static struct qcom_icc_bcm bcm_sh3 = {
1463 	.name = "SH3",
1464 	.keepalive = false,
1465 	.num_nodes = 1,
1466 	.nodes = { &qnm_cmpnoc },
1467 };
1468 
1469 static struct qcom_icc_bcm bcm_mm3 = {
1470 	.name = "MM3",
1471 	.keepalive = false,
1472 	.num_nodes = 5,
1473 	.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp },
1474 };
1475 
1476 static struct qcom_icc_bcm bcm_sh4 = {
1477 	.name = "SH4",
1478 	.keepalive = false,
1479 	.num_nodes = 1,
1480 	.nodes = { &chm_apps },
1481 };
1482 
1483 static struct qcom_icc_bcm bcm_sn0 = {
1484 	.name = "SN0",
1485 	.keepalive = true,
1486 	.num_nodes = 1,
1487 	.nodes = { &qns_gemnoc_sf },
1488 };
1489 
1490 static struct qcom_icc_bcm bcm_co0 = {
1491 	.name = "CO0",
1492 	.keepalive = false,
1493 	.num_nodes = 1,
1494 	.nodes = { &qns_cdsp_mem_noc },
1495 };
1496 
1497 static struct qcom_icc_bcm bcm_cn0 = {
1498 	.name = "CN0",
1499 	.keepalive = true,
1500 	.num_nodes = 52,
1501 	.nodes = { &qnm_snoc,
1502 		   &xm_qdss_dap,
1503 		   &qhs_a1_noc_cfg,
1504 		   &qhs_a2_noc_cfg,
1505 		   &qhs_ahb2phy0,
1506 		   &qhs_ahb2phy1,
1507 		   &qhs_aoss,
1508 		   &qhs_camera_cfg,
1509 		   &qhs_clk_ctl,
1510 		   &qhs_compute_dsp,
1511 		   &qhs_cpr_cx,
1512 		   &qhs_cpr_mmcx,
1513 		   &qhs_cpr_mx,
1514 		   &qhs_crypto0_cfg,
1515 		   &qhs_cx_rdpm,
1516 		   &qhs_dcc_cfg,
1517 		   &qhs_ddrss_cfg,
1518 		   &qhs_display_cfg,
1519 		   &qhs_gpuss_cfg,
1520 		   &qhs_imem_cfg,
1521 		   &qhs_ipa,
1522 		   &qhs_ipc_router,
1523 		   &qhs_lpass_cfg,
1524 		   &qhs_mnoc_cfg,
1525 		   &qhs_npu_cfg,
1526 		   &qhs_pcie0_cfg,
1527 		   &qhs_pcie1_cfg,
1528 		   &qhs_pcie_modem_cfg,
1529 		   &qhs_pdm,
1530 		   &qhs_pimem_cfg,
1531 		   &qhs_prng,
1532 		   &qhs_qdss_cfg,
1533 		   &qhs_qspi,
1534 		   &qhs_qup0,
1535 		   &qhs_qup1,
1536 		   &qhs_qup2,
1537 		   &qhs_sdc2,
1538 		   &qhs_sdc4,
1539 		   &qhs_snoc_cfg,
1540 		   &qhs_tcsr,
1541 		   &qhs_tlmm0,
1542 		   &qhs_tlmm1,
1543 		   &qhs_tlmm2,
1544 		   &qhs_tsif,
1545 		   &qhs_ufs_card_cfg,
1546 		   &qhs_ufs_mem_cfg,
1547 		   &qhs_usb3_0,
1548 		   &qhs_usb3_1,
1549 		   &qhs_venus_cfg,
1550 		   &qhs_vsense_ctrl_cfg,
1551 		   &qns_cnoc_a2noc,
1552 		   &srvc_cnoc
1553 	},
1554 };
1555 
1556 static struct qcom_icc_bcm bcm_sn1 = {
1557 	.name = "SN1",
1558 	.keepalive = false,
1559 	.num_nodes = 1,
1560 	.nodes = { &qxs_imem },
1561 };
1562 
1563 static struct qcom_icc_bcm bcm_sn2 = {
1564 	.name = "SN2",
1565 	.keepalive = false,
1566 	.num_nodes = 1,
1567 	.nodes = { &qns_gemnoc_gc },
1568 };
1569 
1570 static struct qcom_icc_bcm bcm_co2 = {
1571 	.name = "CO2",
1572 	.keepalive = false,
1573 	.num_nodes = 1,
1574 	.nodes = { &qnm_npu },
1575 };
1576 
1577 static struct qcom_icc_bcm bcm_sn3 = {
1578 	.name = "SN3",
1579 	.keepalive = false,
1580 	.num_nodes = 1,
1581 	.nodes = { &qxs_pimem },
1582 };
1583 
1584 static struct qcom_icc_bcm bcm_sn4 = {
1585 	.name = "SN4",
1586 	.keepalive = false,
1587 	.num_nodes = 1,
1588 	.nodes = { &xs_qdss_stm },
1589 };
1590 
1591 static struct qcom_icc_bcm bcm_sn5 = {
1592 	.name = "SN5",
1593 	.keepalive = false,
1594 	.num_nodes = 1,
1595 	.nodes = { &xs_pcie_modem },
1596 };
1597 
1598 static struct qcom_icc_bcm bcm_sn6 = {
1599 	.name = "SN6",
1600 	.keepalive = false,
1601 	.num_nodes = 2,
1602 	.nodes = { &xs_pcie_0, &xs_pcie_1 },
1603 };
1604 
1605 static struct qcom_icc_bcm bcm_sn7 = {
1606 	.name = "SN7",
1607 	.keepalive = false,
1608 	.num_nodes = 1,
1609 	.nodes = { &qnm_aggre1_noc },
1610 };
1611 
1612 static struct qcom_icc_bcm bcm_sn8 = {
1613 	.name = "SN8",
1614 	.keepalive = false,
1615 	.num_nodes = 1,
1616 	.nodes = { &qnm_aggre2_noc },
1617 };
1618 
1619 static struct qcom_icc_bcm bcm_sn9 = {
1620 	.name = "SN9",
1621 	.keepalive = false,
1622 	.num_nodes = 1,
1623 	.nodes = { &qnm_gemnoc_pcie },
1624 };
1625 
1626 static struct qcom_icc_bcm bcm_sn11 = {
1627 	.name = "SN11",
1628 	.keepalive = false,
1629 	.num_nodes = 1,
1630 	.nodes = { &qnm_gemnoc },
1631 };
1632 
1633 static struct qcom_icc_bcm bcm_sn12 = {
1634 	.name = "SN12",
1635 	.keepalive = false,
1636 	.num_nodes = 2,
1637 	.nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc },
1638 };
1639 
1640 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1641 	&bcm_sn12,
1642 };
1643 
1644 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1645 	[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1646 	[MASTER_QSPI_0] = &qhm_qspi,
1647 	[MASTER_QUP_1] = &qhm_qup1,
1648 	[MASTER_QUP_2] = &qhm_qup2,
1649 	[MASTER_TSIF] = &qhm_tsif,
1650 	[MASTER_PCIE_2] = &xm_pcie3_modem,
1651 	[MASTER_SDCC_4] = &xm_sdc4,
1652 	[MASTER_UFS_MEM] = &xm_ufs_mem,
1653 	[MASTER_USB3] = &xm_usb3_0,
1654 	[MASTER_USB3_1] = &xm_usb3_1,
1655 	[A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
1656 	[SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
1657 	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1658 };
1659 
1660 static const struct qcom_icc_desc sm8250_aggre1_noc = {
1661 	.nodes = aggre1_noc_nodes,
1662 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1663 	.bcms = aggre1_noc_bcms,
1664 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1665 };
1666 
1667 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1668 	&bcm_ce0,
1669 	&bcm_sn12,
1670 };
1671 
1672 static struct qcom_icc_bcm * const qup_virt_bcms[] = {
1673 	&bcm_qup0,
1674 };
1675 
1676 static struct qcom_icc_node *qup_virt_nodes[] = {
1677 	[MASTER_QUP_CORE_0] = &qup0_core_master,
1678 	[MASTER_QUP_CORE_1] = &qup1_core_master,
1679 	[MASTER_QUP_CORE_2] = &qup2_core_master,
1680 	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1681 	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1682 	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
1683 };
1684 
1685 static const struct qcom_icc_desc sm8250_qup_virt = {
1686 	.nodes = qup_virt_nodes,
1687 	.num_nodes = ARRAY_SIZE(qup_virt_nodes),
1688 	.bcms = qup_virt_bcms,
1689 	.num_bcms = ARRAY_SIZE(qup_virt_bcms),
1690 };
1691 
1692 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1693 	[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1694 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1695 	[MASTER_QUP_0] = &qhm_qup0,
1696 	[MASTER_CNOC_A2NOC] = &qnm_cnoc,
1697 	[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
1698 	[MASTER_IPA] = &qxm_ipa,
1699 	[MASTER_PCIE] = &xm_pcie3_0,
1700 	[MASTER_PCIE_1] = &xm_pcie3_1,
1701 	[MASTER_QDSS_ETR] = &xm_qdss_etr,
1702 	[MASTER_SDCC_2] = &xm_sdc2,
1703 	[MASTER_UFS_CARD] = &xm_ufs_card,
1704 	[A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
1705 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1706 	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1707 };
1708 
1709 static const struct qcom_icc_desc sm8250_aggre2_noc = {
1710 	.nodes = aggre2_noc_nodes,
1711 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1712 	.bcms = aggre2_noc_bcms,
1713 	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1714 };
1715 
1716 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1717 	&bcm_co0,
1718 	&bcm_co2,
1719 };
1720 
1721 static struct qcom_icc_node * const compute_noc_nodes[] = {
1722 	[MASTER_NPU] = &qnm_npu,
1723 	[SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
1724 };
1725 
1726 static const struct qcom_icc_desc sm8250_compute_noc = {
1727 	.nodes = compute_noc_nodes,
1728 	.num_nodes = ARRAY_SIZE(compute_noc_nodes),
1729 	.bcms = compute_noc_bcms,
1730 	.num_bcms = ARRAY_SIZE(compute_noc_bcms),
1731 };
1732 
1733 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1734 	&bcm_cn0,
1735 };
1736 
1737 static struct qcom_icc_node * const config_noc_nodes[] = {
1738 	[SNOC_CNOC_MAS] = &qnm_snoc,
1739 	[MASTER_QDSS_DAP] = &xm_qdss_dap,
1740 	[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1741 	[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1742 	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1743 	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1744 	[SLAVE_AOSS] = &qhs_aoss,
1745 	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1746 	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1747 	[SLAVE_CDSP_CFG] = &qhs_compute_dsp,
1748 	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1749 	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1750 	[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1751 	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1752 	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1753 	[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1754 	[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1755 	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1756 	[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
1757 	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1758 	[SLAVE_IPA_CFG] = &qhs_ipa,
1759 	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1760 	[SLAVE_LPASS] = &qhs_lpass_cfg,
1761 	[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1762 	[SLAVE_NPU_CFG] = &qhs_npu_cfg,
1763 	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1764 	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1765 	[SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
1766 	[SLAVE_PDM] = &qhs_pdm,
1767 	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1768 	[SLAVE_PRNG] = &qhs_prng,
1769 	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1770 	[SLAVE_QSPI_0] = &qhs_qspi,
1771 	[SLAVE_QUP_0] = &qhs_qup0,
1772 	[SLAVE_QUP_1] = &qhs_qup1,
1773 	[SLAVE_QUP_2] = &qhs_qup2,
1774 	[SLAVE_SDCC_2] = &qhs_sdc2,
1775 	[SLAVE_SDCC_4] = &qhs_sdc4,
1776 	[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1777 	[SLAVE_TCSR] = &qhs_tcsr,
1778 	[SLAVE_TLMM_NORTH] = &qhs_tlmm0,
1779 	[SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
1780 	[SLAVE_TLMM_WEST] = &qhs_tlmm2,
1781 	[SLAVE_TSIF] = &qhs_tsif,
1782 	[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
1783 	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1784 	[SLAVE_USB3] = &qhs_usb3_0,
1785 	[SLAVE_USB3_1] = &qhs_usb3_1,
1786 	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1787 	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1788 	[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1789 	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1790 };
1791 
1792 static const struct qcom_icc_desc sm8250_config_noc = {
1793 	.nodes = config_noc_nodes,
1794 	.num_nodes = ARRAY_SIZE(config_noc_nodes),
1795 	.bcms = config_noc_bcms,
1796 	.num_bcms = ARRAY_SIZE(config_noc_bcms),
1797 };
1798 
1799 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1800 };
1801 
1802 static struct qcom_icc_node * const dc_noc_nodes[] = {
1803 	[MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
1804 	[SLAVE_LLCC_CFG] = &qhs_llcc,
1805 	[SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
1806 };
1807 
1808 static const struct qcom_icc_desc sm8250_dc_noc = {
1809 	.nodes = dc_noc_nodes,
1810 	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1811 	.bcms = dc_noc_bcms,
1812 	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
1813 };
1814 
1815 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1816 	&bcm_sh0,
1817 	&bcm_sh2,
1818 	&bcm_sh3,
1819 	&bcm_sh4,
1820 };
1821 
1822 static struct qcom_icc_node * const gem_noc_nodes[] = {
1823 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
1824 	[MASTER_SYS_TCU] = &alm_sys_tcu,
1825 	[MASTER_AMPSS_M0] = &chm_apps,
1826 	[MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1827 	[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1828 	[MASTER_GRAPHICS_3D] = &qnm_gpu,
1829 	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1830 	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1831 	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1832 	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1833 	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1834 	[SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1835 	[SLAVE_LLCC] = &qns_llcc,
1836 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
1837 	[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1838 	[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1839 	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1840 };
1841 
1842 static const struct qcom_icc_desc sm8250_gem_noc = {
1843 	.nodes = gem_noc_nodes,
1844 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1845 	.bcms = gem_noc_bcms,
1846 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1847 };
1848 
1849 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1850 	&bcm_acv,
1851 	&bcm_mc0,
1852 };
1853 
1854 static struct qcom_icc_node * const mc_virt_nodes[] = {
1855 	[MASTER_LLCC] = &llcc_mc,
1856 	[SLAVE_EBI_CH0] = &ebi,
1857 };
1858 
1859 static const struct qcom_icc_desc sm8250_mc_virt = {
1860 	.nodes = mc_virt_nodes,
1861 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1862 	.bcms = mc_virt_bcms,
1863 	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1864 };
1865 
1866 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1867 	&bcm_mm0,
1868 	&bcm_mm1,
1869 	&bcm_mm2,
1870 	&bcm_mm3,
1871 };
1872 
1873 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1874 	[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1875 	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1876 	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1877 	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1878 	[MASTER_VIDEO_P0] = &qnm_video0,
1879 	[MASTER_VIDEO_P1] = &qnm_video1,
1880 	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
1881 	[MASTER_MDP_PORT0] = &qxm_mdp0,
1882 	[MASTER_MDP_PORT1] = &qxm_mdp1,
1883 	[MASTER_ROTATOR] = &qxm_rot,
1884 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1885 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1886 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1887 };
1888 
1889 static const struct qcom_icc_desc sm8250_mmss_noc = {
1890 	.nodes = mmss_noc_nodes,
1891 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1892 	.bcms = mmss_noc_bcms,
1893 	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1894 };
1895 
1896 static struct qcom_icc_bcm * const npu_noc_bcms[] = {
1897 };
1898 
1899 static struct qcom_icc_node * const npu_noc_nodes[] = {
1900 	[MASTER_NPU_SYS] = &amm_npu_sys,
1901 	[MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
1902 	[MASTER_NPU_NOC_CFG] = &qhm_cfg,
1903 	[SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
1904 	[SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
1905 	[SLAVE_NPU_CP] = &qhs_cp,
1906 	[SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
1907 	[SLAVE_NPU_DPM] = &qhs_dpm,
1908 	[SLAVE_ISENSE_CFG] = &qhs_isense,
1909 	[SLAVE_NPU_LLM_CFG] = &qhs_llm,
1910 	[SLAVE_NPU_TCM] = &qhs_tcm,
1911 	[SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
1912 	[SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
1913 };
1914 
1915 static const struct qcom_icc_desc sm8250_npu_noc = {
1916 	.nodes = npu_noc_nodes,
1917 	.num_nodes = ARRAY_SIZE(npu_noc_nodes),
1918 	.bcms = npu_noc_bcms,
1919 	.num_bcms = ARRAY_SIZE(npu_noc_bcms),
1920 };
1921 
1922 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1923 	&bcm_sn0,
1924 	&bcm_sn1,
1925 	&bcm_sn11,
1926 	&bcm_sn2,
1927 	&bcm_sn3,
1928 	&bcm_sn4,
1929 	&bcm_sn5,
1930 	&bcm_sn6,
1931 	&bcm_sn7,
1932 	&bcm_sn8,
1933 	&bcm_sn9,
1934 };
1935 
1936 static struct qcom_icc_node * const system_noc_nodes[] = {
1937 	[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1938 	[A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
1939 	[A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
1940 	[MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1941 	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1942 	[MASTER_PIMEM] = &qxm_pimem,
1943 	[MASTER_GIC] = &xm_gic,
1944 	[SLAVE_APPSS] = &qhs_apss,
1945 	[SNOC_CNOC_SLV] = &qns_cnoc,
1946 	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1947 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1948 	[SLAVE_OCIMEM] = &qxs_imem,
1949 	[SLAVE_PIMEM] = &qxs_pimem,
1950 	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1951 	[SLAVE_PCIE_0] = &xs_pcie_0,
1952 	[SLAVE_PCIE_1] = &xs_pcie_1,
1953 	[SLAVE_PCIE_2] = &xs_pcie_modem,
1954 	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1955 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1956 };
1957 
1958 static const struct qcom_icc_desc sm8250_system_noc = {
1959 	.nodes = system_noc_nodes,
1960 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1961 	.bcms = system_noc_bcms,
1962 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1963 };
1964 
1965 static const struct of_device_id qnoc_of_match[] = {
1966 	{ .compatible = "qcom,sm8250-aggre1-noc",
1967 	  .data = &sm8250_aggre1_noc},
1968 	{ .compatible = "qcom,sm8250-aggre2-noc",
1969 	  .data = &sm8250_aggre2_noc},
1970 	{ .compatible = "qcom,sm8250-compute-noc",
1971 	  .data = &sm8250_compute_noc},
1972 	{ .compatible = "qcom,sm8250-config-noc",
1973 	  .data = &sm8250_config_noc},
1974 	{ .compatible = "qcom,sm8250-dc-noc",
1975 	  .data = &sm8250_dc_noc},
1976 	{ .compatible = "qcom,sm8250-gem-noc",
1977 	  .data = &sm8250_gem_noc},
1978 	{ .compatible = "qcom,sm8250-mc-virt",
1979 	  .data = &sm8250_mc_virt},
1980 	{ .compatible = "qcom,sm8250-mmss-noc",
1981 	  .data = &sm8250_mmss_noc},
1982 	{ .compatible = "qcom,sm8250-npu-noc",
1983 	  .data = &sm8250_npu_noc},
1984 	{ .compatible = "qcom,sm8250-qup-virt",
1985 	  .data = &sm8250_qup_virt },
1986 	{ .compatible = "qcom,sm8250-system-noc",
1987 	  .data = &sm8250_system_noc},
1988 	{ }
1989 };
1990 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1991 
1992 static struct platform_driver qnoc_driver = {
1993 	.probe = qcom_icc_rpmh_probe,
1994 	.remove = qcom_icc_rpmh_remove,
1995 	.driver = {
1996 		.name = "qnoc-sm8250",
1997 		.of_match_table = qnoc_of_match,
1998 		.sync_state = icc_sync_state,
1999 	},
2000 };
2001 module_platform_driver(qnoc_driver);
2002 
2003 MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
2004 MODULE_LICENSE("GPL v2");
2005