1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/moduleparam.h>
9 #include <linux/vmalloc.h>
10 #include <linux/delay.h>
11 #include <linux/kthread.h>
12 #include <linux/mutex.h>
13 #include <linux/kobject.h>
14 #include <linux/slab.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18 #include <linux/trace_events.h>
19 #include <linux/trace.h>
20
21 #include <scsi/scsi_tcq.h>
22 #include <scsi/scsicam.h>
23 #include <scsi/scsi_transport.h>
24 #include <scsi/scsi_transport_fc.h>
25
26 #include "qla_target.h"
27
28 /*
29 * Driver version
30 */
31 char qla2x00_version_str[40];
32
33 static int apidev_major;
34
35 /*
36 * SRB allocation cache
37 */
38 struct kmem_cache *srb_cachep;
39
40 static struct trace_array *qla_trc_array;
41
42 int ql2xfulldump_on_mpifail;
43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
45 "Set this to take full dump on MPI hang.");
46
47 int ql2xenforce_iocb_limit = 2;
48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
49 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
50 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
51 "1: track usage per queue, 2: track usage per adapter");
52
53 /*
54 * CT6 CTX allocation cache
55 */
56 static struct kmem_cache *ctx_cachep;
57 /*
58 * error level for logging
59 */
60 uint ql_errlev = 0x8001;
61
62 int ql2xsecenable;
63 module_param(ql2xsecenable, int, S_IRUGO);
64 MODULE_PARM_DESC(ql2xsecenable,
65 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
66
67 static int ql2xenableclass2;
68 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
69 MODULE_PARM_DESC(ql2xenableclass2,
70 "Specify if Class 2 operations are supported from the very "
71 "beginning. Default is 0 - class 2 not supported.");
72
73
74 int ql2xlogintimeout = 20;
75 module_param(ql2xlogintimeout, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xlogintimeout,
77 "Login timeout value in seconds.");
78
79 int qlport_down_retry;
80 module_param(qlport_down_retry, int, S_IRUGO);
81 MODULE_PARM_DESC(qlport_down_retry,
82 "Maximum number of command retries to a port that returns "
83 "a PORT-DOWN status.");
84
85 int ql2xplogiabsentdevice;
86 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
87 MODULE_PARM_DESC(ql2xplogiabsentdevice,
88 "Option to enable PLOGI to devices that are not present after "
89 "a Fabric scan. This is needed for several broken switches. "
90 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
91
92 int ql2xloginretrycount;
93 module_param(ql2xloginretrycount, int, S_IRUGO);
94 MODULE_PARM_DESC(ql2xloginretrycount,
95 "Specify an alternate value for the NVRAM login retry count.");
96
97 int ql2xallocfwdump = 1;
98 module_param(ql2xallocfwdump, int, S_IRUGO);
99 MODULE_PARM_DESC(ql2xallocfwdump,
100 "Option to enable allocation of memory for a firmware dump "
101 "during HBA initialization. Memory allocation requirements "
102 "vary by ISP type. Default is 1 - allocate memory.");
103
104 int ql2xextended_error_logging;
105 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
106 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
107 MODULE_PARM_DESC(ql2xextended_error_logging,
108 "Option to enable extended error logging,\n"
109 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
110 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
111 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
112 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
113 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
114 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
115 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
116 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
117 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
118 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
119 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
120 "\t\t0x1e400000 - Preferred value for capturing essential "
121 "debug information (equivalent to old "
122 "ql2xextended_error_logging=1).\n"
123 "\t\tDo LOGICAL OR of the value to enable more than one level");
124
125 int ql2xextended_error_logging_ktrace = 1;
126 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
127 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
128 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
129
130 int ql2xshiftctondsd = 6;
131 module_param(ql2xshiftctondsd, int, S_IRUGO);
132 MODULE_PARM_DESC(ql2xshiftctondsd,
133 "Set to control shifting of command type processing "
134 "based on total number of SG elements.");
135
136 int ql2xfdmienable = 1;
137 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
138 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
139 MODULE_PARM_DESC(ql2xfdmienable,
140 "Enables FDMI registrations. "
141 "0 - no FDMI registrations. "
142 "1 - provide FDMI registrations (default).");
143
144 #define MAX_Q_DEPTH 64
145 static int ql2xmaxqdepth = MAX_Q_DEPTH;
146 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
147 MODULE_PARM_DESC(ql2xmaxqdepth,
148 "Maximum queue depth to set for each LUN. "
149 "Default is 64.");
150
151 int ql2xenabledif = 2;
152 module_param(ql2xenabledif, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xenabledif,
154 " Enable T10-CRC-DIF:\n"
155 " Default is 2.\n"
156 " 0 -- No DIF Support\n"
157 " 1 -- Enable DIF for all types\n"
158 " 2 -- Enable DIF for all types, except Type 0.\n");
159
160 #if (IS_ENABLED(CONFIG_NVME_FC))
161 int ql2xnvmeenable = 1;
162 #else
163 int ql2xnvmeenable;
164 #endif
165 module_param(ql2xnvmeenable, int, 0644);
166 MODULE_PARM_DESC(ql2xnvmeenable,
167 "Enables NVME support. "
168 "0 - no NVMe. Default is Y");
169
170 int ql2xenablehba_err_chk = 2;
171 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
172 MODULE_PARM_DESC(ql2xenablehba_err_chk,
173 " Enable T10-CRC-DIF Error isolation by HBA:\n"
174 " Default is 2.\n"
175 " 0 -- Error isolation disabled\n"
176 " 1 -- Error isolation enabled only for DIX Type 0\n"
177 " 2 -- Error isolation enabled for all Types\n");
178
179 int ql2xiidmaenable = 1;
180 module_param(ql2xiidmaenable, int, S_IRUGO);
181 MODULE_PARM_DESC(ql2xiidmaenable,
182 "Enables iIDMA settings "
183 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
184
185 int ql2xmqsupport = 1;
186 module_param(ql2xmqsupport, int, S_IRUGO);
187 MODULE_PARM_DESC(ql2xmqsupport,
188 "Enable on demand multiple queue pairs support "
189 "Default is 1 for supported. "
190 "Set it to 0 to turn off mq qpair support.");
191
192 int ql2xfwloadbin;
193 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
194 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
195 MODULE_PARM_DESC(ql2xfwloadbin,
196 "Option to specify location from which to load ISP firmware:.\n"
197 " 2 -- load firmware via the request_firmware() (hotplug).\n"
198 " interface.\n"
199 " 1 -- load firmware from flash.\n"
200 " 0 -- use default semantics.\n");
201
202 int ql2xetsenable;
203 module_param(ql2xetsenable, int, S_IRUGO);
204 MODULE_PARM_DESC(ql2xetsenable,
205 "Enables firmware ETS burst."
206 "Default is 0 - skip ETS enablement.");
207
208 int ql2xdbwr = 1;
209 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
210 MODULE_PARM_DESC(ql2xdbwr,
211 "Option to specify scheme for request queue posting.\n"
212 " 0 -- Regular doorbell.\n"
213 " 1 -- CAMRAM doorbell (faster).\n");
214
215 int ql2xgffidenable;
216 module_param(ql2xgffidenable, int, S_IRUGO);
217 MODULE_PARM_DESC(ql2xgffidenable,
218 "Enables GFF_ID checks of port type. "
219 "Default is 0 - Do not use GFF_ID information.");
220
221 int ql2xasynctmfenable = 1;
222 module_param(ql2xasynctmfenable, int, S_IRUGO);
223 MODULE_PARM_DESC(ql2xasynctmfenable,
224 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
225 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
226
227 int ql2xdontresethba;
228 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
229 MODULE_PARM_DESC(ql2xdontresethba,
230 "Option to specify reset behaviour.\n"
231 " 0 (Default) -- Reset on failure.\n"
232 " 1 -- Do not reset on failure.\n");
233
234 uint64_t ql2xmaxlun = MAX_LUNS;
235 module_param(ql2xmaxlun, ullong, S_IRUGO);
236 MODULE_PARM_DESC(ql2xmaxlun,
237 "Defines the maximum LU number to register with the SCSI "
238 "midlayer. Default is 65535.");
239
240 int ql2xmdcapmask = 0x1F;
241 module_param(ql2xmdcapmask, int, S_IRUGO);
242 MODULE_PARM_DESC(ql2xmdcapmask,
243 "Set the Minidump driver capture mask level. "
244 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
245
246 int ql2xmdenable = 1;
247 module_param(ql2xmdenable, int, S_IRUGO);
248 MODULE_PARM_DESC(ql2xmdenable,
249 "Enable/disable MiniDump. "
250 "0 - MiniDump disabled. "
251 "1 (Default) - MiniDump enabled.");
252
253 int ql2xexlogins;
254 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
255 MODULE_PARM_DESC(ql2xexlogins,
256 "Number of extended Logins. "
257 "0 (Default)- Disabled.");
258
259 int ql2xexchoffld = 1024;
260 module_param(ql2xexchoffld, uint, 0644);
261 MODULE_PARM_DESC(ql2xexchoffld,
262 "Number of target exchanges.");
263
264 int ql2xiniexchg = 1024;
265 module_param(ql2xiniexchg, uint, 0644);
266 MODULE_PARM_DESC(ql2xiniexchg,
267 "Number of initiator exchanges.");
268
269 int ql2xfwholdabts;
270 module_param(ql2xfwholdabts, int, S_IRUGO);
271 MODULE_PARM_DESC(ql2xfwholdabts,
272 "Allow FW to hold status IOCB until ABTS rsp received. "
273 "0 (Default) Do not set fw option. "
274 "1 - Set fw option to hold ABTS.");
275
276 int ql2xmvasynctoatio = 1;
277 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
278 MODULE_PARM_DESC(ql2xmvasynctoatio,
279 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
280 "0 (Default). Do not move IOCBs"
281 "1 - Move IOCBs.");
282
283 int ql2xautodetectsfp = 1;
284 module_param(ql2xautodetectsfp, int, 0444);
285 MODULE_PARM_DESC(ql2xautodetectsfp,
286 "Detect SFP range and set appropriate distance.\n"
287 "1 (Default): Enable\n");
288
289 int ql2xenablemsix = 1;
290 module_param(ql2xenablemsix, int, 0444);
291 MODULE_PARM_DESC(ql2xenablemsix,
292 "Set to enable MSI or MSI-X interrupt mechanism.\n"
293 " Default is 1, enable MSI-X interrupt mechanism.\n"
294 " 0 -- enable traditional pin-based mechanism.\n"
295 " 1 -- enable MSI-X interrupt mechanism.\n"
296 " 2 -- enable MSI interrupt mechanism.\n");
297
298 int qla2xuseresexchforels;
299 module_param(qla2xuseresexchforels, int, 0444);
300 MODULE_PARM_DESC(qla2xuseresexchforels,
301 "Reserve 1/2 of emergency exchanges for ELS.\n"
302 " 0 (default): disabled");
303
304 static int ql2xprotmask;
305 module_param(ql2xprotmask, int, 0644);
306 MODULE_PARM_DESC(ql2xprotmask,
307 "Override DIF/DIX protection capabilities mask\n"
308 "Default is 0 which sets protection mask based on "
309 "capabilities reported by HBA firmware.\n");
310
311 static int ql2xprotguard;
312 module_param(ql2xprotguard, int, 0644);
313 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
314 " 0 -- Let HBA firmware decide\n"
315 " 1 -- Force T10 CRC\n"
316 " 2 -- Force IP checksum\n");
317
318 int ql2xdifbundlinginternalbuffers;
319 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
320 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
321 "Force using internal buffers for DIF information\n"
322 "0 (Default). Based on check.\n"
323 "1 Force using internal buffers\n");
324
325 int ql2xsmartsan;
326 module_param(ql2xsmartsan, int, 0444);
327 module_param_named(smartsan, ql2xsmartsan, int, 0444);
328 MODULE_PARM_DESC(ql2xsmartsan,
329 "Send SmartSAN Management Attributes for FDMI Registration."
330 " Default is 0 - No SmartSAN registration,"
331 " 1 - Register SmartSAN Management Attributes.");
332
333 int ql2xrdpenable;
334 module_param(ql2xrdpenable, int, 0444);
335 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
336 MODULE_PARM_DESC(ql2xrdpenable,
337 "Enables RDP responses. "
338 "0 - no RDP responses (default). "
339 "1 - provide RDP responses.");
340 int ql2xabts_wait_nvme = 1;
341 module_param(ql2xabts_wait_nvme, int, 0444);
342 MODULE_PARM_DESC(ql2xabts_wait_nvme,
343 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
344
345
346 static u32 ql2xdelay_before_pci_error_handling = 5;
347 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
348 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
349 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
350
351 static void qla2x00_clear_drv_active(struct qla_hw_data *);
352 static void qla2x00_free_device(scsi_qla_host_t *);
353 static void qla2xxx_map_queues(struct Scsi_Host *shost);
354 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
355
356 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
357 module_param(ql2xnvme_queues, uint, S_IRUGO);
358 MODULE_PARM_DESC(ql2xnvme_queues,
359 "Number of NVMe Queues that can be configured.\n"
360 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
361 "1 - Minimum number of queues supported\n"
362 "8 - Default value");
363
364 int ql2xfc2target = 1;
365 module_param(ql2xfc2target, int, 0444);
366 MODULE_PARM_DESC(qla2xfc2target,
367 "Enables FC2 Target support. "
368 "0 - FC2 Target support is disabled. "
369 "1 - FC2 Target support is enabled (default).");
370
371 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
372 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
373
374 /* TODO Convert to inlines
375 *
376 * Timer routines
377 */
378
379 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)380 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
381 {
382 timer_setup(&vha->timer, qla2x00_timer, 0);
383 vha->timer.expires = jiffies + interval * HZ;
384 add_timer(&vha->timer);
385 vha->timer_active = 1;
386 }
387
388 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)389 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
390 {
391 /* Currently used for 82XX only. */
392 if (vha->device_flags & DFLG_DEV_FAILED) {
393 ql_dbg(ql_dbg_timer, vha, 0x600d,
394 "Device in a failed state, returning.\n");
395 return;
396 }
397
398 mod_timer(&vha->timer, jiffies + interval * HZ);
399 }
400
401 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)402 qla2x00_stop_timer(scsi_qla_host_t *vha)
403 {
404 del_timer_sync(&vha->timer);
405 vha->timer_active = 0;
406 }
407
408 static int qla2x00_do_dpc(void *data);
409
410 static void qla2x00_rst_aen(scsi_qla_host_t *);
411
412 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
413 struct req_que **, struct rsp_que **);
414 static void qla2x00_free_fw_dump(struct qla_hw_data *);
415 static void qla2x00_mem_free(struct qla_hw_data *);
416 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
417 struct qla_qpair *qpair);
418
419 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)420 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
421 struct rsp_que *rsp)
422 {
423 struct qla_hw_data *ha = vha->hw;
424
425 rsp->qpair = ha->base_qpair;
426 rsp->req = req;
427 ha->base_qpair->hw = ha;
428 ha->base_qpair->req = req;
429 ha->base_qpair->rsp = rsp;
430 ha->base_qpair->vha = vha;
431 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
432 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
433 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
434 ha->base_qpair->srb_mempool = ha->srb_mempool;
435 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
436 INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
437 ha->base_qpair->enable_class_2 = ql2xenableclass2;
438 /* init qpair to this cpu. Will adjust at run time. */
439 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
440 ha->base_qpair->pdev = ha->pdev;
441
442 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
443 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
444 }
445
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)446 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
447 struct rsp_que *rsp)
448 {
449 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
450
451 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
452 GFP_KERNEL);
453 if (!ha->req_q_map) {
454 ql_log(ql_log_fatal, vha, 0x003b,
455 "Unable to allocate memory for request queue ptrs.\n");
456 goto fail_req_map;
457 }
458
459 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
460 GFP_KERNEL);
461 if (!ha->rsp_q_map) {
462 ql_log(ql_log_fatal, vha, 0x003c,
463 "Unable to allocate memory for response queue ptrs.\n");
464 goto fail_rsp_map;
465 }
466
467 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
468 if (ha->base_qpair == NULL) {
469 ql_log(ql_log_warn, vha, 0x00e0,
470 "Failed to allocate base queue pair memory.\n");
471 goto fail_base_qpair;
472 }
473
474 qla_init_base_qpair(vha, req, rsp);
475
476 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
477 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
478 GFP_KERNEL);
479 if (!ha->queue_pair_map) {
480 ql_log(ql_log_fatal, vha, 0x0180,
481 "Unable to allocate memory for queue pair ptrs.\n");
482 goto fail_qpair_map;
483 }
484 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
485 kfree(ha->queue_pair_map);
486 ha->queue_pair_map = NULL;
487 goto fail_qpair_map;
488 }
489 }
490
491 /*
492 * Make sure we record at least the request and response queue zero in
493 * case we need to free them if part of the probe fails.
494 */
495 ha->rsp_q_map[0] = rsp;
496 ha->req_q_map[0] = req;
497 set_bit(0, ha->rsp_qid_map);
498 set_bit(0, ha->req_qid_map);
499 return 0;
500
501 fail_qpair_map:
502 kfree(ha->base_qpair);
503 ha->base_qpair = NULL;
504 fail_base_qpair:
505 kfree(ha->rsp_q_map);
506 ha->rsp_q_map = NULL;
507 fail_rsp_map:
508 kfree(ha->req_q_map);
509 ha->req_q_map = NULL;
510 fail_req_map:
511 return -ENOMEM;
512 }
513
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)514 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
515 {
516 if (IS_QLAFX00(ha)) {
517 if (req && req->ring_fx00)
518 dma_free_coherent(&ha->pdev->dev,
519 (req->length_fx00 + 1) * sizeof(request_t),
520 req->ring_fx00, req->dma_fx00);
521 } else if (req && req->ring)
522 dma_free_coherent(&ha->pdev->dev,
523 (req->length + 1) * sizeof(request_t),
524 req->ring, req->dma);
525
526 if (req)
527 kfree(req->outstanding_cmds);
528
529 kfree(req);
530 }
531
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)532 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
533 {
534 if (IS_QLAFX00(ha)) {
535 if (rsp && rsp->ring_fx00)
536 dma_free_coherent(&ha->pdev->dev,
537 (rsp->length_fx00 + 1) * sizeof(request_t),
538 rsp->ring_fx00, rsp->dma_fx00);
539 } else if (rsp && rsp->ring) {
540 dma_free_coherent(&ha->pdev->dev,
541 (rsp->length + 1) * sizeof(response_t),
542 rsp->ring, rsp->dma);
543 }
544 kfree(rsp);
545 }
546
qla2x00_free_queues(struct qla_hw_data * ha)547 static void qla2x00_free_queues(struct qla_hw_data *ha)
548 {
549 struct req_que *req;
550 struct rsp_que *rsp;
551 int cnt;
552 unsigned long flags;
553
554 if (ha->queue_pair_map) {
555 kfree(ha->queue_pair_map);
556 ha->queue_pair_map = NULL;
557 }
558 if (ha->base_qpair) {
559 kfree(ha->base_qpair);
560 ha->base_qpair = NULL;
561 }
562
563 qla_mapq_free_qp_cpu_map(ha);
564 spin_lock_irqsave(&ha->hardware_lock, flags);
565 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
566 if (!test_bit(cnt, ha->req_qid_map))
567 continue;
568
569 req = ha->req_q_map[cnt];
570 clear_bit(cnt, ha->req_qid_map);
571 ha->req_q_map[cnt] = NULL;
572
573 spin_unlock_irqrestore(&ha->hardware_lock, flags);
574 qla2x00_free_req_que(ha, req);
575 spin_lock_irqsave(&ha->hardware_lock, flags);
576 }
577 spin_unlock_irqrestore(&ha->hardware_lock, flags);
578
579 kfree(ha->req_q_map);
580 ha->req_q_map = NULL;
581
582
583 spin_lock_irqsave(&ha->hardware_lock, flags);
584 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
585 if (!test_bit(cnt, ha->rsp_qid_map))
586 continue;
587
588 rsp = ha->rsp_q_map[cnt];
589 clear_bit(cnt, ha->rsp_qid_map);
590 ha->rsp_q_map[cnt] = NULL;
591 spin_unlock_irqrestore(&ha->hardware_lock, flags);
592 qla2x00_free_rsp_que(ha, rsp);
593 spin_lock_irqsave(&ha->hardware_lock, flags);
594 }
595 spin_unlock_irqrestore(&ha->hardware_lock, flags);
596
597 kfree(ha->rsp_q_map);
598 ha->rsp_q_map = NULL;
599 }
600
601 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)602 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
603 {
604 struct qla_hw_data *ha = vha->hw;
605 static const char *const pci_bus_modes[] = {
606 "33", "66", "100", "133",
607 };
608 uint16_t pci_bus;
609
610 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
611 if (pci_bus) {
612 snprintf(str, str_len, "PCI-X (%s MHz)",
613 pci_bus_modes[pci_bus]);
614 } else {
615 pci_bus = (ha->pci_attr & BIT_8) >> 8;
616 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
617 }
618
619 return str;
620 }
621
622 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)623 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
624 {
625 static const char *const pci_bus_modes[] = {
626 "33", "66", "100", "133",
627 };
628 struct qla_hw_data *ha = vha->hw;
629 uint32_t pci_bus;
630
631 if (pci_is_pcie(ha->pdev)) {
632 uint32_t lstat, lspeed, lwidth;
633 const char *speed_str;
634
635 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
636 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
637 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
638
639 switch (lspeed) {
640 case 1:
641 speed_str = "2.5GT/s";
642 break;
643 case 2:
644 speed_str = "5.0GT/s";
645 break;
646 case 3:
647 speed_str = "8.0GT/s";
648 break;
649 case 4:
650 speed_str = "16.0GT/s";
651 break;
652 default:
653 speed_str = "<unknown>";
654 break;
655 }
656 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
657
658 return str;
659 }
660
661 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
662 if (pci_bus == 0 || pci_bus == 8)
663 snprintf(str, str_len, "PCI (%s MHz)",
664 pci_bus_modes[pci_bus >> 3]);
665 else
666 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
667 pci_bus & 4 ? 2 : 1,
668 pci_bus_modes[pci_bus & 3]);
669
670 return str;
671 }
672
673 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)674 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
675 {
676 char un_str[10];
677 struct qla_hw_data *ha = vha->hw;
678
679 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
680 ha->fw_minor_version, ha->fw_subminor_version);
681
682 if (ha->fw_attributes & BIT_9) {
683 strcat(str, "FLX");
684 return (str);
685 }
686
687 switch (ha->fw_attributes & 0xFF) {
688 case 0x7:
689 strcat(str, "EF");
690 break;
691 case 0x17:
692 strcat(str, "TP");
693 break;
694 case 0x37:
695 strcat(str, "IP");
696 break;
697 case 0x77:
698 strcat(str, "VI");
699 break;
700 default:
701 sprintf(un_str, "(%x)", ha->fw_attributes);
702 strcat(str, un_str);
703 break;
704 }
705 if (ha->fw_attributes & 0x100)
706 strcat(str, "X");
707
708 return (str);
709 }
710
711 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)712 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
713 {
714 struct qla_hw_data *ha = vha->hw;
715
716 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
717 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
718 return str;
719 }
720
qla2x00_sp_free_dma(srb_t * sp)721 void qla2x00_sp_free_dma(srb_t *sp)
722 {
723 struct qla_hw_data *ha = sp->vha->hw;
724 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
725
726 if (sp->flags & SRB_DMA_VALID) {
727 scsi_dma_unmap(cmd);
728 sp->flags &= ~SRB_DMA_VALID;
729 }
730
731 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
732 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
733 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
734 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
735 }
736
737 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
738 /* List assured to be having elements */
739 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
740 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
741 }
742
743 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
744 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
745
746 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
747 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
748 }
749
750 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
751 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
752
753 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
754 ctx1->fcp_cmnd_dma);
755 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
756 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
757 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
758 }
759
760 if (sp->flags & SRB_GOT_BUF)
761 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
762 }
763
qla2x00_sp_compl(srb_t * sp,int res)764 void qla2x00_sp_compl(srb_t *sp, int res)
765 {
766 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
767 struct completion *comp = sp->comp;
768
769 /* kref: INIT */
770 kref_put(&sp->cmd_kref, qla2x00_sp_release);
771 cmd->result = res;
772 sp->type = 0;
773 scsi_done(cmd);
774 if (comp)
775 complete(comp);
776 }
777
qla2xxx_qpair_sp_free_dma(srb_t * sp)778 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
779 {
780 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
781 struct qla_hw_data *ha = sp->fcport->vha->hw;
782
783 if (sp->flags & SRB_DMA_VALID) {
784 scsi_dma_unmap(cmd);
785 sp->flags &= ~SRB_DMA_VALID;
786 }
787
788 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
789 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
790 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
791 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
792 }
793
794 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
795 /* List assured to be having elements */
796 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
797 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
798 }
799
800 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
801 struct crc_context *difctx = sp->u.scmd.crc_ctx;
802 struct dsd_dma *dif_dsd, *nxt_dsd;
803
804 list_for_each_entry_safe(dif_dsd, nxt_dsd,
805 &difctx->ldif_dma_hndl_list, list) {
806 list_del(&dif_dsd->list);
807 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
808 dif_dsd->dsd_list_dma);
809 kfree(dif_dsd);
810 difctx->no_dif_bundl--;
811 }
812
813 list_for_each_entry_safe(dif_dsd, nxt_dsd,
814 &difctx->ldif_dsd_list, list) {
815 list_del(&dif_dsd->list);
816 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
817 dif_dsd->dsd_list_dma);
818 kfree(dif_dsd);
819 difctx->no_ldif_dsd--;
820 }
821
822 if (difctx->no_ldif_dsd) {
823 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
824 "%s: difctx->no_ldif_dsd=%x\n",
825 __func__, difctx->no_ldif_dsd);
826 }
827
828 if (difctx->no_dif_bundl) {
829 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
830 "%s: difctx->no_dif_bundl=%x\n",
831 __func__, difctx->no_dif_bundl);
832 }
833 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
834 }
835
836 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
837 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
838
839 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
840 ctx1->fcp_cmnd_dma);
841 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
842 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
843 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
844 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
845 }
846
847 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
848 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
849
850 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
851 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
852 }
853
854 if (sp->flags & SRB_GOT_BUF)
855 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
856 }
857
qla2xxx_qpair_sp_compl(srb_t * sp,int res)858 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
859 {
860 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
861 struct completion *comp = sp->comp;
862
863 /* ref: INIT */
864 kref_put(&sp->cmd_kref, qla2x00_sp_release);
865 cmd->result = res;
866 sp->type = 0;
867 scsi_done(cmd);
868 if (comp)
869 complete(comp);
870 }
871
872 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)873 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
874 {
875 scsi_qla_host_t *vha = shost_priv(host);
876 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
877 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
878 struct qla_hw_data *ha = vha->hw;
879 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
880 srb_t *sp;
881 int rval;
882
883 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
884 WARN_ON_ONCE(!rport)) {
885 cmd->result = DID_NO_CONNECT << 16;
886 goto qc24_fail_command;
887 }
888
889 if (ha->mqenable) {
890 uint32_t tag;
891 uint16_t hwq;
892 struct qla_qpair *qpair = NULL;
893
894 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
895 hwq = blk_mq_unique_tag_to_hwq(tag);
896 qpair = ha->queue_pair_map[hwq];
897
898 if (qpair)
899 return qla2xxx_mqueuecommand(host, cmd, qpair);
900 }
901
902 if (ha->flags.eeh_busy) {
903 if (ha->flags.pci_channel_io_perm_failure) {
904 ql_dbg(ql_dbg_aer, vha, 0x9010,
905 "PCI Channel IO permanent failure, exiting "
906 "cmd=%p.\n", cmd);
907 cmd->result = DID_NO_CONNECT << 16;
908 } else {
909 ql_dbg(ql_dbg_aer, vha, 0x9011,
910 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
911 cmd->result = DID_REQUEUE << 16;
912 }
913 goto qc24_fail_command;
914 }
915
916 rval = fc_remote_port_chkready(rport);
917 if (rval) {
918 cmd->result = rval;
919 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
920 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
921 cmd, rval);
922 goto qc24_fail_command;
923 }
924
925 if (!vha->flags.difdix_supported &&
926 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
927 ql_dbg(ql_dbg_io, vha, 0x3004,
928 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
929 cmd);
930 cmd->result = DID_NO_CONNECT << 16;
931 goto qc24_fail_command;
932 }
933
934 if (!fcport || fcport->deleted) {
935 cmd->result = DID_IMM_RETRY << 16;
936 goto qc24_fail_command;
937 }
938
939 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
940 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
941 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
942 ql_dbg(ql_dbg_io, vha, 0x3005,
943 "Returning DNC, fcport_state=%d loop_state=%d.\n",
944 atomic_read(&fcport->state),
945 atomic_read(&base_vha->loop_state));
946 cmd->result = DID_NO_CONNECT << 16;
947 goto qc24_fail_command;
948 }
949 goto qc24_target_busy;
950 }
951
952 /*
953 * Return target busy if we've received a non-zero retry_delay_timer
954 * in a FCP_RSP.
955 */
956 if (fcport->retry_delay_timestamp == 0) {
957 /* retry delay not set */
958 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
959 fcport->retry_delay_timestamp = 0;
960 else
961 goto qc24_target_busy;
962
963 sp = scsi_cmd_priv(cmd);
964 /* ref: INIT */
965 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
966
967 sp->u.scmd.cmd = cmd;
968 sp->type = SRB_SCSI_CMD;
969 sp->free = qla2x00_sp_free_dma;
970 sp->done = qla2x00_sp_compl;
971
972 rval = ha->isp_ops->start_scsi(sp);
973 if (rval != QLA_SUCCESS) {
974 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
975 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
976 goto qc24_host_busy_free_sp;
977 }
978
979 return 0;
980
981 qc24_host_busy_free_sp:
982 /* ref: INIT */
983 kref_put(&sp->cmd_kref, qla2x00_sp_release);
984
985 qc24_target_busy:
986 return SCSI_MLQUEUE_TARGET_BUSY;
987
988 qc24_fail_command:
989 scsi_done(cmd);
990
991 return 0;
992 }
993
994 /* For MQ supported I/O */
995 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)996 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
997 struct qla_qpair *qpair)
998 {
999 scsi_qla_host_t *vha = shost_priv(host);
1000 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1001 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
1002 struct qla_hw_data *ha = vha->hw;
1003 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1004 srb_t *sp;
1005 int rval;
1006
1007 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
1008 if (rval) {
1009 cmd->result = rval;
1010 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
1011 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1012 cmd, rval);
1013 goto qc24_fail_command;
1014 }
1015
1016 if (!qpair->online) {
1017 ql_dbg(ql_dbg_io, vha, 0x3077,
1018 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1019 cmd->result = DID_NO_CONNECT << 16;
1020 goto qc24_fail_command;
1021 }
1022
1023 if (!fcport || fcport->deleted) {
1024 cmd->result = DID_IMM_RETRY << 16;
1025 goto qc24_fail_command;
1026 }
1027
1028 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1029 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1030 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1031 ql_dbg(ql_dbg_io, vha, 0x3077,
1032 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1033 atomic_read(&fcport->state),
1034 atomic_read(&base_vha->loop_state));
1035 cmd->result = DID_NO_CONNECT << 16;
1036 goto qc24_fail_command;
1037 }
1038 goto qc24_target_busy;
1039 }
1040
1041 /*
1042 * Return target busy if we've received a non-zero retry_delay_timer
1043 * in a FCP_RSP.
1044 */
1045 if (fcport->retry_delay_timestamp == 0) {
1046 /* retry delay not set */
1047 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1048 fcport->retry_delay_timestamp = 0;
1049 else
1050 goto qc24_target_busy;
1051
1052 sp = scsi_cmd_priv(cmd);
1053 /* ref: INIT */
1054 qla2xxx_init_sp(sp, vha, qpair, fcport);
1055
1056 sp->u.scmd.cmd = cmd;
1057 sp->type = SRB_SCSI_CMD;
1058 sp->free = qla2xxx_qpair_sp_free_dma;
1059 sp->done = qla2xxx_qpair_sp_compl;
1060
1061 rval = ha->isp_ops->start_scsi_mq(sp);
1062 if (rval != QLA_SUCCESS) {
1063 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1064 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1065 goto qc24_host_busy_free_sp;
1066 }
1067
1068 return 0;
1069
1070 qc24_host_busy_free_sp:
1071 /* ref: INIT */
1072 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1073
1074 qc24_target_busy:
1075 return SCSI_MLQUEUE_TARGET_BUSY;
1076
1077 qc24_fail_command:
1078 scsi_done(cmd);
1079
1080 return 0;
1081 }
1082
1083 /*
1084 * qla2x00_wait_for_hba_online
1085 * Wait till the HBA is online after going through
1086 * <= MAX_RETRIES_OF_ISP_ABORT or
1087 * finally HBA is disabled ie marked offline
1088 *
1089 * Input:
1090 * ha - pointer to host adapter structure
1091 *
1092 * Note:
1093 * Does context switching-Release SPIN_LOCK
1094 * (if any) before calling this routine.
1095 *
1096 * Return:
1097 * Success (Adapter is online) : 0
1098 * Failed (Adapter is offline/disabled) : 1
1099 */
1100 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1101 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1102 {
1103 int return_status;
1104 unsigned long wait_online;
1105 struct qla_hw_data *ha = vha->hw;
1106 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1107
1108 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1109 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1110 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1111 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1112 ha->dpc_active) && time_before(jiffies, wait_online)) {
1113
1114 msleep(1000);
1115 }
1116 if (base_vha->flags.online)
1117 return_status = QLA_SUCCESS;
1118 else
1119 return_status = QLA_FUNCTION_FAILED;
1120
1121 return (return_status);
1122 }
1123
test_fcport_count(scsi_qla_host_t * vha)1124 static inline int test_fcport_count(scsi_qla_host_t *vha)
1125 {
1126 struct qla_hw_data *ha = vha->hw;
1127 unsigned long flags;
1128 int res;
1129 /* Return 0 = sleep, x=wake */
1130
1131 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1132 ql_dbg(ql_dbg_init, vha, 0x00ec,
1133 "tgt %p, fcport_count=%d\n",
1134 vha, vha->fcport_count);
1135 res = (vha->fcport_count == 0);
1136 if (res) {
1137 struct fc_port *fcport;
1138
1139 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1140 if (fcport->deleted != QLA_SESS_DELETED) {
1141 /* session(s) may not be fully logged in
1142 * (ie fcport_count=0), but session
1143 * deletion thread(s) may be inflight.
1144 */
1145
1146 res = 0;
1147 break;
1148 }
1149 }
1150 }
1151 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1152
1153 return res;
1154 }
1155
1156 /*
1157 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1158 * it has dependency on UNLOADING flag to stop device discovery
1159 */
1160 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1161 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1162 {
1163 u8 i;
1164
1165 qla2x00_mark_all_devices_lost(vha);
1166
1167 for (i = 0; i < 10; i++) {
1168 if (wait_event_timeout(vha->fcport_waitQ,
1169 test_fcport_count(vha), HZ) > 0)
1170 break;
1171 }
1172
1173 flush_workqueue(vha->hw->wq);
1174 }
1175
1176 /*
1177 * qla2x00_wait_for_hba_ready
1178 * Wait till the HBA is ready before doing driver unload
1179 *
1180 * Input:
1181 * ha - pointer to host adapter structure
1182 *
1183 * Note:
1184 * Does context switching-Release SPIN_LOCK
1185 * (if any) before calling this routine.
1186 *
1187 */
1188 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1189 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1190 {
1191 struct qla_hw_data *ha = vha->hw;
1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1193
1194 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1195 ha->flags.mbox_busy) ||
1196 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1197 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1198 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1199 break;
1200 msleep(1000);
1201 }
1202 }
1203
1204 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1205 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1206 {
1207 int return_status;
1208 unsigned long wait_reset;
1209 struct qla_hw_data *ha = vha->hw;
1210 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1211
1212 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1213 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1214 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1215 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1216 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1217
1218 msleep(1000);
1219
1220 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1221 ha->flags.chip_reset_done)
1222 break;
1223 }
1224 if (ha->flags.chip_reset_done)
1225 return_status = QLA_SUCCESS;
1226 else
1227 return_status = QLA_FUNCTION_FAILED;
1228
1229 return return_status;
1230 }
1231
1232 /**************************************************************************
1233 * qla2xxx_eh_abort
1234 *
1235 * Description:
1236 * The abort function will abort the specified command.
1237 *
1238 * Input:
1239 * cmd = Linux SCSI command packet to be aborted.
1240 *
1241 * Returns:
1242 * Either SUCCESS or FAILED.
1243 *
1244 * Note:
1245 * Only return FAILED if command not returned by firmware.
1246 **************************************************************************/
1247 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1248 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1249 {
1250 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1251 DECLARE_COMPLETION_ONSTACK(comp);
1252 srb_t *sp;
1253 int ret;
1254 unsigned int id;
1255 uint64_t lun;
1256 int rval;
1257 struct qla_hw_data *ha = vha->hw;
1258 uint32_t ratov_j;
1259 struct qla_qpair *qpair;
1260 unsigned long flags;
1261 int fast_fail_status = SUCCESS;
1262
1263 if (qla2x00_isp_reg_stat(ha)) {
1264 ql_log(ql_log_info, vha, 0x8042,
1265 "PCI/Register disconnect, exiting.\n");
1266 qla_pci_set_eeh_busy(vha);
1267 return FAILED;
1268 }
1269
1270 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
1271 ret = fc_block_scsi_eh(cmd);
1272 if (ret != 0)
1273 fast_fail_status = ret;
1274
1275 sp = scsi_cmd_priv(cmd);
1276 qpair = sp->qpair;
1277
1278 vha->cmd_timeout_cnt++;
1279
1280 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1281 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1282
1283 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1284 sp->comp = ∁
1285 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1286
1287
1288 id = cmd->device->id;
1289 lun = cmd->device->lun;
1290
1291 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1292 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1293 vha->host_no, id, lun, sp, cmd, sp->handle);
1294
1295 /*
1296 * Abort will release the original Command/sp from FW. Let the
1297 * original command call scsi_done. In return, he will wakeup
1298 * this sleeping thread.
1299 */
1300 rval = ha->isp_ops->abort_command(sp);
1301
1302 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1303 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1304
1305 /* Wait for the command completion. */
1306 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1307 ratov_j = msecs_to_jiffies(ratov_j);
1308 switch (rval) {
1309 case QLA_SUCCESS:
1310 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1311 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1312 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1313 __func__, ha->r_a_tov/10);
1314 ret = FAILED;
1315 } else {
1316 ret = fast_fail_status;
1317 }
1318 break;
1319 default:
1320 ret = FAILED;
1321 break;
1322 }
1323
1324 sp->comp = NULL;
1325
1326 ql_log(ql_log_info, vha, 0x801c,
1327 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1328 vha->host_no, id, lun, ret);
1329
1330 return ret;
1331 }
1332
1333 #define ABORT_POLLING_PERIOD 1000
1334 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1335
1336 /*
1337 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1338 */
1339 static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1340 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1341 uint64_t l, enum nexus_wait_type type)
1342 {
1343 int cnt, match, status;
1344 unsigned long flags;
1345 scsi_qla_host_t *vha = qpair->vha;
1346 struct req_que *req = qpair->req;
1347 srb_t *sp;
1348 struct scsi_cmnd *cmd;
1349 unsigned long wait_iter = ABORT_WAIT_ITER;
1350 bool found;
1351 struct qla_hw_data *ha = vha->hw;
1352
1353 status = QLA_SUCCESS;
1354
1355 while (wait_iter--) {
1356 found = false;
1357
1358 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1359 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1360 sp = req->outstanding_cmds[cnt];
1361 if (!sp)
1362 continue;
1363 if (sp->type != SRB_SCSI_CMD)
1364 continue;
1365 if (vha->vp_idx != sp->vha->vp_idx)
1366 continue;
1367 match = 0;
1368 cmd = GET_CMD_SP(sp);
1369 switch (type) {
1370 case WAIT_HOST:
1371 match = 1;
1372 break;
1373 case WAIT_TARGET:
1374 if (sp->fcport)
1375 match = sp->fcport->d_id.b24 == t;
1376 else
1377 match = 0;
1378 break;
1379 case WAIT_LUN:
1380 if (sp->fcport)
1381 match = (sp->fcport->d_id.b24 == t &&
1382 cmd->device->lun == l);
1383 else
1384 match = 0;
1385 break;
1386 }
1387 if (!match)
1388 continue;
1389
1390 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1391
1392 if (unlikely(pci_channel_offline(ha->pdev)) ||
1393 ha->flags.eeh_busy) {
1394 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1395 "Return:eh_wait.\n");
1396 return status;
1397 }
1398
1399 /*
1400 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1401 * it means scsi_done has not called. Wait for it to
1402 * clear from outstanding_cmds.
1403 */
1404 msleep(ABORT_POLLING_PERIOD);
1405 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1406 found = true;
1407 }
1408 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1409
1410 if (!found)
1411 break;
1412 }
1413
1414 if (wait_iter == -1)
1415 status = QLA_FUNCTION_FAILED;
1416
1417 return status;
1418 }
1419
1420 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1422 uint64_t l, enum nexus_wait_type type)
1423 {
1424 struct qla_qpair *qpair;
1425 struct qla_hw_data *ha = vha->hw;
1426 int i, status = QLA_SUCCESS;
1427
1428 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1429 type);
1430 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1431 qpair = ha->queue_pair_map[i];
1432 if (!qpair)
1433 continue;
1434 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1435 type);
1436 }
1437 return status;
1438 }
1439
1440 static char *reset_errors[] = {
1441 "HBA not online",
1442 "HBA not ready",
1443 "Task management failed",
1444 "Waiting for command completions",
1445 };
1446
1447 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1449 {
1450 struct scsi_device *sdev = cmd->device;
1451 scsi_qla_host_t *vha = shost_priv(sdev->host);
1452 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1453 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1454 struct qla_hw_data *ha = vha->hw;
1455 int err;
1456
1457 if (qla2x00_isp_reg_stat(ha)) {
1458 ql_log(ql_log_info, vha, 0x803e,
1459 "PCI/Register disconnect, exiting.\n");
1460 qla_pci_set_eeh_busy(vha);
1461 return FAILED;
1462 }
1463
1464 if (!fcport) {
1465 return FAILED;
1466 }
1467
1468 err = fc_block_rport(rport);
1469 if (err != 0)
1470 return err;
1471
1472 if (fcport->deleted)
1473 return FAILED;
1474
1475 ql_log(ql_log_info, vha, 0x8009,
1476 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1477 sdev->id, sdev->lun, cmd);
1478
1479 err = 0;
1480 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1481 ql_log(ql_log_warn, vha, 0x800a,
1482 "Wait for hba online failed for cmd=%p.\n", cmd);
1483 goto eh_reset_failed;
1484 }
1485 err = 2;
1486 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1487 != QLA_SUCCESS) {
1488 ql_log(ql_log_warn, vha, 0x800c,
1489 "do_reset failed for cmd=%p.\n", cmd);
1490 goto eh_reset_failed;
1491 }
1492 err = 3;
1493 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1494 cmd->device->lun,
1495 WAIT_LUN) != QLA_SUCCESS) {
1496 ql_log(ql_log_warn, vha, 0x800d,
1497 "wait for pending cmds failed for cmd=%p.\n", cmd);
1498 goto eh_reset_failed;
1499 }
1500
1501 ql_log(ql_log_info, vha, 0x800e,
1502 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1503 vha->host_no, sdev->id, sdev->lun, cmd);
1504
1505 return SUCCESS;
1506
1507 eh_reset_failed:
1508 ql_log(ql_log_info, vha, 0x800f,
1509 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1510 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1511 cmd);
1512 vha->reset_cmd_err_cnt++;
1513 return FAILED;
1514 }
1515
1516 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1517 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1518 {
1519 struct scsi_device *sdev = cmd->device;
1520 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1521 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1522 struct qla_hw_data *ha = vha->hw;
1523 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1524 int err;
1525
1526 if (qla2x00_isp_reg_stat(ha)) {
1527 ql_log(ql_log_info, vha, 0x803f,
1528 "PCI/Register disconnect, exiting.\n");
1529 qla_pci_set_eeh_busy(vha);
1530 return FAILED;
1531 }
1532
1533 if (!fcport) {
1534 return FAILED;
1535 }
1536
1537 err = fc_block_rport(rport);
1538 if (err != 0)
1539 return err;
1540
1541 if (fcport->deleted)
1542 return FAILED;
1543
1544 ql_log(ql_log_info, vha, 0x8009,
1545 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1546 sdev->id, cmd);
1547
1548 err = 0;
1549 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1550 ql_log(ql_log_warn, vha, 0x800a,
1551 "Wait for hba online failed for cmd=%p.\n", cmd);
1552 goto eh_reset_failed;
1553 }
1554 err = 2;
1555 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1556 ql_log(ql_log_warn, vha, 0x800c,
1557 "target_reset failed for cmd=%p.\n", cmd);
1558 goto eh_reset_failed;
1559 }
1560 err = 3;
1561 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1562 WAIT_TARGET) != QLA_SUCCESS) {
1563 ql_log(ql_log_warn, vha, 0x800d,
1564 "wait for pending cmds failed for cmd=%p.\n", cmd);
1565 goto eh_reset_failed;
1566 }
1567
1568 ql_log(ql_log_info, vha, 0x800e,
1569 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1570 vha->host_no, sdev->id, cmd);
1571
1572 return SUCCESS;
1573
1574 eh_reset_failed:
1575 ql_log(ql_log_info, vha, 0x800f,
1576 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1577 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1578 cmd);
1579 vha->reset_cmd_err_cnt++;
1580 return FAILED;
1581 }
1582
1583 /**************************************************************************
1584 * qla2xxx_eh_bus_reset
1585 *
1586 * Description:
1587 * The bus reset function will reset the bus and abort any executing
1588 * commands.
1589 *
1590 * Input:
1591 * cmd = Linux SCSI command packet of the command that cause the
1592 * bus reset.
1593 *
1594 * Returns:
1595 * SUCCESS/FAILURE (defined as macro in scsi.h).
1596 *
1597 **************************************************************************/
1598 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1599 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1600 {
1601 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1602 int ret = FAILED;
1603 unsigned int id;
1604 uint64_t lun;
1605 struct qla_hw_data *ha = vha->hw;
1606
1607 if (qla2x00_isp_reg_stat(ha)) {
1608 ql_log(ql_log_info, vha, 0x8040,
1609 "PCI/Register disconnect, exiting.\n");
1610 qla_pci_set_eeh_busy(vha);
1611 return FAILED;
1612 }
1613
1614 id = cmd->device->id;
1615 lun = cmd->device->lun;
1616
1617 if (qla2x00_chip_is_down(vha))
1618 return ret;
1619
1620 ql_log(ql_log_info, vha, 0x8012,
1621 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1622
1623 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1624 ql_log(ql_log_fatal, vha, 0x8013,
1625 "Wait for hba online failed board disabled.\n");
1626 goto eh_bus_reset_done;
1627 }
1628
1629 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1630 ret = SUCCESS;
1631
1632 if (ret == FAILED)
1633 goto eh_bus_reset_done;
1634
1635 /* Flush outstanding commands. */
1636 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1637 QLA_SUCCESS) {
1638 ql_log(ql_log_warn, vha, 0x8014,
1639 "Wait for pending commands failed.\n");
1640 ret = FAILED;
1641 }
1642
1643 eh_bus_reset_done:
1644 ql_log(ql_log_warn, vha, 0x802b,
1645 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1646 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1647
1648 return ret;
1649 }
1650
1651 /**************************************************************************
1652 * qla2xxx_eh_host_reset
1653 *
1654 * Description:
1655 * The reset function will reset the Adapter.
1656 *
1657 * Input:
1658 * cmd = Linux SCSI command packet of the command that cause the
1659 * adapter reset.
1660 *
1661 * Returns:
1662 * Either SUCCESS or FAILED.
1663 *
1664 * Note:
1665 **************************************************************************/
1666 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1667 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1668 {
1669 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1670 struct qla_hw_data *ha = vha->hw;
1671 int ret = FAILED;
1672 unsigned int id;
1673 uint64_t lun;
1674 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1675
1676 if (qla2x00_isp_reg_stat(ha)) {
1677 ql_log(ql_log_info, vha, 0x8041,
1678 "PCI/Register disconnect, exiting.\n");
1679 qla_pci_set_eeh_busy(vha);
1680 return SUCCESS;
1681 }
1682
1683 id = cmd->device->id;
1684 lun = cmd->device->lun;
1685
1686 ql_log(ql_log_info, vha, 0x8018,
1687 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1688
1689 /*
1690 * No point in issuing another reset if one is active. Also do not
1691 * attempt a reset if we are updating flash.
1692 */
1693 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1694 goto eh_host_reset_lock;
1695
1696 if (vha != base_vha) {
1697 if (qla2x00_vp_abort_isp(vha))
1698 goto eh_host_reset_lock;
1699 } else {
1700 if (IS_P3P_TYPE(vha->hw)) {
1701 if (!qla82xx_fcoe_ctx_reset(vha)) {
1702 /* Ctx reset success */
1703 ret = SUCCESS;
1704 goto eh_host_reset_lock;
1705 }
1706 /* fall thru if ctx reset failed */
1707 }
1708 if (ha->wq)
1709 flush_workqueue(ha->wq);
1710
1711 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1712 if (ha->isp_ops->abort_isp(base_vha)) {
1713 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1714 /* failed. schedule dpc to try */
1715 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1716
1717 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1718 ql_log(ql_log_warn, vha, 0x802a,
1719 "wait for hba online failed.\n");
1720 goto eh_host_reset_lock;
1721 }
1722 }
1723 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1724 }
1725
1726 /* Waiting for command to be returned to OS.*/
1727 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1728 QLA_SUCCESS)
1729 ret = SUCCESS;
1730
1731 eh_host_reset_lock:
1732 ql_log(ql_log_info, vha, 0x8017,
1733 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1734 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1735
1736 return ret;
1737 }
1738
1739 /*
1740 * qla2x00_loop_reset
1741 * Issue loop reset.
1742 *
1743 * Input:
1744 * ha = adapter block pointer.
1745 *
1746 * Returns:
1747 * 0 = success
1748 */
1749 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1750 qla2x00_loop_reset(scsi_qla_host_t *vha)
1751 {
1752 int ret;
1753 struct qla_hw_data *ha = vha->hw;
1754
1755 if (IS_QLAFX00(ha))
1756 return QLA_SUCCESS;
1757
1758 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1759 atomic_set(&vha->loop_state, LOOP_DOWN);
1760 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1761 qla2x00_mark_all_devices_lost(vha);
1762 ret = qla2x00_full_login_lip(vha);
1763 if (ret != QLA_SUCCESS) {
1764 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1765 "full_login_lip=%d.\n", ret);
1766 }
1767 }
1768
1769 if (ha->flags.enable_lip_reset) {
1770 ret = qla2x00_lip_reset(vha);
1771 if (ret != QLA_SUCCESS)
1772 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1773 "lip_reset failed (%d).\n", ret);
1774 }
1775
1776 /* Issue marker command only when we are going to start the I/O */
1777 vha->marker_needed = 1;
1778
1779 return QLA_SUCCESS;
1780 }
1781
1782 /*
1783 * The caller must ensure that no completion interrupts will happen
1784 * while this function is in progress.
1785 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1786 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1787 unsigned long *flags)
1788 __releases(qp->qp_lock_ptr)
1789 __acquires(qp->qp_lock_ptr)
1790 {
1791 DECLARE_COMPLETION_ONSTACK(comp);
1792 scsi_qla_host_t *vha = qp->vha;
1793 struct qla_hw_data *ha = vha->hw;
1794 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1795 int rval;
1796 bool ret_cmd;
1797 uint32_t ratov_j;
1798
1799 lockdep_assert_held(qp->qp_lock_ptr);
1800
1801 if (qla2x00_chip_is_down(vha)) {
1802 sp->done(sp, res);
1803 return;
1804 }
1805
1806 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1807 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1808 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1809 !qla2x00_isp_reg_stat(ha))) {
1810 if (sp->comp) {
1811 sp->done(sp, res);
1812 return;
1813 }
1814
1815 sp->comp = ∁
1816 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1817
1818 rval = ha->isp_ops->abort_command(sp);
1819 /* Wait for command completion. */
1820 ret_cmd = false;
1821 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1822 ratov_j = msecs_to_jiffies(ratov_j);
1823 switch (rval) {
1824 case QLA_SUCCESS:
1825 if (wait_for_completion_timeout(&comp, ratov_j)) {
1826 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1827 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1828 __func__, ha->r_a_tov/10);
1829 ret_cmd = true;
1830 }
1831 /* else FW return SP to driver */
1832 break;
1833 default:
1834 ret_cmd = true;
1835 break;
1836 }
1837
1838 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1839 switch (sp->type) {
1840 case SRB_SCSI_CMD:
1841 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1842 sp->done(sp, res);
1843 break;
1844 default:
1845 if (ret_cmd)
1846 sp->done(sp, res);
1847 break;
1848 }
1849 } else {
1850 sp->done(sp, res);
1851 }
1852 }
1853
1854 /*
1855 * The caller must ensure that no completion interrupts will happen
1856 * while this function is in progress.
1857 */
1858 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1859 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1860 {
1861 int cnt;
1862 unsigned long flags;
1863 srb_t *sp;
1864 scsi_qla_host_t *vha = qp->vha;
1865 struct qla_hw_data *ha = vha->hw;
1866 struct req_que *req;
1867 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1868 struct qla_tgt_cmd *cmd;
1869
1870 if (!ha->req_q_map)
1871 return;
1872 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1873 req = qp->req;
1874 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1875 sp = req->outstanding_cmds[cnt];
1876 if (sp) {
1877 /*
1878 * perform lockless completion during driver unload
1879 */
1880 if (qla2x00_chip_is_down(vha)) {
1881 req->outstanding_cmds[cnt] = NULL;
1882 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1883 sp->done(sp, res);
1884 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1885 continue;
1886 }
1887
1888 switch (sp->cmd_type) {
1889 case TYPE_SRB:
1890 qla2x00_abort_srb(qp, sp, res, &flags);
1891 break;
1892 case TYPE_TGT_CMD:
1893 if (!vha->hw->tgt.tgt_ops || !tgt ||
1894 qla_ini_mode_enabled(vha)) {
1895 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1896 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1897 vha->dpc_flags);
1898 continue;
1899 }
1900 cmd = (struct qla_tgt_cmd *)sp;
1901 cmd->aborted = 1;
1902 break;
1903 case TYPE_TGT_TMCMD:
1904 /* Skip task management functions. */
1905 break;
1906 default:
1907 break;
1908 }
1909 req->outstanding_cmds[cnt] = NULL;
1910 }
1911 }
1912 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1913 }
1914
1915 /*
1916 * The caller must ensure that no completion interrupts will happen
1917 * while this function is in progress.
1918 */
1919 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1920 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1921 {
1922 int que;
1923 struct qla_hw_data *ha = vha->hw;
1924
1925 /* Continue only if initialization complete. */
1926 if (!ha->base_qpair)
1927 return;
1928 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1929
1930 if (!ha->queue_pair_map)
1931 return;
1932 for (que = 0; que < ha->max_qpairs; que++) {
1933 if (!ha->queue_pair_map[que])
1934 continue;
1935
1936 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1937 }
1938 }
1939
1940 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1941 qla2xxx_slave_alloc(struct scsi_device *sdev)
1942 {
1943 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1944
1945 if (!rport || fc_remote_port_chkready(rport))
1946 return -ENXIO;
1947
1948 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1949
1950 return 0;
1951 }
1952
1953 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1954 qla2xxx_slave_configure(struct scsi_device *sdev)
1955 {
1956 scsi_qla_host_t *vha = shost_priv(sdev->host);
1957 struct req_que *req = vha->req;
1958
1959 if (IS_T10_PI_CAPABLE(vha->hw))
1960 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1961
1962 scsi_change_queue_depth(sdev, req->max_q_depth);
1963 return 0;
1964 }
1965
1966 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1967 qla2xxx_slave_destroy(struct scsi_device *sdev)
1968 {
1969 sdev->hostdata = NULL;
1970 }
1971
1972 /**
1973 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1974 * @ha: HA context
1975 *
1976 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1977 * supported addressing method.
1978 */
1979 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1980 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1981 {
1982 /* Assume a 32bit DMA mask. */
1983 ha->flags.enable_64bit_addressing = 0;
1984
1985 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1986 /* Any upper-dword bits set? */
1987 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1988 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1989 /* Ok, a 64bit DMA mask is applicable. */
1990 ha->flags.enable_64bit_addressing = 1;
1991 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1992 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1993 return;
1994 }
1995 }
1996
1997 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1998 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1999 }
2000
2001 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)2002 qla2x00_enable_intrs(struct qla_hw_data *ha)
2003 {
2004 unsigned long flags = 0;
2005 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2006
2007 spin_lock_irqsave(&ha->hardware_lock, flags);
2008 ha->interrupts_on = 1;
2009 /* enable risc and host interrupts */
2010 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
2011 rd_reg_word(®->ictrl);
2012 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2013
2014 }
2015
2016 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)2017 qla2x00_disable_intrs(struct qla_hw_data *ha)
2018 {
2019 unsigned long flags = 0;
2020 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2021
2022 spin_lock_irqsave(&ha->hardware_lock, flags);
2023 ha->interrupts_on = 0;
2024 /* disable risc and host interrupts */
2025 wrt_reg_word(®->ictrl, 0);
2026 rd_reg_word(®->ictrl);
2027 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2028 }
2029
2030 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)2031 qla24xx_enable_intrs(struct qla_hw_data *ha)
2032 {
2033 unsigned long flags = 0;
2034 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2035
2036 spin_lock_irqsave(&ha->hardware_lock, flags);
2037 ha->interrupts_on = 1;
2038 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
2039 rd_reg_dword(®->ictrl);
2040 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2041 }
2042
2043 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)2044 qla24xx_disable_intrs(struct qla_hw_data *ha)
2045 {
2046 unsigned long flags = 0;
2047 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2048
2049 if (IS_NOPOLLING_TYPE(ha))
2050 return;
2051 spin_lock_irqsave(&ha->hardware_lock, flags);
2052 ha->interrupts_on = 0;
2053 wrt_reg_dword(®->ictrl, 0);
2054 rd_reg_dword(®->ictrl);
2055 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2056 }
2057
2058 static int
qla2x00_iospace_config(struct qla_hw_data * ha)2059 qla2x00_iospace_config(struct qla_hw_data *ha)
2060 {
2061 resource_size_t pio;
2062 uint16_t msix;
2063
2064 if (pci_request_selected_regions(ha->pdev, ha->bars,
2065 QLA2XXX_DRIVER_NAME)) {
2066 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2067 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2068 pci_name(ha->pdev));
2069 goto iospace_error_exit;
2070 }
2071 if (!(ha->bars & 1))
2072 goto skip_pio;
2073
2074 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2075 pio = pci_resource_start(ha->pdev, 0);
2076 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2077 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2078 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2079 "Invalid pci I/O region size (%s).\n",
2080 pci_name(ha->pdev));
2081 pio = 0;
2082 }
2083 } else {
2084 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2085 "Region #0 no a PIO resource (%s).\n",
2086 pci_name(ha->pdev));
2087 pio = 0;
2088 }
2089 ha->pio_address = pio;
2090 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2091 "PIO address=%llu.\n",
2092 (unsigned long long)ha->pio_address);
2093
2094 skip_pio:
2095 /* Use MMIO operations for all accesses. */
2096 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2097 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2098 "Region #1 not an MMIO resource (%s), aborting.\n",
2099 pci_name(ha->pdev));
2100 goto iospace_error_exit;
2101 }
2102 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2103 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2104 "Invalid PCI mem region size (%s), aborting.\n",
2105 pci_name(ha->pdev));
2106 goto iospace_error_exit;
2107 }
2108
2109 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2110 if (!ha->iobase) {
2111 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2112 "Cannot remap MMIO (%s), aborting.\n",
2113 pci_name(ha->pdev));
2114 goto iospace_error_exit;
2115 }
2116
2117 /* Determine queue resources */
2118 ha->max_req_queues = ha->max_rsp_queues = 1;
2119 ha->msix_count = QLA_BASE_VECTORS;
2120
2121 /* Check if FW supports MQ or not */
2122 if (!(ha->fw_attributes & BIT_6))
2123 goto mqiobase_exit;
2124
2125 if (!ql2xmqsupport || !ql2xnvmeenable ||
2126 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2127 goto mqiobase_exit;
2128
2129 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2130 pci_resource_len(ha->pdev, 3));
2131 if (ha->mqiobase) {
2132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2133 "MQIO Base=%p.\n", ha->mqiobase);
2134 /* Read MSIX vector size of the board */
2135 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2136 ha->msix_count = msix + 1;
2137 /* Max queues are bounded by available msix vectors */
2138 /* MB interrupt uses 1 vector */
2139 ha->max_req_queues = ha->msix_count - 1;
2140 ha->max_rsp_queues = ha->max_req_queues;
2141 /* Queue pairs is the max value minus the base queue pair */
2142 ha->max_qpairs = ha->max_rsp_queues - 1;
2143 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2144 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2145
2146 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2147 "MSI-X vector count: %d.\n", ha->msix_count);
2148 } else
2149 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2150 "BAR 3 not enabled.\n");
2151
2152 mqiobase_exit:
2153 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2154 "MSIX Count: %d.\n", ha->msix_count);
2155 return (0);
2156
2157 iospace_error_exit:
2158 return (-ENOMEM);
2159 }
2160
2161
2162 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2163 qla83xx_iospace_config(struct qla_hw_data *ha)
2164 {
2165 uint16_t msix;
2166
2167 if (pci_request_selected_regions(ha->pdev, ha->bars,
2168 QLA2XXX_DRIVER_NAME)) {
2169 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2170 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2171 pci_name(ha->pdev));
2172
2173 goto iospace_error_exit;
2174 }
2175
2176 /* Use MMIO operations for all accesses. */
2177 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2178 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2179 "Invalid pci I/O region size (%s).\n",
2180 pci_name(ha->pdev));
2181 goto iospace_error_exit;
2182 }
2183 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2184 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2185 "Invalid PCI mem region size (%s), aborting\n",
2186 pci_name(ha->pdev));
2187 goto iospace_error_exit;
2188 }
2189
2190 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2191 if (!ha->iobase) {
2192 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2193 "Cannot remap MMIO (%s), aborting.\n",
2194 pci_name(ha->pdev));
2195 goto iospace_error_exit;
2196 }
2197
2198 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2199 /* 83XX 26XX always use MQ type access for queues
2200 * - mbar 2, a.k.a region 4 */
2201 ha->max_req_queues = ha->max_rsp_queues = 1;
2202 ha->msix_count = QLA_BASE_VECTORS;
2203 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2204 pci_resource_len(ha->pdev, 4));
2205
2206 if (!ha->mqiobase) {
2207 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2208 "BAR2/region4 not enabled\n");
2209 goto mqiobase_exit;
2210 }
2211
2212 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2213 pci_resource_len(ha->pdev, 2));
2214 if (ha->msixbase) {
2215 /* Read MSIX vector size of the board */
2216 pci_read_config_word(ha->pdev,
2217 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2218 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2219 /*
2220 * By default, driver uses at least two msix vectors
2221 * (default & rspq)
2222 */
2223 if (ql2xmqsupport || ql2xnvmeenable) {
2224 /* MB interrupt uses 1 vector */
2225 ha->max_req_queues = ha->msix_count - 1;
2226
2227 /* ATIOQ needs 1 vector. That's 1 less QPair */
2228 if (QLA_TGT_MODE_ENABLED())
2229 ha->max_req_queues--;
2230
2231 ha->max_rsp_queues = ha->max_req_queues;
2232
2233 /* Queue pairs is the max value minus
2234 * the base queue pair */
2235 ha->max_qpairs = ha->max_req_queues - 1;
2236 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2237 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2238 }
2239 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2240 "MSI-X vector count: %d.\n", ha->msix_count);
2241 } else
2242 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2243 "BAR 1 not enabled.\n");
2244
2245 mqiobase_exit:
2246 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2247 "MSIX Count: %d.\n", ha->msix_count);
2248 return 0;
2249
2250 iospace_error_exit:
2251 return -ENOMEM;
2252 }
2253
2254 static struct isp_operations qla2100_isp_ops = {
2255 .pci_config = qla2100_pci_config,
2256 .reset_chip = qla2x00_reset_chip,
2257 .chip_diag = qla2x00_chip_diag,
2258 .config_rings = qla2x00_config_rings,
2259 .reset_adapter = qla2x00_reset_adapter,
2260 .nvram_config = qla2x00_nvram_config,
2261 .update_fw_options = qla2x00_update_fw_options,
2262 .load_risc = qla2x00_load_risc,
2263 .pci_info_str = qla2x00_pci_info_str,
2264 .fw_version_str = qla2x00_fw_version_str,
2265 .intr_handler = qla2100_intr_handler,
2266 .enable_intrs = qla2x00_enable_intrs,
2267 .disable_intrs = qla2x00_disable_intrs,
2268 .abort_command = qla2x00_abort_command,
2269 .target_reset = qla2x00_abort_target,
2270 .lun_reset = qla2x00_lun_reset,
2271 .fabric_login = qla2x00_login_fabric,
2272 .fabric_logout = qla2x00_fabric_logout,
2273 .calc_req_entries = qla2x00_calc_iocbs_32,
2274 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2275 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2276 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2277 .read_nvram = qla2x00_read_nvram_data,
2278 .write_nvram = qla2x00_write_nvram_data,
2279 .fw_dump = qla2100_fw_dump,
2280 .beacon_on = NULL,
2281 .beacon_off = NULL,
2282 .beacon_blink = NULL,
2283 .read_optrom = qla2x00_read_optrom_data,
2284 .write_optrom = qla2x00_write_optrom_data,
2285 .get_flash_version = qla2x00_get_flash_version,
2286 .start_scsi = qla2x00_start_scsi,
2287 .start_scsi_mq = NULL,
2288 .abort_isp = qla2x00_abort_isp,
2289 .iospace_config = qla2x00_iospace_config,
2290 .initialize_adapter = qla2x00_initialize_adapter,
2291 };
2292
2293 static struct isp_operations qla2300_isp_ops = {
2294 .pci_config = qla2300_pci_config,
2295 .reset_chip = qla2x00_reset_chip,
2296 .chip_diag = qla2x00_chip_diag,
2297 .config_rings = qla2x00_config_rings,
2298 .reset_adapter = qla2x00_reset_adapter,
2299 .nvram_config = qla2x00_nvram_config,
2300 .update_fw_options = qla2x00_update_fw_options,
2301 .load_risc = qla2x00_load_risc,
2302 .pci_info_str = qla2x00_pci_info_str,
2303 .fw_version_str = qla2x00_fw_version_str,
2304 .intr_handler = qla2300_intr_handler,
2305 .enable_intrs = qla2x00_enable_intrs,
2306 .disable_intrs = qla2x00_disable_intrs,
2307 .abort_command = qla2x00_abort_command,
2308 .target_reset = qla2x00_abort_target,
2309 .lun_reset = qla2x00_lun_reset,
2310 .fabric_login = qla2x00_login_fabric,
2311 .fabric_logout = qla2x00_fabric_logout,
2312 .calc_req_entries = qla2x00_calc_iocbs_32,
2313 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2314 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2315 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2316 .read_nvram = qla2x00_read_nvram_data,
2317 .write_nvram = qla2x00_write_nvram_data,
2318 .fw_dump = qla2300_fw_dump,
2319 .beacon_on = qla2x00_beacon_on,
2320 .beacon_off = qla2x00_beacon_off,
2321 .beacon_blink = qla2x00_beacon_blink,
2322 .read_optrom = qla2x00_read_optrom_data,
2323 .write_optrom = qla2x00_write_optrom_data,
2324 .get_flash_version = qla2x00_get_flash_version,
2325 .start_scsi = qla2x00_start_scsi,
2326 .start_scsi_mq = NULL,
2327 .abort_isp = qla2x00_abort_isp,
2328 .iospace_config = qla2x00_iospace_config,
2329 .initialize_adapter = qla2x00_initialize_adapter,
2330 };
2331
2332 static struct isp_operations qla24xx_isp_ops = {
2333 .pci_config = qla24xx_pci_config,
2334 .reset_chip = qla24xx_reset_chip,
2335 .chip_diag = qla24xx_chip_diag,
2336 .config_rings = qla24xx_config_rings,
2337 .reset_adapter = qla24xx_reset_adapter,
2338 .nvram_config = qla24xx_nvram_config,
2339 .update_fw_options = qla24xx_update_fw_options,
2340 .load_risc = qla24xx_load_risc,
2341 .pci_info_str = qla24xx_pci_info_str,
2342 .fw_version_str = qla24xx_fw_version_str,
2343 .intr_handler = qla24xx_intr_handler,
2344 .enable_intrs = qla24xx_enable_intrs,
2345 .disable_intrs = qla24xx_disable_intrs,
2346 .abort_command = qla24xx_abort_command,
2347 .target_reset = qla24xx_abort_target,
2348 .lun_reset = qla24xx_lun_reset,
2349 .fabric_login = qla24xx_login_fabric,
2350 .fabric_logout = qla24xx_fabric_logout,
2351 .calc_req_entries = NULL,
2352 .build_iocbs = NULL,
2353 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2354 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2355 .read_nvram = qla24xx_read_nvram_data,
2356 .write_nvram = qla24xx_write_nvram_data,
2357 .fw_dump = qla24xx_fw_dump,
2358 .beacon_on = qla24xx_beacon_on,
2359 .beacon_off = qla24xx_beacon_off,
2360 .beacon_blink = qla24xx_beacon_blink,
2361 .read_optrom = qla24xx_read_optrom_data,
2362 .write_optrom = qla24xx_write_optrom_data,
2363 .get_flash_version = qla24xx_get_flash_version,
2364 .start_scsi = qla24xx_start_scsi,
2365 .start_scsi_mq = NULL,
2366 .abort_isp = qla2x00_abort_isp,
2367 .iospace_config = qla2x00_iospace_config,
2368 .initialize_adapter = qla2x00_initialize_adapter,
2369 };
2370
2371 static struct isp_operations qla25xx_isp_ops = {
2372 .pci_config = qla25xx_pci_config,
2373 .reset_chip = qla24xx_reset_chip,
2374 .chip_diag = qla24xx_chip_diag,
2375 .config_rings = qla24xx_config_rings,
2376 .reset_adapter = qla24xx_reset_adapter,
2377 .nvram_config = qla24xx_nvram_config,
2378 .update_fw_options = qla24xx_update_fw_options,
2379 .load_risc = qla24xx_load_risc,
2380 .pci_info_str = qla24xx_pci_info_str,
2381 .fw_version_str = qla24xx_fw_version_str,
2382 .intr_handler = qla24xx_intr_handler,
2383 .enable_intrs = qla24xx_enable_intrs,
2384 .disable_intrs = qla24xx_disable_intrs,
2385 .abort_command = qla24xx_abort_command,
2386 .target_reset = qla24xx_abort_target,
2387 .lun_reset = qla24xx_lun_reset,
2388 .fabric_login = qla24xx_login_fabric,
2389 .fabric_logout = qla24xx_fabric_logout,
2390 .calc_req_entries = NULL,
2391 .build_iocbs = NULL,
2392 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2393 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2394 .read_nvram = qla25xx_read_nvram_data,
2395 .write_nvram = qla25xx_write_nvram_data,
2396 .fw_dump = qla25xx_fw_dump,
2397 .beacon_on = qla24xx_beacon_on,
2398 .beacon_off = qla24xx_beacon_off,
2399 .beacon_blink = qla24xx_beacon_blink,
2400 .read_optrom = qla25xx_read_optrom_data,
2401 .write_optrom = qla24xx_write_optrom_data,
2402 .get_flash_version = qla24xx_get_flash_version,
2403 .start_scsi = qla24xx_dif_start_scsi,
2404 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2405 .abort_isp = qla2x00_abort_isp,
2406 .iospace_config = qla2x00_iospace_config,
2407 .initialize_adapter = qla2x00_initialize_adapter,
2408 };
2409
2410 static struct isp_operations qla81xx_isp_ops = {
2411 .pci_config = qla25xx_pci_config,
2412 .reset_chip = qla24xx_reset_chip,
2413 .chip_diag = qla24xx_chip_diag,
2414 .config_rings = qla24xx_config_rings,
2415 .reset_adapter = qla24xx_reset_adapter,
2416 .nvram_config = qla81xx_nvram_config,
2417 .update_fw_options = qla24xx_update_fw_options,
2418 .load_risc = qla81xx_load_risc,
2419 .pci_info_str = qla24xx_pci_info_str,
2420 .fw_version_str = qla24xx_fw_version_str,
2421 .intr_handler = qla24xx_intr_handler,
2422 .enable_intrs = qla24xx_enable_intrs,
2423 .disable_intrs = qla24xx_disable_intrs,
2424 .abort_command = qla24xx_abort_command,
2425 .target_reset = qla24xx_abort_target,
2426 .lun_reset = qla24xx_lun_reset,
2427 .fabric_login = qla24xx_login_fabric,
2428 .fabric_logout = qla24xx_fabric_logout,
2429 .calc_req_entries = NULL,
2430 .build_iocbs = NULL,
2431 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2432 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2433 .read_nvram = NULL,
2434 .write_nvram = NULL,
2435 .fw_dump = qla81xx_fw_dump,
2436 .beacon_on = qla24xx_beacon_on,
2437 .beacon_off = qla24xx_beacon_off,
2438 .beacon_blink = qla83xx_beacon_blink,
2439 .read_optrom = qla25xx_read_optrom_data,
2440 .write_optrom = qla24xx_write_optrom_data,
2441 .get_flash_version = qla24xx_get_flash_version,
2442 .start_scsi = qla24xx_dif_start_scsi,
2443 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2444 .abort_isp = qla2x00_abort_isp,
2445 .iospace_config = qla2x00_iospace_config,
2446 .initialize_adapter = qla2x00_initialize_adapter,
2447 };
2448
2449 static struct isp_operations qla82xx_isp_ops = {
2450 .pci_config = qla82xx_pci_config,
2451 .reset_chip = qla82xx_reset_chip,
2452 .chip_diag = qla24xx_chip_diag,
2453 .config_rings = qla82xx_config_rings,
2454 .reset_adapter = qla24xx_reset_adapter,
2455 .nvram_config = qla81xx_nvram_config,
2456 .update_fw_options = qla24xx_update_fw_options,
2457 .load_risc = qla82xx_load_risc,
2458 .pci_info_str = qla24xx_pci_info_str,
2459 .fw_version_str = qla24xx_fw_version_str,
2460 .intr_handler = qla82xx_intr_handler,
2461 .enable_intrs = qla82xx_enable_intrs,
2462 .disable_intrs = qla82xx_disable_intrs,
2463 .abort_command = qla24xx_abort_command,
2464 .target_reset = qla24xx_abort_target,
2465 .lun_reset = qla24xx_lun_reset,
2466 .fabric_login = qla24xx_login_fabric,
2467 .fabric_logout = qla24xx_fabric_logout,
2468 .calc_req_entries = NULL,
2469 .build_iocbs = NULL,
2470 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2471 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2472 .read_nvram = qla24xx_read_nvram_data,
2473 .write_nvram = qla24xx_write_nvram_data,
2474 .fw_dump = qla82xx_fw_dump,
2475 .beacon_on = qla82xx_beacon_on,
2476 .beacon_off = qla82xx_beacon_off,
2477 .beacon_blink = NULL,
2478 .read_optrom = qla82xx_read_optrom_data,
2479 .write_optrom = qla82xx_write_optrom_data,
2480 .get_flash_version = qla82xx_get_flash_version,
2481 .start_scsi = qla82xx_start_scsi,
2482 .start_scsi_mq = NULL,
2483 .abort_isp = qla82xx_abort_isp,
2484 .iospace_config = qla82xx_iospace_config,
2485 .initialize_adapter = qla2x00_initialize_adapter,
2486 };
2487
2488 static struct isp_operations qla8044_isp_ops = {
2489 .pci_config = qla82xx_pci_config,
2490 .reset_chip = qla82xx_reset_chip,
2491 .chip_diag = qla24xx_chip_diag,
2492 .config_rings = qla82xx_config_rings,
2493 .reset_adapter = qla24xx_reset_adapter,
2494 .nvram_config = qla81xx_nvram_config,
2495 .update_fw_options = qla24xx_update_fw_options,
2496 .load_risc = qla82xx_load_risc,
2497 .pci_info_str = qla24xx_pci_info_str,
2498 .fw_version_str = qla24xx_fw_version_str,
2499 .intr_handler = qla8044_intr_handler,
2500 .enable_intrs = qla82xx_enable_intrs,
2501 .disable_intrs = qla82xx_disable_intrs,
2502 .abort_command = qla24xx_abort_command,
2503 .target_reset = qla24xx_abort_target,
2504 .lun_reset = qla24xx_lun_reset,
2505 .fabric_login = qla24xx_login_fabric,
2506 .fabric_logout = qla24xx_fabric_logout,
2507 .calc_req_entries = NULL,
2508 .build_iocbs = NULL,
2509 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2510 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2511 .read_nvram = NULL,
2512 .write_nvram = NULL,
2513 .fw_dump = qla8044_fw_dump,
2514 .beacon_on = qla82xx_beacon_on,
2515 .beacon_off = qla82xx_beacon_off,
2516 .beacon_blink = NULL,
2517 .read_optrom = qla8044_read_optrom_data,
2518 .write_optrom = qla8044_write_optrom_data,
2519 .get_flash_version = qla82xx_get_flash_version,
2520 .start_scsi = qla82xx_start_scsi,
2521 .start_scsi_mq = NULL,
2522 .abort_isp = qla8044_abort_isp,
2523 .iospace_config = qla82xx_iospace_config,
2524 .initialize_adapter = qla2x00_initialize_adapter,
2525 };
2526
2527 static struct isp_operations qla83xx_isp_ops = {
2528 .pci_config = qla25xx_pci_config,
2529 .reset_chip = qla24xx_reset_chip,
2530 .chip_diag = qla24xx_chip_diag,
2531 .config_rings = qla24xx_config_rings,
2532 .reset_adapter = qla24xx_reset_adapter,
2533 .nvram_config = qla81xx_nvram_config,
2534 .update_fw_options = qla24xx_update_fw_options,
2535 .load_risc = qla81xx_load_risc,
2536 .pci_info_str = qla24xx_pci_info_str,
2537 .fw_version_str = qla24xx_fw_version_str,
2538 .intr_handler = qla24xx_intr_handler,
2539 .enable_intrs = qla24xx_enable_intrs,
2540 .disable_intrs = qla24xx_disable_intrs,
2541 .abort_command = qla24xx_abort_command,
2542 .target_reset = qla24xx_abort_target,
2543 .lun_reset = qla24xx_lun_reset,
2544 .fabric_login = qla24xx_login_fabric,
2545 .fabric_logout = qla24xx_fabric_logout,
2546 .calc_req_entries = NULL,
2547 .build_iocbs = NULL,
2548 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2549 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2550 .read_nvram = NULL,
2551 .write_nvram = NULL,
2552 .fw_dump = qla83xx_fw_dump,
2553 .beacon_on = qla24xx_beacon_on,
2554 .beacon_off = qla24xx_beacon_off,
2555 .beacon_blink = qla83xx_beacon_blink,
2556 .read_optrom = qla25xx_read_optrom_data,
2557 .write_optrom = qla24xx_write_optrom_data,
2558 .get_flash_version = qla24xx_get_flash_version,
2559 .start_scsi = qla24xx_dif_start_scsi,
2560 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2561 .abort_isp = qla2x00_abort_isp,
2562 .iospace_config = qla83xx_iospace_config,
2563 .initialize_adapter = qla2x00_initialize_adapter,
2564 };
2565
2566 static struct isp_operations qlafx00_isp_ops = {
2567 .pci_config = qlafx00_pci_config,
2568 .reset_chip = qlafx00_soft_reset,
2569 .chip_diag = qlafx00_chip_diag,
2570 .config_rings = qlafx00_config_rings,
2571 .reset_adapter = qlafx00_soft_reset,
2572 .nvram_config = NULL,
2573 .update_fw_options = NULL,
2574 .load_risc = NULL,
2575 .pci_info_str = qlafx00_pci_info_str,
2576 .fw_version_str = qlafx00_fw_version_str,
2577 .intr_handler = qlafx00_intr_handler,
2578 .enable_intrs = qlafx00_enable_intrs,
2579 .disable_intrs = qlafx00_disable_intrs,
2580 .abort_command = qla24xx_async_abort_command,
2581 .target_reset = qlafx00_abort_target,
2582 .lun_reset = qlafx00_lun_reset,
2583 .fabric_login = NULL,
2584 .fabric_logout = NULL,
2585 .calc_req_entries = NULL,
2586 .build_iocbs = NULL,
2587 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2588 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2589 .read_nvram = qla24xx_read_nvram_data,
2590 .write_nvram = qla24xx_write_nvram_data,
2591 .fw_dump = NULL,
2592 .beacon_on = qla24xx_beacon_on,
2593 .beacon_off = qla24xx_beacon_off,
2594 .beacon_blink = NULL,
2595 .read_optrom = qla24xx_read_optrom_data,
2596 .write_optrom = qla24xx_write_optrom_data,
2597 .get_flash_version = qla24xx_get_flash_version,
2598 .start_scsi = qlafx00_start_scsi,
2599 .start_scsi_mq = NULL,
2600 .abort_isp = qlafx00_abort_isp,
2601 .iospace_config = qlafx00_iospace_config,
2602 .initialize_adapter = qlafx00_initialize_adapter,
2603 };
2604
2605 static struct isp_operations qla27xx_isp_ops = {
2606 .pci_config = qla25xx_pci_config,
2607 .reset_chip = qla24xx_reset_chip,
2608 .chip_diag = qla24xx_chip_diag,
2609 .config_rings = qla24xx_config_rings,
2610 .reset_adapter = qla24xx_reset_adapter,
2611 .nvram_config = qla81xx_nvram_config,
2612 .update_fw_options = qla24xx_update_fw_options,
2613 .load_risc = qla81xx_load_risc,
2614 .pci_info_str = qla24xx_pci_info_str,
2615 .fw_version_str = qla24xx_fw_version_str,
2616 .intr_handler = qla24xx_intr_handler,
2617 .enable_intrs = qla24xx_enable_intrs,
2618 .disable_intrs = qla24xx_disable_intrs,
2619 .abort_command = qla24xx_abort_command,
2620 .target_reset = qla24xx_abort_target,
2621 .lun_reset = qla24xx_lun_reset,
2622 .fabric_login = qla24xx_login_fabric,
2623 .fabric_logout = qla24xx_fabric_logout,
2624 .calc_req_entries = NULL,
2625 .build_iocbs = NULL,
2626 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2627 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2628 .read_nvram = NULL,
2629 .write_nvram = NULL,
2630 .fw_dump = qla27xx_fwdump,
2631 .mpi_fw_dump = qla27xx_mpi_fwdump,
2632 .beacon_on = qla24xx_beacon_on,
2633 .beacon_off = qla24xx_beacon_off,
2634 .beacon_blink = qla83xx_beacon_blink,
2635 .read_optrom = qla25xx_read_optrom_data,
2636 .write_optrom = qla24xx_write_optrom_data,
2637 .get_flash_version = qla24xx_get_flash_version,
2638 .start_scsi = qla24xx_dif_start_scsi,
2639 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2640 .abort_isp = qla2x00_abort_isp,
2641 .iospace_config = qla83xx_iospace_config,
2642 .initialize_adapter = qla2x00_initialize_adapter,
2643 };
2644
2645 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2646 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2647 {
2648 ha->device_type = DT_EXTENDED_IDS;
2649 switch (ha->pdev->device) {
2650 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2651 ha->isp_type |= DT_ISP2100;
2652 ha->device_type &= ~DT_EXTENDED_IDS;
2653 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2654 break;
2655 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2656 ha->isp_type |= DT_ISP2200;
2657 ha->device_type &= ~DT_EXTENDED_IDS;
2658 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2659 break;
2660 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2661 ha->isp_type |= DT_ISP2300;
2662 ha->device_type |= DT_ZIO_SUPPORTED;
2663 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2664 break;
2665 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2666 ha->isp_type |= DT_ISP2312;
2667 ha->device_type |= DT_ZIO_SUPPORTED;
2668 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2669 break;
2670 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2671 ha->isp_type |= DT_ISP2322;
2672 ha->device_type |= DT_ZIO_SUPPORTED;
2673 if (ha->pdev->subsystem_vendor == 0x1028 &&
2674 ha->pdev->subsystem_device == 0x0170)
2675 ha->device_type |= DT_OEM_001;
2676 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2677 break;
2678 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2679 ha->isp_type |= DT_ISP6312;
2680 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2681 break;
2682 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2683 ha->isp_type |= DT_ISP6322;
2684 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2685 break;
2686 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2687 ha->isp_type |= DT_ISP2422;
2688 ha->device_type |= DT_ZIO_SUPPORTED;
2689 ha->device_type |= DT_FWI2;
2690 ha->device_type |= DT_IIDMA;
2691 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2692 break;
2693 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2694 ha->isp_type |= DT_ISP2432;
2695 ha->device_type |= DT_ZIO_SUPPORTED;
2696 ha->device_type |= DT_FWI2;
2697 ha->device_type |= DT_IIDMA;
2698 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2699 break;
2700 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2701 ha->isp_type |= DT_ISP8432;
2702 ha->device_type |= DT_ZIO_SUPPORTED;
2703 ha->device_type |= DT_FWI2;
2704 ha->device_type |= DT_IIDMA;
2705 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2706 break;
2707 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2708 ha->isp_type |= DT_ISP5422;
2709 ha->device_type |= DT_FWI2;
2710 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2711 break;
2712 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2713 ha->isp_type |= DT_ISP5432;
2714 ha->device_type |= DT_FWI2;
2715 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2716 break;
2717 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2718 ha->isp_type |= DT_ISP2532;
2719 ha->device_type |= DT_ZIO_SUPPORTED;
2720 ha->device_type |= DT_FWI2;
2721 ha->device_type |= DT_IIDMA;
2722 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2723 break;
2724 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2725 ha->isp_type |= DT_ISP8001;
2726 ha->device_type |= DT_ZIO_SUPPORTED;
2727 ha->device_type |= DT_FWI2;
2728 ha->device_type |= DT_IIDMA;
2729 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2730 break;
2731 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2732 ha->isp_type |= DT_ISP8021;
2733 ha->device_type |= DT_ZIO_SUPPORTED;
2734 ha->device_type |= DT_FWI2;
2735 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2736 /* Initialize 82XX ISP flags */
2737 qla82xx_init_flags(ha);
2738 break;
2739 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2740 ha->isp_type |= DT_ISP8044;
2741 ha->device_type |= DT_ZIO_SUPPORTED;
2742 ha->device_type |= DT_FWI2;
2743 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2744 /* Initialize 82XX ISP flags */
2745 qla82xx_init_flags(ha);
2746 break;
2747 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2748 ha->isp_type |= DT_ISP2031;
2749 ha->device_type |= DT_ZIO_SUPPORTED;
2750 ha->device_type |= DT_FWI2;
2751 ha->device_type |= DT_IIDMA;
2752 ha->device_type |= DT_T10_PI;
2753 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2754 break;
2755 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2756 ha->isp_type |= DT_ISP8031;
2757 ha->device_type |= DT_ZIO_SUPPORTED;
2758 ha->device_type |= DT_FWI2;
2759 ha->device_type |= DT_IIDMA;
2760 ha->device_type |= DT_T10_PI;
2761 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2762 break;
2763 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2764 ha->isp_type |= DT_ISPFX00;
2765 break;
2766 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2767 ha->isp_type |= DT_ISP2071;
2768 ha->device_type |= DT_ZIO_SUPPORTED;
2769 ha->device_type |= DT_FWI2;
2770 ha->device_type |= DT_IIDMA;
2771 ha->device_type |= DT_T10_PI;
2772 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2773 break;
2774 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2775 ha->isp_type |= DT_ISP2271;
2776 ha->device_type |= DT_ZIO_SUPPORTED;
2777 ha->device_type |= DT_FWI2;
2778 ha->device_type |= DT_IIDMA;
2779 ha->device_type |= DT_T10_PI;
2780 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2781 break;
2782 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2783 ha->isp_type |= DT_ISP2261;
2784 ha->device_type |= DT_ZIO_SUPPORTED;
2785 ha->device_type |= DT_FWI2;
2786 ha->device_type |= DT_IIDMA;
2787 ha->device_type |= DT_T10_PI;
2788 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2789 break;
2790 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2791 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2792 ha->isp_type |= DT_ISP2081;
2793 ha->device_type |= DT_ZIO_SUPPORTED;
2794 ha->device_type |= DT_FWI2;
2795 ha->device_type |= DT_IIDMA;
2796 ha->device_type |= DT_T10_PI;
2797 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2798 break;
2799 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2800 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2801 ha->isp_type |= DT_ISP2281;
2802 ha->device_type |= DT_ZIO_SUPPORTED;
2803 ha->device_type |= DT_FWI2;
2804 ha->device_type |= DT_IIDMA;
2805 ha->device_type |= DT_T10_PI;
2806 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2807 break;
2808 }
2809
2810 if (IS_QLA82XX(ha))
2811 ha->port_no = ha->portnum & 1;
2812 else {
2813 /* Get adapter physical port no from interrupt pin register. */
2814 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2815 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2816 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2817 ha->port_no--;
2818 else
2819 ha->port_no = !(ha->port_no & 1);
2820 }
2821
2822 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2823 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2824 ha->device_type, ha->port_no, ha->fw_srisc_address);
2825 }
2826
2827 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2828 qla2xxx_scan_start(struct Scsi_Host *shost)
2829 {
2830 scsi_qla_host_t *vha = shost_priv(shost);
2831
2832 if (vha->hw->flags.running_gold_fw)
2833 return;
2834
2835 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2836 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2837 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2838 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2839 }
2840
2841 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2842 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2843 {
2844 scsi_qla_host_t *vha = shost_priv(shost);
2845
2846 if (test_bit(UNLOADING, &vha->dpc_flags))
2847 return 1;
2848 if (!vha->host)
2849 return 1;
2850 if (time > vha->hw->loop_reset_delay * HZ)
2851 return 1;
2852
2853 return atomic_read(&vha->loop_state) == LOOP_READY;
2854 }
2855
qla_heartbeat_work_fn(struct work_struct * work)2856 static void qla_heartbeat_work_fn(struct work_struct *work)
2857 {
2858 struct qla_hw_data *ha = container_of(work,
2859 struct qla_hw_data, heartbeat_work);
2860 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2861
2862 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2863 qla_no_op_mb(base_vha);
2864 }
2865
qla2x00_iocb_work_fn(struct work_struct * work)2866 static void qla2x00_iocb_work_fn(struct work_struct *work)
2867 {
2868 struct scsi_qla_host *vha = container_of(work,
2869 struct scsi_qla_host, iocb_work);
2870 struct qla_hw_data *ha = vha->hw;
2871 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2872 int i = 2;
2873 unsigned long flags;
2874
2875 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2876 return;
2877
2878 while (!list_empty(&vha->work_list) && i > 0) {
2879 qla2x00_do_work(vha);
2880 i--;
2881 }
2882
2883 spin_lock_irqsave(&vha->work_lock, flags);
2884 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2885 spin_unlock_irqrestore(&vha->work_lock, flags);
2886 }
2887
2888 static void
qla_trace_init(void)2889 qla_trace_init(void)
2890 {
2891 qla_trc_array = trace_array_get_by_name("qla2xxx");
2892 if (!qla_trc_array) {
2893 ql_log(ql_log_fatal, NULL, 0x0001,
2894 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2895 return;
2896 }
2897
2898 QLA_TRACE_ENABLE(qla_trc_array);
2899 }
2900
2901 static void
qla_trace_uninit(void)2902 qla_trace_uninit(void)
2903 {
2904 if (!qla_trc_array)
2905 return;
2906 trace_array_put(qla_trc_array);
2907 }
2908
2909 /*
2910 * PCI driver interface
2911 */
2912 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2913 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2914 {
2915 int ret = -ENODEV;
2916 struct Scsi_Host *host;
2917 scsi_qla_host_t *base_vha = NULL;
2918 struct qla_hw_data *ha;
2919 char pci_info[30];
2920 char fw_str[30], wq_name[30];
2921 struct scsi_host_template *sht;
2922 int bars, mem_only = 0;
2923 uint16_t req_length = 0, rsp_length = 0;
2924 struct req_que *req = NULL;
2925 struct rsp_que *rsp = NULL;
2926 int i;
2927
2928 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2929 sht = &qla2xxx_driver_template;
2930 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2940 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2941 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2942 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2943 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2944 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2945 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2946 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2947 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2948 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2949 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2950 mem_only = 1;
2951 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2952 "Mem only adapter.\n");
2953 }
2954 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2955 "Bars=%d.\n", bars);
2956
2957 if (mem_only) {
2958 if (pci_enable_device_mem(pdev))
2959 return ret;
2960 } else {
2961 if (pci_enable_device(pdev))
2962 return ret;
2963 }
2964
2965 if (is_kdump_kernel()) {
2966 ql2xmqsupport = 0;
2967 ql2xallocfwdump = 0;
2968 }
2969
2970 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2971 if (!ha) {
2972 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2973 "Unable to allocate memory for ha.\n");
2974 goto disable_device;
2975 }
2976 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2977 "Memory allocated for ha=%p.\n", ha);
2978 ha->pdev = pdev;
2979 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2980 spin_lock_init(&ha->tgt.q_full_lock);
2981 spin_lock_init(&ha->tgt.sess_lock);
2982 spin_lock_init(&ha->tgt.atio_lock);
2983
2984 spin_lock_init(&ha->sadb_lock);
2985 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2986 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2987
2988 spin_lock_init(&ha->sadb_fp_lock);
2989
2990 if (qla_edif_sadb_build_free_pool(ha)) {
2991 kfree(ha);
2992 goto disable_device;
2993 }
2994
2995 atomic_set(&ha->nvme_active_aen_cnt, 0);
2996
2997 /* Clear our data area */
2998 ha->bars = bars;
2999 ha->mem_only = mem_only;
3000 spin_lock_init(&ha->hardware_lock);
3001 spin_lock_init(&ha->vport_slock);
3002 mutex_init(&ha->selflogin_lock);
3003 mutex_init(&ha->optrom_mutex);
3004
3005 /* Set ISP-type information. */
3006 qla2x00_set_isp_flags(ha);
3007
3008 /* Set EEH reset type to fundamental if required by hba */
3009 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3010 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3011 pdev->needs_freset = 1;
3012
3013 ha->prev_topology = 0;
3014 ha->init_cb_size = sizeof(init_cb_t);
3015 ha->link_data_rate = PORT_SPEED_UNKNOWN;
3016 ha->optrom_size = OPTROM_SIZE_2300;
3017 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3018 atomic_set(&ha->num_pend_mbx_stage1, 0);
3019 atomic_set(&ha->num_pend_mbx_stage2, 0);
3020 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3021 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3022 INIT_LIST_HEAD(&ha->tmf_pending);
3023 INIT_LIST_HEAD(&ha->tmf_active);
3024
3025 /* Assign ISP specific operations. */
3026 if (IS_QLA2100(ha)) {
3027 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3028 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3029 req_length = REQUEST_ENTRY_CNT_2100;
3030 rsp_length = RESPONSE_ENTRY_CNT_2100;
3031 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3032 ha->gid_list_info_size = 4;
3033 ha->flash_conf_off = ~0;
3034 ha->flash_data_off = ~0;
3035 ha->nvram_conf_off = ~0;
3036 ha->nvram_data_off = ~0;
3037 ha->isp_ops = &qla2100_isp_ops;
3038 } else if (IS_QLA2200(ha)) {
3039 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3040 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3041 req_length = REQUEST_ENTRY_CNT_2200;
3042 rsp_length = RESPONSE_ENTRY_CNT_2100;
3043 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3044 ha->gid_list_info_size = 4;
3045 ha->flash_conf_off = ~0;
3046 ha->flash_data_off = ~0;
3047 ha->nvram_conf_off = ~0;
3048 ha->nvram_data_off = ~0;
3049 ha->isp_ops = &qla2100_isp_ops;
3050 } else if (IS_QLA23XX(ha)) {
3051 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3052 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3053 req_length = REQUEST_ENTRY_CNT_2200;
3054 rsp_length = RESPONSE_ENTRY_CNT_2300;
3055 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3056 ha->gid_list_info_size = 6;
3057 if (IS_QLA2322(ha) || IS_QLA6322(ha))
3058 ha->optrom_size = OPTROM_SIZE_2322;
3059 ha->flash_conf_off = ~0;
3060 ha->flash_data_off = ~0;
3061 ha->nvram_conf_off = ~0;
3062 ha->nvram_data_off = ~0;
3063 ha->isp_ops = &qla2300_isp_ops;
3064 } else if (IS_QLA24XX_TYPE(ha)) {
3065 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3066 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3067 req_length = REQUEST_ENTRY_CNT_24XX;
3068 rsp_length = RESPONSE_ENTRY_CNT_2300;
3069 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3070 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3071 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3072 ha->gid_list_info_size = 8;
3073 ha->optrom_size = OPTROM_SIZE_24XX;
3074 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3075 ha->isp_ops = &qla24xx_isp_ops;
3076 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3077 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3078 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3079 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3080 } else if (IS_QLA25XX(ha)) {
3081 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3082 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3083 req_length = REQUEST_ENTRY_CNT_24XX;
3084 rsp_length = RESPONSE_ENTRY_CNT_2300;
3085 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3086 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3087 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3088 ha->gid_list_info_size = 8;
3089 ha->optrom_size = OPTROM_SIZE_25XX;
3090 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3091 ha->isp_ops = &qla25xx_isp_ops;
3092 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3093 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3094 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3095 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3096 } else if (IS_QLA81XX(ha)) {
3097 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3098 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3099 req_length = REQUEST_ENTRY_CNT_24XX;
3100 rsp_length = RESPONSE_ENTRY_CNT_2300;
3101 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3102 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3103 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3104 ha->gid_list_info_size = 8;
3105 ha->optrom_size = OPTROM_SIZE_81XX;
3106 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3107 ha->isp_ops = &qla81xx_isp_ops;
3108 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3109 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3110 ha->nvram_conf_off = ~0;
3111 ha->nvram_data_off = ~0;
3112 } else if (IS_QLA82XX(ha)) {
3113 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3114 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3115 req_length = REQUEST_ENTRY_CNT_82XX;
3116 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3117 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3118 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3119 ha->gid_list_info_size = 8;
3120 ha->optrom_size = OPTROM_SIZE_82XX;
3121 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3122 ha->isp_ops = &qla82xx_isp_ops;
3123 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3124 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3125 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3126 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3127 } else if (IS_QLA8044(ha)) {
3128 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3129 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3130 req_length = REQUEST_ENTRY_CNT_82XX;
3131 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3132 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3133 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3134 ha->gid_list_info_size = 8;
3135 ha->optrom_size = OPTROM_SIZE_83XX;
3136 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3137 ha->isp_ops = &qla8044_isp_ops;
3138 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3139 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3140 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3141 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3142 } else if (IS_QLA83XX(ha)) {
3143 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3144 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3145 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3146 req_length = REQUEST_ENTRY_CNT_83XX;
3147 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3148 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3149 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3150 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3151 ha->gid_list_info_size = 8;
3152 ha->optrom_size = OPTROM_SIZE_83XX;
3153 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3154 ha->isp_ops = &qla83xx_isp_ops;
3155 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3156 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3157 ha->nvram_conf_off = ~0;
3158 ha->nvram_data_off = ~0;
3159 } else if (IS_QLAFX00(ha)) {
3160 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3161 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3162 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3163 req_length = REQUEST_ENTRY_CNT_FX00;
3164 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3165 ha->isp_ops = &qlafx00_isp_ops;
3166 ha->port_down_retry_count = 30; /* default value */
3167 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3168 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3169 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3170 ha->mr.fw_hbt_en = 1;
3171 ha->mr.host_info_resend = false;
3172 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3173 } else if (IS_QLA27XX(ha)) {
3174 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3175 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3176 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3177 req_length = REQUEST_ENTRY_CNT_83XX;
3178 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3179 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3180 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3181 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3182 ha->gid_list_info_size = 8;
3183 ha->optrom_size = OPTROM_SIZE_83XX;
3184 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3185 ha->isp_ops = &qla27xx_isp_ops;
3186 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3187 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3188 ha->nvram_conf_off = ~0;
3189 ha->nvram_data_off = ~0;
3190 } else if (IS_QLA28XX(ha)) {
3191 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3192 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3193 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3194 req_length = REQUEST_ENTRY_CNT_83XX;
3195 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3196 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3197 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3198 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3199 ha->gid_list_info_size = 8;
3200 ha->optrom_size = OPTROM_SIZE_28XX;
3201 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3202 ha->isp_ops = &qla27xx_isp_ops;
3203 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3204 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3205 ha->nvram_conf_off = ~0;
3206 ha->nvram_data_off = ~0;
3207 }
3208
3209 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3210 "mbx_count=%d, req_length=%d, "
3211 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3212 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3213 "max_fibre_devices=%d.\n",
3214 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3215 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3216 ha->nvram_npiv_size, ha->max_fibre_devices);
3217 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3218 "isp_ops=%p, flash_conf_off=%d, "
3219 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3220 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3221 ha->nvram_conf_off, ha->nvram_data_off);
3222
3223 /* Configure PCI I/O space */
3224 ret = ha->isp_ops->iospace_config(ha);
3225 if (ret)
3226 goto iospace_config_failed;
3227
3228 ql_log_pci(ql_log_info, pdev, 0x001d,
3229 "Found an ISP%04X irq %d iobase 0x%p.\n",
3230 pdev->device, pdev->irq, ha->iobase);
3231 mutex_init(&ha->vport_lock);
3232 mutex_init(&ha->mq_lock);
3233 init_completion(&ha->mbx_cmd_comp);
3234 complete(&ha->mbx_cmd_comp);
3235 init_completion(&ha->mbx_intr_comp);
3236 init_completion(&ha->dcbx_comp);
3237 init_completion(&ha->lb_portup_comp);
3238
3239 set_bit(0, (unsigned long *) ha->vp_idx_map);
3240
3241 qla2x00_config_dma_addressing(ha);
3242 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3243 "64 Bit addressing is %s.\n",
3244 ha->flags.enable_64bit_addressing ? "enable" :
3245 "disable");
3246 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3247 if (ret) {
3248 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3249 "Failed to allocate memory for adapter, aborting.\n");
3250
3251 goto probe_hw_failed;
3252 }
3253
3254 req->max_q_depth = MAX_Q_DEPTH;
3255 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3256 req->max_q_depth = ql2xmaxqdepth;
3257
3258
3259 base_vha = qla2x00_create_host(sht, ha);
3260 if (!base_vha) {
3261 ret = -ENOMEM;
3262 goto probe_hw_failed;
3263 }
3264
3265 pci_set_drvdata(pdev, base_vha);
3266 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3267
3268 host = base_vha->host;
3269 base_vha->req = req;
3270 if (IS_QLA2XXX_MIDTYPE(ha))
3271 base_vha->mgmt_svr_loop_id =
3272 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3273 else
3274 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3275 base_vha->vp_idx;
3276
3277 /* Setup fcport template structure. */
3278 ha->mr.fcport.vha = base_vha;
3279 ha->mr.fcport.port_type = FCT_UNKNOWN;
3280 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3281 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3282 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3283 ha->mr.fcport.scan_state = 1;
3284
3285 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3286 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3287 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3288
3289 /* Set the SG table size based on ISP type */
3290 if (!IS_FWI2_CAPABLE(ha)) {
3291 if (IS_QLA2100(ha))
3292 host->sg_tablesize = 32;
3293 } else {
3294 if (!IS_QLA82XX(ha))
3295 host->sg_tablesize = QLA_SG_ALL;
3296 }
3297 host->max_id = ha->max_fibre_devices;
3298 host->cmd_per_lun = 3;
3299 host->unique_id = host->host_no;
3300
3301 if (ql2xenabledif && ql2xenabledif != 2) {
3302 ql_log(ql_log_warn, base_vha, 0x302d,
3303 "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3304 ql2xenabledif = 2;
3305 }
3306
3307 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3308 host->max_cmd_len = 32;
3309 else
3310 host->max_cmd_len = MAX_CMDSZ;
3311 host->max_channel = MAX_BUSES - 1;
3312 /* Older HBAs support only 16-bit LUNs */
3313 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3314 ql2xmaxlun > 0xffff)
3315 host->max_lun = 0xffff;
3316 else
3317 host->max_lun = ql2xmaxlun;
3318 host->transportt = qla2xxx_transport_template;
3319 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3320
3321 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3322 "max_id=%d this_id=%d "
3323 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3324 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3325 host->this_id, host->cmd_per_lun, host->unique_id,
3326 host->max_cmd_len, host->max_channel, host->max_lun,
3327 host->transportt, sht->vendor_id);
3328
3329 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3330
3331 /* Set up the irqs */
3332 ret = qla2x00_request_irqs(ha, rsp);
3333 if (ret)
3334 goto probe_failed;
3335
3336 /* Alloc arrays of request and response ring ptrs */
3337 ret = qla2x00_alloc_queues(ha, req, rsp);
3338 if (ret) {
3339 ql_log(ql_log_fatal, base_vha, 0x003d,
3340 "Failed to allocate memory for queue pointers..."
3341 "aborting.\n");
3342 ret = -ENODEV;
3343 goto probe_failed;
3344 }
3345
3346 if (ha->mqenable) {
3347 /* number of hardware queues supported by blk/scsi-mq*/
3348 host->nr_hw_queues = ha->max_qpairs;
3349
3350 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3351 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3352 } else {
3353 if (ql2xnvmeenable) {
3354 host->nr_hw_queues = ha->max_qpairs;
3355 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3356 "FC-NVMe support is enabled, HW queues=%d\n",
3357 host->nr_hw_queues);
3358 } else {
3359 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3360 "blk/scsi-mq disabled.\n");
3361 }
3362 }
3363
3364 qlt_probe_one_stage1(base_vha, ha);
3365
3366 pci_save_state(pdev);
3367
3368 /* Assign back pointers */
3369 rsp->req = req;
3370 req->rsp = rsp;
3371
3372 if (IS_QLAFX00(ha)) {
3373 ha->rsp_q_map[0] = rsp;
3374 ha->req_q_map[0] = req;
3375 set_bit(0, ha->req_qid_map);
3376 set_bit(0, ha->rsp_qid_map);
3377 }
3378
3379 /* FWI2-capable only. */
3380 req->req_q_in = &ha->iobase->isp24.req_q_in;
3381 req->req_q_out = &ha->iobase->isp24.req_q_out;
3382 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3383 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3384 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3385 IS_QLA28XX(ha)) {
3386 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3387 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3388 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3389 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3390 }
3391
3392 if (IS_QLAFX00(ha)) {
3393 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3394 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3395 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3396 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3397 }
3398
3399 if (IS_P3P_TYPE(ha)) {
3400 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3401 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3402 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3403 }
3404
3405 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3406 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3407 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3408 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3409 "req->req_q_in=%p req->req_q_out=%p "
3410 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3411 req->req_q_in, req->req_q_out,
3412 rsp->rsp_q_in, rsp->rsp_q_out);
3413 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3414 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3415 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3416 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3417 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3418 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3419
3420 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3421 if (unlikely(!ha->wq)) {
3422 ret = -ENOMEM;
3423 goto probe_failed;
3424 }
3425
3426 if (ha->isp_ops->initialize_adapter(base_vha)) {
3427 ql_log(ql_log_fatal, base_vha, 0x00d6,
3428 "Failed to initialize adapter - Adapter flags %x.\n",
3429 base_vha->device_flags);
3430
3431 if (IS_QLA82XX(ha)) {
3432 qla82xx_idc_lock(ha);
3433 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3434 QLA8XXX_DEV_FAILED);
3435 qla82xx_idc_unlock(ha);
3436 ql_log(ql_log_fatal, base_vha, 0x00d7,
3437 "HW State: FAILED.\n");
3438 } else if (IS_QLA8044(ha)) {
3439 qla8044_idc_lock(ha);
3440 qla8044_wr_direct(base_vha,
3441 QLA8044_CRB_DEV_STATE_INDEX,
3442 QLA8XXX_DEV_FAILED);
3443 qla8044_idc_unlock(ha);
3444 ql_log(ql_log_fatal, base_vha, 0x0150,
3445 "HW State: FAILED.\n");
3446 }
3447
3448 ret = -ENODEV;
3449 goto probe_failed;
3450 }
3451
3452 if (IS_QLAFX00(ha))
3453 host->can_queue = QLAFX00_MAX_CANQUEUE;
3454 else
3455 host->can_queue = req->num_outstanding_cmds - 10;
3456
3457 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3458 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3459 host->can_queue, base_vha->req,
3460 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3461
3462 /* Check if FW supports MQ or not for ISP25xx */
3463 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3464 ha->mqenable = 0;
3465
3466 if (ha->mqenable) {
3467 bool startit = false;
3468
3469 if (QLA_TGT_MODE_ENABLED())
3470 startit = false;
3471
3472 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3473 startit = true;
3474
3475 /* Create start of day qpairs for Block MQ */
3476 for (i = 0; i < ha->max_qpairs; i++)
3477 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3478 }
3479 qla_init_iocb_limit(base_vha);
3480
3481 if (ha->flags.running_gold_fw)
3482 goto skip_dpc;
3483
3484 /*
3485 * Startup the kernel thread for this host adapter
3486 */
3487 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3488 "%s_dpc", base_vha->host_str);
3489 if (IS_ERR(ha->dpc_thread)) {
3490 ql_log(ql_log_fatal, base_vha, 0x00ed,
3491 "Failed to start DPC thread.\n");
3492 ret = PTR_ERR(ha->dpc_thread);
3493 ha->dpc_thread = NULL;
3494 goto probe_failed;
3495 }
3496 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3497 "DPC thread started successfully.\n");
3498
3499 /*
3500 * If we're not coming up in initiator mode, we might sit for
3501 * a while without waking up the dpc thread, which leads to a
3502 * stuck process warning. So just kick the dpc once here and
3503 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3504 */
3505 qla2xxx_wake_dpc(base_vha);
3506
3507 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3508
3509 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3510 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3511 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3512 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3513
3514 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3515 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3516 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3517 INIT_WORK(&ha->idc_state_handler,
3518 qla83xx_idc_state_handler_work);
3519 INIT_WORK(&ha->nic_core_unrecoverable,
3520 qla83xx_nic_core_unrecoverable_work);
3521 }
3522
3523 skip_dpc:
3524 list_add_tail(&base_vha->list, &ha->vp_list);
3525 base_vha->host->irq = ha->pdev->irq;
3526
3527 /* Initialized the timer */
3528 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3529 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3530 "Started qla2x00_timer with "
3531 "interval=%d.\n", WATCH_INTERVAL);
3532 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3533 "Detected hba at address=%p.\n",
3534 ha);
3535
3536 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3537 if (ha->fw_attributes & BIT_4) {
3538 int prot = 0, guard;
3539
3540 base_vha->flags.difdix_supported = 1;
3541 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3542 "Registering for DIF/DIX type 1 and 3 protection.\n");
3543 if (ql2xprotmask)
3544 scsi_host_set_prot(host, ql2xprotmask);
3545 else
3546 scsi_host_set_prot(host,
3547 prot | SHOST_DIF_TYPE1_PROTECTION
3548 | SHOST_DIF_TYPE2_PROTECTION
3549 | SHOST_DIF_TYPE3_PROTECTION
3550 | SHOST_DIX_TYPE1_PROTECTION
3551 | SHOST_DIX_TYPE2_PROTECTION
3552 | SHOST_DIX_TYPE3_PROTECTION);
3553
3554 guard = SHOST_DIX_GUARD_CRC;
3555
3556 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3557 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3558 guard |= SHOST_DIX_GUARD_IP;
3559
3560 if (ql2xprotguard)
3561 scsi_host_set_guard(host, ql2xprotguard);
3562 else
3563 scsi_host_set_guard(host, guard);
3564 } else
3565 base_vha->flags.difdix_supported = 0;
3566 }
3567
3568 ha->isp_ops->enable_intrs(ha);
3569
3570 if (IS_QLAFX00(ha)) {
3571 ret = qlafx00_fx_disc(base_vha,
3572 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3573 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3574 QLA_SG_ALL : 128;
3575 }
3576
3577 ret = scsi_add_host(host, &pdev->dev);
3578 if (ret)
3579 goto probe_failed;
3580
3581 base_vha->flags.init_done = 1;
3582 base_vha->flags.online = 1;
3583 ha->prev_minidump_failed = 0;
3584
3585 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3586 "Init done and hba is online.\n");
3587
3588 if (qla_ini_mode_enabled(base_vha) ||
3589 qla_dual_mode_enabled(base_vha))
3590 scsi_scan_host(host);
3591 else
3592 ql_log(ql_log_info, base_vha, 0x0122,
3593 "skipping scsi_scan_host() for non-initiator port\n");
3594
3595 qla2x00_alloc_sysfs_attr(base_vha);
3596
3597 if (IS_QLAFX00(ha)) {
3598 ret = qlafx00_fx_disc(base_vha,
3599 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3600
3601 /* Register system information */
3602 ret = qlafx00_fx_disc(base_vha,
3603 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3604 }
3605
3606 qla2x00_init_host_attr(base_vha);
3607
3608 qla2x00_dfs_setup(base_vha);
3609
3610 ql_log(ql_log_info, base_vha, 0x00fb,
3611 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3612 ql_log(ql_log_info, base_vha, 0x00fc,
3613 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3614 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3615 sizeof(pci_info)),
3616 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3617 base_vha->host_no,
3618 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3619
3620 qlt_add_target(ha, base_vha);
3621
3622 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3623
3624 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3625 return -ENODEV;
3626
3627 return 0;
3628
3629 probe_failed:
3630 qla_enode_stop(base_vha);
3631 qla_edb_stop(base_vha);
3632 vfree(base_vha->scan.l);
3633 if (base_vha->gnl.l) {
3634 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3635 base_vha->gnl.l, base_vha->gnl.ldma);
3636 base_vha->gnl.l = NULL;
3637 }
3638
3639 if (base_vha->timer_active)
3640 qla2x00_stop_timer(base_vha);
3641 base_vha->flags.online = 0;
3642 if (ha->dpc_thread) {
3643 struct task_struct *t = ha->dpc_thread;
3644
3645 ha->dpc_thread = NULL;
3646 kthread_stop(t);
3647 }
3648
3649 qla2x00_free_device(base_vha);
3650 scsi_host_put(base_vha->host);
3651 /*
3652 * Need to NULL out local req/rsp after
3653 * qla2x00_free_device => qla2x00_free_queues frees
3654 * what these are pointing to. Or else we'll
3655 * fall over below in qla2x00_free_req/rsp_que.
3656 */
3657 req = NULL;
3658 rsp = NULL;
3659
3660 probe_hw_failed:
3661 qla2x00_mem_free(ha);
3662 qla2x00_free_req_que(ha, req);
3663 qla2x00_free_rsp_que(ha, rsp);
3664 qla2x00_clear_drv_active(ha);
3665
3666 iospace_config_failed:
3667 if (IS_P3P_TYPE(ha)) {
3668 if (!ha->nx_pcibase)
3669 iounmap((device_reg_t *)ha->nx_pcibase);
3670 if (!ql2xdbwr)
3671 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3672 } else {
3673 if (ha->iobase)
3674 iounmap(ha->iobase);
3675 if (ha->cregbase)
3676 iounmap(ha->cregbase);
3677 }
3678 pci_release_selected_regions(ha->pdev, ha->bars);
3679 kfree(ha);
3680
3681 disable_device:
3682 pci_disable_device(pdev);
3683 return ret;
3684 }
3685
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3686 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3687 {
3688 scsi_qla_host_t *vp;
3689 unsigned long flags;
3690 struct qla_hw_data *ha;
3691
3692 if (!base_vha)
3693 return;
3694
3695 ha = base_vha->hw;
3696
3697 spin_lock_irqsave(&ha->vport_slock, flags);
3698 list_for_each_entry(vp, &ha->vp_list, list)
3699 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3700
3701 /*
3702 * Indicate device removal to prevent future board_disable
3703 * and wait until any pending board_disable has completed.
3704 */
3705 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3706 spin_unlock_irqrestore(&ha->vport_slock, flags);
3707 }
3708
3709 static void
qla2x00_shutdown(struct pci_dev * pdev)3710 qla2x00_shutdown(struct pci_dev *pdev)
3711 {
3712 scsi_qla_host_t *vha;
3713 struct qla_hw_data *ha;
3714
3715 vha = pci_get_drvdata(pdev);
3716 ha = vha->hw;
3717
3718 ql_log(ql_log_info, vha, 0xfffa,
3719 "Adapter shutdown\n");
3720
3721 /*
3722 * Prevent future board_disable and wait
3723 * until any pending board_disable has completed.
3724 */
3725 __qla_set_remove_flag(vha);
3726 cancel_work_sync(&ha->board_disable);
3727
3728 if (!atomic_read(&pdev->enable_cnt))
3729 return;
3730
3731 /* Notify ISPFX00 firmware */
3732 if (IS_QLAFX00(ha))
3733 qlafx00_driver_shutdown(vha, 20);
3734
3735 /* Turn-off FCE trace */
3736 if (ha->flags.fce_enabled) {
3737 qla2x00_disable_fce_trace(vha, NULL, NULL);
3738 ha->flags.fce_enabled = 0;
3739 }
3740
3741 /* Turn-off EFT trace */
3742 if (ha->eft)
3743 qla2x00_disable_eft_trace(vha);
3744
3745 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3746 IS_QLA28XX(ha)) {
3747 if (ha->flags.fw_started)
3748 qla2x00_abort_isp_cleanup(vha);
3749 } else {
3750 /* Stop currently executing firmware. */
3751 qla2x00_try_to_stop_firmware(vha);
3752 }
3753
3754 /* Disable timer */
3755 if (vha->timer_active)
3756 qla2x00_stop_timer(vha);
3757
3758 /* Turn adapter off line */
3759 vha->flags.online = 0;
3760
3761 /* turn-off interrupts on the card */
3762 if (ha->interrupts_on) {
3763 vha->flags.init_done = 0;
3764 ha->isp_ops->disable_intrs(ha);
3765 }
3766
3767 qla2x00_free_irqs(vha);
3768
3769 qla2x00_free_fw_dump(ha);
3770
3771 pci_disable_device(pdev);
3772 ql_log(ql_log_info, vha, 0xfffe,
3773 "Adapter shutdown successfully.\n");
3774 }
3775
3776 /* Deletes all the virtual ports for a given ha */
3777 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3778 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3779 {
3780 scsi_qla_host_t *vha;
3781 unsigned long flags;
3782
3783 mutex_lock(&ha->vport_lock);
3784 while (ha->cur_vport_count) {
3785 spin_lock_irqsave(&ha->vport_slock, flags);
3786
3787 BUG_ON(base_vha->list.next == &ha->vp_list);
3788 /* This assumes first entry in ha->vp_list is always base vha */
3789 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3790 scsi_host_get(vha->host);
3791
3792 spin_unlock_irqrestore(&ha->vport_slock, flags);
3793 mutex_unlock(&ha->vport_lock);
3794
3795 qla_nvme_delete(vha);
3796
3797 fc_vport_terminate(vha->fc_vport);
3798 scsi_host_put(vha->host);
3799
3800 mutex_lock(&ha->vport_lock);
3801 }
3802 mutex_unlock(&ha->vport_lock);
3803 }
3804
3805 /* Stops all deferred work threads */
3806 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3807 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3808 {
3809 /* Cancel all work and destroy DPC workqueues */
3810 if (ha->dpc_lp_wq) {
3811 cancel_work_sync(&ha->idc_aen);
3812 destroy_workqueue(ha->dpc_lp_wq);
3813 ha->dpc_lp_wq = NULL;
3814 }
3815
3816 if (ha->dpc_hp_wq) {
3817 cancel_work_sync(&ha->nic_core_reset);
3818 cancel_work_sync(&ha->idc_state_handler);
3819 cancel_work_sync(&ha->nic_core_unrecoverable);
3820 destroy_workqueue(ha->dpc_hp_wq);
3821 ha->dpc_hp_wq = NULL;
3822 }
3823
3824 /* Kill the kernel thread for this host */
3825 if (ha->dpc_thread) {
3826 struct task_struct *t = ha->dpc_thread;
3827
3828 /*
3829 * qla2xxx_wake_dpc checks for ->dpc_thread
3830 * so we need to zero it out.
3831 */
3832 ha->dpc_thread = NULL;
3833 kthread_stop(t);
3834 }
3835 }
3836
3837 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3838 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3839 {
3840 if (IS_QLA82XX(ha)) {
3841
3842 iounmap((device_reg_t *)ha->nx_pcibase);
3843 if (!ql2xdbwr)
3844 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3845 } else {
3846 if (ha->iobase)
3847 iounmap(ha->iobase);
3848
3849 if (ha->cregbase)
3850 iounmap(ha->cregbase);
3851
3852 if (ha->mqiobase)
3853 iounmap(ha->mqiobase);
3854
3855 if (ha->msixbase)
3856 iounmap(ha->msixbase);
3857 }
3858 }
3859
3860 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3861 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3862 {
3863 if (IS_QLA8044(ha)) {
3864 qla8044_idc_lock(ha);
3865 qla8044_clear_drv_active(ha);
3866 qla8044_idc_unlock(ha);
3867 } else if (IS_QLA82XX(ha)) {
3868 qla82xx_idc_lock(ha);
3869 qla82xx_clear_drv_active(ha);
3870 qla82xx_idc_unlock(ha);
3871 }
3872 }
3873
3874 static void
qla2x00_remove_one(struct pci_dev * pdev)3875 qla2x00_remove_one(struct pci_dev *pdev)
3876 {
3877 scsi_qla_host_t *base_vha;
3878 struct qla_hw_data *ha;
3879
3880 base_vha = pci_get_drvdata(pdev);
3881 ha = base_vha->hw;
3882 ql_log(ql_log_info, base_vha, 0xb079,
3883 "Removing driver\n");
3884 __qla_set_remove_flag(base_vha);
3885 cancel_work_sync(&ha->board_disable);
3886
3887 /*
3888 * If the PCI device is disabled then there was a PCI-disconnect and
3889 * qla2x00_disable_board_on_pci_error has taken care of most of the
3890 * resources.
3891 */
3892 if (!atomic_read(&pdev->enable_cnt)) {
3893 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3894 base_vha->gnl.l, base_vha->gnl.ldma);
3895 base_vha->gnl.l = NULL;
3896 scsi_host_put(base_vha->host);
3897 kfree(ha);
3898 pci_set_drvdata(pdev, NULL);
3899 return;
3900 }
3901 qla2x00_wait_for_hba_ready(base_vha);
3902
3903 /*
3904 * if UNLOADING flag is already set, then continue unload,
3905 * where it was set first.
3906 */
3907 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3908 return;
3909
3910 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3911 IS_QLA28XX(ha)) {
3912 if (ha->flags.fw_started)
3913 qla2x00_abort_isp_cleanup(base_vha);
3914 } else if (!IS_QLAFX00(ha)) {
3915 if (IS_QLA8031(ha)) {
3916 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3917 "Clearing fcoe driver presence.\n");
3918 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3919 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3920 "Error while clearing DRV-Presence.\n");
3921 }
3922
3923 qla2x00_try_to_stop_firmware(base_vha);
3924 }
3925
3926 qla2x00_wait_for_sess_deletion(base_vha);
3927
3928 qla_nvme_delete(base_vha);
3929
3930 dma_free_coherent(&ha->pdev->dev,
3931 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3932
3933 base_vha->gnl.l = NULL;
3934 qla_enode_stop(base_vha);
3935 qla_edb_stop(base_vha);
3936
3937 vfree(base_vha->scan.l);
3938
3939 if (IS_QLAFX00(ha))
3940 qlafx00_driver_shutdown(base_vha, 20);
3941
3942 qla2x00_delete_all_vps(ha, base_vha);
3943
3944 qla2x00_dfs_remove(base_vha);
3945
3946 qla84xx_put_chip(base_vha);
3947
3948 /* Disable timer */
3949 if (base_vha->timer_active)
3950 qla2x00_stop_timer(base_vha);
3951
3952 base_vha->flags.online = 0;
3953
3954 /* free DMA memory */
3955 if (ha->exlogin_buf)
3956 qla2x00_free_exlogin_buffer(ha);
3957
3958 /* free DMA memory */
3959 if (ha->exchoffld_buf)
3960 qla2x00_free_exchoffld_buffer(ha);
3961
3962 qla2x00_destroy_deferred_work(ha);
3963
3964 qlt_remove_target(ha, base_vha);
3965
3966 qla2x00_free_sysfs_attr(base_vha, true);
3967
3968 fc_remove_host(base_vha->host);
3969
3970 scsi_remove_host(base_vha->host);
3971
3972 qla2x00_free_device(base_vha);
3973
3974 qla2x00_clear_drv_active(ha);
3975
3976 scsi_host_put(base_vha->host);
3977
3978 qla2x00_unmap_iobases(ha);
3979
3980 pci_release_selected_regions(ha->pdev, ha->bars);
3981 kfree(ha);
3982
3983 pci_disable_device(pdev);
3984 }
3985
3986 static inline void
qla24xx_free_purex_list(struct purex_list * list)3987 qla24xx_free_purex_list(struct purex_list *list)
3988 {
3989 struct purex_item *item, *next;
3990 ulong flags;
3991
3992 spin_lock_irqsave(&list->lock, flags);
3993 list_for_each_entry_safe(item, next, &list->head, list) {
3994 list_del(&item->list);
3995 if (item == &item->vha->default_item)
3996 continue;
3997 kfree(item);
3998 }
3999 spin_unlock_irqrestore(&list->lock, flags);
4000 }
4001
4002 static void
qla2x00_free_device(scsi_qla_host_t * vha)4003 qla2x00_free_device(scsi_qla_host_t *vha)
4004 {
4005 struct qla_hw_data *ha = vha->hw;
4006
4007 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
4008
4009 /* Disable timer */
4010 if (vha->timer_active)
4011 qla2x00_stop_timer(vha);
4012
4013 qla25xx_delete_queues(vha);
4014 vha->flags.online = 0;
4015
4016 /* turn-off interrupts on the card */
4017 if (ha->interrupts_on) {
4018 vha->flags.init_done = 0;
4019 ha->isp_ops->disable_intrs(ha);
4020 }
4021
4022 qla2x00_free_fcports(vha);
4023
4024 qla2x00_free_irqs(vha);
4025
4026 /* Flush the work queue and remove it */
4027 if (ha->wq) {
4028 destroy_workqueue(ha->wq);
4029 ha->wq = NULL;
4030 }
4031
4032
4033 qla24xx_free_purex_list(&vha->purex_list);
4034
4035 qla2x00_mem_free(ha);
4036
4037 qla82xx_md_free(vha);
4038
4039 qla_edif_sadb_release_free_pool(ha);
4040 qla_edif_sadb_release(ha);
4041
4042 qla2x00_free_queues(ha);
4043 }
4044
qla2x00_free_fcports(struct scsi_qla_host * vha)4045 void qla2x00_free_fcports(struct scsi_qla_host *vha)
4046 {
4047 fc_port_t *fcport, *tfcport;
4048
4049 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4050 qla2x00_free_fcport(fcport);
4051 }
4052
4053 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)4054 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4055 {
4056 int now;
4057
4058 if (!fcport->rport)
4059 return;
4060
4061 if (fcport->rport) {
4062 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4063 "%s %8phN. rport %p roles %x\n",
4064 __func__, fcport->port_name, fcport->rport,
4065 fcport->rport->roles);
4066 fc_remote_port_delete(fcport->rport);
4067 }
4068 qlt_do_generation_tick(vha, &now);
4069 }
4070
4071 /*
4072 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4073 *
4074 * Input: ha = adapter block pointer. fcport = port structure pointer.
4075 *
4076 * Return: None.
4077 *
4078 * Context:
4079 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4080 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4081 int do_login)
4082 {
4083 if (IS_QLAFX00(vha->hw)) {
4084 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4085 qla2x00_schedule_rport_del(vha, fcport);
4086 return;
4087 }
4088
4089 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4090 vha->vp_idx == fcport->vha->vp_idx) {
4091 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4092 qla2x00_schedule_rport_del(vha, fcport);
4093 }
4094
4095 /*
4096 * We may need to retry the login, so don't change the state of the
4097 * port but do the retries.
4098 */
4099 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4100 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4101
4102 if (!do_login)
4103 return;
4104
4105 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4106 }
4107
4108 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4109 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4110 {
4111 fc_port_t *fcport;
4112
4113 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4114 "Mark all dev lost\n");
4115
4116 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4117 if (ql2xfc2target &&
4118 fcport->loop_id != FC_NO_LOOP_ID &&
4119 (fcport->flags & FCF_FCP2_DEVICE) &&
4120 fcport->port_type == FCT_TARGET &&
4121 !qla2x00_reset_active(vha)) {
4122 ql_dbg(ql_dbg_disc, vha, 0x211a,
4123 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4124 fcport->flags, fcport->port_type,
4125 fcport->d_id.b24, fcport->port_name);
4126 continue;
4127 }
4128 fcport->scan_state = 0;
4129 qlt_schedule_sess_for_deletion(fcport);
4130 }
4131 }
4132
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4133 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4134 {
4135 int i;
4136
4137 if (IS_FWI2_CAPABLE(ha))
4138 return;
4139
4140 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4141 set_bit(i, ha->loop_id_map);
4142 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4143 set_bit(BROADCAST, ha->loop_id_map);
4144 }
4145
4146 /*
4147 * qla2x00_mem_alloc
4148 * Allocates adapter memory.
4149 *
4150 * Returns:
4151 * 0 = success.
4152 * !0 = failure.
4153 */
4154 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4155 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4156 struct req_que **req, struct rsp_que **rsp)
4157 {
4158 char name[16];
4159 int rc;
4160
4161 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4162 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4163 if (!ha->vp_map)
4164 goto fail;
4165 }
4166
4167 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4168 &ha->init_cb_dma, GFP_KERNEL);
4169 if (!ha->init_cb)
4170 goto fail_free_vp_map;
4171
4172 rc = btree_init32(&ha->host_map);
4173 if (rc)
4174 goto fail_free_init_cb;
4175
4176 if (qlt_mem_alloc(ha) < 0)
4177 goto fail_free_btree;
4178
4179 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4180 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4181 if (!ha->gid_list)
4182 goto fail_free_tgt_mem;
4183
4184 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4185 if (!ha->srb_mempool)
4186 goto fail_free_gid_list;
4187
4188 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4189 /* Allocate cache for CT6 Ctx. */
4190 if (!ctx_cachep) {
4191 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4192 sizeof(struct ct6_dsd), 0,
4193 SLAB_HWCACHE_ALIGN, NULL);
4194 if (!ctx_cachep)
4195 goto fail_free_srb_mempool;
4196 }
4197 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4198 ctx_cachep);
4199 if (!ha->ctx_mempool)
4200 goto fail_free_srb_mempool;
4201 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4202 "ctx_cachep=%p ctx_mempool=%p.\n",
4203 ctx_cachep, ha->ctx_mempool);
4204 }
4205
4206 /* Get memory for cached NVRAM */
4207 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4208 if (!ha->nvram)
4209 goto fail_free_ctx_mempool;
4210
4211 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4212 ha->pdev->device);
4213 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4214 DMA_POOL_SIZE, 8, 0);
4215 if (!ha->s_dma_pool)
4216 goto fail_free_nvram;
4217
4218 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4219 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4220 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4221
4222 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4223 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4224 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4225 if (!ha->dl_dma_pool) {
4226 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4227 "Failed to allocate memory for dl_dma_pool.\n");
4228 goto fail_s_dma_pool;
4229 }
4230
4231 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4232 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4233 if (!ha->fcp_cmnd_dma_pool) {
4234 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4235 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4236 goto fail_dl_dma_pool;
4237 }
4238
4239 if (ql2xenabledif) {
4240 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4241 struct dsd_dma *dsd, *nxt;
4242 uint i;
4243 /* Creata a DMA pool of buffers for DIF bundling */
4244 ha->dif_bundl_pool = dma_pool_create(name,
4245 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4246 if (!ha->dif_bundl_pool) {
4247 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4248 "%s: failed create dif_bundl_pool\n",
4249 __func__);
4250 goto fail_dif_bundl_dma_pool;
4251 }
4252
4253 INIT_LIST_HEAD(&ha->pool.good.head);
4254 INIT_LIST_HEAD(&ha->pool.unusable.head);
4255 ha->pool.good.count = 0;
4256 ha->pool.unusable.count = 0;
4257 for (i = 0; i < 128; i++) {
4258 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4259 if (!dsd) {
4260 ql_dbg_pci(ql_dbg_init, ha->pdev,
4261 0xe0ee, "%s: failed alloc dsd\n",
4262 __func__);
4263 return -ENOMEM;
4264 }
4265 ha->dif_bundle_kallocs++;
4266
4267 dsd->dsd_addr = dma_pool_alloc(
4268 ha->dif_bundl_pool, GFP_ATOMIC,
4269 &dsd->dsd_list_dma);
4270 if (!dsd->dsd_addr) {
4271 ql_dbg_pci(ql_dbg_init, ha->pdev,
4272 0xe0ee,
4273 "%s: failed alloc ->dsd_addr\n",
4274 __func__);
4275 kfree(dsd);
4276 ha->dif_bundle_kallocs--;
4277 continue;
4278 }
4279 ha->dif_bundle_dma_allocs++;
4280
4281 /*
4282 * if DMA buffer crosses 4G boundary,
4283 * put it on bad list
4284 */
4285 if (MSD(dsd->dsd_list_dma) ^
4286 MSD(dsd->dsd_list_dma + bufsize)) {
4287 list_add_tail(&dsd->list,
4288 &ha->pool.unusable.head);
4289 ha->pool.unusable.count++;
4290 } else {
4291 list_add_tail(&dsd->list,
4292 &ha->pool.good.head);
4293 ha->pool.good.count++;
4294 }
4295 }
4296
4297 /* return the good ones back to the pool */
4298 list_for_each_entry_safe(dsd, nxt,
4299 &ha->pool.good.head, list) {
4300 list_del(&dsd->list);
4301 dma_pool_free(ha->dif_bundl_pool,
4302 dsd->dsd_addr, dsd->dsd_list_dma);
4303 ha->dif_bundle_dma_allocs--;
4304 kfree(dsd);
4305 ha->dif_bundle_kallocs--;
4306 }
4307
4308 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4309 "%s: dif dma pool (good=%u unusable=%u)\n",
4310 __func__, ha->pool.good.count,
4311 ha->pool.unusable.count);
4312 }
4313
4314 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4315 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4316 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4317 ha->dif_bundl_pool);
4318 }
4319
4320 /* Allocate memory for SNS commands */
4321 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4322 /* Get consistent memory allocated for SNS commands */
4323 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4324 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4325 if (!ha->sns_cmd)
4326 goto fail_dma_pool;
4327 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4328 "sns_cmd: %p.\n", ha->sns_cmd);
4329 } else {
4330 /* Get consistent memory allocated for MS IOCB */
4331 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4332 &ha->ms_iocb_dma);
4333 if (!ha->ms_iocb)
4334 goto fail_dma_pool;
4335 /* Get consistent memory allocated for CT SNS commands */
4336 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4337 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4338 if (!ha->ct_sns)
4339 goto fail_free_ms_iocb;
4340 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4341 "ms_iocb=%p ct_sns=%p.\n",
4342 ha->ms_iocb, ha->ct_sns);
4343 }
4344
4345 /* Allocate memory for request ring */
4346 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4347 if (!*req) {
4348 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4349 "Failed to allocate memory for req.\n");
4350 goto fail_req;
4351 }
4352 (*req)->length = req_len;
4353 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4354 ((*req)->length + 1) * sizeof(request_t),
4355 &(*req)->dma, GFP_KERNEL);
4356 if (!(*req)->ring) {
4357 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4358 "Failed to allocate memory for req_ring.\n");
4359 goto fail_req_ring;
4360 }
4361 /* Allocate memory for response ring */
4362 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4363 if (!*rsp) {
4364 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4365 "Failed to allocate memory for rsp.\n");
4366 goto fail_rsp;
4367 }
4368 (*rsp)->hw = ha;
4369 (*rsp)->length = rsp_len;
4370 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4371 ((*rsp)->length + 1) * sizeof(response_t),
4372 &(*rsp)->dma, GFP_KERNEL);
4373 if (!(*rsp)->ring) {
4374 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4375 "Failed to allocate memory for rsp_ring.\n");
4376 goto fail_rsp_ring;
4377 }
4378 (*req)->rsp = *rsp;
4379 (*rsp)->req = *req;
4380 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4381 "req=%p req->length=%d req->ring=%p rsp=%p "
4382 "rsp->length=%d rsp->ring=%p.\n",
4383 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4384 (*rsp)->ring);
4385 /* Allocate memory for NVRAM data for vports */
4386 if (ha->nvram_npiv_size) {
4387 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4388 sizeof(struct qla_npiv_entry),
4389 GFP_KERNEL);
4390 if (!ha->npiv_info) {
4391 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4392 "Failed to allocate memory for npiv_info.\n");
4393 goto fail_npiv_info;
4394 }
4395 } else
4396 ha->npiv_info = NULL;
4397
4398 /* Get consistent memory allocated for EX-INIT-CB. */
4399 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4400 IS_QLA28XX(ha)) {
4401 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4402 &ha->ex_init_cb_dma);
4403 if (!ha->ex_init_cb)
4404 goto fail_ex_init_cb;
4405 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4406 "ex_init_cb=%p.\n", ha->ex_init_cb);
4407 }
4408
4409 /* Get consistent memory allocated for Special Features-CB. */
4410 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4411 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4412 &ha->sf_init_cb_dma);
4413 if (!ha->sf_init_cb)
4414 goto fail_sf_init_cb;
4415 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4416 "sf_init_cb=%p.\n", ha->sf_init_cb);
4417 }
4418
4419
4420 /* Get consistent memory allocated for Async Port-Database. */
4421 if (!IS_FWI2_CAPABLE(ha)) {
4422 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4423 &ha->async_pd_dma);
4424 if (!ha->async_pd)
4425 goto fail_async_pd;
4426 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4427 "async_pd=%p.\n", ha->async_pd);
4428 }
4429
4430 INIT_LIST_HEAD(&ha->vp_list);
4431
4432 /* Allocate memory for our loop_id bitmap */
4433 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4434 sizeof(long),
4435 GFP_KERNEL);
4436 if (!ha->loop_id_map)
4437 goto fail_loop_id_map;
4438 else {
4439 qla2x00_set_reserved_loop_ids(ha);
4440 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4441 "loop_id_map=%p.\n", ha->loop_id_map);
4442 }
4443
4444 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4445 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4446 if (!ha->sfp_data) {
4447 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4448 "Unable to allocate memory for SFP read-data.\n");
4449 goto fail_sfp_data;
4450 }
4451
4452 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4453 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4454 GFP_KERNEL);
4455 if (!ha->flt) {
4456 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4457 "Unable to allocate memory for FLT.\n");
4458 goto fail_flt_buffer;
4459 }
4460
4461 /* allocate the purex dma pool */
4462 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4463 ELS_MAX_PAYLOAD, 8, 0);
4464
4465 if (!ha->purex_dma_pool) {
4466 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4467 "Unable to allocate purex_dma_pool.\n");
4468 goto fail_flt;
4469 }
4470
4471 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4472 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4473 ha->elsrej.size,
4474 &ha->elsrej.cdma,
4475 GFP_KERNEL);
4476 if (!ha->elsrej.c) {
4477 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4478 "Alloc failed for els reject cmd.\n");
4479 goto fail_elsrej;
4480 }
4481 ha->elsrej.c->er_cmd = ELS_LS_RJT;
4482 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4483 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4484
4485 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4486 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4487 &ha->lsrjt.cdma, GFP_KERNEL);
4488 if (!ha->lsrjt.c) {
4489 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4490 "Alloc failed for nvme fc reject cmd.\n");
4491 goto fail_lsrjt;
4492 }
4493
4494 return 0;
4495
4496 fail_lsrjt:
4497 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4498 ha->elsrej.c, ha->elsrej.cdma);
4499 fail_elsrej:
4500 dma_pool_destroy(ha->purex_dma_pool);
4501 fail_flt:
4502 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4503 ha->flt, ha->flt_dma);
4504
4505 fail_flt_buffer:
4506 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4507 ha->sfp_data, ha->sfp_data_dma);
4508 fail_sfp_data:
4509 kfree(ha->loop_id_map);
4510 fail_loop_id_map:
4511 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4512 fail_async_pd:
4513 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4514 fail_sf_init_cb:
4515 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4516 fail_ex_init_cb:
4517 kfree(ha->npiv_info);
4518 fail_npiv_info:
4519 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4520 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4521 (*rsp)->ring = NULL;
4522 (*rsp)->dma = 0;
4523 fail_rsp_ring:
4524 kfree(*rsp);
4525 *rsp = NULL;
4526 fail_rsp:
4527 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4528 sizeof(request_t), (*req)->ring, (*req)->dma);
4529 (*req)->ring = NULL;
4530 (*req)->dma = 0;
4531 fail_req_ring:
4532 kfree(*req);
4533 *req = NULL;
4534 fail_req:
4535 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4536 ha->ct_sns, ha->ct_sns_dma);
4537 ha->ct_sns = NULL;
4538 ha->ct_sns_dma = 0;
4539 fail_free_ms_iocb:
4540 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4541 ha->ms_iocb = NULL;
4542 ha->ms_iocb_dma = 0;
4543
4544 if (ha->sns_cmd)
4545 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4546 ha->sns_cmd, ha->sns_cmd_dma);
4547 fail_dma_pool:
4548 if (ql2xenabledif) {
4549 struct dsd_dma *dsd, *nxt;
4550
4551 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4552 list) {
4553 list_del(&dsd->list);
4554 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4555 dsd->dsd_list_dma);
4556 ha->dif_bundle_dma_allocs--;
4557 kfree(dsd);
4558 ha->dif_bundle_kallocs--;
4559 ha->pool.unusable.count--;
4560 }
4561 dma_pool_destroy(ha->dif_bundl_pool);
4562 ha->dif_bundl_pool = NULL;
4563 }
4564
4565 fail_dif_bundl_dma_pool:
4566 if (IS_QLA82XX(ha) || ql2xenabledif) {
4567 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4568 ha->fcp_cmnd_dma_pool = NULL;
4569 }
4570 fail_dl_dma_pool:
4571 if (IS_QLA82XX(ha) || ql2xenabledif) {
4572 dma_pool_destroy(ha->dl_dma_pool);
4573 ha->dl_dma_pool = NULL;
4574 }
4575 fail_s_dma_pool:
4576 dma_pool_destroy(ha->s_dma_pool);
4577 ha->s_dma_pool = NULL;
4578 fail_free_nvram:
4579 kfree(ha->nvram);
4580 ha->nvram = NULL;
4581 fail_free_ctx_mempool:
4582 mempool_destroy(ha->ctx_mempool);
4583 ha->ctx_mempool = NULL;
4584 fail_free_srb_mempool:
4585 mempool_destroy(ha->srb_mempool);
4586 ha->srb_mempool = NULL;
4587 fail_free_gid_list:
4588 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4589 ha->gid_list,
4590 ha->gid_list_dma);
4591 ha->gid_list = NULL;
4592 ha->gid_list_dma = 0;
4593 fail_free_tgt_mem:
4594 qlt_mem_free(ha);
4595 fail_free_btree:
4596 btree_destroy32(&ha->host_map);
4597 fail_free_init_cb:
4598 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4599 ha->init_cb_dma);
4600 ha->init_cb = NULL;
4601 ha->init_cb_dma = 0;
4602 fail_free_vp_map:
4603 kfree(ha->vp_map);
4604 ha->vp_map = NULL;
4605 fail:
4606 ql_log(ql_log_fatal, NULL, 0x0030,
4607 "Memory allocation failure.\n");
4608 return -ENOMEM;
4609 }
4610
4611 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4612 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4613 {
4614 int rval;
4615 uint16_t size, max_cnt;
4616 uint32_t temp;
4617 struct qla_hw_data *ha = vha->hw;
4618
4619 /* Return if we don't need to alloacate any extended logins */
4620 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4621 return QLA_SUCCESS;
4622
4623 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4624 return QLA_SUCCESS;
4625
4626 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4627 max_cnt = 0;
4628 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4629 if (rval != QLA_SUCCESS) {
4630 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4631 "Failed to get exlogin status.\n");
4632 return rval;
4633 }
4634
4635 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4636 temp *= size;
4637
4638 if (temp != ha->exlogin_size) {
4639 qla2x00_free_exlogin_buffer(ha);
4640 ha->exlogin_size = temp;
4641
4642 ql_log(ql_log_info, vha, 0xd024,
4643 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4644 max_cnt, size, temp);
4645
4646 ql_log(ql_log_info, vha, 0xd025,
4647 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4648
4649 /* Get consistent memory for extended logins */
4650 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4651 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4652 if (!ha->exlogin_buf) {
4653 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4654 "Failed to allocate memory for exlogin_buf_dma.\n");
4655 return -ENOMEM;
4656 }
4657 }
4658
4659 /* Now configure the dma buffer */
4660 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4661 if (rval) {
4662 ql_log(ql_log_fatal, vha, 0xd033,
4663 "Setup extended login buffer ****FAILED****.\n");
4664 qla2x00_free_exlogin_buffer(ha);
4665 }
4666
4667 return rval;
4668 }
4669
4670 /*
4671 * qla2x00_free_exlogin_buffer
4672 *
4673 * Input:
4674 * ha = adapter block pointer
4675 */
4676 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4677 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4678 {
4679 if (ha->exlogin_buf) {
4680 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4681 ha->exlogin_buf, ha->exlogin_buf_dma);
4682 ha->exlogin_buf = NULL;
4683 ha->exlogin_size = 0;
4684 }
4685 }
4686
4687 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4688 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4689 {
4690 u32 temp;
4691 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4692 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4693
4694 if (max_cnt > vha->hw->max_exchg)
4695 max_cnt = vha->hw->max_exchg;
4696
4697 if (qla_ini_mode_enabled(vha)) {
4698 if (vha->ql2xiniexchg > max_cnt)
4699 vha->ql2xiniexchg = max_cnt;
4700
4701 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4702 *ret_cnt = vha->ql2xiniexchg;
4703
4704 } else if (qla_tgt_mode_enabled(vha)) {
4705 if (vha->ql2xexchoffld > max_cnt) {
4706 vha->ql2xexchoffld = max_cnt;
4707 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4708 }
4709
4710 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4711 *ret_cnt = vha->ql2xexchoffld;
4712 } else if (qla_dual_mode_enabled(vha)) {
4713 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4714 if (temp > max_cnt) {
4715 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4716 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4717 temp = max_cnt;
4718 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4719 }
4720
4721 if (temp > FW_DEF_EXCHANGES_CNT)
4722 *ret_cnt = temp;
4723 }
4724 }
4725
4726 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4727 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4728 {
4729 int rval;
4730 u16 size, max_cnt;
4731 u32 actual_cnt, totsz;
4732 struct qla_hw_data *ha = vha->hw;
4733
4734 if (!ha->flags.exchoffld_enabled)
4735 return QLA_SUCCESS;
4736
4737 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4738 return QLA_SUCCESS;
4739
4740 max_cnt = 0;
4741 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4742 if (rval != QLA_SUCCESS) {
4743 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4744 "Failed to get exlogin status.\n");
4745 return rval;
4746 }
4747
4748 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4749 ql_log(ql_log_info, vha, 0xd014,
4750 "Actual exchange offload count: %d.\n", actual_cnt);
4751
4752 totsz = actual_cnt * size;
4753
4754 if (totsz != ha->exchoffld_size) {
4755 qla2x00_free_exchoffld_buffer(ha);
4756 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4757 ha->exchoffld_size = 0;
4758 ha->flags.exchoffld_enabled = 0;
4759 return QLA_SUCCESS;
4760 }
4761
4762 ha->exchoffld_size = totsz;
4763
4764 ql_log(ql_log_info, vha, 0xd016,
4765 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4766 max_cnt, actual_cnt, size, totsz);
4767
4768 ql_log(ql_log_info, vha, 0xd017,
4769 "Exchange Buffers requested size = 0x%x\n",
4770 ha->exchoffld_size);
4771
4772 /* Get consistent memory for extended logins */
4773 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4774 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4775 if (!ha->exchoffld_buf) {
4776 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4777 "Failed to allocate memory for Exchange Offload.\n");
4778
4779 if (ha->max_exchg >
4780 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4781 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4782 } else if (ha->max_exchg >
4783 (FW_DEF_EXCHANGES_CNT + 512)) {
4784 ha->max_exchg -= 512;
4785 } else {
4786 ha->flags.exchoffld_enabled = 0;
4787 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4788 "Disabling Exchange offload due to lack of memory\n");
4789 }
4790 ha->exchoffld_size = 0;
4791
4792 return -ENOMEM;
4793 }
4794 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4795 /* pathological case */
4796 qla2x00_free_exchoffld_buffer(ha);
4797 ha->exchoffld_size = 0;
4798 ha->flags.exchoffld_enabled = 0;
4799 ql_log(ql_log_info, vha, 0xd016,
4800 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4801 ha->exchoffld_size, actual_cnt, size, totsz);
4802 return 0;
4803 }
4804
4805 /* Now configure the dma buffer */
4806 rval = qla_set_exchoffld_mem_cfg(vha);
4807 if (rval) {
4808 ql_log(ql_log_fatal, vha, 0xd02e,
4809 "Setup exchange offload buffer ****FAILED****.\n");
4810 qla2x00_free_exchoffld_buffer(ha);
4811 } else {
4812 /* re-adjust number of target exchange */
4813 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4814
4815 if (qla_ini_mode_enabled(vha))
4816 icb->exchange_count = 0;
4817 else
4818 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4819 }
4820
4821 return rval;
4822 }
4823
4824 /*
4825 * qla2x00_free_exchoffld_buffer
4826 *
4827 * Input:
4828 * ha = adapter block pointer
4829 */
4830 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4831 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4832 {
4833 if (ha->exchoffld_buf) {
4834 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4835 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4836 ha->exchoffld_buf = NULL;
4837 ha->exchoffld_size = 0;
4838 }
4839 }
4840
4841 /*
4842 * qla2x00_free_fw_dump
4843 * Frees fw dump stuff.
4844 *
4845 * Input:
4846 * ha = adapter block pointer
4847 */
4848 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4849 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4850 {
4851 struct fwdt *fwdt = ha->fwdt;
4852 uint j;
4853
4854 if (ha->fce)
4855 dma_free_coherent(&ha->pdev->dev,
4856 FCE_SIZE, ha->fce, ha->fce_dma);
4857
4858 if (ha->eft)
4859 dma_free_coherent(&ha->pdev->dev,
4860 EFT_SIZE, ha->eft, ha->eft_dma);
4861
4862 vfree(ha->fw_dump);
4863
4864 ha->fce = NULL;
4865 ha->fce_dma = 0;
4866 ha->flags.fce_enabled = 0;
4867 ha->eft = NULL;
4868 ha->eft_dma = 0;
4869 ha->fw_dumped = false;
4870 ha->fw_dump_cap_flags = 0;
4871 ha->fw_dump_reading = 0;
4872 ha->fw_dump = NULL;
4873 ha->fw_dump_len = 0;
4874
4875 for (j = 0; j < 2; j++, fwdt++) {
4876 vfree(fwdt->template);
4877 fwdt->template = NULL;
4878 fwdt->length = 0;
4879 }
4880 }
4881
4882 /*
4883 * qla2x00_mem_free
4884 * Frees all adapter allocated memory.
4885 *
4886 * Input:
4887 * ha = adapter block pointer.
4888 */
4889 static void
qla2x00_mem_free(struct qla_hw_data * ha)4890 qla2x00_mem_free(struct qla_hw_data *ha)
4891 {
4892 qla2x00_free_fw_dump(ha);
4893
4894 if (ha->mctp_dump)
4895 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4896 ha->mctp_dump_dma);
4897 ha->mctp_dump = NULL;
4898
4899 mempool_destroy(ha->srb_mempool);
4900 ha->srb_mempool = NULL;
4901
4902 if (ha->dcbx_tlv)
4903 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4904 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4905 ha->dcbx_tlv = NULL;
4906
4907 if (ha->xgmac_data)
4908 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4909 ha->xgmac_data, ha->xgmac_data_dma);
4910 ha->xgmac_data = NULL;
4911
4912 if (ha->sns_cmd)
4913 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4914 ha->sns_cmd, ha->sns_cmd_dma);
4915 ha->sns_cmd = NULL;
4916 ha->sns_cmd_dma = 0;
4917
4918 if (ha->ct_sns)
4919 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4920 ha->ct_sns, ha->ct_sns_dma);
4921 ha->ct_sns = NULL;
4922 ha->ct_sns_dma = 0;
4923
4924 if (ha->sfp_data)
4925 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4926 ha->sfp_data_dma);
4927 ha->sfp_data = NULL;
4928
4929 if (ha->flt)
4930 dma_free_coherent(&ha->pdev->dev,
4931 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4932 ha->flt, ha->flt_dma);
4933 ha->flt = NULL;
4934 ha->flt_dma = 0;
4935
4936 if (ha->ms_iocb)
4937 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4938 ha->ms_iocb = NULL;
4939 ha->ms_iocb_dma = 0;
4940
4941 if (ha->sf_init_cb)
4942 dma_pool_free(ha->s_dma_pool,
4943 ha->sf_init_cb, ha->sf_init_cb_dma);
4944
4945 if (ha->ex_init_cb)
4946 dma_pool_free(ha->s_dma_pool,
4947 ha->ex_init_cb, ha->ex_init_cb_dma);
4948 ha->ex_init_cb = NULL;
4949 ha->ex_init_cb_dma = 0;
4950
4951 if (ha->async_pd)
4952 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4953 ha->async_pd = NULL;
4954 ha->async_pd_dma = 0;
4955
4956 dma_pool_destroy(ha->s_dma_pool);
4957 ha->s_dma_pool = NULL;
4958
4959 if (ha->gid_list)
4960 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4961 ha->gid_list, ha->gid_list_dma);
4962 ha->gid_list = NULL;
4963 ha->gid_list_dma = 0;
4964
4965 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4966 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4967
4968 /* clean up allocated prev pool */
4969 list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4970 &ha->base_qpair->dsd_list, list) {
4971 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4972 dsd_ptr->dsd_list_dma);
4973 list_del(&dsd_ptr->list);
4974 kfree(dsd_ptr);
4975 }
4976 }
4977
4978 dma_pool_destroy(ha->dl_dma_pool);
4979 ha->dl_dma_pool = NULL;
4980
4981 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4982 ha->fcp_cmnd_dma_pool = NULL;
4983
4984 mempool_destroy(ha->ctx_mempool);
4985 ha->ctx_mempool = NULL;
4986
4987 if (ql2xenabledif && ha->dif_bundl_pool) {
4988 struct dsd_dma *dsd, *nxt;
4989
4990 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4991 list) {
4992 list_del(&dsd->list);
4993 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4994 dsd->dsd_list_dma);
4995 ha->dif_bundle_dma_allocs--;
4996 kfree(dsd);
4997 ha->dif_bundle_kallocs--;
4998 ha->pool.unusable.count--;
4999 }
5000 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
5001 list_del(&dsd->list);
5002 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
5003 dsd->dsd_list_dma);
5004 ha->dif_bundle_dma_allocs--;
5005 kfree(dsd);
5006 ha->dif_bundle_kallocs--;
5007 }
5008 }
5009
5010 dma_pool_destroy(ha->dif_bundl_pool);
5011 ha->dif_bundl_pool = NULL;
5012
5013 qlt_mem_free(ha);
5014 qla_remove_hostmap(ha);
5015
5016 if (ha->init_cb)
5017 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5018 ha->init_cb, ha->init_cb_dma);
5019
5020 dma_pool_destroy(ha->purex_dma_pool);
5021 ha->purex_dma_pool = NULL;
5022
5023 if (ha->elsrej.c) {
5024 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5025 ha->elsrej.c, ha->elsrej.cdma);
5026 ha->elsrej.c = NULL;
5027 }
5028
5029 if (ha->lsrjt.c) {
5030 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5031 ha->lsrjt.cdma);
5032 ha->lsrjt.c = NULL;
5033 }
5034
5035 ha->init_cb = NULL;
5036 ha->init_cb_dma = 0;
5037
5038 vfree(ha->optrom_buffer);
5039 ha->optrom_buffer = NULL;
5040 kfree(ha->nvram);
5041 ha->nvram = NULL;
5042 kfree(ha->npiv_info);
5043 ha->npiv_info = NULL;
5044 kfree(ha->swl);
5045 ha->swl = NULL;
5046 kfree(ha->loop_id_map);
5047 ha->sf_init_cb = NULL;
5048 ha->sf_init_cb_dma = 0;
5049 ha->loop_id_map = NULL;
5050
5051 kfree(ha->vp_map);
5052 ha->vp_map = NULL;
5053 }
5054
qla2x00_create_host(const struct scsi_host_template * sht,struct qla_hw_data * ha)5055 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5056 struct qla_hw_data *ha)
5057 {
5058 struct Scsi_Host *host;
5059 struct scsi_qla_host *vha = NULL;
5060
5061 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5062 if (!host) {
5063 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5064 "Failed to allocate host from the scsi layer, aborting.\n");
5065 return NULL;
5066 }
5067
5068 /* Clear our data area */
5069 vha = shost_priv(host);
5070 memset(vha, 0, sizeof(scsi_qla_host_t));
5071
5072 vha->host = host;
5073 vha->host_no = host->host_no;
5074 vha->hw = ha;
5075
5076 vha->qlini_mode = ql2x_ini_mode;
5077 vha->ql2xexchoffld = ql2xexchoffld;
5078 vha->ql2xiniexchg = ql2xiniexchg;
5079
5080 INIT_LIST_HEAD(&vha->vp_fcports);
5081 INIT_LIST_HEAD(&vha->work_list);
5082 INIT_LIST_HEAD(&vha->list);
5083 INIT_LIST_HEAD(&vha->qla_cmd_list);
5084 INIT_LIST_HEAD(&vha->logo_list);
5085 INIT_LIST_HEAD(&vha->plogi_ack_list);
5086 INIT_LIST_HEAD(&vha->qp_list);
5087 INIT_LIST_HEAD(&vha->gnl.fcports);
5088 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5089
5090 INIT_LIST_HEAD(&vha->purex_list.head);
5091 spin_lock_init(&vha->purex_list.lock);
5092
5093 spin_lock_init(&vha->work_lock);
5094 spin_lock_init(&vha->cmd_list_lock);
5095 init_waitqueue_head(&vha->fcport_waitQ);
5096 init_waitqueue_head(&vha->vref_waitq);
5097 qla_enode_init(vha);
5098 qla_edb_init(vha);
5099
5100
5101 vha->gnl.size = sizeof(struct get_name_list_extended) *
5102 (ha->max_loop_id + 1);
5103 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5104 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5105 if (!vha->gnl.l) {
5106 ql_log(ql_log_fatal, vha, 0xd04a,
5107 "Alloc failed for name list.\n");
5108 scsi_host_put(vha->host);
5109 return NULL;
5110 }
5111
5112 /* todo: what about ext login? */
5113 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5114 vha->scan.l = vmalloc(vha->scan.size);
5115 if (!vha->scan.l) {
5116 ql_log(ql_log_fatal, vha, 0xd04a,
5117 "Alloc failed for scan database.\n");
5118 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5119 vha->gnl.l, vha->gnl.ldma);
5120 vha->gnl.l = NULL;
5121 scsi_host_put(vha->host);
5122 return NULL;
5123 }
5124 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5125
5126 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5127 QLA2XXX_DRIVER_NAME, vha->host_no);
5128 ql_dbg(ql_dbg_init, vha, 0x0041,
5129 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5130 vha->host, vha->hw, vha,
5131 dev_name(&(ha->pdev->dev)));
5132
5133 return vha;
5134 }
5135
5136 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5137 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5138 {
5139 struct qla_work_evt *e;
5140
5141 if (test_bit(UNLOADING, &vha->dpc_flags))
5142 return NULL;
5143
5144 if (qla_vha_mark_busy(vha))
5145 return NULL;
5146
5147 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5148 if (!e) {
5149 QLA_VHA_MARK_NOT_BUSY(vha);
5150 return NULL;
5151 }
5152
5153 INIT_LIST_HEAD(&e->list);
5154 e->type = type;
5155 e->flags = QLA_EVT_FLAG_FREE;
5156 return e;
5157 }
5158
5159 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5160 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5161 {
5162 unsigned long flags;
5163 bool q = false;
5164
5165 spin_lock_irqsave(&vha->work_lock, flags);
5166 list_add_tail(&e->list, &vha->work_list);
5167
5168 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5169 q = true;
5170
5171 spin_unlock_irqrestore(&vha->work_lock, flags);
5172
5173 if (q)
5174 queue_work(vha->hw->wq, &vha->iocb_work);
5175
5176 return QLA_SUCCESS;
5177 }
5178
5179 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5180 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5181 u32 data)
5182 {
5183 struct qla_work_evt *e;
5184
5185 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5186 if (!e)
5187 return QLA_FUNCTION_FAILED;
5188
5189 e->u.aen.code = code;
5190 e->u.aen.data = data;
5191 return qla2x00_post_work(vha, e);
5192 }
5193
5194 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5195 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5196 {
5197 struct qla_work_evt *e;
5198
5199 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5200 if (!e)
5201 return QLA_FUNCTION_FAILED;
5202
5203 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5204 return qla2x00_post_work(vha, e);
5205 }
5206
5207 #define qla2x00_post_async_work(name, type) \
5208 int qla2x00_post_async_##name##_work( \
5209 struct scsi_qla_host *vha, \
5210 fc_port_t *fcport, uint16_t *data) \
5211 { \
5212 struct qla_work_evt *e; \
5213 \
5214 e = qla2x00_alloc_work(vha, type); \
5215 if (!e) \
5216 return QLA_FUNCTION_FAILED; \
5217 \
5218 e->u.logio.fcport = fcport; \
5219 if (data) { \
5220 e->u.logio.data[0] = data[0]; \
5221 e->u.logio.data[1] = data[1]; \
5222 } \
5223 fcport->flags |= FCF_ASYNC_ACTIVE; \
5224 return qla2x00_post_work(vha, e); \
5225 }
5226
5227 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5228 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5229 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5230 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5231 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5232
5233 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5234 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5235 {
5236 struct qla_work_evt *e;
5237
5238 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5239 if (!e)
5240 return QLA_FUNCTION_FAILED;
5241
5242 e->u.uevent.code = code;
5243 return qla2x00_post_work(vha, e);
5244 }
5245
5246 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5247 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5248 {
5249 char event_string[40];
5250 char *envp[] = { event_string, NULL };
5251
5252 switch (code) {
5253 case QLA_UEVENT_CODE_FW_DUMP:
5254 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5255 vha->host_no);
5256 break;
5257 default:
5258 /* do nothing */
5259 break;
5260 }
5261 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5262 }
5263
5264 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5265 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5266 uint32_t *data, int cnt)
5267 {
5268 struct qla_work_evt *e;
5269
5270 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5271 if (!e)
5272 return QLA_FUNCTION_FAILED;
5273
5274 e->u.aenfx.evtcode = evtcode;
5275 e->u.aenfx.count = cnt;
5276 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5277 return qla2x00_post_work(vha, e);
5278 }
5279
qla24xx_sched_upd_fcport(fc_port_t * fcport)5280 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5281 {
5282 unsigned long flags;
5283
5284 if (IS_SW_RESV_ADDR(fcport->d_id))
5285 return;
5286
5287 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5288 if (fcport->disc_state == DSC_UPD_FCPORT) {
5289 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5290 return;
5291 }
5292 fcport->jiffies_at_registration = jiffies;
5293 fcport->sec_since_registration = 0;
5294 fcport->next_disc_state = DSC_DELETED;
5295 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5296 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5297
5298 queue_work(system_unbound_wq, &fcport->reg_work);
5299 }
5300
5301 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5302 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5303 {
5304 unsigned long flags;
5305 fc_port_t *fcport = NULL, *tfcp;
5306 struct qlt_plogi_ack_t *pla =
5307 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5308 uint8_t free_fcport = 0;
5309
5310 ql_dbg(ql_dbg_disc, vha, 0xffff,
5311 "%s %d %8phC enter\n",
5312 __func__, __LINE__, e->u.new_sess.port_name);
5313
5314 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5315 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5316 if (fcport) {
5317 fcport->d_id = e->u.new_sess.id;
5318 if (pla) {
5319 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5320 memcpy(fcport->node_name,
5321 pla->iocb.u.isp24.u.plogi.node_name,
5322 WWN_SIZE);
5323 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5324 /* we took an extra ref_count to prevent PLOGI ACK when
5325 * fcport/sess has not been created.
5326 */
5327 pla->ref_count--;
5328 }
5329 } else {
5330 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5331 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5332 if (fcport) {
5333 fcport->d_id = e->u.new_sess.id;
5334 fcport->flags |= FCF_FABRIC_DEVICE;
5335 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5336 fcport->tgt_short_link_down_cnt = 0;
5337
5338 memcpy(fcport->port_name, e->u.new_sess.port_name,
5339 WWN_SIZE);
5340
5341 fcport->fc4_type = e->u.new_sess.fc4_type;
5342 if (NVME_PRIORITY(vha->hw, fcport))
5343 fcport->do_prli_nvme = 1;
5344 else
5345 fcport->do_prli_nvme = 0;
5346
5347 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5348 fcport->dm_login_expire = jiffies +
5349 QLA_N2N_WAIT_TIME * HZ;
5350 fcport->fc4_type = FS_FC4TYPE_FCP;
5351 fcport->n2n_flag = 1;
5352 if (vha->flags.nvme_enabled)
5353 fcport->fc4_type |= FS_FC4TYPE_NVME;
5354 }
5355
5356 } else {
5357 ql_dbg(ql_dbg_disc, vha, 0xffff,
5358 "%s %8phC mem alloc fail.\n",
5359 __func__, e->u.new_sess.port_name);
5360
5361 if (pla) {
5362 list_del(&pla->list);
5363 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5364 }
5365 return;
5366 }
5367
5368 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5369 /* search again to make sure no one else got ahead */
5370 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5371 e->u.new_sess.port_name, 1);
5372 if (tfcp) {
5373 /* should rarily happen */
5374 ql_dbg(ql_dbg_disc, vha, 0xffff,
5375 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5376 __func__, tfcp->port_name, tfcp->disc_state,
5377 tfcp->fw_login_state);
5378
5379 free_fcport = 1;
5380 } else {
5381 list_add_tail(&fcport->list, &vha->vp_fcports);
5382
5383 }
5384 if (pla) {
5385 qlt_plogi_ack_link(vha, pla, fcport,
5386 QLT_PLOGI_LINK_SAME_WWN);
5387 pla->ref_count--;
5388 }
5389 }
5390 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5391
5392 if (fcport) {
5393 fcport->id_changed = 1;
5394 fcport->scan_state = QLA_FCPORT_FOUND;
5395 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5396 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5397
5398 if (pla) {
5399 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5400 u16 wd3_lo;
5401
5402 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5403 fcport->local = 0;
5404 fcport->loop_id =
5405 le16_to_cpu(
5406 pla->iocb.u.isp24.nport_handle);
5407 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5408 wd3_lo =
5409 le16_to_cpu(
5410 pla->iocb.u.isp24.u.prli.wd3_lo);
5411
5412 if (wd3_lo & BIT_7)
5413 fcport->conf_compl_supported = 1;
5414
5415 if ((wd3_lo & BIT_4) == 0)
5416 fcport->port_type = FCT_INITIATOR;
5417 else
5418 fcport->port_type = FCT_TARGET;
5419 }
5420 qlt_plogi_ack_unref(vha, pla);
5421 } else {
5422 fc_port_t *dfcp = NULL;
5423
5424 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5425 tfcp = qla2x00_find_fcport_by_nportid(vha,
5426 &e->u.new_sess.id, 1);
5427 if (tfcp && (tfcp != fcport)) {
5428 /*
5429 * We have a conflict fcport with same NportID.
5430 */
5431 ql_dbg(ql_dbg_disc, vha, 0xffff,
5432 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5433 __func__, tfcp->port_name, tfcp->disc_state,
5434 tfcp->fw_login_state);
5435
5436 switch (tfcp->disc_state) {
5437 case DSC_DELETED:
5438 break;
5439 case DSC_DELETE_PEND:
5440 fcport->login_pause = 1;
5441 tfcp->conflict = fcport;
5442 break;
5443 default:
5444 fcport->login_pause = 1;
5445 tfcp->conflict = fcport;
5446 dfcp = tfcp;
5447 break;
5448 }
5449 }
5450 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5451 if (dfcp)
5452 qlt_schedule_sess_for_deletion(tfcp);
5453
5454 if (N2N_TOPO(vha->hw)) {
5455 fcport->flags &= ~FCF_FABRIC_DEVICE;
5456 fcport->keep_nport_handle = 1;
5457 if (vha->flags.nvme_enabled) {
5458 fcport->fc4_type =
5459 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5460 fcport->n2n_flag = 1;
5461 }
5462 fcport->fw_login_state = 0;
5463
5464 schedule_delayed_work(&vha->scan.scan_work, 5);
5465 } else {
5466 qla24xx_fcport_handle_login(vha, fcport);
5467 }
5468 }
5469 }
5470
5471 if (free_fcport) {
5472 qla2x00_free_fcport(fcport);
5473 if (pla) {
5474 list_del(&pla->list);
5475 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5476 }
5477 }
5478 }
5479
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5480 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5481 {
5482 struct srb *sp = e->u.iosb.sp;
5483 int rval;
5484
5485 rval = qla2x00_start_sp(sp);
5486 if (rval != QLA_SUCCESS) {
5487 ql_dbg(ql_dbg_disc, vha, 0x2043,
5488 "%s: %s: Re-issue IOCB failed (%d).\n",
5489 __func__, sp->name, rval);
5490 qla24xx_sp_unmap(vha, sp);
5491 }
5492 }
5493
5494 void
qla2x00_do_work(struct scsi_qla_host * vha)5495 qla2x00_do_work(struct scsi_qla_host *vha)
5496 {
5497 struct qla_work_evt *e, *tmp;
5498 unsigned long flags;
5499 LIST_HEAD(work);
5500 int rc;
5501
5502 spin_lock_irqsave(&vha->work_lock, flags);
5503 list_splice_init(&vha->work_list, &work);
5504 spin_unlock_irqrestore(&vha->work_lock, flags);
5505
5506 list_for_each_entry_safe(e, tmp, &work, list) {
5507 rc = QLA_SUCCESS;
5508 switch (e->type) {
5509 case QLA_EVT_AEN:
5510 fc_host_post_event(vha->host, fc_get_event_number(),
5511 e->u.aen.code, e->u.aen.data);
5512 break;
5513 case QLA_EVT_IDC_ACK:
5514 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5515 break;
5516 case QLA_EVT_ASYNC_LOGIN:
5517 qla2x00_async_login(vha, e->u.logio.fcport,
5518 e->u.logio.data);
5519 break;
5520 case QLA_EVT_ASYNC_LOGOUT:
5521 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5522 break;
5523 case QLA_EVT_ASYNC_ADISC:
5524 qla2x00_async_adisc(vha, e->u.logio.fcport,
5525 e->u.logio.data);
5526 break;
5527 case QLA_EVT_UEVENT:
5528 qla2x00_uevent_emit(vha, e->u.uevent.code);
5529 break;
5530 case QLA_EVT_AENFX:
5531 qlafx00_process_aen(vha, e);
5532 break;
5533 case QLA_EVT_UNMAP:
5534 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5535 break;
5536 case QLA_EVT_RELOGIN:
5537 qla2x00_relogin(vha);
5538 break;
5539 case QLA_EVT_NEW_SESS:
5540 qla24xx_create_new_sess(vha, e);
5541 break;
5542 case QLA_EVT_GPDB:
5543 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5544 e->u.fcport.opt);
5545 break;
5546 case QLA_EVT_PRLI:
5547 qla24xx_async_prli(vha, e->u.fcport.fcport);
5548 break;
5549 case QLA_EVT_GPSC:
5550 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5551 break;
5552 case QLA_EVT_GNL:
5553 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5554 break;
5555 case QLA_EVT_NACK:
5556 qla24xx_do_nack_work(vha, e);
5557 break;
5558 case QLA_EVT_ASYNC_PRLO:
5559 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5560 break;
5561 case QLA_EVT_ASYNC_PRLO_DONE:
5562 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5563 e->u.logio.data);
5564 break;
5565 case QLA_EVT_GPNFT:
5566 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5567 e->u.gpnft.sp);
5568 break;
5569 case QLA_EVT_GPNFT_DONE:
5570 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5571 break;
5572 case QLA_EVT_GNNFT_DONE:
5573 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5574 break;
5575 case QLA_EVT_GFPNID:
5576 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5577 break;
5578 case QLA_EVT_SP_RETRY:
5579 qla_sp_retry(vha, e);
5580 break;
5581 case QLA_EVT_IIDMA:
5582 qla_do_iidma_work(vha, e->u.fcport.fcport);
5583 break;
5584 case QLA_EVT_ELS_PLOGI:
5585 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5586 e->u.fcport.fcport);
5587 break;
5588 case QLA_EVT_SA_REPLACE:
5589 rc = qla24xx_issue_sa_replace_iocb(vha, e);
5590 break;
5591 }
5592
5593 if (rc == EAGAIN) {
5594 /* put 'work' at head of 'vha->work_list' */
5595 spin_lock_irqsave(&vha->work_lock, flags);
5596 list_splice(&work, &vha->work_list);
5597 spin_unlock_irqrestore(&vha->work_lock, flags);
5598 break;
5599 }
5600 list_del_init(&e->list);
5601 if (e->flags & QLA_EVT_FLAG_FREE)
5602 kfree(e);
5603
5604 /* For each work completed decrement vha ref count */
5605 QLA_VHA_MARK_NOT_BUSY(vha);
5606 }
5607 }
5608
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5609 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5610 {
5611 struct qla_work_evt *e;
5612
5613 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5614
5615 if (!e) {
5616 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5617 return QLA_FUNCTION_FAILED;
5618 }
5619
5620 return qla2x00_post_work(vha, e);
5621 }
5622
5623 /* Relogins all the fcports of a vport
5624 * Context: dpc thread
5625 */
qla2x00_relogin(struct scsi_qla_host * vha)5626 void qla2x00_relogin(struct scsi_qla_host *vha)
5627 {
5628 fc_port_t *fcport;
5629 int status, relogin_needed = 0;
5630 struct event_arg ea;
5631
5632 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5633 /*
5634 * If the port is not ONLINE then try to login
5635 * to it if we haven't run out of retries.
5636 */
5637 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5638 fcport->login_retry) {
5639 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5640 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5641 fcport->disc_state == DSC_LOGIN_COMPLETE)
5642 continue;
5643
5644 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5645 fcport->disc_state == DSC_DELETE_PEND) {
5646 relogin_needed = 1;
5647 } else {
5648 if (vha->hw->current_topology != ISP_CFG_NL) {
5649 memset(&ea, 0, sizeof(ea));
5650 ea.fcport = fcport;
5651 qla24xx_handle_relogin_event(vha, &ea);
5652 } else if (vha->hw->current_topology ==
5653 ISP_CFG_NL &&
5654 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5655 (void)qla24xx_fcport_handle_login(vha,
5656 fcport);
5657 } else if (vha->hw->current_topology ==
5658 ISP_CFG_NL) {
5659 fcport->login_retry--;
5660 status =
5661 qla2x00_local_device_login(vha,
5662 fcport);
5663 if (status == QLA_SUCCESS) {
5664 fcport->old_loop_id =
5665 fcport->loop_id;
5666 ql_dbg(ql_dbg_disc, vha, 0x2003,
5667 "Port login OK: logged in ID 0x%x.\n",
5668 fcport->loop_id);
5669 qla2x00_update_fcport
5670 (vha, fcport);
5671 } else if (status == 1) {
5672 set_bit(RELOGIN_NEEDED,
5673 &vha->dpc_flags);
5674 /* retry the login again */
5675 ql_dbg(ql_dbg_disc, vha, 0x2007,
5676 "Retrying %d login again loop_id 0x%x.\n",
5677 fcport->login_retry,
5678 fcport->loop_id);
5679 } else {
5680 fcport->login_retry = 0;
5681 }
5682
5683 if (fcport->login_retry == 0 &&
5684 status != QLA_SUCCESS)
5685 qla2x00_clear_loop_id(fcport);
5686 }
5687 }
5688 }
5689 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5690 break;
5691 }
5692
5693 if (relogin_needed)
5694 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5695
5696 ql_dbg(ql_dbg_disc, vha, 0x400e,
5697 "Relogin end.\n");
5698 }
5699
5700 /* Schedule work on any of the dpc-workqueues */
5701 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5702 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5703 {
5704 struct qla_hw_data *ha = base_vha->hw;
5705
5706 switch (work_code) {
5707 case MBA_IDC_AEN: /* 0x8200 */
5708 if (ha->dpc_lp_wq)
5709 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5710 break;
5711
5712 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5713 if (!ha->flags.nic_core_reset_hdlr_active) {
5714 if (ha->dpc_hp_wq)
5715 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5716 } else
5717 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5718 "NIC Core reset is already active. Skip "
5719 "scheduling it again.\n");
5720 break;
5721 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5722 if (ha->dpc_hp_wq)
5723 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5724 break;
5725 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5726 if (ha->dpc_hp_wq)
5727 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5728 break;
5729 default:
5730 ql_log(ql_log_warn, base_vha, 0xb05f,
5731 "Unknown work-code=0x%x.\n", work_code);
5732 }
5733
5734 return;
5735 }
5736
5737 /* Work: Perform NIC Core Unrecoverable state handling */
5738 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5739 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5740 {
5741 struct qla_hw_data *ha =
5742 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5743 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5744 uint32_t dev_state = 0;
5745
5746 qla83xx_idc_lock(base_vha, 0);
5747 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5748 qla83xx_reset_ownership(base_vha);
5749 if (ha->flags.nic_core_reset_owner) {
5750 ha->flags.nic_core_reset_owner = 0;
5751 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5752 QLA8XXX_DEV_FAILED);
5753 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5754 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5755 }
5756 qla83xx_idc_unlock(base_vha, 0);
5757 }
5758
5759 /* Work: Execute IDC state handler */
5760 void
qla83xx_idc_state_handler_work(struct work_struct * work)5761 qla83xx_idc_state_handler_work(struct work_struct *work)
5762 {
5763 struct qla_hw_data *ha =
5764 container_of(work, struct qla_hw_data, idc_state_handler);
5765 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5766 uint32_t dev_state = 0;
5767
5768 qla83xx_idc_lock(base_vha, 0);
5769 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5770 if (dev_state == QLA8XXX_DEV_FAILED ||
5771 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5772 qla83xx_idc_state_handler(base_vha);
5773 qla83xx_idc_unlock(base_vha, 0);
5774 }
5775
5776 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5777 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5778 {
5779 int rval = QLA_SUCCESS;
5780 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5781 uint32_t heart_beat_counter1, heart_beat_counter2;
5782
5783 do {
5784 if (time_after(jiffies, heart_beat_wait)) {
5785 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5786 "Nic Core f/w is not alive.\n");
5787 rval = QLA_FUNCTION_FAILED;
5788 break;
5789 }
5790
5791 qla83xx_idc_lock(base_vha, 0);
5792 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5793 &heart_beat_counter1);
5794 qla83xx_idc_unlock(base_vha, 0);
5795 msleep(100);
5796 qla83xx_idc_lock(base_vha, 0);
5797 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5798 &heart_beat_counter2);
5799 qla83xx_idc_unlock(base_vha, 0);
5800 } while (heart_beat_counter1 == heart_beat_counter2);
5801
5802 return rval;
5803 }
5804
5805 /* Work: Perform NIC Core Reset handling */
5806 void
qla83xx_nic_core_reset_work(struct work_struct * work)5807 qla83xx_nic_core_reset_work(struct work_struct *work)
5808 {
5809 struct qla_hw_data *ha =
5810 container_of(work, struct qla_hw_data, nic_core_reset);
5811 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5812 uint32_t dev_state = 0;
5813
5814 if (IS_QLA2031(ha)) {
5815 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5816 ql_log(ql_log_warn, base_vha, 0xb081,
5817 "Failed to dump mctp\n");
5818 return;
5819 }
5820
5821 if (!ha->flags.nic_core_reset_hdlr_active) {
5822 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5823 qla83xx_idc_lock(base_vha, 0);
5824 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5825 &dev_state);
5826 qla83xx_idc_unlock(base_vha, 0);
5827 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5828 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5829 "Nic Core f/w is alive.\n");
5830 return;
5831 }
5832 }
5833
5834 ha->flags.nic_core_reset_hdlr_active = 1;
5835 if (qla83xx_nic_core_reset(base_vha)) {
5836 /* NIC Core reset failed. */
5837 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5838 "NIC Core reset failed.\n");
5839 }
5840 ha->flags.nic_core_reset_hdlr_active = 0;
5841 }
5842 }
5843
5844 /* Work: Handle 8200 IDC aens */
5845 void
qla83xx_service_idc_aen(struct work_struct * work)5846 qla83xx_service_idc_aen(struct work_struct *work)
5847 {
5848 struct qla_hw_data *ha =
5849 container_of(work, struct qla_hw_data, idc_aen);
5850 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5851 uint32_t dev_state, idc_control;
5852
5853 qla83xx_idc_lock(base_vha, 0);
5854 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5855 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5856 qla83xx_idc_unlock(base_vha, 0);
5857 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5858 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5859 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5860 "Application requested NIC Core Reset.\n");
5861 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5862 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5863 QLA_SUCCESS) {
5864 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5865 "Other protocol driver requested NIC Core Reset.\n");
5866 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5867 }
5868 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5869 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5870 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5871 }
5872 }
5873
5874 /*
5875 * Control the frequency of IDC lock retries
5876 */
5877 #define QLA83XX_WAIT_LOGIC_MS 100
5878
5879 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5880 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5881 {
5882 int rval;
5883 uint32_t data;
5884 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5885 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5886 struct qla_hw_data *ha = base_vha->hw;
5887
5888 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5889 "Trying force recovery of the IDC lock.\n");
5890
5891 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5892 if (rval)
5893 return rval;
5894
5895 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5896 return QLA_SUCCESS;
5897 } else {
5898 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5899 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5900 data);
5901 if (rval)
5902 return rval;
5903
5904 msleep(200);
5905
5906 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5907 &data);
5908 if (rval)
5909 return rval;
5910
5911 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5912 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5913 ~(idc_lck_rcvry_stage_mask));
5914 rval = qla83xx_wr_reg(base_vha,
5915 QLA83XX_IDC_LOCK_RECOVERY, data);
5916 if (rval)
5917 return rval;
5918
5919 /* Forcefully perform IDC UnLock */
5920 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5921 &data);
5922 if (rval)
5923 return rval;
5924 /* Clear lock-id by setting 0xff */
5925 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5926 0xff);
5927 if (rval)
5928 return rval;
5929 /* Clear lock-recovery by setting 0x0 */
5930 rval = qla83xx_wr_reg(base_vha,
5931 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5932 if (rval)
5933 return rval;
5934 } else
5935 return QLA_SUCCESS;
5936 }
5937
5938 return rval;
5939 }
5940
5941 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5942 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5943 {
5944 int rval = QLA_SUCCESS;
5945 uint32_t o_drv_lockid, n_drv_lockid;
5946 unsigned long lock_recovery_timeout;
5947
5948 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5949 retry_lockid:
5950 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5951 if (rval)
5952 goto exit;
5953
5954 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5955 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5956 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5957 return QLA_SUCCESS;
5958 else
5959 return QLA_FUNCTION_FAILED;
5960 }
5961
5962 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5963 if (rval)
5964 goto exit;
5965
5966 if (o_drv_lockid == n_drv_lockid) {
5967 msleep(QLA83XX_WAIT_LOGIC_MS);
5968 goto retry_lockid;
5969 } else
5970 return QLA_SUCCESS;
5971
5972 exit:
5973 return rval;
5974 }
5975
5976 /*
5977 * Context: task, can sleep
5978 */
5979 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5980 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5981 {
5982 uint32_t data;
5983 uint32_t lock_owner;
5984 struct qla_hw_data *ha = base_vha->hw;
5985
5986 might_sleep();
5987
5988 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5989 retry_lock:
5990 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5991 == QLA_SUCCESS) {
5992 if (data) {
5993 /* Setting lock-id to our function-number */
5994 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5995 ha->portnum);
5996 } else {
5997 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5998 &lock_owner);
5999 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6000 "Failed to acquire IDC lock, acquired by %d, "
6001 "retrying...\n", lock_owner);
6002
6003 /* Retry/Perform IDC-Lock recovery */
6004 if (qla83xx_idc_lock_recovery(base_vha)
6005 == QLA_SUCCESS) {
6006 msleep(QLA83XX_WAIT_LOGIC_MS);
6007 goto retry_lock;
6008 } else
6009 ql_log(ql_log_warn, base_vha, 0xb075,
6010 "IDC Lock recovery FAILED.\n");
6011 }
6012
6013 }
6014
6015 return;
6016 }
6017
6018 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)6019 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6020 struct purex_entry_24xx *purex)
6021 {
6022 char fwstr[16];
6023 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6024 struct port_database_24xx *pdb;
6025
6026 /* Domain Controller is always logged-out. */
6027 /* if RDP request is not from Domain Controller: */
6028 if (sid != 0xfffc01)
6029 return false;
6030
6031 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6032
6033 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
6034 if (!pdb) {
6035 ql_dbg(ql_dbg_init, vha, 0x0181,
6036 "%s: Failed allocate pdb\n", __func__);
6037 } else if (qla24xx_get_port_database(vha,
6038 le16_to_cpu(purex->nport_handle), pdb)) {
6039 ql_dbg(ql_dbg_init, vha, 0x0181,
6040 "%s: Failed get pdb sid=%x\n", __func__, sid);
6041 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6042 pdb->current_login_state != PDS_PRLI_COMPLETE) {
6043 ql_dbg(ql_dbg_init, vha, 0x0181,
6044 "%s: Port not logged in sid=%#x\n", __func__, sid);
6045 } else {
6046 /* RDP request is from logged in port */
6047 kfree(pdb);
6048 return false;
6049 }
6050 kfree(pdb);
6051
6052 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6053 fwstr[strcspn(fwstr, " ")] = 0;
6054 /* if FW version allows RDP response length upto 2048 bytes: */
6055 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6056 return false;
6057
6058 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6059
6060 /* RDP response length is to be reduced to maximum 256 bytes */
6061 return true;
6062 }
6063
6064 /*
6065 * Function Name: qla24xx_process_purex_iocb
6066 *
6067 * Description:
6068 * Prepare a RDP response and send to Fabric switch
6069 *
6070 * PARAMETERS:
6071 * vha: SCSI qla host
6072 * purex: RDP request received by HBA
6073 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)6074 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6075 struct purex_item *item)
6076 {
6077 struct qla_hw_data *ha = vha->hw;
6078 struct purex_entry_24xx *purex =
6079 (struct purex_entry_24xx *)&item->iocb;
6080 dma_addr_t rsp_els_dma;
6081 dma_addr_t rsp_payload_dma;
6082 dma_addr_t stat_dma;
6083 dma_addr_t sfp_dma;
6084 struct els_entry_24xx *rsp_els = NULL;
6085 struct rdp_rsp_payload *rsp_payload = NULL;
6086 struct link_statistics *stat = NULL;
6087 uint8_t *sfp = NULL;
6088 uint16_t sfp_flags = 0;
6089 uint rsp_payload_length = sizeof(*rsp_payload);
6090 int rval;
6091
6092 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6093 "%s: Enter\n", __func__);
6094
6095 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6096 "-------- ELS REQ -------\n");
6097 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6098 purex, sizeof(*purex));
6099
6100 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6101 rsp_payload_length =
6102 offsetof(typeof(*rsp_payload), optical_elmt_desc);
6103 ql_dbg(ql_dbg_init, vha, 0x0181,
6104 "Reducing RSP payload length to %u bytes...\n",
6105 rsp_payload_length);
6106 }
6107
6108 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6109 &rsp_els_dma, GFP_KERNEL);
6110 if (!rsp_els) {
6111 ql_log(ql_log_warn, vha, 0x0183,
6112 "Failed allocate dma buffer ELS RSP.\n");
6113 goto dealloc;
6114 }
6115
6116 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6117 &rsp_payload_dma, GFP_KERNEL);
6118 if (!rsp_payload) {
6119 ql_log(ql_log_warn, vha, 0x0184,
6120 "Failed allocate dma buffer ELS RSP payload.\n");
6121 goto dealloc;
6122 }
6123
6124 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6125 &sfp_dma, GFP_KERNEL);
6126
6127 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6128 &stat_dma, GFP_KERNEL);
6129
6130 /* Prepare Response IOCB */
6131 rsp_els->entry_type = ELS_IOCB_TYPE;
6132 rsp_els->entry_count = 1;
6133 rsp_els->sys_define = 0;
6134 rsp_els->entry_status = 0;
6135 rsp_els->handle = 0;
6136 rsp_els->nport_handle = purex->nport_handle;
6137 rsp_els->tx_dsd_count = cpu_to_le16(1);
6138 rsp_els->vp_index = purex->vp_idx;
6139 rsp_els->sof_type = EST_SOFI3;
6140 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6141 rsp_els->rx_dsd_count = 0;
6142 rsp_els->opcode = purex->els_frame_payload[0];
6143
6144 rsp_els->d_id[0] = purex->s_id[0];
6145 rsp_els->d_id[1] = purex->s_id[1];
6146 rsp_els->d_id[2] = purex->s_id[2];
6147
6148 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6149 rsp_els->rx_byte_count = 0;
6150 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6151
6152 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6153 rsp_els->tx_len = rsp_els->tx_byte_count;
6154
6155 rsp_els->rx_address = 0;
6156 rsp_els->rx_len = 0;
6157
6158 /* Prepare Response Payload */
6159 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6160 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6161 sizeof(rsp_payload->hdr));
6162
6163 /* Link service Request Info Descriptor */
6164 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6165 rsp_payload->ls_req_info_desc.desc_len =
6166 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6167 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6168 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6169
6170 /* Link service Request Info Descriptor 2 */
6171 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6172 rsp_payload->ls_req_info_desc2.desc_len =
6173 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6174 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6175 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6176
6177
6178 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6179 rsp_payload->sfp_diag_desc.desc_len =
6180 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6181
6182 if (sfp) {
6183 /* SFP Flags */
6184 memset(sfp, 0, SFP_RTDI_LEN);
6185 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6186 if (!rval) {
6187 /* SFP Flags bits 3-0: Port Tx Laser Type */
6188 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6189 sfp_flags |= BIT_0; /* short wave */
6190 else if (sfp[0] & BIT_1)
6191 sfp_flags |= BIT_1; /* long wave 1310nm */
6192 else if (sfp[1] & BIT_4)
6193 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6194 }
6195
6196 /* SFP Type */
6197 memset(sfp, 0, SFP_RTDI_LEN);
6198 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6199 if (!rval) {
6200 sfp_flags |= BIT_4; /* optical */
6201 if (sfp[0] == 0x3)
6202 sfp_flags |= BIT_6; /* sfp+ */
6203 }
6204
6205 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6206
6207 /* SFP Diagnostics */
6208 memset(sfp, 0, SFP_RTDI_LEN);
6209 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6210 if (!rval) {
6211 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6212 rsp_payload->sfp_diag_desc.temperature = trx[0];
6213 rsp_payload->sfp_diag_desc.vcc = trx[1];
6214 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6215 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6216 rsp_payload->sfp_diag_desc.rx_power = trx[4];
6217 }
6218 }
6219
6220 /* Port Speed Descriptor */
6221 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6222 rsp_payload->port_speed_desc.desc_len =
6223 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6224 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6225 qla25xx_fdmi_port_speed_capability(ha));
6226 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6227 qla25xx_fdmi_port_speed_currently(ha));
6228
6229 /* Link Error Status Descriptor */
6230 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6231 rsp_payload->ls_err_desc.desc_len =
6232 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6233
6234 if (stat) {
6235 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6236 if (!rval) {
6237 rsp_payload->ls_err_desc.link_fail_cnt =
6238 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6239 rsp_payload->ls_err_desc.loss_sync_cnt =
6240 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6241 rsp_payload->ls_err_desc.loss_sig_cnt =
6242 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6243 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6244 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6245 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6246 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6247 rsp_payload->ls_err_desc.inval_crc_cnt =
6248 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6249 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6250 }
6251 }
6252
6253 /* Portname Descriptor */
6254 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6255 rsp_payload->port_name_diag_desc.desc_len =
6256 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6257 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6258 vha->node_name,
6259 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6260 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6261 vha->port_name,
6262 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6263
6264 /* F-Port Portname Descriptor */
6265 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6266 rsp_payload->port_name_direct_desc.desc_len =
6267 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6268 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6269 vha->fabric_node_name,
6270 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6271 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6272 vha->fabric_port_name,
6273 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6274
6275 /* Bufer Credit Descriptor */
6276 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6277 rsp_payload->buffer_credit_desc.desc_len =
6278 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6279 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6280 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6281 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6282
6283 if (ha->flags.plogi_template_valid) {
6284 uint32_t tmp =
6285 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6286 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6287 }
6288
6289 if (rsp_payload_length < sizeof(*rsp_payload))
6290 goto send;
6291
6292 /* Optical Element Descriptor, Temperature */
6293 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6294 rsp_payload->optical_elmt_desc[0].desc_len =
6295 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6296 /* Optical Element Descriptor, Voltage */
6297 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6298 rsp_payload->optical_elmt_desc[1].desc_len =
6299 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6300 /* Optical Element Descriptor, Tx Bias Current */
6301 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6302 rsp_payload->optical_elmt_desc[2].desc_len =
6303 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6304 /* Optical Element Descriptor, Tx Power */
6305 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6306 rsp_payload->optical_elmt_desc[3].desc_len =
6307 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6308 /* Optical Element Descriptor, Rx Power */
6309 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6310 rsp_payload->optical_elmt_desc[4].desc_len =
6311 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6312
6313 if (sfp) {
6314 memset(sfp, 0, SFP_RTDI_LEN);
6315 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6316 if (!rval) {
6317 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6318
6319 /* Optical Element Descriptor, Temperature */
6320 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6321 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6322 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6323 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6324 rsp_payload->optical_elmt_desc[0].element_flags =
6325 cpu_to_be32(1 << 28);
6326
6327 /* Optical Element Descriptor, Voltage */
6328 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6329 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6330 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6331 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6332 rsp_payload->optical_elmt_desc[1].element_flags =
6333 cpu_to_be32(2 << 28);
6334
6335 /* Optical Element Descriptor, Tx Bias Current */
6336 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6337 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6338 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6339 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6340 rsp_payload->optical_elmt_desc[2].element_flags =
6341 cpu_to_be32(3 << 28);
6342
6343 /* Optical Element Descriptor, Tx Power */
6344 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6345 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6346 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6347 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6348 rsp_payload->optical_elmt_desc[3].element_flags =
6349 cpu_to_be32(4 << 28);
6350
6351 /* Optical Element Descriptor, Rx Power */
6352 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6353 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6354 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6355 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6356 rsp_payload->optical_elmt_desc[4].element_flags =
6357 cpu_to_be32(5 << 28);
6358 }
6359
6360 memset(sfp, 0, SFP_RTDI_LEN);
6361 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6362 if (!rval) {
6363 /* Temperature high/low alarm/warning */
6364 rsp_payload->optical_elmt_desc[0].element_flags |=
6365 cpu_to_be32(
6366 (sfp[0] >> 7 & 1) << 3 |
6367 (sfp[0] >> 6 & 1) << 2 |
6368 (sfp[4] >> 7 & 1) << 1 |
6369 (sfp[4] >> 6 & 1) << 0);
6370
6371 /* Voltage high/low alarm/warning */
6372 rsp_payload->optical_elmt_desc[1].element_flags |=
6373 cpu_to_be32(
6374 (sfp[0] >> 5 & 1) << 3 |
6375 (sfp[0] >> 4 & 1) << 2 |
6376 (sfp[4] >> 5 & 1) << 1 |
6377 (sfp[4] >> 4 & 1) << 0);
6378
6379 /* Tx Bias Current high/low alarm/warning */
6380 rsp_payload->optical_elmt_desc[2].element_flags |=
6381 cpu_to_be32(
6382 (sfp[0] >> 3 & 1) << 3 |
6383 (sfp[0] >> 2 & 1) << 2 |
6384 (sfp[4] >> 3 & 1) << 1 |
6385 (sfp[4] >> 2 & 1) << 0);
6386
6387 /* Tx Power high/low alarm/warning */
6388 rsp_payload->optical_elmt_desc[3].element_flags |=
6389 cpu_to_be32(
6390 (sfp[0] >> 1 & 1) << 3 |
6391 (sfp[0] >> 0 & 1) << 2 |
6392 (sfp[4] >> 1 & 1) << 1 |
6393 (sfp[4] >> 0 & 1) << 0);
6394
6395 /* Rx Power high/low alarm/warning */
6396 rsp_payload->optical_elmt_desc[4].element_flags |=
6397 cpu_to_be32(
6398 (sfp[1] >> 7 & 1) << 3 |
6399 (sfp[1] >> 6 & 1) << 2 |
6400 (sfp[5] >> 7 & 1) << 1 |
6401 (sfp[5] >> 6 & 1) << 0);
6402 }
6403 }
6404
6405 /* Optical Product Data Descriptor */
6406 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6407 rsp_payload->optical_prod_desc.desc_len =
6408 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6409
6410 if (sfp) {
6411 memset(sfp, 0, SFP_RTDI_LEN);
6412 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6413 if (!rval) {
6414 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6415 sfp + 0,
6416 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6417 memcpy(rsp_payload->optical_prod_desc.part_number,
6418 sfp + 20,
6419 sizeof(rsp_payload->optical_prod_desc.part_number));
6420 memcpy(rsp_payload->optical_prod_desc.revision,
6421 sfp + 36,
6422 sizeof(rsp_payload->optical_prod_desc.revision));
6423 memcpy(rsp_payload->optical_prod_desc.serial_number,
6424 sfp + 48,
6425 sizeof(rsp_payload->optical_prod_desc.serial_number));
6426 }
6427
6428 memset(sfp, 0, SFP_RTDI_LEN);
6429 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6430 if (!rval) {
6431 memcpy(rsp_payload->optical_prod_desc.date,
6432 sfp + 0,
6433 sizeof(rsp_payload->optical_prod_desc.date));
6434 }
6435 }
6436
6437 send:
6438 ql_dbg(ql_dbg_init, vha, 0x0183,
6439 "Sending ELS Response to RDP Request...\n");
6440 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6441 "-------- ELS RSP -------\n");
6442 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6443 rsp_els, sizeof(*rsp_els));
6444 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6445 "-------- ELS RSP PAYLOAD -------\n");
6446 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6447 rsp_payload, rsp_payload_length);
6448
6449 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6450
6451 if (rval) {
6452 ql_log(ql_log_warn, vha, 0x0188,
6453 "%s: iocb failed to execute -> %x\n", __func__, rval);
6454 } else if (rsp_els->comp_status) {
6455 ql_log(ql_log_warn, vha, 0x0189,
6456 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6457 __func__, rsp_els->comp_status,
6458 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6459 } else {
6460 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6461 }
6462
6463 dealloc:
6464 if (stat)
6465 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6466 stat, stat_dma);
6467 if (sfp)
6468 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6469 sfp, sfp_dma);
6470 if (rsp_payload)
6471 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6472 rsp_payload, rsp_payload_dma);
6473 if (rsp_els)
6474 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6475 rsp_els, rsp_els_dma);
6476 }
6477
6478 void
qla24xx_free_purex_item(struct purex_item * item)6479 qla24xx_free_purex_item(struct purex_item *item)
6480 {
6481 if (item == &item->vha->default_item)
6482 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6483 else
6484 kfree(item);
6485 }
6486
qla24xx_process_purex_list(struct purex_list * list)6487 void qla24xx_process_purex_list(struct purex_list *list)
6488 {
6489 struct list_head head = LIST_HEAD_INIT(head);
6490 struct purex_item *item, *next;
6491 ulong flags;
6492
6493 spin_lock_irqsave(&list->lock, flags);
6494 list_splice_init(&list->head, &head);
6495 spin_unlock_irqrestore(&list->lock, flags);
6496
6497 list_for_each_entry_safe(item, next, &head, list) {
6498 list_del(&item->list);
6499 item->process_item(item->vha, item);
6500 qla24xx_free_purex_item(item);
6501 }
6502 }
6503
6504 /*
6505 * Context: task, can sleep
6506 */
6507 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6508 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6509 {
6510 #if 0
6511 uint16_t options = (requester_id << 15) | BIT_7;
6512 #endif
6513 uint16_t retry;
6514 uint32_t data;
6515 struct qla_hw_data *ha = base_vha->hw;
6516
6517 might_sleep();
6518
6519 /* IDC-unlock implementation using driver-unlock/lock-id
6520 * remote registers
6521 */
6522 retry = 0;
6523 retry_unlock:
6524 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6525 == QLA_SUCCESS) {
6526 if (data == ha->portnum) {
6527 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6528 /* Clearing lock-id by setting 0xff */
6529 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6530 } else if (retry < 10) {
6531 /* SV: XXX: IDC unlock retrying needed here? */
6532
6533 /* Retry for IDC-unlock */
6534 msleep(QLA83XX_WAIT_LOGIC_MS);
6535 retry++;
6536 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6537 "Failed to release IDC lock, retrying=%d\n", retry);
6538 goto retry_unlock;
6539 }
6540 } else if (retry < 10) {
6541 /* Retry for IDC-unlock */
6542 msleep(QLA83XX_WAIT_LOGIC_MS);
6543 retry++;
6544 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6545 "Failed to read drv-lockid, retrying=%d\n", retry);
6546 goto retry_unlock;
6547 }
6548
6549 return;
6550
6551 #if 0
6552 /* XXX: IDC-unlock implementation using access-control mbx */
6553 retry = 0;
6554 retry_unlock2:
6555 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6556 if (retry < 10) {
6557 /* Retry for IDC-unlock */
6558 msleep(QLA83XX_WAIT_LOGIC_MS);
6559 retry++;
6560 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6561 "Failed to release IDC lock, retrying=%d\n", retry);
6562 goto retry_unlock2;
6563 }
6564 }
6565
6566 return;
6567 #endif
6568 }
6569
6570 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6571 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6572 {
6573 int rval = QLA_SUCCESS;
6574 struct qla_hw_data *ha = vha->hw;
6575 uint32_t drv_presence;
6576
6577 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6578 if (rval == QLA_SUCCESS) {
6579 drv_presence |= (1 << ha->portnum);
6580 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6581 drv_presence);
6582 }
6583
6584 return rval;
6585 }
6586
6587 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6588 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6589 {
6590 int rval = QLA_SUCCESS;
6591
6592 qla83xx_idc_lock(vha, 0);
6593 rval = __qla83xx_set_drv_presence(vha);
6594 qla83xx_idc_unlock(vha, 0);
6595
6596 return rval;
6597 }
6598
6599 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6600 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6601 {
6602 int rval = QLA_SUCCESS;
6603 struct qla_hw_data *ha = vha->hw;
6604 uint32_t drv_presence;
6605
6606 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6607 if (rval == QLA_SUCCESS) {
6608 drv_presence &= ~(1 << ha->portnum);
6609 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6610 drv_presence);
6611 }
6612
6613 return rval;
6614 }
6615
6616 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6617 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6618 {
6619 int rval = QLA_SUCCESS;
6620
6621 qla83xx_idc_lock(vha, 0);
6622 rval = __qla83xx_clear_drv_presence(vha);
6623 qla83xx_idc_unlock(vha, 0);
6624
6625 return rval;
6626 }
6627
6628 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6629 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6630 {
6631 struct qla_hw_data *ha = vha->hw;
6632 uint32_t drv_ack, drv_presence;
6633 unsigned long ack_timeout;
6634
6635 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6636 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6637 while (1) {
6638 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6639 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6640 if ((drv_ack & drv_presence) == drv_presence)
6641 break;
6642
6643 if (time_after_eq(jiffies, ack_timeout)) {
6644 ql_log(ql_log_warn, vha, 0xb067,
6645 "RESET ACK TIMEOUT! drv_presence=0x%x "
6646 "drv_ack=0x%x\n", drv_presence, drv_ack);
6647 /*
6648 * The function(s) which did not ack in time are forced
6649 * to withdraw any further participation in the IDC
6650 * reset.
6651 */
6652 if (drv_ack != drv_presence)
6653 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6654 drv_ack);
6655 break;
6656 }
6657
6658 qla83xx_idc_unlock(vha, 0);
6659 msleep(1000);
6660 qla83xx_idc_lock(vha, 0);
6661 }
6662
6663 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6664 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6665 }
6666
6667 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6668 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6669 {
6670 int rval = QLA_SUCCESS;
6671 uint32_t idc_control;
6672
6673 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6674 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6675
6676 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6677 __qla83xx_get_idc_control(vha, &idc_control);
6678 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6679 __qla83xx_set_idc_control(vha, 0);
6680
6681 qla83xx_idc_unlock(vha, 0);
6682 rval = qla83xx_restart_nic_firmware(vha);
6683 qla83xx_idc_lock(vha, 0);
6684
6685 if (rval != QLA_SUCCESS) {
6686 ql_log(ql_log_fatal, vha, 0xb06a,
6687 "Failed to restart NIC f/w.\n");
6688 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6689 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6690 } else {
6691 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6692 "Success in restarting nic f/w.\n");
6693 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6694 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6695 }
6696
6697 return rval;
6698 }
6699
6700 /* Assumes idc_lock always held on entry */
6701 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6702 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6703 {
6704 struct qla_hw_data *ha = base_vha->hw;
6705 int rval = QLA_SUCCESS;
6706 unsigned long dev_init_timeout;
6707 uint32_t dev_state;
6708
6709 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6710 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6711
6712 while (1) {
6713
6714 if (time_after_eq(jiffies, dev_init_timeout)) {
6715 ql_log(ql_log_warn, base_vha, 0xb06e,
6716 "Initialization TIMEOUT!\n");
6717 /* Init timeout. Disable further NIC Core
6718 * communication.
6719 */
6720 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6721 QLA8XXX_DEV_FAILED);
6722 ql_log(ql_log_info, base_vha, 0xb06f,
6723 "HW State: FAILED.\n");
6724 }
6725
6726 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6727 switch (dev_state) {
6728 case QLA8XXX_DEV_READY:
6729 if (ha->flags.nic_core_reset_owner)
6730 qla83xx_idc_audit(base_vha,
6731 IDC_AUDIT_COMPLETION);
6732 ha->flags.nic_core_reset_owner = 0;
6733 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6734 "Reset_owner reset by 0x%x.\n",
6735 ha->portnum);
6736 goto exit;
6737 case QLA8XXX_DEV_COLD:
6738 if (ha->flags.nic_core_reset_owner)
6739 rval = qla83xx_device_bootstrap(base_vha);
6740 else {
6741 /* Wait for AEN to change device-state */
6742 qla83xx_idc_unlock(base_vha, 0);
6743 msleep(1000);
6744 qla83xx_idc_lock(base_vha, 0);
6745 }
6746 break;
6747 case QLA8XXX_DEV_INITIALIZING:
6748 /* Wait for AEN to change device-state */
6749 qla83xx_idc_unlock(base_vha, 0);
6750 msleep(1000);
6751 qla83xx_idc_lock(base_vha, 0);
6752 break;
6753 case QLA8XXX_DEV_NEED_RESET:
6754 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6755 qla83xx_need_reset_handler(base_vha);
6756 else {
6757 /* Wait for AEN to change device-state */
6758 qla83xx_idc_unlock(base_vha, 0);
6759 msleep(1000);
6760 qla83xx_idc_lock(base_vha, 0);
6761 }
6762 /* reset timeout value after need reset handler */
6763 dev_init_timeout = jiffies +
6764 (ha->fcoe_dev_init_timeout * HZ);
6765 break;
6766 case QLA8XXX_DEV_NEED_QUIESCENT:
6767 /* XXX: DEBUG for now */
6768 qla83xx_idc_unlock(base_vha, 0);
6769 msleep(1000);
6770 qla83xx_idc_lock(base_vha, 0);
6771 break;
6772 case QLA8XXX_DEV_QUIESCENT:
6773 /* XXX: DEBUG for now */
6774 if (ha->flags.quiesce_owner)
6775 goto exit;
6776
6777 qla83xx_idc_unlock(base_vha, 0);
6778 msleep(1000);
6779 qla83xx_idc_lock(base_vha, 0);
6780 dev_init_timeout = jiffies +
6781 (ha->fcoe_dev_init_timeout * HZ);
6782 break;
6783 case QLA8XXX_DEV_FAILED:
6784 if (ha->flags.nic_core_reset_owner)
6785 qla83xx_idc_audit(base_vha,
6786 IDC_AUDIT_COMPLETION);
6787 ha->flags.nic_core_reset_owner = 0;
6788 __qla83xx_clear_drv_presence(base_vha);
6789 qla83xx_idc_unlock(base_vha, 0);
6790 qla8xxx_dev_failed_handler(base_vha);
6791 rval = QLA_FUNCTION_FAILED;
6792 qla83xx_idc_lock(base_vha, 0);
6793 goto exit;
6794 case QLA8XXX_BAD_VALUE:
6795 qla83xx_idc_unlock(base_vha, 0);
6796 msleep(1000);
6797 qla83xx_idc_lock(base_vha, 0);
6798 break;
6799 default:
6800 ql_log(ql_log_warn, base_vha, 0xb071,
6801 "Unknown Device State: %x.\n", dev_state);
6802 qla83xx_idc_unlock(base_vha, 0);
6803 qla8xxx_dev_failed_handler(base_vha);
6804 rval = QLA_FUNCTION_FAILED;
6805 qla83xx_idc_lock(base_vha, 0);
6806 goto exit;
6807 }
6808 }
6809
6810 exit:
6811 return rval;
6812 }
6813
6814 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6815 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6816 {
6817 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6818 board_disable);
6819 struct pci_dev *pdev = ha->pdev;
6820 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6821
6822 ql_log(ql_log_warn, base_vha, 0x015b,
6823 "Disabling adapter.\n");
6824
6825 if (!atomic_read(&pdev->enable_cnt)) {
6826 ql_log(ql_log_info, base_vha, 0xfffc,
6827 "PCI device disabled, no action req for PCI error=%lx\n",
6828 base_vha->pci_flags);
6829 return;
6830 }
6831
6832 /*
6833 * if UNLOADING flag is already set, then continue unload,
6834 * where it was set first.
6835 */
6836 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6837 return;
6838
6839 qla2x00_wait_for_sess_deletion(base_vha);
6840
6841 qla2x00_delete_all_vps(ha, base_vha);
6842
6843 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6844
6845 qla2x00_dfs_remove(base_vha);
6846
6847 qla84xx_put_chip(base_vha);
6848
6849 if (base_vha->timer_active)
6850 qla2x00_stop_timer(base_vha);
6851
6852 base_vha->flags.online = 0;
6853
6854 qla2x00_destroy_deferred_work(ha);
6855
6856 /*
6857 * Do not try to stop beacon blink as it will issue a mailbox
6858 * command.
6859 */
6860 qla2x00_free_sysfs_attr(base_vha, false);
6861
6862 fc_remove_host(base_vha->host);
6863
6864 scsi_remove_host(base_vha->host);
6865
6866 base_vha->flags.init_done = 0;
6867 qla25xx_delete_queues(base_vha);
6868 qla2x00_free_fcports(base_vha);
6869 qla2x00_free_irqs(base_vha);
6870 qla2x00_mem_free(ha);
6871 qla82xx_md_free(base_vha);
6872 qla2x00_free_queues(ha);
6873
6874 qla2x00_unmap_iobases(ha);
6875
6876 pci_release_selected_regions(ha->pdev, ha->bars);
6877 pci_disable_device(pdev);
6878
6879 /*
6880 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6881 */
6882 }
6883
6884 /**************************************************************************
6885 * qla2x00_do_dpc
6886 * This kernel thread is a task that is schedule by the interrupt handler
6887 * to perform the background processing for interrupts.
6888 *
6889 * Notes:
6890 * This task always run in the context of a kernel thread. It
6891 * is kick-off by the driver's detect code and starts up
6892 * up one per adapter. It immediately goes to sleep and waits for
6893 * some fibre event. When either the interrupt handler or
6894 * the timer routine detects a event it will one of the task
6895 * bits then wake us up.
6896 **************************************************************************/
6897 static int
qla2x00_do_dpc(void * data)6898 qla2x00_do_dpc(void *data)
6899 {
6900 scsi_qla_host_t *base_vha;
6901 struct qla_hw_data *ha;
6902 uint32_t online;
6903 struct qla_qpair *qpair;
6904
6905 ha = (struct qla_hw_data *)data;
6906 base_vha = pci_get_drvdata(ha->pdev);
6907
6908 set_user_nice(current, MIN_NICE);
6909
6910 set_current_state(TASK_INTERRUPTIBLE);
6911 while (!kthread_should_stop()) {
6912 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6913 "DPC handler sleeping.\n");
6914
6915 schedule();
6916
6917 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6918 qla_pci_set_eeh_busy(base_vha);
6919
6920 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6921 goto end_loop;
6922
6923 if (ha->flags.eeh_busy) {
6924 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6925 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6926 goto end_loop;
6927 }
6928
6929 ha->dpc_active = 1;
6930
6931 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6932 "DPC handler waking up, dpc_flags=0x%lx.\n",
6933 base_vha->dpc_flags);
6934
6935 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6936 break;
6937
6938 if (IS_P3P_TYPE(ha)) {
6939 if (IS_QLA8044(ha)) {
6940 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6941 &base_vha->dpc_flags)) {
6942 qla8044_idc_lock(ha);
6943 qla8044_wr_direct(base_vha,
6944 QLA8044_CRB_DEV_STATE_INDEX,
6945 QLA8XXX_DEV_FAILED);
6946 qla8044_idc_unlock(ha);
6947 ql_log(ql_log_info, base_vha, 0x4004,
6948 "HW State: FAILED.\n");
6949 qla8044_device_state_handler(base_vha);
6950 continue;
6951 }
6952
6953 } else {
6954 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6955 &base_vha->dpc_flags)) {
6956 qla82xx_idc_lock(ha);
6957 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6958 QLA8XXX_DEV_FAILED);
6959 qla82xx_idc_unlock(ha);
6960 ql_log(ql_log_info, base_vha, 0x0151,
6961 "HW State: FAILED.\n");
6962 qla82xx_device_state_handler(base_vha);
6963 continue;
6964 }
6965 }
6966
6967 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6968 &base_vha->dpc_flags)) {
6969
6970 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6971 "FCoE context reset scheduled.\n");
6972 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6973 &base_vha->dpc_flags))) {
6974 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6975 /* FCoE-ctx reset failed.
6976 * Escalate to chip-reset
6977 */
6978 set_bit(ISP_ABORT_NEEDED,
6979 &base_vha->dpc_flags);
6980 }
6981 clear_bit(ABORT_ISP_ACTIVE,
6982 &base_vha->dpc_flags);
6983 }
6984
6985 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6986 "FCoE context reset end.\n");
6987 }
6988 } else if (IS_QLAFX00(ha)) {
6989 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6990 &base_vha->dpc_flags)) {
6991 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6992 "Firmware Reset Recovery\n");
6993 if (qlafx00_reset_initialize(base_vha)) {
6994 /* Failed. Abort isp later. */
6995 if (!test_bit(UNLOADING,
6996 &base_vha->dpc_flags)) {
6997 set_bit(ISP_UNRECOVERABLE,
6998 &base_vha->dpc_flags);
6999 ql_dbg(ql_dbg_dpc, base_vha,
7000 0x4021,
7001 "Reset Recovery Failed\n");
7002 }
7003 }
7004 }
7005
7006 if (test_and_clear_bit(FX00_TARGET_SCAN,
7007 &base_vha->dpc_flags)) {
7008 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
7009 "ISPFx00 Target Scan scheduled\n");
7010 if (qlafx00_rescan_isp(base_vha)) {
7011 if (!test_bit(UNLOADING,
7012 &base_vha->dpc_flags))
7013 set_bit(ISP_UNRECOVERABLE,
7014 &base_vha->dpc_flags);
7015 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7016 "ISPFx00 Target Scan Failed\n");
7017 }
7018 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7019 "ISPFx00 Target Scan End\n");
7020 }
7021 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7022 &base_vha->dpc_flags)) {
7023 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7024 "ISPFx00 Host Info resend scheduled\n");
7025 qlafx00_fx_disc(base_vha,
7026 &base_vha->hw->mr.fcport,
7027 FXDISC_REG_HOST_INFO);
7028 }
7029 }
7030
7031 if (test_and_clear_bit(DETECT_SFP_CHANGE,
7032 &base_vha->dpc_flags)) {
7033 /* Semantic:
7034 * - NO-OP -- await next ISP-ABORT. Preferred method
7035 * to minimize disruptions that will occur
7036 * when a forced chip-reset occurs.
7037 * - Force -- ISP-ABORT scheduled.
7038 */
7039 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7040 }
7041
7042 if (test_and_clear_bit
7043 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7044 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7045 bool do_reset = true;
7046
7047 switch (base_vha->qlini_mode) {
7048 case QLA2XXX_INI_MODE_ENABLED:
7049 break;
7050 case QLA2XXX_INI_MODE_DISABLED:
7051 if (!qla_tgt_mode_enabled(base_vha) &&
7052 !ha->flags.fw_started)
7053 do_reset = false;
7054 break;
7055 case QLA2XXX_INI_MODE_DUAL:
7056 if (!qla_dual_mode_enabled(base_vha) &&
7057 !ha->flags.fw_started)
7058 do_reset = false;
7059 break;
7060 default:
7061 break;
7062 }
7063
7064 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7065 &base_vha->dpc_flags))) {
7066 base_vha->flags.online = 1;
7067 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7068 "ISP abort scheduled.\n");
7069 if (ha->isp_ops->abort_isp(base_vha)) {
7070 /* failed. retry later */
7071 set_bit(ISP_ABORT_NEEDED,
7072 &base_vha->dpc_flags);
7073 }
7074 clear_bit(ABORT_ISP_ACTIVE,
7075 &base_vha->dpc_flags);
7076 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7077 "ISP abort end.\n");
7078 }
7079 }
7080
7081 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7082 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7083 qla24xx_process_purex_list
7084 (&base_vha->purex_list);
7085 clear_bit(PROCESS_PUREX_IOCB,
7086 &base_vha->dpc_flags);
7087 }
7088 }
7089
7090 if (IS_QLAFX00(ha))
7091 goto loop_resync_check;
7092
7093 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7094 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7095 "Quiescence mode scheduled.\n");
7096 if (IS_P3P_TYPE(ha)) {
7097 if (IS_QLA82XX(ha))
7098 qla82xx_device_state_handler(base_vha);
7099 if (IS_QLA8044(ha))
7100 qla8044_device_state_handler(base_vha);
7101 clear_bit(ISP_QUIESCE_NEEDED,
7102 &base_vha->dpc_flags);
7103 if (!ha->flags.quiesce_owner) {
7104 qla2x00_perform_loop_resync(base_vha);
7105 if (IS_QLA82XX(ha)) {
7106 qla82xx_idc_lock(ha);
7107 qla82xx_clear_qsnt_ready(
7108 base_vha);
7109 qla82xx_idc_unlock(ha);
7110 } else if (IS_QLA8044(ha)) {
7111 qla8044_idc_lock(ha);
7112 qla8044_clear_qsnt_ready(
7113 base_vha);
7114 qla8044_idc_unlock(ha);
7115 }
7116 }
7117 } else {
7118 clear_bit(ISP_QUIESCE_NEEDED,
7119 &base_vha->dpc_flags);
7120 qla2x00_quiesce_io(base_vha);
7121 }
7122 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7123 "Quiescence mode end.\n");
7124 }
7125
7126 if (test_and_clear_bit(RESET_MARKER_NEEDED,
7127 &base_vha->dpc_flags) &&
7128 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7129
7130 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7131 "Reset marker scheduled.\n");
7132 qla2x00_rst_aen(base_vha);
7133 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7134 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7135 "Reset marker end.\n");
7136 }
7137
7138 /* Retry each device up to login retry count */
7139 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7140 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7141 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7142
7143 if (!base_vha->relogin_jif ||
7144 time_after_eq(jiffies, base_vha->relogin_jif)) {
7145 base_vha->relogin_jif = jiffies + HZ;
7146 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7147
7148 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7149 "Relogin scheduled.\n");
7150 qla24xx_post_relogin_work(base_vha);
7151 }
7152 }
7153 loop_resync_check:
7154 if (!qla2x00_reset_active(base_vha) &&
7155 test_and_clear_bit(LOOP_RESYNC_NEEDED,
7156 &base_vha->dpc_flags)) {
7157 /*
7158 * Allow abort_isp to complete before moving on to scanning.
7159 */
7160 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7161 "Loop resync scheduled.\n");
7162
7163 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7164 &base_vha->dpc_flags))) {
7165
7166 qla2x00_loop_resync(base_vha);
7167
7168 clear_bit(LOOP_RESYNC_ACTIVE,
7169 &base_vha->dpc_flags);
7170 }
7171
7172 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7173 "Loop resync end.\n");
7174 }
7175
7176 if (IS_QLAFX00(ha))
7177 goto intr_on_check;
7178
7179 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7180 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7181 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7182 qla2xxx_flash_npiv_conf(base_vha);
7183 }
7184
7185 intr_on_check:
7186 if (!ha->interrupts_on)
7187 ha->isp_ops->enable_intrs(ha);
7188
7189 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7190 &base_vha->dpc_flags)) {
7191 if (ha->beacon_blink_led == 1)
7192 ha->isp_ops->beacon_blink(base_vha);
7193 }
7194
7195 /* qpair online check */
7196 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7197 &base_vha->dpc_flags)) {
7198 if (ha->flags.eeh_busy ||
7199 ha->flags.pci_channel_io_perm_failure)
7200 online = 0;
7201 else
7202 online = 1;
7203
7204 mutex_lock(&ha->mq_lock);
7205 list_for_each_entry(qpair, &base_vha->qp_list,
7206 qp_list_elem)
7207 qpair->online = online;
7208 mutex_unlock(&ha->mq_lock);
7209 }
7210
7211 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7212 &base_vha->dpc_flags)) {
7213 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7214
7215 if (threshold > ha->orig_fw_xcb_count)
7216 threshold = ha->orig_fw_xcb_count;
7217
7218 ql_log(ql_log_info, base_vha, 0xffffff,
7219 "SET ZIO Activity exchange threshold to %d.\n",
7220 threshold);
7221 if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7222 ql_log(ql_log_info, base_vha, 0xffffff,
7223 "Unable to SET ZIO Activity exchange threshold to %d.\n",
7224 threshold);
7225 }
7226 }
7227
7228 if (!IS_QLAFX00(ha))
7229 qla2x00_do_dpc_all_vps(base_vha);
7230
7231 if (test_and_clear_bit(N2N_LINK_RESET,
7232 &base_vha->dpc_flags)) {
7233 qla2x00_lip_reset(base_vha);
7234 }
7235
7236 ha->dpc_active = 0;
7237 end_loop:
7238 set_current_state(TASK_INTERRUPTIBLE);
7239 } /* End of while(1) */
7240 __set_current_state(TASK_RUNNING);
7241
7242 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7243 "DPC handler exiting.\n");
7244
7245 /*
7246 * Make sure that nobody tries to wake us up again.
7247 */
7248 ha->dpc_active = 0;
7249
7250 /* Cleanup any residual CTX SRBs. */
7251 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7252
7253 return 0;
7254 }
7255
7256 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7257 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7258 {
7259 struct qla_hw_data *ha = vha->hw;
7260 struct task_struct *t = ha->dpc_thread;
7261
7262 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7263 wake_up_process(t);
7264 }
7265
7266 /*
7267 * qla2x00_rst_aen
7268 * Processes asynchronous reset.
7269 *
7270 * Input:
7271 * ha = adapter block pointer.
7272 */
7273 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7274 qla2x00_rst_aen(scsi_qla_host_t *vha)
7275 {
7276 if (vha->flags.online && !vha->flags.reset_active &&
7277 !atomic_read(&vha->loop_down_timer) &&
7278 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7279 do {
7280 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7281
7282 /*
7283 * Issue marker command only when we are going to start
7284 * the I/O.
7285 */
7286 vha->marker_needed = 1;
7287 } while (!atomic_read(&vha->loop_down_timer) &&
7288 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7289 }
7290 }
7291
qla_do_heartbeat(struct scsi_qla_host * vha)7292 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7293 {
7294 struct qla_hw_data *ha = vha->hw;
7295 u32 cmpl_cnt;
7296 u16 i;
7297 bool do_heartbeat = false;
7298
7299 /*
7300 * Allow do_heartbeat only if we don’t have any active interrupts,
7301 * but there are still IOs outstanding with firmware.
7302 */
7303 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7304 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7305 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7306 do_heartbeat = true;
7307 goto skip;
7308 }
7309 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7310
7311 for (i = 0; i < ha->max_qpairs; i++) {
7312 if (ha->queue_pair_map[i]) {
7313 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7314 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7315 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7316 do_heartbeat = true;
7317 break;
7318 }
7319 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7320 }
7321 }
7322
7323 skip:
7324 return do_heartbeat;
7325 }
7326
qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7327 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7328 {
7329 struct qla_hw_data *ha = vha->hw;
7330
7331 if (vha->vp_idx)
7332 return;
7333
7334 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7335 return;
7336
7337 /*
7338 * dpc thread cannot run if heartbeat is running at the same time.
7339 * We also do not want to starve heartbeat task. Therefore, do
7340 * heartbeat task at least once every 5 seconds.
7341 */
7342 if (dpc_started &&
7343 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7344 return;
7345
7346 if (qla_do_heartbeat(vha)) {
7347 ha->last_heartbeat_run_jiffies = jiffies;
7348 queue_work(ha->wq, &ha->heartbeat_work);
7349 }
7350 }
7351
qla_wind_down_chip(scsi_qla_host_t * vha)7352 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7353 {
7354 struct qla_hw_data *ha = vha->hw;
7355
7356 if (!ha->flags.eeh_busy)
7357 return;
7358 if (ha->pci_error_state)
7359 /* system is trying to recover */
7360 return;
7361
7362 /*
7363 * Current system is not handling PCIE error. At this point, this is
7364 * best effort to wind down the adapter.
7365 */
7366 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7367 !ha->flags.eeh_flush) {
7368 ql_log(ql_log_info, vha, 0x9009,
7369 "PCI Error detected, attempting to reset hardware.\n");
7370
7371 ha->isp_ops->reset_chip(vha);
7372 ha->isp_ops->disable_intrs(ha);
7373
7374 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7375 ha->eeh_jif = jiffies;
7376
7377 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7378 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7379 pci_clear_master(ha->pdev);
7380
7381 /* flush all command */
7382 qla2x00_abort_isp_cleanup(vha);
7383 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7384
7385 ql_log(ql_log_info, vha, 0x900a,
7386 "PCI Error handling complete, all IOs aborted.\n");
7387 }
7388 }
7389
7390 /**************************************************************************
7391 * qla2x00_timer
7392 *
7393 * Description:
7394 * One second timer
7395 *
7396 * Context: Interrupt
7397 ***************************************************************************/
7398 void
qla2x00_timer(struct timer_list * t)7399 qla2x00_timer(struct timer_list *t)
7400 {
7401 scsi_qla_host_t *vha = from_timer(vha, t, timer);
7402 unsigned long cpu_flags = 0;
7403 int start_dpc = 0;
7404 int index;
7405 srb_t *sp;
7406 uint16_t w;
7407 struct qla_hw_data *ha = vha->hw;
7408 struct req_que *req;
7409 unsigned long flags;
7410 fc_port_t *fcport = NULL;
7411
7412 if (ha->flags.eeh_busy) {
7413 qla_wind_down_chip(vha);
7414
7415 ql_dbg(ql_dbg_timer, vha, 0x6000,
7416 "EEH = %d, restarting timer.\n",
7417 ha->flags.eeh_busy);
7418 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7419 return;
7420 }
7421
7422 /*
7423 * Hardware read to raise pending EEH errors during mailbox waits. If
7424 * the read returns -1 then disable the board.
7425 */
7426 if (!pci_channel_offline(ha->pdev)) {
7427 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7428 qla2x00_check_reg16_for_disconnect(vha, w);
7429 }
7430
7431 /* Make sure qla82xx_watchdog is run only for physical port */
7432 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7433 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7434 start_dpc++;
7435 if (IS_QLA82XX(ha))
7436 qla82xx_watchdog(vha);
7437 else if (IS_QLA8044(ha))
7438 qla8044_watchdog(vha);
7439 }
7440
7441 if (!vha->vp_idx && IS_QLAFX00(ha))
7442 qlafx00_timer_routine(vha);
7443
7444 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7445 vha->link_down_time++;
7446
7447 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7448 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7449 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7450 fcport->tgt_link_down_time++;
7451 }
7452 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7453
7454 /* Loop down handler. */
7455 if (atomic_read(&vha->loop_down_timer) > 0 &&
7456 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7457 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7458 && vha->flags.online) {
7459
7460 if (atomic_read(&vha->loop_down_timer) ==
7461 vha->loop_down_abort_time) {
7462
7463 ql_log(ql_log_info, vha, 0x6008,
7464 "Loop down - aborting the queues before time expires.\n");
7465
7466 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7467 atomic_set(&vha->loop_state, LOOP_DEAD);
7468
7469 /*
7470 * Schedule an ISP abort to return any FCP2-device
7471 * commands.
7472 */
7473 /* NPIV - scan physical port only */
7474 if (!vha->vp_idx) {
7475 spin_lock_irqsave(&ha->hardware_lock,
7476 cpu_flags);
7477 req = ha->req_q_map[0];
7478 for (index = 1;
7479 index < req->num_outstanding_cmds;
7480 index++) {
7481 fc_port_t *sfcp;
7482
7483 sp = req->outstanding_cmds[index];
7484 if (!sp)
7485 continue;
7486 if (sp->cmd_type != TYPE_SRB)
7487 continue;
7488 if (sp->type != SRB_SCSI_CMD)
7489 continue;
7490 sfcp = sp->fcport;
7491 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7492 continue;
7493
7494 if (IS_QLA82XX(ha))
7495 set_bit(FCOE_CTX_RESET_NEEDED,
7496 &vha->dpc_flags);
7497 else
7498 set_bit(ISP_ABORT_NEEDED,
7499 &vha->dpc_flags);
7500 break;
7501 }
7502 spin_unlock_irqrestore(&ha->hardware_lock,
7503 cpu_flags);
7504 }
7505 start_dpc++;
7506 }
7507
7508 /* if the loop has been down for 4 minutes, reinit adapter */
7509 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7510 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7511 ql_log(ql_log_warn, vha, 0x6009,
7512 "Loop down - aborting ISP.\n");
7513
7514 if (IS_QLA82XX(ha))
7515 set_bit(FCOE_CTX_RESET_NEEDED,
7516 &vha->dpc_flags);
7517 else
7518 set_bit(ISP_ABORT_NEEDED,
7519 &vha->dpc_flags);
7520 }
7521 }
7522 ql_dbg(ql_dbg_timer, vha, 0x600a,
7523 "Loop down - seconds remaining %d.\n",
7524 atomic_read(&vha->loop_down_timer));
7525 }
7526 /* Check if beacon LED needs to be blinked for physical host only */
7527 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7528 /* There is no beacon_blink function for ISP82xx */
7529 if (!IS_P3P_TYPE(ha)) {
7530 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7531 start_dpc++;
7532 }
7533 }
7534
7535 /* check if edif running */
7536 if (vha->hw->flags.edif_enabled)
7537 qla_edif_timer(vha);
7538
7539 /* Process any deferred work. */
7540 if (!list_empty(&vha->work_list)) {
7541 unsigned long flags;
7542 bool q = false;
7543
7544 spin_lock_irqsave(&vha->work_lock, flags);
7545 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7546 q = true;
7547 spin_unlock_irqrestore(&vha->work_lock, flags);
7548 if (q)
7549 queue_work(vha->hw->wq, &vha->iocb_work);
7550 }
7551
7552 /*
7553 * FC-NVME
7554 * see if the active AEN count has changed from what was last reported.
7555 */
7556 index = atomic_read(&ha->nvme_active_aen_cnt);
7557 if (!vha->vp_idx &&
7558 (index != ha->nvme_last_rptd_aen) &&
7559 ha->zio_mode == QLA_ZIO_MODE_6 &&
7560 !ha->flags.host_shutting_down) {
7561 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7562 ql_log(ql_log_info, vha, 0x3002,
7563 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7564 ha->nvme_last_rptd_aen);
7565 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7566 start_dpc++;
7567 }
7568
7569 if (!vha->vp_idx &&
7570 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7571 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7572 ql_log(ql_log_info, vha, 0x3002,
7573 "Sched: Set ZIO exchange threshold to %d.\n",
7574 ha->last_zio_threshold);
7575 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7576 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7577 start_dpc++;
7578 }
7579 qla_adjust_buf(vha);
7580
7581 /* borrowing w to signify dpc will run */
7582 w = 0;
7583 /* Schedule the DPC routine if needed */
7584 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7585 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7586 start_dpc ||
7587 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7588 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7589 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7590 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7591 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7592 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7593 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7594 ql_dbg(ql_dbg_timer, vha, 0x600b,
7595 "isp_abort_needed=%d loop_resync_needed=%d "
7596 "start_dpc=%d reset_marker_needed=%d",
7597 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7598 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7599 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7600 ql_dbg(ql_dbg_timer, vha, 0x600c,
7601 "beacon_blink_needed=%d isp_unrecoverable=%d "
7602 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7603 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7604 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7605 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7606 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7607 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7608 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7609 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7610 qla2xxx_wake_dpc(vha);
7611 w = 1;
7612 }
7613
7614 qla_heart_beat(vha, w);
7615
7616 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7617 }
7618
7619 /* Firmware interface routines. */
7620
7621 #define FW_ISP21XX 0
7622 #define FW_ISP22XX 1
7623 #define FW_ISP2300 2
7624 #define FW_ISP2322 3
7625 #define FW_ISP24XX 4
7626 #define FW_ISP25XX 5
7627 #define FW_ISP81XX 6
7628 #define FW_ISP82XX 7
7629 #define FW_ISP2031 8
7630 #define FW_ISP8031 9
7631 #define FW_ISP27XX 10
7632 #define FW_ISP28XX 11
7633
7634 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7635 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7636 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7637 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7638 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7639 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7640 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7641 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7642 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7643 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7644 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7645 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7646
7647
7648 static DEFINE_MUTEX(qla_fw_lock);
7649
7650 static struct fw_blob qla_fw_blobs[] = {
7651 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7652 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7653 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7654 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7655 { .name = FW_FILE_ISP24XX, },
7656 { .name = FW_FILE_ISP25XX, },
7657 { .name = FW_FILE_ISP81XX, },
7658 { .name = FW_FILE_ISP82XX, },
7659 { .name = FW_FILE_ISP2031, },
7660 { .name = FW_FILE_ISP8031, },
7661 { .name = FW_FILE_ISP27XX, },
7662 { .name = FW_FILE_ISP28XX, },
7663 { .name = NULL, },
7664 };
7665
7666 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7667 qla2x00_request_firmware(scsi_qla_host_t *vha)
7668 {
7669 struct qla_hw_data *ha = vha->hw;
7670 struct fw_blob *blob;
7671
7672 if (IS_QLA2100(ha)) {
7673 blob = &qla_fw_blobs[FW_ISP21XX];
7674 } else if (IS_QLA2200(ha)) {
7675 blob = &qla_fw_blobs[FW_ISP22XX];
7676 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7677 blob = &qla_fw_blobs[FW_ISP2300];
7678 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7679 blob = &qla_fw_blobs[FW_ISP2322];
7680 } else if (IS_QLA24XX_TYPE(ha)) {
7681 blob = &qla_fw_blobs[FW_ISP24XX];
7682 } else if (IS_QLA25XX(ha)) {
7683 blob = &qla_fw_blobs[FW_ISP25XX];
7684 } else if (IS_QLA81XX(ha)) {
7685 blob = &qla_fw_blobs[FW_ISP81XX];
7686 } else if (IS_QLA82XX(ha)) {
7687 blob = &qla_fw_blobs[FW_ISP82XX];
7688 } else if (IS_QLA2031(ha)) {
7689 blob = &qla_fw_blobs[FW_ISP2031];
7690 } else if (IS_QLA8031(ha)) {
7691 blob = &qla_fw_blobs[FW_ISP8031];
7692 } else if (IS_QLA27XX(ha)) {
7693 blob = &qla_fw_blobs[FW_ISP27XX];
7694 } else if (IS_QLA28XX(ha)) {
7695 blob = &qla_fw_blobs[FW_ISP28XX];
7696 } else {
7697 return NULL;
7698 }
7699
7700 if (!blob->name)
7701 return NULL;
7702
7703 mutex_lock(&qla_fw_lock);
7704 if (blob->fw)
7705 goto out;
7706
7707 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7708 ql_log(ql_log_warn, vha, 0x0063,
7709 "Failed to load firmware image (%s).\n", blob->name);
7710 blob->fw = NULL;
7711 blob = NULL;
7712 }
7713
7714 out:
7715 mutex_unlock(&qla_fw_lock);
7716 return blob;
7717 }
7718
7719 static void
qla2x00_release_firmware(void)7720 qla2x00_release_firmware(void)
7721 {
7722 struct fw_blob *blob;
7723
7724 mutex_lock(&qla_fw_lock);
7725 for (blob = qla_fw_blobs; blob->name; blob++)
7726 release_firmware(blob->fw);
7727 mutex_unlock(&qla_fw_lock);
7728 }
7729
qla_pci_error_cleanup(scsi_qla_host_t * vha)7730 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7731 {
7732 struct qla_hw_data *ha = vha->hw;
7733 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7734 struct qla_qpair *qpair = NULL;
7735 struct scsi_qla_host *vp, *tvp;
7736 fc_port_t *fcport;
7737 int i;
7738 unsigned long flags;
7739
7740 ql_dbg(ql_dbg_aer, vha, 0x9000,
7741 "%s\n", __func__);
7742 ha->chip_reset++;
7743
7744 ha->base_qpair->chip_reset = ha->chip_reset;
7745 for (i = 0; i < ha->max_qpairs; i++) {
7746 if (ha->queue_pair_map[i])
7747 ha->queue_pair_map[i]->chip_reset =
7748 ha->base_qpair->chip_reset;
7749 }
7750
7751 /*
7752 * purge mailbox might take a while. Slot Reset/chip reset
7753 * will take care of the purge
7754 */
7755
7756 mutex_lock(&ha->mq_lock);
7757 ha->base_qpair->online = 0;
7758 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7759 qpair->online = 0;
7760 wmb();
7761 mutex_unlock(&ha->mq_lock);
7762
7763 qla2x00_mark_all_devices_lost(vha);
7764
7765 spin_lock_irqsave(&ha->vport_slock, flags);
7766 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7767 atomic_inc(&vp->vref_count);
7768 spin_unlock_irqrestore(&ha->vport_slock, flags);
7769 qla2x00_mark_all_devices_lost(vp);
7770 spin_lock_irqsave(&ha->vport_slock, flags);
7771 atomic_dec(&vp->vref_count);
7772 }
7773 spin_unlock_irqrestore(&ha->vport_slock, flags);
7774
7775 /* Clear all async request states across all VPs. */
7776 list_for_each_entry(fcport, &vha->vp_fcports, list)
7777 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7778
7779 spin_lock_irqsave(&ha->vport_slock, flags);
7780 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7781 atomic_inc(&vp->vref_count);
7782 spin_unlock_irqrestore(&ha->vport_slock, flags);
7783 list_for_each_entry(fcport, &vp->vp_fcports, list)
7784 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7785 spin_lock_irqsave(&ha->vport_slock, flags);
7786 atomic_dec(&vp->vref_count);
7787 }
7788 spin_unlock_irqrestore(&ha->vport_slock, flags);
7789 }
7790
7791
7792 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7793 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7794 {
7795 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7796 struct qla_hw_data *ha = vha->hw;
7797 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7798
7799 ql_log(ql_log_warn, vha, 0x9000,
7800 "PCI error detected, state %x.\n", state);
7801 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7802
7803 if (!atomic_read(&pdev->enable_cnt)) {
7804 ql_log(ql_log_info, vha, 0xffff,
7805 "PCI device is disabled,state %x\n", state);
7806 ret = PCI_ERS_RESULT_NEED_RESET;
7807 goto out;
7808 }
7809
7810 switch (state) {
7811 case pci_channel_io_normal:
7812 qla_pci_set_eeh_busy(vha);
7813 if (ql2xmqsupport || ql2xnvmeenable) {
7814 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7815 qla2xxx_wake_dpc(vha);
7816 }
7817 ret = PCI_ERS_RESULT_CAN_RECOVER;
7818 break;
7819 case pci_channel_io_frozen:
7820 qla_pci_set_eeh_busy(vha);
7821 ret = PCI_ERS_RESULT_NEED_RESET;
7822 break;
7823 case pci_channel_io_perm_failure:
7824 ha->flags.pci_channel_io_perm_failure = 1;
7825 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7826 if (ql2xmqsupport || ql2xnvmeenable) {
7827 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7828 qla2xxx_wake_dpc(vha);
7829 }
7830 ret = PCI_ERS_RESULT_DISCONNECT;
7831 }
7832 out:
7833 ql_dbg(ql_dbg_aer, vha, 0x600d,
7834 "PCI error detected returning [%x].\n", ret);
7835 return ret;
7836 }
7837
7838 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7839 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7840 {
7841 int risc_paused = 0;
7842 uint32_t stat;
7843 unsigned long flags;
7844 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7845 struct qla_hw_data *ha = base_vha->hw;
7846 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7847 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7848
7849 ql_log(ql_log_warn, base_vha, 0x9000,
7850 "mmio enabled\n");
7851
7852 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7853
7854 if (IS_QLA82XX(ha))
7855 return PCI_ERS_RESULT_RECOVERED;
7856
7857 if (qla2x00_isp_reg_stat(ha)) {
7858 ql_log(ql_log_info, base_vha, 0x803f,
7859 "During mmio enabled, PCI/Register disconnect still detected.\n");
7860 goto out;
7861 }
7862
7863 spin_lock_irqsave(&ha->hardware_lock, flags);
7864 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7865 stat = rd_reg_word(®->hccr);
7866 if (stat & HCCR_RISC_PAUSE)
7867 risc_paused = 1;
7868 } else if (IS_QLA23XX(ha)) {
7869 stat = rd_reg_dword(®->u.isp2300.host_status);
7870 if (stat & HSR_RISC_PAUSED)
7871 risc_paused = 1;
7872 } else if (IS_FWI2_CAPABLE(ha)) {
7873 stat = rd_reg_dword(®24->host_status);
7874 if (stat & HSRX_RISC_PAUSED)
7875 risc_paused = 1;
7876 }
7877 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7878
7879 if (risc_paused) {
7880 ql_log(ql_log_info, base_vha, 0x9003,
7881 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7882 qla2xxx_dump_fw(base_vha);
7883 }
7884 out:
7885 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7886 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7887 "mmio enabled returning.\n");
7888 return PCI_ERS_RESULT_NEED_RESET;
7889 }
7890
7891 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7892 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7893 {
7894 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7895 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7896 struct qla_hw_data *ha = base_vha->hw;
7897 int rc;
7898 struct qla_qpair *qpair = NULL;
7899
7900 ql_log(ql_log_warn, base_vha, 0x9004,
7901 "Slot Reset.\n");
7902
7903 ha->pci_error_state = QLA_PCI_SLOT_RESET;
7904 /* Workaround: qla2xxx driver which access hardware earlier
7905 * needs error state to be pci_channel_io_online.
7906 * Otherwise mailbox command timesout.
7907 */
7908 pdev->error_state = pci_channel_io_normal;
7909
7910 pci_restore_state(pdev);
7911
7912 /* pci_restore_state() clears the saved_state flag of the device
7913 * save restored state which resets saved_state flag
7914 */
7915 pci_save_state(pdev);
7916
7917 if (ha->mem_only)
7918 rc = pci_enable_device_mem(pdev);
7919 else
7920 rc = pci_enable_device(pdev);
7921
7922 if (rc) {
7923 ql_log(ql_log_warn, base_vha, 0x9005,
7924 "Can't re-enable PCI device after reset.\n");
7925 goto exit_slot_reset;
7926 }
7927
7928
7929 if (ha->isp_ops->pci_config(base_vha))
7930 goto exit_slot_reset;
7931
7932 mutex_lock(&ha->mq_lock);
7933 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7934 qpair->online = 1;
7935 mutex_unlock(&ha->mq_lock);
7936
7937 ha->flags.eeh_busy = 0;
7938 base_vha->flags.online = 1;
7939 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7940 ha->isp_ops->abort_isp(base_vha);
7941 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7942
7943 if (qla2x00_isp_reg_stat(ha)) {
7944 ha->flags.eeh_busy = 1;
7945 qla_pci_error_cleanup(base_vha);
7946 ql_log(ql_log_warn, base_vha, 0x9005,
7947 "Device unable to recover from PCI error.\n");
7948 } else {
7949 ret = PCI_ERS_RESULT_RECOVERED;
7950 }
7951
7952 exit_slot_reset:
7953 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7954 "Slot Reset returning %x.\n", ret);
7955
7956 return ret;
7957 }
7958
7959 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7960 qla2xxx_pci_resume(struct pci_dev *pdev)
7961 {
7962 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7963 struct qla_hw_data *ha = base_vha->hw;
7964 int ret;
7965
7966 ql_log(ql_log_warn, base_vha, 0x900f,
7967 "Pci Resume.\n");
7968
7969
7970 ret = qla2x00_wait_for_hba_online(base_vha);
7971 if (ret != QLA_SUCCESS) {
7972 ql_log(ql_log_fatal, base_vha, 0x9002,
7973 "The device failed to resume I/O from slot/link_reset.\n");
7974 }
7975 ha->pci_error_state = QLA_PCI_RESUME;
7976 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7977 "Pci Resume returning.\n");
7978 }
7979
qla_pci_set_eeh_busy(struct scsi_qla_host * vha)7980 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7981 {
7982 struct qla_hw_data *ha = vha->hw;
7983 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7984 bool do_cleanup = false;
7985 unsigned long flags;
7986
7987 if (ha->flags.eeh_busy)
7988 return;
7989
7990 spin_lock_irqsave(&base_vha->work_lock, flags);
7991 if (!ha->flags.eeh_busy) {
7992 ha->eeh_jif = jiffies;
7993 ha->flags.eeh_flush = 0;
7994
7995 ha->flags.eeh_busy = 1;
7996 do_cleanup = true;
7997 }
7998 spin_unlock_irqrestore(&base_vha->work_lock, flags);
7999
8000 if (do_cleanup)
8001 qla_pci_error_cleanup(base_vha);
8002 }
8003
8004 /*
8005 * this routine will schedule a task to pause IO from interrupt context
8006 * if caller sees a PCIE error event (register read = 0xf's)
8007 */
qla_schedule_eeh_work(struct scsi_qla_host * vha)8008 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
8009 {
8010 struct qla_hw_data *ha = vha->hw;
8011 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8012
8013 if (ha->flags.eeh_busy)
8014 return;
8015
8016 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8017 qla2xxx_wake_dpc(base_vha);
8018 }
8019
8020 static void
qla_pci_reset_prepare(struct pci_dev * pdev)8021 qla_pci_reset_prepare(struct pci_dev *pdev)
8022 {
8023 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8024 struct qla_hw_data *ha = base_vha->hw;
8025 struct qla_qpair *qpair;
8026
8027 ql_log(ql_log_warn, base_vha, 0xffff,
8028 "%s.\n", __func__);
8029
8030 /*
8031 * PCI FLR/function reset is about to reset the
8032 * slot. Stop the chip to stop all DMA access.
8033 * It is assumed that pci_reset_done will be called
8034 * after FLR to resume Chip operation.
8035 */
8036 ha->flags.eeh_busy = 1;
8037 mutex_lock(&ha->mq_lock);
8038 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8039 qpair->online = 0;
8040 mutex_unlock(&ha->mq_lock);
8041
8042 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8043 qla2x00_abort_isp_cleanup(base_vha);
8044 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8045 }
8046
8047 static void
qla_pci_reset_done(struct pci_dev * pdev)8048 qla_pci_reset_done(struct pci_dev *pdev)
8049 {
8050 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8051 struct qla_hw_data *ha = base_vha->hw;
8052 struct qla_qpair *qpair;
8053
8054 ql_log(ql_log_warn, base_vha, 0xffff,
8055 "%s.\n", __func__);
8056
8057 /*
8058 * FLR just completed by PCI layer. Resume adapter
8059 */
8060 ha->flags.eeh_busy = 0;
8061 mutex_lock(&ha->mq_lock);
8062 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8063 qpair->online = 1;
8064 mutex_unlock(&ha->mq_lock);
8065
8066 base_vha->flags.online = 1;
8067 ha->isp_ops->abort_isp(base_vha);
8068 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8069 }
8070
qla2xxx_map_queues(struct Scsi_Host * shost)8071 static void qla2xxx_map_queues(struct Scsi_Host *shost)
8072 {
8073 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8074 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8075
8076 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8077 blk_mq_map_queues(qmap);
8078 else
8079 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
8080 }
8081
8082 struct scsi_host_template qla2xxx_driver_template = {
8083 .module = THIS_MODULE,
8084 .name = QLA2XXX_DRIVER_NAME,
8085 .queuecommand = qla2xxx_queuecommand,
8086
8087 .eh_timed_out = fc_eh_timed_out,
8088 .eh_abort_handler = qla2xxx_eh_abort,
8089 .eh_should_retry_cmd = fc_eh_should_retry_cmd,
8090 .eh_device_reset_handler = qla2xxx_eh_device_reset,
8091 .eh_target_reset_handler = qla2xxx_eh_target_reset,
8092 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
8093 .eh_host_reset_handler = qla2xxx_eh_host_reset,
8094
8095 .slave_configure = qla2xxx_slave_configure,
8096
8097 .slave_alloc = qla2xxx_slave_alloc,
8098 .slave_destroy = qla2xxx_slave_destroy,
8099 .scan_finished = qla2xxx_scan_finished,
8100 .scan_start = qla2xxx_scan_start,
8101 .change_queue_depth = scsi_change_queue_depth,
8102 .map_queues = qla2xxx_map_queues,
8103 .this_id = -1,
8104 .cmd_per_lun = 3,
8105 .sg_tablesize = SG_ALL,
8106
8107 .max_sectors = 0xFFFF,
8108 .shost_groups = qla2x00_host_groups,
8109
8110 .supported_mode = MODE_INITIATOR,
8111 .track_queue_depth = 1,
8112 .cmd_size = sizeof(srb_t),
8113 };
8114
8115 static const struct pci_error_handlers qla2xxx_err_handler = {
8116 .error_detected = qla2xxx_pci_error_detected,
8117 .mmio_enabled = qla2xxx_pci_mmio_enabled,
8118 .slot_reset = qla2xxx_pci_slot_reset,
8119 .resume = qla2xxx_pci_resume,
8120 .reset_prepare = qla_pci_reset_prepare,
8121 .reset_done = qla_pci_reset_done,
8122 };
8123
8124 static struct pci_device_id qla2xxx_pci_tbl[] = {
8125 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8126 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8127 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8128 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8129 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8130 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8131 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8132 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8133 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8134 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8135 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8136 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8137 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8138 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8139 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8140 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8141 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8142 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8143 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8144 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8145 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8146 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8147 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8148 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8149 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8150 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8151 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8152 { 0 },
8153 };
8154 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8155
8156 static struct pci_driver qla2xxx_pci_driver = {
8157 .name = QLA2XXX_DRIVER_NAME,
8158 .driver = {
8159 .owner = THIS_MODULE,
8160 },
8161 .id_table = qla2xxx_pci_tbl,
8162 .probe = qla2x00_probe_one,
8163 .remove = qla2x00_remove_one,
8164 .shutdown = qla2x00_shutdown,
8165 .err_handler = &qla2xxx_err_handler,
8166 };
8167
8168 static const struct file_operations apidev_fops = {
8169 .owner = THIS_MODULE,
8170 .llseek = noop_llseek,
8171 };
8172
8173 /**
8174 * qla2x00_module_init - Module initialization.
8175 **/
8176 static int __init
qla2x00_module_init(void)8177 qla2x00_module_init(void)
8178 {
8179 int ret = 0;
8180
8181 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8182 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8183 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8184 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8185 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8186 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8187 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8188 BUILD_BUG_ON(sizeof(request_t) != 64);
8189 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8190 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8191 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8192 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8193 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8194 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8195 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8196 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8197 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8198 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8199 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8200 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8201 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8202 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8203 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8204 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8205 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8206 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8207 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8208 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8209 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8210 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8211 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8212 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8213 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8214 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8215 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8216 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8217 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8218 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8219 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8220 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8221 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8222 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8223 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8224 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8225 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8226 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8227 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8228 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8229 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8230 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8231 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8232 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8233 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8234 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8235 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8236 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8237 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8238 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8239 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8240 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8241 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8242 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8243 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8244 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8245 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8246 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8247 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8248 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8249 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8250 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8251 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8252 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8253 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8254 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8255 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8256 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8257 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8258 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8259 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8260 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8261 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8262 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8263 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8264 BUILD_BUG_ON(sizeof(target_id_t) != 2);
8265
8266 qla_trace_init();
8267
8268 /* Allocate cache for SRBs. */
8269 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8270 SLAB_HWCACHE_ALIGN, NULL);
8271 if (srb_cachep == NULL) {
8272 ql_log(ql_log_fatal, NULL, 0x0001,
8273 "Unable to allocate SRB cache...Failing load!.\n");
8274 return -ENOMEM;
8275 }
8276
8277 /* Initialize target kmem_cache and mem_pools */
8278 ret = qlt_init();
8279 if (ret < 0) {
8280 goto destroy_cache;
8281 } else if (ret > 0) {
8282 /*
8283 * If initiator mode is explictly disabled by qlt_init(),
8284 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8285 * performing scsi_scan_target() during LOOP UP event.
8286 */
8287 qla2xxx_transport_functions.disable_target_scan = 1;
8288 qla2xxx_transport_vport_functions.disable_target_scan = 1;
8289 }
8290
8291 /* Derive version string. */
8292 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8293 if (ql2xextended_error_logging)
8294 strcat(qla2x00_version_str, "-debug");
8295 if (ql2xextended_error_logging == 1)
8296 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8297
8298 qla2xxx_transport_template =
8299 fc_attach_transport(&qla2xxx_transport_functions);
8300 if (!qla2xxx_transport_template) {
8301 ql_log(ql_log_fatal, NULL, 0x0002,
8302 "fc_attach_transport failed...Failing load!.\n");
8303 ret = -ENODEV;
8304 goto qlt_exit;
8305 }
8306
8307 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8308 if (apidev_major < 0) {
8309 ql_log(ql_log_fatal, NULL, 0x0003,
8310 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8311 }
8312
8313 qla2xxx_transport_vport_template =
8314 fc_attach_transport(&qla2xxx_transport_vport_functions);
8315 if (!qla2xxx_transport_vport_template) {
8316 ql_log(ql_log_fatal, NULL, 0x0004,
8317 "fc_attach_transport vport failed...Failing load!.\n");
8318 ret = -ENODEV;
8319 goto unreg_chrdev;
8320 }
8321 ql_log(ql_log_info, NULL, 0x0005,
8322 "QLogic Fibre Channel HBA Driver: %s.\n",
8323 qla2x00_version_str);
8324 ret = pci_register_driver(&qla2xxx_pci_driver);
8325 if (ret) {
8326 ql_log(ql_log_fatal, NULL, 0x0006,
8327 "pci_register_driver failed...ret=%d Failing load!.\n",
8328 ret);
8329 goto release_vport_transport;
8330 }
8331 return ret;
8332
8333 release_vport_transport:
8334 fc_release_transport(qla2xxx_transport_vport_template);
8335
8336 unreg_chrdev:
8337 if (apidev_major >= 0)
8338 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8339 fc_release_transport(qla2xxx_transport_template);
8340
8341 qlt_exit:
8342 qlt_exit();
8343
8344 destroy_cache:
8345 kmem_cache_destroy(srb_cachep);
8346
8347 qla_trace_uninit();
8348 return ret;
8349 }
8350
8351 /**
8352 * qla2x00_module_exit - Module cleanup.
8353 **/
8354 static void __exit
qla2x00_module_exit(void)8355 qla2x00_module_exit(void)
8356 {
8357 pci_unregister_driver(&qla2xxx_pci_driver);
8358 qla2x00_release_firmware();
8359 kmem_cache_destroy(ctx_cachep);
8360 fc_release_transport(qla2xxx_transport_vport_template);
8361 if (apidev_major >= 0)
8362 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8363 fc_release_transport(qla2xxx_transport_template);
8364 qlt_exit();
8365 kmem_cache_destroy(srb_cachep);
8366 qla_trace_uninit();
8367 }
8368
8369 module_init(qla2x00_module_init);
8370 module_exit(qla2x00_module_exit);
8371
8372 MODULE_AUTHOR("QLogic Corporation");
8373 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8374 MODULE_LICENSE("GPL");
8375 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8376 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8377 MODULE_FIRMWARE(FW_FILE_ISP2300);
8378 MODULE_FIRMWARE(FW_FILE_ISP2322);
8379 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8380 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8381