1 /*
2  * Copyright (c) 2010 - 2017 Intel Corporation.  All rights reserved.
3  * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33 
34 #include <linux/pci.h>
35 #include <linux/io.h>
36 #include <linux/delay.h>
37 #include <linux/vmalloc.h>
38 #include <linux/module.h>
39 
40 #include "qib.h"
41 
42 /*
43  * This file contains PCIe utility routines that are common to the
44  * various QLogic InfiniPath adapters
45  */
46 
47 /*
48  * Code to adjust PCIe capabilities.
49  * To minimize the change footprint, we call it
50  * from qib_pcie_params, which every chip-specific
51  * file calls, even though this violates some
52  * expectations of harmlessness.
53  */
54 static void qib_tune_pcie_caps(struct qib_devdata *);
55 static void qib_tune_pcie_coalesce(struct qib_devdata *);
56 
57 /*
58  * Do all the common PCIe setup and initialization.
59  * devdata is not yet allocated, and is not allocated until after this
60  * routine returns success.  Therefore qib_dev_err() can't be used for error
61  * printing.
62  */
qib_pcie_init(struct pci_dev * pdev,const struct pci_device_id * ent)63 int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
64 {
65 	int ret;
66 
67 	ret = pci_enable_device(pdev);
68 	if (ret) {
69 		/*
70 		 * This can happen (in theory) iff:
71 		 * We did a chip reset, and then failed to reprogram the
72 		 * BAR, or the chip reset due to an internal error.  We then
73 		 * unloaded the driver and reloaded it.
74 		 *
75 		 * Both reset cases set the BAR back to initial state.  For
76 		 * the latter case, the AER sticky error bit at offset 0x718
77 		 * should be set, but the Linux kernel doesn't yet know
78 		 * about that, it appears.  If the original BAR was retained
79 		 * in the kernel data structures, this may be OK.
80 		 */
81 		qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
82 			      -ret);
83 		goto done;
84 	}
85 
86 	ret = pci_request_regions(pdev, QIB_DRV_NAME);
87 	if (ret) {
88 		qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
89 		goto bail;
90 	}
91 
92 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
93 	if (ret) {
94 		/*
95 		 * If the 64 bit setup fails, try 32 bit.  Some systems
96 		 * do not setup 64 bit maps on systems with 2GB or less
97 		 * memory installed.
98 		 */
99 		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
100 		if (ret) {
101 			qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
102 			goto bail;
103 		}
104 	}
105 
106 	pci_set_master(pdev);
107 	goto done;
108 
109 bail:
110 	pci_disable_device(pdev);
111 	pci_release_regions(pdev);
112 done:
113 	return ret;
114 }
115 
116 /*
117  * Do remaining PCIe setup, once dd is allocated, and save away
118  * fields required to re-initialize after a chip reset, or for
119  * various other purposes
120  */
qib_pcie_ddinit(struct qib_devdata * dd,struct pci_dev * pdev,const struct pci_device_id * ent)121 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
122 		    const struct pci_device_id *ent)
123 {
124 	unsigned long len;
125 	resource_size_t addr;
126 
127 	dd->pcidev = pdev;
128 	pci_set_drvdata(pdev, dd);
129 
130 	addr = pci_resource_start(pdev, 0);
131 	len = pci_resource_len(pdev, 0);
132 
133 	dd->kregbase = ioremap(addr, len);
134 	if (!dd->kregbase)
135 		return -ENOMEM;
136 
137 	dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
138 	dd->physaddr = addr;        /* used for io_remap, etc. */
139 
140 	/*
141 	 * Save BARs to rewrite after device reset.  Save all 64 bits of
142 	 * BAR, just in case.
143 	 */
144 	dd->pcibar0 = addr;
145 	dd->pcibar1 = addr >> 32;
146 	dd->deviceid = ent->device; /* save for later use */
147 	dd->vendorid = ent->vendor;
148 
149 	return 0;
150 }
151 
152 /*
153  * Do PCIe cleanup, after chip-specific cleanup, etc.  Just prior
154  * to releasing the dd memory.
155  * void because none of the core pcie cleanup returns are void
156  */
qib_pcie_ddcleanup(struct qib_devdata * dd)157 void qib_pcie_ddcleanup(struct qib_devdata *dd)
158 {
159 	u64 __iomem *base = (void __iomem *) dd->kregbase;
160 
161 	dd->kregbase = NULL;
162 	iounmap(base);
163 	if (dd->piobase)
164 		iounmap(dd->piobase);
165 	if (dd->userbase)
166 		iounmap(dd->userbase);
167 	if (dd->piovl15base)
168 		iounmap(dd->piovl15base);
169 
170 	pci_disable_device(dd->pcidev);
171 	pci_release_regions(dd->pcidev);
172 
173 	pci_set_drvdata(dd->pcidev, NULL);
174 }
175 
176 /*
177  * We save the msi lo and hi values, so we can restore them after
178  * chip reset (the kernel PCI infrastructure doesn't yet handle that
179  * correctly.
180  */
qib_cache_msi_info(struct qib_devdata * dd,int pos)181 static void qib_cache_msi_info(struct qib_devdata *dd, int pos)
182 {
183 	struct pci_dev *pdev = dd->pcidev;
184 	u16 control;
185 
186 	pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &dd->msi_lo);
187 	pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, &dd->msi_hi);
188 	pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
189 
190 	/* now save the data (vector) info */
191 	pci_read_config_word(pdev,
192 			     pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
193 			     &dd->msi_data);
194 }
195 
qib_pcie_params(struct qib_devdata * dd,u32 minw,u32 * nent)196 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent)
197 {
198 	u16 linkstat, speed;
199 	int nvec;
200 	int maxvec;
201 	unsigned int flags = PCI_IRQ_MSIX | PCI_IRQ_MSI;
202 
203 	if (!pci_is_pcie(dd->pcidev)) {
204 		qib_dev_err(dd, "Can't find PCI Express capability!\n");
205 		/* set up something... */
206 		dd->lbus_width = 1;
207 		dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
208 		nvec = -1;
209 		goto bail;
210 	}
211 
212 	if (dd->flags & QIB_HAS_INTX)
213 		flags |= PCI_IRQ_LEGACY;
214 	maxvec = (nent && *nent) ? *nent : 1;
215 	nvec = pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags);
216 	if (nvec < 0)
217 		goto bail;
218 
219 	/*
220 	 * If nent exists, make sure to record how many vectors were allocated.
221 	 * If msix_enabled is false, return 0 so the fallback code works
222 	 * correctly.
223 	 */
224 	if (nent)
225 		*nent = !dd->pcidev->msix_enabled ? 0 : nvec;
226 
227 	if (dd->pcidev->msi_enabled)
228 		qib_cache_msi_info(dd, dd->pcidev->msi_cap);
229 
230 	pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
231 	/*
232 	 * speed is bits 0-3, linkwidth is bits 4-8
233 	 * no defines for them in headers
234 	 */
235 	speed = linkstat & 0xf;
236 	linkstat >>= 4;
237 	linkstat &= 0x1f;
238 	dd->lbus_width = linkstat;
239 
240 	switch (speed) {
241 	case 1:
242 		dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
243 		break;
244 	case 2:
245 		dd->lbus_speed = 5000; /* Gen1, 5GHz */
246 		break;
247 	default: /* not defined, assume gen1 */
248 		dd->lbus_speed = 2500;
249 		break;
250 	}
251 
252 	/*
253 	 * Check against expected pcie width and complain if "wrong"
254 	 * on first initialization, not afterwards (i.e., reset).
255 	 */
256 	if (minw && linkstat < minw)
257 		qib_dev_err(dd,
258 			    "PCIe width %u (x%u HCA), performance reduced\n",
259 			    linkstat, minw);
260 
261 	qib_tune_pcie_caps(dd);
262 
263 	qib_tune_pcie_coalesce(dd);
264 
265 bail:
266 	/* fill in string, even on errors */
267 	snprintf(dd->lbus_info, sizeof(dd->lbus_info),
268 		 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
269 	return nvec < 0 ? nvec : 0;
270 }
271 
272 /**
273  * qib_free_irq - Cleanup INTx and MSI interrupts
274  * @dd: valid pointer to qib dev data
275  *
276  * Since cleanup for INTx and MSI interrupts is trivial, have a common
277  * routine.
278  *
279  */
qib_free_irq(struct qib_devdata * dd)280 void qib_free_irq(struct qib_devdata *dd)
281 {
282 	pci_free_irq(dd->pcidev, 0, dd);
283 	pci_free_irq_vectors(dd->pcidev);
284 }
285 
286 /*
287  * Setup pcie interrupt stuff again after a reset.  I'd like to just call
288  * pci_enable_msi() again for msi, but when I do that,
289  * the MSI enable bit doesn't get set in the command word, and
290  * we switch to a different interrupt vector, which is confusing,
291  * so I instead just do it all inline.  Perhaps somehow can tie this
292  * into the PCIe hotplug support at some point
293  */
qib_reinit_intr(struct qib_devdata * dd)294 int qib_reinit_intr(struct qib_devdata *dd)
295 {
296 	int pos;
297 	u16 control;
298 	int ret = 0;
299 
300 	/* If we aren't using MSI, don't restore it */
301 	if (!dd->msi_lo)
302 		goto bail;
303 
304 	pos = dd->pcidev->msi_cap;
305 	if (!pos) {
306 		qib_dev_err(dd,
307 			"Can't find MSI capability, can't restore MSI settings\n");
308 		ret = 0;
309 		/* nothing special for MSIx, just MSI */
310 		goto bail;
311 	}
312 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
313 			       dd->msi_lo);
314 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
315 			       dd->msi_hi);
316 	pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
317 	if (!(control & PCI_MSI_FLAGS_ENABLE)) {
318 		control |= PCI_MSI_FLAGS_ENABLE;
319 		pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
320 				      control);
321 	}
322 	/* now rewrite the data (vector) info */
323 	pci_write_config_word(dd->pcidev, pos +
324 			      ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
325 			      dd->msi_data);
326 	ret = 1;
327 bail:
328 	qib_free_irq(dd);
329 
330 	if (!ret && (dd->flags & QIB_HAS_INTX))
331 		ret = 1;
332 
333 	/* and now set the pci master bit again */
334 	pci_set_master(dd->pcidev);
335 
336 	return ret;
337 }
338 
339 /*
340  * These two routines are helper routines for the device reset code
341  * to move all the pcie code out of the chip-specific driver code.
342  */
qib_pcie_getcmd(struct qib_devdata * dd,u16 * cmd,u8 * iline,u8 * cline)343 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
344 {
345 	pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
346 	pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
347 	pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
348 }
349 
qib_pcie_reenable(struct qib_devdata * dd,u16 cmd,u8 iline,u8 cline)350 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
351 {
352 	int r;
353 
354 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
355 				   dd->pcibar0);
356 	if (r)
357 		qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
358 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
359 				   dd->pcibar1);
360 	if (r)
361 		qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
362 	/* now re-enable memory access, and restore cosmetic settings */
363 	pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
364 	pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
365 	pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
366 	r = pci_enable_device(dd->pcidev);
367 	if (r)
368 		qib_dev_err(dd,
369 			"pci_enable_device failed after reset: %d\n", r);
370 }
371 
372 
373 static int qib_pcie_coalesce;
374 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
375 MODULE_PARM_DESC(pcie_coalesce, "tune PCIe coalescing on some Intel chipsets");
376 
377 /*
378  * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
379  * chipsets.   This is known to be unsafe for some revisions of some
380  * of these chipsets, with some BIOS settings, and enabling it on those
381  * systems may result in the system crashing, and/or data corruption.
382  */
qib_tune_pcie_coalesce(struct qib_devdata * dd)383 static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
384 {
385 	struct pci_dev *parent;
386 	u16 devid;
387 	u32 mask, bits, val;
388 
389 	if (!qib_pcie_coalesce)
390 		return;
391 
392 	/* Find out supported and configured values for parent (root) */
393 	parent = dd->pcidev->bus->self;
394 	if (parent->bus->parent) {
395 		qib_devinfo(dd->pcidev, "Parent not root\n");
396 		return;
397 	}
398 	if (!pci_is_pcie(parent))
399 		return;
400 	if (parent->vendor != 0x8086)
401 		return;
402 
403 	/*
404 	 *  - bit 12: Max_rdcmp_Imt_EN: need to set to 1
405 	 *  - bit 11: COALESCE_FORCE: need to set to 0
406 	 *  - bit 10: COALESCE_EN: need to set to 1
407 	 *  (but limitations on some on some chipsets)
408 	 *
409 	 *  On the Intel 5000, 5100, and 7300 chipsets, there is
410 	 *  also: - bit 25:24: COALESCE_MODE, need to set to 0
411 	 */
412 	devid = parent->device;
413 	if (devid >= 0x25e2 && devid <= 0x25fa) {
414 		/* 5000 P/V/X/Z */
415 		if (parent->revision <= 0xb2)
416 			bits = 1U << 10;
417 		else
418 			bits = 7U << 10;
419 		mask = (3U << 24) | (7U << 10);
420 	} else if (devid >= 0x65e2 && devid <= 0x65fa) {
421 		/* 5100 */
422 		bits = 1U << 10;
423 		mask = (3U << 24) | (7U << 10);
424 	} else if (devid >= 0x4021 && devid <= 0x402e) {
425 		/* 5400 */
426 		bits = 7U << 10;
427 		mask = 7U << 10;
428 	} else if (devid >= 0x3604 && devid <= 0x360a) {
429 		/* 7300 */
430 		bits = 7U << 10;
431 		mask = (3U << 24) | (7U << 10);
432 	} else {
433 		/* not one of the chipsets that we know about */
434 		return;
435 	}
436 	pci_read_config_dword(parent, 0x48, &val);
437 	val &= ~mask;
438 	val |= bits;
439 	pci_write_config_dword(parent, 0x48, val);
440 }
441 
442 /*
443  * BIOS may not set PCIe bus-utilization parameters for best performance.
444  * Check and optionally adjust them to maximize our throughput.
445  */
446 static int qib_pcie_caps;
447 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
448 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
449 
qib_tune_pcie_caps(struct qib_devdata * dd)450 static void qib_tune_pcie_caps(struct qib_devdata *dd)
451 {
452 	struct pci_dev *parent;
453 	u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
454 	u16 rc_mrrs, ep_mrrs, max_mrrs;
455 
456 	/* Find out supported and configured values for parent (root) */
457 	parent = dd->pcidev->bus->self;
458 	if (!pci_is_root_bus(parent->bus)) {
459 		qib_devinfo(dd->pcidev, "Parent not root\n");
460 		return;
461 	}
462 
463 	if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
464 		return;
465 
466 	rc_mpss = parent->pcie_mpss;
467 	rc_mps = ffs(pcie_get_mps(parent)) - 8;
468 	/* Find out supported and configured values for endpoint (us) */
469 	ep_mpss = dd->pcidev->pcie_mpss;
470 	ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
471 
472 	/* Find max payload supported by root, endpoint */
473 	if (rc_mpss > ep_mpss)
474 		rc_mpss = ep_mpss;
475 
476 	/* If Supported greater than limit in module param, limit it */
477 	if (rc_mpss > (qib_pcie_caps & 7))
478 		rc_mpss = qib_pcie_caps & 7;
479 	/* If less than (allowed, supported), bump root payload */
480 	if (rc_mpss > rc_mps) {
481 		rc_mps = rc_mpss;
482 		pcie_set_mps(parent, 128 << rc_mps);
483 	}
484 	/* If less than (allowed, supported), bump endpoint payload */
485 	if (rc_mpss > ep_mps) {
486 		ep_mps = rc_mpss;
487 		pcie_set_mps(dd->pcidev, 128 << ep_mps);
488 	}
489 
490 	/*
491 	 * Now the Read Request size.
492 	 * No field for max supported, but PCIe spec limits it to 4096,
493 	 * which is code '5' (log2(4096) - 7)
494 	 */
495 	max_mrrs = 5;
496 	if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
497 		max_mrrs = (qib_pcie_caps >> 4) & 7;
498 
499 	max_mrrs = 128 << max_mrrs;
500 	rc_mrrs = pcie_get_readrq(parent);
501 	ep_mrrs = pcie_get_readrq(dd->pcidev);
502 
503 	if (max_mrrs > rc_mrrs) {
504 		rc_mrrs = max_mrrs;
505 		pcie_set_readrq(parent, rc_mrrs);
506 	}
507 	if (max_mrrs > ep_mrrs) {
508 		ep_mrrs = max_mrrs;
509 		pcie_set_readrq(dd->pcidev, ep_mrrs);
510 	}
511 }
512 /* End of PCIe capability tuning */
513 
514 /*
515  * From here through qib_pci_err_handler definition is invoked via
516  * PCI error infrastructure, registered via pci
517  */
518 static pci_ers_result_t
qib_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)519 qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
520 {
521 	struct qib_devdata *dd = pci_get_drvdata(pdev);
522 	pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
523 
524 	switch (state) {
525 	case pci_channel_io_normal:
526 		qib_devinfo(pdev, "State Normal, ignoring\n");
527 		break;
528 
529 	case pci_channel_io_frozen:
530 		qib_devinfo(pdev, "State Frozen, requesting reset\n");
531 		pci_disable_device(pdev);
532 		ret = PCI_ERS_RESULT_NEED_RESET;
533 		break;
534 
535 	case pci_channel_io_perm_failure:
536 		qib_devinfo(pdev, "State Permanent Failure, disabling\n");
537 		if (dd) {
538 			/* no more register accesses! */
539 			dd->flags &= ~QIB_PRESENT;
540 			qib_disable_after_error(dd);
541 		}
542 		 /* else early, or other problem */
543 		ret =  PCI_ERS_RESULT_DISCONNECT;
544 		break;
545 
546 	default: /* shouldn't happen */
547 		qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
548 			state);
549 		break;
550 	}
551 	return ret;
552 }
553 
554 static pci_ers_result_t
qib_pci_mmio_enabled(struct pci_dev * pdev)555 qib_pci_mmio_enabled(struct pci_dev *pdev)
556 {
557 	u64 words = 0U;
558 	struct qib_devdata *dd = pci_get_drvdata(pdev);
559 	pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
560 
561 	if (dd && dd->pport) {
562 		words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
563 		if (words == ~0ULL)
564 			ret = PCI_ERS_RESULT_NEED_RESET;
565 	}
566 	qib_devinfo(pdev,
567 		"QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
568 		words, ret);
569 	return  ret;
570 }
571 
572 static pci_ers_result_t
qib_pci_slot_reset(struct pci_dev * pdev)573 qib_pci_slot_reset(struct pci_dev *pdev)
574 {
575 	qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
576 	return PCI_ERS_RESULT_CAN_RECOVER;
577 }
578 
579 static void
qib_pci_resume(struct pci_dev * pdev)580 qib_pci_resume(struct pci_dev *pdev)
581 {
582 	struct qib_devdata *dd = pci_get_drvdata(pdev);
583 
584 	qib_devinfo(pdev, "QIB resume function called\n");
585 	/*
586 	 * Running jobs will fail, since it's asynchronous
587 	 * unlike sysfs-requested reset.   Better than
588 	 * doing nothing.
589 	 */
590 	qib_init(dd, 1); /* same as re-init after reset */
591 }
592 
593 const struct pci_error_handlers qib_pci_err_handler = {
594 	.error_detected = qib_pci_error_detected,
595 	.mmio_enabled = qib_pci_mmio_enabled,
596 	.slot_reset = qib_pci_slot_reset,
597 	.resume = qib_pci_resume,
598 };
599