1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2023, Linaro Ltd. All rights reserved.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16 #include <linux/usb/tcpm.h>
17 #include <linux/usb/typec_mux.h>
18 #include <linux/workqueue.h>
19 #include "qcom_pmic_typec_port.h"
20
21 struct pmic_typec_port_irq_data {
22 int virq;
23 int irq;
24 struct pmic_typec_port *pmic_typec_port;
25 };
26
27 struct pmic_typec_port {
28 struct device *dev;
29 struct tcpm_port *tcpm_port;
30 struct regmap *regmap;
31 u32 base;
32 unsigned int nr_irqs;
33 struct pmic_typec_port_irq_data *irq_data;
34
35 struct regulator *vdd_vbus;
36
37 int cc;
38 bool debouncing_cc;
39 struct delayed_work cc_debounce_dwork;
40
41 spinlock_t lock; /* Register atomicity */
42 };
43
44 static const char * const typec_cc_status_name[] = {
45 [TYPEC_CC_OPEN] = "Open",
46 [TYPEC_CC_RA] = "Ra",
47 [TYPEC_CC_RD] = "Rd",
48 [TYPEC_CC_RP_DEF] = "Rp-def",
49 [TYPEC_CC_RP_1_5] = "Rp-1.5",
50 [TYPEC_CC_RP_3_0] = "Rp-3.0",
51 };
52
53 static const char *rp_unknown = "unknown";
54
cc_to_name(enum typec_cc_status cc)55 static const char *cc_to_name(enum typec_cc_status cc)
56 {
57 if (cc > TYPEC_CC_RP_3_0)
58 return rp_unknown;
59
60 return typec_cc_status_name[cc];
61 }
62
63 static const char * const rp_sel_name[] = {
64 [TYPEC_SRC_RP_SEL_80UA] = "Rp-def-80uA",
65 [TYPEC_SRC_RP_SEL_180UA] = "Rp-1.5-180uA",
66 [TYPEC_SRC_RP_SEL_330UA] = "Rp-3.0-330uA",
67 };
68
rp_sel_to_name(int rp_sel)69 static const char *rp_sel_to_name(int rp_sel)
70 {
71 if (rp_sel > TYPEC_SRC_RP_SEL_330UA)
72 return rp_unknown;
73
74 return rp_sel_name[rp_sel];
75 }
76
77 #define misc_to_cc(msic) !!(misc & CC_ORIENTATION) ? "cc1" : "cc2"
78 #define misc_to_vconn(msic) !!(misc & CC_ORIENTATION) ? "cc2" : "cc1"
79
qcom_pmic_typec_port_cc_debounce(struct work_struct * work)80 static void qcom_pmic_typec_port_cc_debounce(struct work_struct *work)
81 {
82 struct pmic_typec_port *pmic_typec_port =
83 container_of(work, struct pmic_typec_port, cc_debounce_dwork.work);
84 unsigned long flags;
85
86 spin_lock_irqsave(&pmic_typec_port->lock, flags);
87 pmic_typec_port->debouncing_cc = false;
88 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
89
90 dev_dbg(pmic_typec_port->dev, "Debounce cc complete\n");
91 }
92
pmic_typec_port_isr(int irq,void * dev_id)93 static irqreturn_t pmic_typec_port_isr(int irq, void *dev_id)
94 {
95 struct pmic_typec_port_irq_data *irq_data = dev_id;
96 struct pmic_typec_port *pmic_typec_port = irq_data->pmic_typec_port;
97 u32 misc_stat;
98 bool vbus_change = false;
99 bool cc_change = false;
100 unsigned long flags;
101 int ret;
102
103 spin_lock_irqsave(&pmic_typec_port->lock, flags);
104
105 ret = regmap_read(pmic_typec_port->regmap,
106 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
107 &misc_stat);
108 if (ret)
109 goto done;
110
111 switch (irq_data->virq) {
112 case PMIC_TYPEC_VBUS_IRQ:
113 vbus_change = true;
114 break;
115 case PMIC_TYPEC_CC_STATE_IRQ:
116 case PMIC_TYPEC_ATTACH_DETACH_IRQ:
117 if (!pmic_typec_port->debouncing_cc)
118 cc_change = true;
119 break;
120 }
121
122 done:
123 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
124
125 if (vbus_change)
126 tcpm_vbus_change(pmic_typec_port->tcpm_port);
127
128 if (cc_change)
129 tcpm_cc_change(pmic_typec_port->tcpm_port);
130
131 return IRQ_HANDLED;
132 }
133
qcom_pmic_typec_port_get_vbus(struct pmic_typec_port * pmic_typec_port)134 int qcom_pmic_typec_port_get_vbus(struct pmic_typec_port *pmic_typec_port)
135 {
136 struct device *dev = pmic_typec_port->dev;
137 unsigned int misc;
138 int ret;
139
140 ret = regmap_read(pmic_typec_port->regmap,
141 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
142 &misc);
143 if (ret)
144 misc = 0;
145
146 dev_dbg(dev, "get_vbus: 0x%08x detect %d\n", misc, !!(misc & TYPEC_VBUS_DETECT));
147
148 return !!(misc & TYPEC_VBUS_DETECT);
149 }
150
qcom_pmic_typec_port_set_vbus(struct pmic_typec_port * pmic_typec_port,bool on)151 int qcom_pmic_typec_port_set_vbus(struct pmic_typec_port *pmic_typec_port, bool on)
152 {
153 u32 sm_stat;
154 u32 val;
155 int ret;
156
157 if (on) {
158 ret = regulator_enable(pmic_typec_port->vdd_vbus);
159 if (ret)
160 return ret;
161
162 val = TYPEC_SM_VBUS_VSAFE5V;
163 } else {
164 ret = regulator_disable(pmic_typec_port->vdd_vbus);
165 if (ret)
166 return ret;
167
168 val = TYPEC_SM_VBUS_VSAFE0V;
169 }
170
171 /* Poll waiting for transition to required vSafe5V or vSafe0V */
172 ret = regmap_read_poll_timeout(pmic_typec_port->regmap,
173 pmic_typec_port->base + TYPEC_SM_STATUS_REG,
174 sm_stat, sm_stat & val,
175 100, 250000);
176 if (ret)
177 dev_warn(pmic_typec_port->dev, "vbus vsafe%dv fail\n", on ? 5 : 0);
178
179 return 0;
180 }
181
qcom_pmic_typec_port_get_cc(struct pmic_typec_port * pmic_typec_port,enum typec_cc_status * cc1,enum typec_cc_status * cc2)182 int qcom_pmic_typec_port_get_cc(struct pmic_typec_port *pmic_typec_port,
183 enum typec_cc_status *cc1,
184 enum typec_cc_status *cc2)
185 {
186 struct device *dev = pmic_typec_port->dev;
187 unsigned int misc, val;
188 bool attached;
189 int ret = 0;
190
191 ret = regmap_read(pmic_typec_port->regmap,
192 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
193 if (ret)
194 goto done;
195
196 attached = !!(misc & CC_ATTACHED);
197
198 if (pmic_typec_port->debouncing_cc) {
199 ret = -EBUSY;
200 goto done;
201 }
202
203 *cc1 = TYPEC_CC_OPEN;
204 *cc2 = TYPEC_CC_OPEN;
205
206 if (!attached)
207 goto done;
208
209 if (misc & SNK_SRC_MODE) {
210 ret = regmap_read(pmic_typec_port->regmap,
211 pmic_typec_port->base + TYPEC_SRC_STATUS_REG,
212 &val);
213 if (ret)
214 goto done;
215 switch (val & DETECTED_SRC_TYPE_MASK) {
216 case AUDIO_ACCESS_RA_RA:
217 val = TYPEC_CC_RA;
218 *cc1 = TYPEC_CC_RA;
219 *cc2 = TYPEC_CC_RA;
220 break;
221 case SRC_RD_OPEN:
222 val = TYPEC_CC_RD;
223 break;
224 case SRC_RD_RA_VCONN:
225 val = TYPEC_CC_RD;
226 *cc1 = TYPEC_CC_RA;
227 *cc2 = TYPEC_CC_RA;
228 break;
229 default:
230 dev_warn(dev, "unexpected src status %.2x\n", val);
231 val = TYPEC_CC_RD;
232 break;
233 }
234 } else {
235 ret = regmap_read(pmic_typec_port->regmap,
236 pmic_typec_port->base + TYPEC_SNK_STATUS_REG,
237 &val);
238 if (ret)
239 goto done;
240 switch (val & DETECTED_SNK_TYPE_MASK) {
241 case SNK_RP_STD:
242 val = TYPEC_CC_RP_DEF;
243 break;
244 case SNK_RP_1P5:
245 val = TYPEC_CC_RP_1_5;
246 break;
247 case SNK_RP_3P0:
248 val = TYPEC_CC_RP_3_0;
249 break;
250 default:
251 dev_warn(dev, "unexpected snk status %.2x\n", val);
252 val = TYPEC_CC_RP_DEF;
253 break;
254 }
255 val = TYPEC_CC_RP_DEF;
256 }
257
258 if (misc & CC_ORIENTATION)
259 *cc2 = val;
260 else
261 *cc1 = val;
262
263 done:
264 dev_dbg(dev, "get_cc: misc 0x%08x cc1 0x%08x %s cc2 0x%08x %s attached %d cc=%s\n",
265 misc, *cc1, cc_to_name(*cc1), *cc2, cc_to_name(*cc2), attached,
266 misc_to_cc(misc));
267
268 return ret;
269 }
270
qcom_pmic_set_cc_debounce(struct pmic_typec_port * pmic_typec_port)271 static void qcom_pmic_set_cc_debounce(struct pmic_typec_port *pmic_typec_port)
272 {
273 pmic_typec_port->debouncing_cc = true;
274 schedule_delayed_work(&pmic_typec_port->cc_debounce_dwork,
275 msecs_to_jiffies(2));
276 }
277
qcom_pmic_typec_port_set_cc(struct pmic_typec_port * pmic_typec_port,enum typec_cc_status cc)278 int qcom_pmic_typec_port_set_cc(struct pmic_typec_port *pmic_typec_port,
279 enum typec_cc_status cc)
280 {
281 struct device *dev = pmic_typec_port->dev;
282 unsigned int mode, currsrc;
283 unsigned int misc;
284 unsigned long flags;
285 int ret;
286
287 spin_lock_irqsave(&pmic_typec_port->lock, flags);
288
289 ret = regmap_read(pmic_typec_port->regmap,
290 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
291 &misc);
292 if (ret)
293 goto done;
294
295 mode = EN_SRC_ONLY;
296
297 switch (cc) {
298 case TYPEC_CC_OPEN:
299 currsrc = TYPEC_SRC_RP_SEL_80UA;
300 break;
301 case TYPEC_CC_RP_DEF:
302 currsrc = TYPEC_SRC_RP_SEL_80UA;
303 break;
304 case TYPEC_CC_RP_1_5:
305 currsrc = TYPEC_SRC_RP_SEL_180UA;
306 break;
307 case TYPEC_CC_RP_3_0:
308 currsrc = TYPEC_SRC_RP_SEL_330UA;
309 break;
310 case TYPEC_CC_RD:
311 currsrc = TYPEC_SRC_RP_SEL_80UA;
312 mode = EN_SNK_ONLY;
313 break;
314 default:
315 dev_warn(dev, "unexpected set_cc %d\n", cc);
316 ret = -EINVAL;
317 goto done;
318 }
319
320 if (mode == EN_SRC_ONLY) {
321 ret = regmap_write(pmic_typec_port->regmap,
322 pmic_typec_port->base + TYPEC_CURRSRC_CFG_REG,
323 currsrc);
324 if (ret)
325 goto done;
326 }
327
328 pmic_typec_port->cc = cc;
329 qcom_pmic_set_cc_debounce(pmic_typec_port);
330 ret = 0;
331
332 done:
333 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
334
335 dev_dbg(dev, "set_cc: currsrc=%x %s mode %s debounce %d attached %d cc=%s\n",
336 currsrc, rp_sel_to_name(currsrc),
337 mode == EN_SRC_ONLY ? "EN_SRC_ONLY" : "EN_SNK_ONLY",
338 pmic_typec_port->debouncing_cc, !!(misc & CC_ATTACHED),
339 misc_to_cc(misc));
340
341 return ret;
342 }
343
qcom_pmic_typec_port_set_vconn(struct pmic_typec_port * pmic_typec_port,bool on)344 int qcom_pmic_typec_port_set_vconn(struct pmic_typec_port *pmic_typec_port, bool on)
345 {
346 struct device *dev = pmic_typec_port->dev;
347 unsigned int orientation, misc, mask, value;
348 unsigned long flags;
349 int ret;
350
351 spin_lock_irqsave(&pmic_typec_port->lock, flags);
352
353 ret = regmap_read(pmic_typec_port->regmap,
354 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
355 if (ret)
356 goto done;
357
358 /* Set VCONN on the inversion of the active CC channel */
359 orientation = (misc & CC_ORIENTATION) ? 0 : VCONN_EN_ORIENTATION;
360 if (on) {
361 mask = VCONN_EN_ORIENTATION | VCONN_EN_VALUE;
362 value = orientation | VCONN_EN_VALUE | VCONN_EN_SRC;
363 } else {
364 mask = VCONN_EN_VALUE;
365 value = 0;
366 }
367
368 ret = regmap_update_bits(pmic_typec_port->regmap,
369 pmic_typec_port->base + TYPEC_VCONN_CONTROL_REG,
370 mask, value);
371 done:
372 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
373
374 dev_dbg(dev, "set_vconn: orientation %d control 0x%08x state %s cc %s vconn %s\n",
375 orientation, value, on ? "on" : "off", misc_to_vconn(misc), misc_to_cc(misc));
376
377 return ret;
378 }
379
qcom_pmic_typec_port_start_toggling(struct pmic_typec_port * pmic_typec_port,enum typec_port_type port_type,enum typec_cc_status cc)380 int qcom_pmic_typec_port_start_toggling(struct pmic_typec_port *pmic_typec_port,
381 enum typec_port_type port_type,
382 enum typec_cc_status cc)
383 {
384 struct device *dev = pmic_typec_port->dev;
385 unsigned int misc;
386 u8 mode = 0;
387 unsigned long flags;
388 int ret;
389
390 switch (port_type) {
391 case TYPEC_PORT_SRC:
392 mode = EN_SRC_ONLY;
393 break;
394 case TYPEC_PORT_SNK:
395 mode = EN_SNK_ONLY;
396 break;
397 case TYPEC_PORT_DRP:
398 mode = EN_TRY_SNK;
399 break;
400 }
401
402 spin_lock_irqsave(&pmic_typec_port->lock, flags);
403
404 ret = regmap_read(pmic_typec_port->regmap,
405 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
406 if (ret)
407 goto done;
408
409 dev_dbg(dev, "start_toggling: misc 0x%08x attached %d port_type %d current cc %d new %d\n",
410 misc, !!(misc & CC_ATTACHED), port_type, pmic_typec_port->cc, cc);
411
412 qcom_pmic_set_cc_debounce(pmic_typec_port);
413
414 /* force it to toggle at least once */
415 ret = regmap_write(pmic_typec_port->regmap,
416 pmic_typec_port->base + TYPEC_MODE_CFG_REG,
417 TYPEC_DISABLE_CMD);
418 if (ret)
419 goto done;
420
421 ret = regmap_write(pmic_typec_port->regmap,
422 pmic_typec_port->base + TYPEC_MODE_CFG_REG,
423 mode);
424 done:
425 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
426
427 return ret;
428 }
429
430 #define TYPEC_INTR_EN_CFG_1_MASK \
431 (TYPEC_LEGACY_CABLE_INT_EN | \
432 TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN | \
433 TYPEC_TRYSOURCE_DETECT_INT_EN | \
434 TYPEC_TRYSINK_DETECT_INT_EN | \
435 TYPEC_CCOUT_DETACH_INT_EN | \
436 TYPEC_CCOUT_ATTACH_INT_EN | \
437 TYPEC_VBUS_DEASSERT_INT_EN | \
438 TYPEC_VBUS_ASSERT_INT_EN)
439
440 #define TYPEC_INTR_EN_CFG_2_MASK \
441 (TYPEC_STATE_MACHINE_CHANGE_INT_EN | TYPEC_VBUS_ERROR_INT_EN | \
442 TYPEC_DEBOUNCE_DONE_INT_EN)
443
qcom_pmic_typec_port_start(struct pmic_typec_port * pmic_typec_port,struct tcpm_port * tcpm_port)444 int qcom_pmic_typec_port_start(struct pmic_typec_port *pmic_typec_port,
445 struct tcpm_port *tcpm_port)
446 {
447 int i;
448 int mask;
449 int ret;
450
451 /* Configure interrupt sources */
452 ret = regmap_write(pmic_typec_port->regmap,
453 pmic_typec_port->base + TYPEC_INTERRUPT_EN_CFG_1_REG,
454 TYPEC_INTR_EN_CFG_1_MASK);
455 if (ret)
456 goto done;
457
458 ret = regmap_write(pmic_typec_port->regmap,
459 pmic_typec_port->base + TYPEC_INTERRUPT_EN_CFG_2_REG,
460 TYPEC_INTR_EN_CFG_2_MASK);
461 if (ret)
462 goto done;
463
464 /* start in TRY_SNK mode */
465 ret = regmap_write(pmic_typec_port->regmap,
466 pmic_typec_port->base + TYPEC_MODE_CFG_REG, EN_TRY_SNK);
467 if (ret)
468 goto done;
469
470 /* Configure VCONN for software control */
471 ret = regmap_update_bits(pmic_typec_port->regmap,
472 pmic_typec_port->base + TYPEC_VCONN_CONTROL_REG,
473 VCONN_EN_SRC | VCONN_EN_VALUE, VCONN_EN_SRC);
474 if (ret)
475 goto done;
476
477 /* Set CC threshold to 1.6 Volts | tPDdebounce = 10-20ms */
478 mask = SEL_SRC_UPPER_REF | USE_TPD_FOR_EXITING_ATTACHSRC;
479 ret = regmap_update_bits(pmic_typec_port->regmap,
480 pmic_typec_port->base + TYPEC_EXIT_STATE_CFG_REG,
481 mask, mask);
482 if (ret)
483 goto done;
484
485 pmic_typec_port->tcpm_port = tcpm_port;
486
487 for (i = 0; i < pmic_typec_port->nr_irqs; i++)
488 enable_irq(pmic_typec_port->irq_data[i].irq);
489
490 done:
491 return ret;
492 }
493
qcom_pmic_typec_port_stop(struct pmic_typec_port * pmic_typec_port)494 void qcom_pmic_typec_port_stop(struct pmic_typec_port *pmic_typec_port)
495 {
496 int i;
497
498 for (i = 0; i < pmic_typec_port->nr_irqs; i++)
499 disable_irq(pmic_typec_port->irq_data[i].irq);
500 }
501
qcom_pmic_typec_port_alloc(struct device * dev)502 struct pmic_typec_port *qcom_pmic_typec_port_alloc(struct device *dev)
503 {
504 return devm_kzalloc(dev, sizeof(struct pmic_typec_port), GFP_KERNEL);
505 }
506
qcom_pmic_typec_port_probe(struct platform_device * pdev,struct pmic_typec_port * pmic_typec_port,struct pmic_typec_port_resources * res,struct regmap * regmap,u32 base)507 int qcom_pmic_typec_port_probe(struct platform_device *pdev,
508 struct pmic_typec_port *pmic_typec_port,
509 struct pmic_typec_port_resources *res,
510 struct regmap *regmap,
511 u32 base)
512 {
513 struct device *dev = &pdev->dev;
514 struct pmic_typec_port_irq_data *irq_data;
515 int i, ret, irq;
516
517 if (!res->nr_irqs || res->nr_irqs > PMIC_TYPEC_MAX_IRQS)
518 return -EINVAL;
519
520 irq_data = devm_kzalloc(dev, sizeof(*irq_data) * res->nr_irqs,
521 GFP_KERNEL);
522 if (!irq_data)
523 return -ENOMEM;
524
525 pmic_typec_port->vdd_vbus = devm_regulator_get(dev, "vdd-vbus");
526 if (IS_ERR(pmic_typec_port->vdd_vbus))
527 return PTR_ERR(pmic_typec_port->vdd_vbus);
528
529 pmic_typec_port->dev = dev;
530 pmic_typec_port->base = base;
531 pmic_typec_port->regmap = regmap;
532 pmic_typec_port->nr_irqs = res->nr_irqs;
533 pmic_typec_port->irq_data = irq_data;
534 spin_lock_init(&pmic_typec_port->lock);
535 INIT_DELAYED_WORK(&pmic_typec_port->cc_debounce_dwork,
536 qcom_pmic_typec_port_cc_debounce);
537
538 irq = platform_get_irq(pdev, 0);
539 if (irq < 0)
540 return irq;
541
542 for (i = 0; i < res->nr_irqs; i++, irq_data++) {
543 irq = platform_get_irq_byname(pdev,
544 res->irq_params[i].irq_name);
545 if (irq < 0)
546 return irq;
547
548 irq_data->pmic_typec_port = pmic_typec_port;
549 irq_data->irq = irq;
550 irq_data->virq = res->irq_params[i].virq;
551 ret = devm_request_threaded_irq(dev, irq, NULL, pmic_typec_port_isr,
552 IRQF_ONESHOT | IRQF_NO_AUTOEN,
553 res->irq_params[i].irq_name,
554 irq_data);
555 if (ret)
556 return ret;
557 }
558
559 return 0;
560 }
561