1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/clk-provider.h>
8 #include <linux/cpufreq.h>
9 #include <linux/init.h>
10 #include <linux/interconnect.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_opp.h>
17 #include <linux/slab.h>
18 #include <linux/spinlock.h>
19 #include <linux/units.h>
20
21 #define LUT_MAX_ENTRIES 40U
22 #define LUT_SRC GENMASK(31, 30)
23 #define LUT_L_VAL GENMASK(7, 0)
24 #define LUT_CORE_COUNT GENMASK(18, 16)
25 #define LUT_VOLT GENMASK(11, 0)
26 #define CLK_HW_DIV 2
27 #define LUT_TURBO_IND 1
28
29 #define GT_IRQ_STATUS BIT(2)
30
31 #define MAX_FREQ_DOMAINS 4
32
33 struct qcom_cpufreq_soc_data {
34 u32 reg_enable;
35 u32 reg_domain_state;
36 u32 reg_dcvs_ctrl;
37 u32 reg_freq_lut;
38 u32 reg_volt_lut;
39 u32 reg_intr_clr;
40 u32 reg_current_vote;
41 u32 reg_perf_state;
42 u8 lut_row_size;
43 };
44
45 struct qcom_cpufreq_data {
46 void __iomem *base;
47
48 /*
49 * Mutex to synchronize between de-init sequence and re-starting LMh
50 * polling/interrupts
51 */
52 struct mutex throttle_lock;
53 int throttle_irq;
54 char irq_name[15];
55 bool cancel_throttle;
56 struct delayed_work throttle_work;
57 struct cpufreq_policy *policy;
58 struct clk_hw cpu_clk;
59
60 bool per_core_dcvs;
61 };
62
63 static struct {
64 struct qcom_cpufreq_data *data;
65 const struct qcom_cpufreq_soc_data *soc_data;
66 } qcom_cpufreq;
67
68 static unsigned long cpu_hw_rate, xo_rate;
69 static bool icc_scaling_enabled;
70
qcom_cpufreq_set_bw(struct cpufreq_policy * policy,unsigned long freq_khz)71 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
72 unsigned long freq_khz)
73 {
74 unsigned long freq_hz = freq_khz * 1000;
75 struct dev_pm_opp *opp;
76 struct device *dev;
77 int ret;
78
79 dev = get_cpu_device(policy->cpu);
80 if (!dev)
81 return -ENODEV;
82
83 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
84 if (IS_ERR(opp))
85 return PTR_ERR(opp);
86
87 ret = dev_pm_opp_set_opp(dev, opp);
88 dev_pm_opp_put(opp);
89 return ret;
90 }
91
qcom_cpufreq_update_opp(struct device * cpu_dev,unsigned long freq_khz,unsigned long volt)92 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
93 unsigned long freq_khz,
94 unsigned long volt)
95 {
96 unsigned long freq_hz = freq_khz * 1000;
97 int ret;
98
99 /* Skip voltage update if the opp table is not available */
100 if (!icc_scaling_enabled)
101 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
102
103 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
104 if (ret) {
105 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
106 return ret;
107 }
108
109 return dev_pm_opp_enable(cpu_dev, freq_hz);
110 }
111
qcom_cpufreq_hw_target_index(struct cpufreq_policy * policy,unsigned int index)112 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
113 unsigned int index)
114 {
115 struct qcom_cpufreq_data *data = policy->driver_data;
116 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data;
117 unsigned long freq = policy->freq_table[index].frequency;
118 unsigned int i;
119
120 writel_relaxed(index, data->base + soc_data->reg_perf_state);
121
122 if (data->per_core_dcvs)
123 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
124 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
125
126 if (icc_scaling_enabled)
127 qcom_cpufreq_set_bw(policy, freq);
128
129 return 0;
130 }
131
qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data * data)132 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
133 {
134 unsigned int lval;
135
136 if (qcom_cpufreq.soc_data->reg_current_vote)
137 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_vote) & 0x3ff;
138 else
139 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_state) & 0xff;
140
141 return lval * xo_rate;
142 }
143
144 /* Get the frequency requested by the cpufreq core for the CPU */
qcom_cpufreq_get_freq(struct cpufreq_policy * policy)145 static unsigned int qcom_cpufreq_get_freq(struct cpufreq_policy *policy)
146 {
147 struct qcom_cpufreq_data *data;
148 const struct qcom_cpufreq_soc_data *soc_data;
149 unsigned int index;
150
151 if (!policy)
152 return 0;
153
154 data = policy->driver_data;
155 soc_data = qcom_cpufreq.soc_data;
156
157 index = readl_relaxed(data->base + soc_data->reg_perf_state);
158 index = min(index, LUT_MAX_ENTRIES - 1);
159
160 return policy->freq_table[index].frequency;
161 }
162
__qcom_cpufreq_hw_get(struct cpufreq_policy * policy)163 static unsigned int __qcom_cpufreq_hw_get(struct cpufreq_policy *policy)
164 {
165 struct qcom_cpufreq_data *data;
166
167 if (!policy)
168 return 0;
169
170 data = policy->driver_data;
171
172 if (data->throttle_irq >= 0)
173 return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ;
174
175 return qcom_cpufreq_get_freq(policy);
176 }
177
qcom_cpufreq_hw_get(unsigned int cpu)178 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
179 {
180 return __qcom_cpufreq_hw_get(cpufreq_cpu_get_raw(cpu));
181 }
182
qcom_cpufreq_hw_fast_switch(struct cpufreq_policy * policy,unsigned int target_freq)183 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
184 unsigned int target_freq)
185 {
186 struct qcom_cpufreq_data *data = policy->driver_data;
187 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data;
188 unsigned int index;
189 unsigned int i;
190
191 index = policy->cached_resolved_idx;
192 writel_relaxed(index, data->base + soc_data->reg_perf_state);
193
194 if (data->per_core_dcvs)
195 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
196 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
197
198 return policy->freq_table[index].frequency;
199 }
200
qcom_cpufreq_hw_read_lut(struct device * cpu_dev,struct cpufreq_policy * policy)201 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
202 struct cpufreq_policy *policy)
203 {
204 u32 data, src, lval, i, core_count, prev_freq = 0, freq;
205 u32 volt;
206 struct cpufreq_frequency_table *table;
207 struct dev_pm_opp *opp;
208 unsigned long rate;
209 int ret;
210 struct qcom_cpufreq_data *drv_data = policy->driver_data;
211 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data;
212
213 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
214 if (!table)
215 return -ENOMEM;
216
217 ret = dev_pm_opp_of_add_table(cpu_dev);
218 if (!ret) {
219 /* Disable all opps and cross-validate against LUT later */
220 icc_scaling_enabled = true;
221 for (rate = 0; ; rate++) {
222 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
223 if (IS_ERR(opp))
224 break;
225
226 dev_pm_opp_put(opp);
227 dev_pm_opp_disable(cpu_dev, rate);
228 }
229 } else if (ret != -ENODEV) {
230 dev_err(cpu_dev, "Invalid opp table in device tree\n");
231 kfree(table);
232 return ret;
233 } else {
234 policy->fast_switch_possible = true;
235 icc_scaling_enabled = false;
236 }
237
238 for (i = 0; i < LUT_MAX_ENTRIES; i++) {
239 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
240 i * soc_data->lut_row_size);
241 src = FIELD_GET(LUT_SRC, data);
242 lval = FIELD_GET(LUT_L_VAL, data);
243 core_count = FIELD_GET(LUT_CORE_COUNT, data);
244
245 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
246 i * soc_data->lut_row_size);
247 volt = FIELD_GET(LUT_VOLT, data) * 1000;
248
249 if (src)
250 freq = xo_rate * lval / 1000;
251 else
252 freq = cpu_hw_rate / 1000;
253
254 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
255 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
256 table[i].frequency = freq;
257 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
258 freq, core_count);
259 } else {
260 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
261 table[i].frequency = CPUFREQ_ENTRY_INVALID;
262 }
263
264 } else if (core_count == LUT_TURBO_IND) {
265 table[i].frequency = CPUFREQ_ENTRY_INVALID;
266 }
267
268 /*
269 * Two of the same frequencies with the same core counts means
270 * end of table
271 */
272 if (i > 0 && prev_freq == freq) {
273 struct cpufreq_frequency_table *prev = &table[i - 1];
274
275 /*
276 * Only treat the last frequency that might be a boost
277 * as the boost frequency
278 */
279 if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
280 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
281 prev->frequency = prev_freq;
282 prev->flags = CPUFREQ_BOOST_FREQ;
283 } else {
284 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
285 freq);
286 }
287 }
288
289 break;
290 }
291
292 prev_freq = freq;
293 }
294
295 table[i].frequency = CPUFREQ_TABLE_END;
296 policy->freq_table = table;
297 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
298
299 return 0;
300 }
301
qcom_get_related_cpus(int index,struct cpumask * m)302 static void qcom_get_related_cpus(int index, struct cpumask *m)
303 {
304 struct device_node *cpu_np;
305 struct of_phandle_args args;
306 int cpu, ret;
307
308 for_each_possible_cpu(cpu) {
309 cpu_np = of_cpu_device_node_get(cpu);
310 if (!cpu_np)
311 continue;
312
313 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
314 "#freq-domain-cells", 0,
315 &args);
316 of_node_put(cpu_np);
317 if (ret < 0)
318 continue;
319
320 if (index == args.args[0])
321 cpumask_set_cpu(cpu, m);
322 }
323 }
324
qcom_lmh_dcvs_notify(struct qcom_cpufreq_data * data)325 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
326 {
327 struct cpufreq_policy *policy = data->policy;
328 int cpu = cpumask_first(policy->related_cpus);
329 struct device *dev = get_cpu_device(cpu);
330 unsigned long freq_hz, throttled_freq;
331 struct dev_pm_opp *opp;
332
333 /*
334 * Get the h/w throttled frequency, normalize it using the
335 * registered opp table and use it to calculate thermal pressure.
336 */
337 freq_hz = qcom_lmh_get_throttle_freq(data);
338
339 opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
340 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
341 opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
342
343 if (IS_ERR(opp)) {
344 dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp);
345 } else {
346 dev_pm_opp_put(opp);
347 }
348
349 throttled_freq = freq_hz / HZ_PER_KHZ;
350
351 /* Update thermal pressure (the boost frequencies are accepted) */
352 arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
353
354 /*
355 * In the unlikely case policy is unregistered do not enable
356 * polling or h/w interrupt
357 */
358 mutex_lock(&data->throttle_lock);
359 if (data->cancel_throttle)
360 goto out;
361
362 /*
363 * If h/w throttled frequency is higher than what cpufreq has requested
364 * for, then stop polling and switch back to interrupt mechanism.
365 */
366 if (throttled_freq >= qcom_cpufreq_get_freq(cpufreq_cpu_get_raw(cpu)))
367 enable_irq(data->throttle_irq);
368 else
369 mod_delayed_work(system_highpri_wq, &data->throttle_work,
370 msecs_to_jiffies(10));
371
372 out:
373 mutex_unlock(&data->throttle_lock);
374 }
375
qcom_lmh_dcvs_poll(struct work_struct * work)376 static void qcom_lmh_dcvs_poll(struct work_struct *work)
377 {
378 struct qcom_cpufreq_data *data;
379
380 data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
381 qcom_lmh_dcvs_notify(data);
382 }
383
qcom_lmh_dcvs_handle_irq(int irq,void * data)384 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
385 {
386 struct qcom_cpufreq_data *c_data = data;
387
388 /* Disable interrupt and enable polling */
389 disable_irq_nosync(c_data->throttle_irq);
390 schedule_delayed_work(&c_data->throttle_work, 0);
391
392 if (qcom_cpufreq.soc_data->reg_intr_clr)
393 writel_relaxed(GT_IRQ_STATUS,
394 c_data->base + qcom_cpufreq.soc_data->reg_intr_clr);
395
396 return IRQ_HANDLED;
397 }
398
399 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
400 .reg_enable = 0x0,
401 .reg_dcvs_ctrl = 0xbc,
402 .reg_freq_lut = 0x110,
403 .reg_volt_lut = 0x114,
404 .reg_current_vote = 0x704,
405 .reg_perf_state = 0x920,
406 .lut_row_size = 32,
407 };
408
409 static const struct qcom_cpufreq_soc_data epss_soc_data = {
410 .reg_enable = 0x0,
411 .reg_domain_state = 0x20,
412 .reg_dcvs_ctrl = 0xb0,
413 .reg_freq_lut = 0x100,
414 .reg_volt_lut = 0x200,
415 .reg_intr_clr = 0x308,
416 .reg_perf_state = 0x320,
417 .lut_row_size = 4,
418 };
419
420 static const struct of_device_id qcom_cpufreq_hw_match[] = {
421 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
422 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
423 {}
424 };
425 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
426
qcom_cpufreq_hw_lmh_init(struct cpufreq_policy * policy,int index)427 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
428 {
429 struct qcom_cpufreq_data *data = policy->driver_data;
430 struct platform_device *pdev = cpufreq_get_driver_data();
431 int ret;
432
433 /*
434 * Look for LMh interrupt. If no interrupt line is specified /
435 * if there is an error, allow cpufreq to be enabled as usual.
436 */
437 data->throttle_irq = platform_get_irq_optional(pdev, index);
438 if (data->throttle_irq == -ENXIO)
439 return 0;
440 if (data->throttle_irq < 0)
441 return data->throttle_irq;
442
443 data->cancel_throttle = false;
444
445 mutex_init(&data->throttle_lock);
446 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
447
448 snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu);
449 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
450 IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data);
451 if (ret) {
452 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret);
453 return 0;
454 }
455
456 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
457 if (ret)
458 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
459 data->irq_name, data->throttle_irq);
460
461 return 0;
462 }
463
qcom_cpufreq_hw_cpu_online(struct cpufreq_policy * policy)464 static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
465 {
466 struct qcom_cpufreq_data *data = policy->driver_data;
467 struct platform_device *pdev = cpufreq_get_driver_data();
468 int ret;
469
470 if (data->throttle_irq <= 0)
471 return 0;
472
473 mutex_lock(&data->throttle_lock);
474 data->cancel_throttle = false;
475 mutex_unlock(&data->throttle_lock);
476
477 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
478 if (ret)
479 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
480 data->irq_name, data->throttle_irq);
481
482 return ret;
483 }
484
qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy * policy)485 static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
486 {
487 struct qcom_cpufreq_data *data = policy->driver_data;
488
489 if (data->throttle_irq <= 0)
490 return 0;
491
492 mutex_lock(&data->throttle_lock);
493 data->cancel_throttle = true;
494 mutex_unlock(&data->throttle_lock);
495
496 cancel_delayed_work_sync(&data->throttle_work);
497 irq_set_affinity_and_hint(data->throttle_irq, NULL);
498 disable_irq_nosync(data->throttle_irq);
499
500 return 0;
501 }
502
qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data * data)503 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
504 {
505 if (data->throttle_irq <= 0)
506 return;
507
508 free_irq(data->throttle_irq, data);
509 }
510
qcom_cpufreq_hw_cpu_init(struct cpufreq_policy * policy)511 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
512 {
513 struct platform_device *pdev = cpufreq_get_driver_data();
514 struct device *dev = &pdev->dev;
515 struct of_phandle_args args;
516 struct device_node *cpu_np;
517 struct device *cpu_dev;
518 struct qcom_cpufreq_data *data;
519 int ret, index;
520
521 cpu_dev = get_cpu_device(policy->cpu);
522 if (!cpu_dev) {
523 pr_err("%s: failed to get cpu%d device\n", __func__,
524 policy->cpu);
525 return -ENODEV;
526 }
527
528 cpu_np = of_cpu_device_node_get(policy->cpu);
529 if (!cpu_np)
530 return -EINVAL;
531
532 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
533 "#freq-domain-cells", 0, &args);
534 of_node_put(cpu_np);
535 if (ret)
536 return ret;
537
538 index = args.args[0];
539 data = &qcom_cpufreq.data[index];
540
541 /* HW should be in enabled state to proceed */
542 if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1)) {
543 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
544 return -ENODEV;
545 }
546
547 if (readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_dcvs_ctrl) & 0x1)
548 data->per_core_dcvs = true;
549
550 qcom_get_related_cpus(index, policy->cpus);
551
552 policy->driver_data = data;
553 policy->dvfs_possible_from_any_cpu = true;
554 data->policy = policy;
555
556 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
557 if (ret) {
558 dev_err(dev, "Domain-%d failed to read LUT\n", index);
559 return ret;
560 }
561
562 ret = dev_pm_opp_get_opp_count(cpu_dev);
563 if (ret <= 0) {
564 dev_err(cpu_dev, "Failed to add OPPs\n");
565 return -ENODEV;
566 }
567
568 if (policy_has_boost_freq(policy)) {
569 ret = cpufreq_enable_boost_support();
570 if (ret)
571 dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
572 }
573
574 return qcom_cpufreq_hw_lmh_init(policy, index);
575 }
576
qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy * policy)577 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
578 {
579 struct device *cpu_dev = get_cpu_device(policy->cpu);
580 struct qcom_cpufreq_data *data = policy->driver_data;
581
582 dev_pm_opp_remove_all_dynamic(cpu_dev);
583 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
584 qcom_cpufreq_hw_lmh_exit(data);
585 kfree(policy->freq_table);
586 kfree(data);
587
588 return 0;
589 }
590
qcom_cpufreq_ready(struct cpufreq_policy * policy)591 static void qcom_cpufreq_ready(struct cpufreq_policy *policy)
592 {
593 struct qcom_cpufreq_data *data = policy->driver_data;
594
595 if (data->throttle_irq >= 0)
596 enable_irq(data->throttle_irq);
597 }
598
599 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
600 &cpufreq_freq_attr_scaling_available_freqs,
601 &cpufreq_freq_attr_scaling_boost_freqs,
602 NULL
603 };
604
605 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
606 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
607 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
608 CPUFREQ_IS_COOLING_DEV,
609 .verify = cpufreq_generic_frequency_table_verify,
610 .target_index = qcom_cpufreq_hw_target_index,
611 .get = qcom_cpufreq_hw_get,
612 .init = qcom_cpufreq_hw_cpu_init,
613 .exit = qcom_cpufreq_hw_cpu_exit,
614 .online = qcom_cpufreq_hw_cpu_online,
615 .offline = qcom_cpufreq_hw_cpu_offline,
616 .register_em = cpufreq_register_em_with_opp,
617 .fast_switch = qcom_cpufreq_hw_fast_switch,
618 .name = "qcom-cpufreq-hw",
619 .attr = qcom_cpufreq_hw_attr,
620 .ready = qcom_cpufreq_ready,
621 };
622
qcom_cpufreq_hw_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)623 static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
624 {
625 struct qcom_cpufreq_data *data = container_of(hw, struct qcom_cpufreq_data, cpu_clk);
626
627 return __qcom_cpufreq_hw_get(data->policy) * HZ_PER_KHZ;
628 }
629
630 /*
631 * Since we cannot determine the closest rate of the target rate, let's just
632 * return the actual rate at which the clock is running at. This is needed to
633 * make clk_set_rate() API work properly.
634 */
qcom_cpufreq_hw_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)635 static int qcom_cpufreq_hw_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
636 {
637 req->rate = qcom_cpufreq_hw_recalc_rate(hw, 0);
638
639 return 0;
640 }
641
642 static const struct clk_ops qcom_cpufreq_hw_clk_ops = {
643 .recalc_rate = qcom_cpufreq_hw_recalc_rate,
644 .determine_rate = qcom_cpufreq_hw_determine_rate,
645 };
646
qcom_cpufreq_hw_driver_probe(struct platform_device * pdev)647 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
648 {
649 struct clk_hw_onecell_data *clk_data;
650 struct device *dev = &pdev->dev;
651 struct device *cpu_dev;
652 struct clk *clk;
653 int ret, i, num_domains;
654
655 clk = clk_get(dev, "xo");
656 if (IS_ERR(clk))
657 return PTR_ERR(clk);
658
659 xo_rate = clk_get_rate(clk);
660 clk_put(clk);
661
662 clk = clk_get(dev, "alternate");
663 if (IS_ERR(clk))
664 return PTR_ERR(clk);
665
666 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
667 clk_put(clk);
668
669 cpufreq_qcom_hw_driver.driver_data = pdev;
670
671 /* Check for optional interconnect paths on CPU0 */
672 cpu_dev = get_cpu_device(0);
673 if (!cpu_dev)
674 return -EPROBE_DEFER;
675
676 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
677 if (ret)
678 return dev_err_probe(dev, ret, "Failed to find icc paths\n");
679
680 for (num_domains = 0; num_domains < MAX_FREQ_DOMAINS; num_domains++)
681 if (!platform_get_resource(pdev, IORESOURCE_MEM, num_domains))
682 break;
683
684 qcom_cpufreq.data = devm_kzalloc(dev, sizeof(struct qcom_cpufreq_data) * num_domains,
685 GFP_KERNEL);
686 if (!qcom_cpufreq.data)
687 return -ENOMEM;
688
689 qcom_cpufreq.soc_data = of_device_get_match_data(dev);
690 if (!qcom_cpufreq.soc_data)
691 return -ENODEV;
692
693 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), GFP_KERNEL);
694 if (!clk_data)
695 return -ENOMEM;
696
697 clk_data->num = num_domains;
698
699 for (i = 0; i < num_domains; i++) {
700 struct qcom_cpufreq_data *data = &qcom_cpufreq.data[i];
701 struct clk_init_data clk_init = {};
702 void __iomem *base;
703
704 base = devm_platform_ioremap_resource(pdev, i);
705 if (IS_ERR(base)) {
706 dev_err(dev, "Failed to map resource index %d\n", i);
707 return PTR_ERR(base);
708 }
709
710 data->base = base;
711
712 /* Register CPU clock for each frequency domain */
713 clk_init.name = kasprintf(GFP_KERNEL, "qcom_cpufreq%d", i);
714 if (!clk_init.name)
715 return -ENOMEM;
716
717 clk_init.flags = CLK_GET_RATE_NOCACHE;
718 clk_init.ops = &qcom_cpufreq_hw_clk_ops;
719 data->cpu_clk.init = &clk_init;
720
721 ret = devm_clk_hw_register(dev, &data->cpu_clk);
722 if (ret < 0) {
723 dev_err(dev, "Failed to register clock %d: %d\n", i, ret);
724 kfree(clk_init.name);
725 return ret;
726 }
727
728 clk_data->hws[i] = &data->cpu_clk;
729 kfree(clk_init.name);
730 }
731
732 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
733 if (ret < 0) {
734 dev_err(dev, "Failed to add clock provider\n");
735 return ret;
736 }
737
738 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
739 if (ret)
740 dev_err(dev, "CPUFreq HW driver failed to register\n");
741 else
742 dev_dbg(dev, "QCOM CPUFreq HW driver initialized\n");
743
744 return ret;
745 }
746
qcom_cpufreq_hw_driver_remove(struct platform_device * pdev)747 static void qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
748 {
749 cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
750 }
751
752 static struct platform_driver qcom_cpufreq_hw_driver = {
753 .probe = qcom_cpufreq_hw_driver_probe,
754 .remove_new = qcom_cpufreq_hw_driver_remove,
755 .driver = {
756 .name = "qcom-cpufreq-hw",
757 .of_match_table = qcom_cpufreq_hw_match,
758 },
759 };
760
qcom_cpufreq_hw_init(void)761 static int __init qcom_cpufreq_hw_init(void)
762 {
763 return platform_driver_register(&qcom_cpufreq_hw_driver);
764 }
765 postcore_initcall(qcom_cpufreq_hw_init);
766
qcom_cpufreq_hw_exit(void)767 static void __exit qcom_cpufreq_hw_exit(void)
768 {
769 platform_driver_unregister(&qcom_cpufreq_hw_driver);
770 }
771 module_exit(qcom_cpufreq_hw_exit);
772
773 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
774 MODULE_LICENSE("GPL v2");
775