1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "kvm/tdx.h" 32 #include "sev.h" 33 #include "qapi/error.h" 34 #include "qemu/error-report.h" 35 #include "qapi/qapi-visit-machine.h" 36 #include "standard-headers/asm-x86/kvm_para.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/i386/topology.h" 39 #include "exec/watchpoint.h" 40 #ifndef CONFIG_USER_ONLY 41 #include "confidential-guest.h" 42 #include "system/reset.h" 43 #include "qapi/qapi-commands-machine.h" 44 #include "system/address-spaces.h" 45 #include "hw/boards.h" 46 #include "hw/i386/sgx-epc.h" 47 #endif 48 #include "system/qtest.h" 49 #include "tcg/tcg-cpu.h" 50 51 #include "disas/capstone.h" 52 #include "cpu-internal.h" 53 54 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 55 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 56 uint32_t *eax, uint32_t *ebx, 57 uint32_t *ecx, uint32_t *edx); 58 59 /* Helpers for building CPUID[2] descriptors: */ 60 61 struct CPUID2CacheDescriptorInfo { 62 enum CacheType type; 63 int level; 64 int size; 65 int line_size; 66 int associativity; 67 }; 68 69 /* 70 * Known CPUID 2 cache descriptors. 71 * TLB, prefetch and sectored cache related descriptors are not included. 72 * From Intel SDM Volume 2A, CPUID instruction 73 */ 74 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 75 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 76 .associativity = 4, .line_size = 32, }, 77 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 78 .associativity = 4, .line_size = 32, }, 79 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 80 .associativity = 4, .line_size = 64, }, 81 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 82 .associativity = 2, .line_size = 32, }, 83 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 84 .associativity = 4, .line_size = 32, }, 85 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 86 .associativity = 4, .line_size = 64, }, 87 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 88 .associativity = 6, .line_size = 64, }, 89 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 90 .associativity = 2, .line_size = 64, }, 91 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 /* 94 * lines per sector is not supported cpuid2_cache_descriptor(), 95 * so descriptors 0x22, 0x23 are not included 96 */ 97 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 98 .associativity = 16, .line_size = 64, }, 99 /* 100 * lines per sector is not supported cpuid2_cache_descriptor(), 101 * so descriptors 0x25, 0x29 are not included 102 */ 103 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 104 .associativity = 8, .line_size = 64, }, 105 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 106 .associativity = 8, .line_size = 64, }, 107 /* 108 * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL) 109 * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2 110 * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid 111 * to just ignore L3's code if there's no L3. 112 * 113 * This already covers all the cases in QEMU, so code 0x40 is not 114 * included. 115 */ 116 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 117 .associativity = 4, .line_size = 32, }, 118 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 119 .associativity = 4, .line_size = 32, }, 120 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 121 .associativity = 4, .line_size = 32, }, 122 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 123 .associativity = 4, .line_size = 32, }, 124 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 125 .associativity = 4, .line_size = 32, }, 126 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 129 .associativity = 8, .line_size = 64, }, 130 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 131 .associativity = 12, .line_size = 64, }, 132 /* 133 * Descriptor 0x49 has 2 cases: 134 * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size. 135 * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size 136 * (Intel Xeon processor MP, Family 0FH, Model 06H). 137 * 138 * When it represents L3, then it depends on CPU family/model. Fortunately, 139 * the legacy cache/CPU models don't have such special L3. So, just add it 140 * to represent the general L2 case. 141 */ 142 [0x49] = { .level = 2, .type = UNIFIED_CACHE, .size = 4 * MiB, 143 .associativity = 16, .line_size = 64, }, 144 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 145 .associativity = 12, .line_size = 64, }, 146 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 147 .associativity = 16, .line_size = 64, }, 148 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 149 .associativity = 12, .line_size = 64, }, 150 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 151 .associativity = 16, .line_size = 64, }, 152 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 153 .associativity = 24, .line_size = 64, }, 154 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 155 .associativity = 8, .line_size = 64, }, 156 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 157 .associativity = 4, .line_size = 64, }, 158 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 159 .associativity = 4, .line_size = 64, }, 160 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 161 .associativity = 4, .line_size = 64, }, 162 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 163 .associativity = 4, .line_size = 64, }, 164 /* 165 * lines per sector is not supported cpuid2_cache_descriptor(), 166 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 167 */ 168 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 169 .associativity = 8, .line_size = 64, }, 170 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 171 .associativity = 2, .line_size = 64, }, 172 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 173 .associativity = 8, .line_size = 64, }, 174 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 175 .associativity = 8, .line_size = 32, }, 176 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 177 .associativity = 8, .line_size = 32, }, 178 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 179 .associativity = 8, .line_size = 32, }, 180 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 181 .associativity = 8, .line_size = 32, }, 182 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 183 .associativity = 4, .line_size = 64, }, 184 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 185 .associativity = 8, .line_size = 64, }, 186 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 187 .associativity = 4, .line_size = 64, }, 188 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 189 .associativity = 4, .line_size = 64, }, 190 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 191 .associativity = 4, .line_size = 64, }, 192 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 193 .associativity = 8, .line_size = 64, }, 194 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 195 .associativity = 8, .line_size = 64, }, 196 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 197 .associativity = 8, .line_size = 64, }, 198 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 199 .associativity = 12, .line_size = 64, }, 200 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 201 .associativity = 12, .line_size = 64, }, 202 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 203 .associativity = 12, .line_size = 64, }, 204 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 205 .associativity = 16, .line_size = 64, }, 206 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 207 .associativity = 16, .line_size = 64, }, 208 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 209 .associativity = 16, .line_size = 64, }, 210 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 211 .associativity = 24, .line_size = 64, }, 212 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 213 .associativity = 24, .line_size = 64, }, 214 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 215 .associativity = 24, .line_size = 64, }, 216 }; 217 218 /* 219 * "CPUID leaf 2 does not report cache descriptor information, 220 * use CPUID leaf 4 to query cache parameters" 221 */ 222 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 223 224 /* 225 * Return a CPUID 2 cache descriptor for a given cache. 226 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 227 */ 228 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache, bool *unmacthed) 229 { 230 int i; 231 232 assert(cache->size > 0); 233 assert(cache->level > 0); 234 assert(cache->line_size > 0); 235 assert(cache->associativity > 0); 236 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 237 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 238 if (d->level == cache->level && d->type == cache->type && 239 d->size == cache->size && d->line_size == cache->line_size && 240 d->associativity == cache->associativity) { 241 return i; 242 } 243 } 244 245 *unmacthed |= true; 246 return CACHE_DESCRIPTOR_UNAVAILABLE; 247 } 248 249 static const CPUCaches legacy_intel_cpuid2_cache_info; 250 251 /* Encode cache info for CPUID[2] */ 252 static void encode_cache_cpuid2(X86CPU *cpu, 253 const CPUCaches *caches, 254 uint32_t *eax, uint32_t *ebx, 255 uint32_t *ecx, uint32_t *edx) 256 { 257 CPUX86State *env = &cpu->env; 258 int l1d, l1i, l2, l3; 259 bool unmatched = false; 260 261 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 262 *ebx = *ecx = *edx = 0; 263 264 l1d = cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); 265 l1i = cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); 266 l2 = cpuid2_cache_descriptor(caches->l2_cache, &unmatched); 267 l3 = cpuid2_cache_descriptor(caches->l3_cache, &unmatched); 268 269 if (!cpu->consistent_cache || 270 (env->cpuid_min_level < 0x4 && !unmatched)) { 271 /* 272 * Though SDM defines code 0x40 for cases with no L2 or L3. It's 273 * also valid to just ignore l3's code if there's no l2. 274 */ 275 if (cpu->enable_l3_cache) { 276 *ecx = l3; 277 } 278 *edx = (l1d << 16) | (l1i << 8) | l2; 279 } else { 280 *ecx = 0; 281 *edx = CACHE_DESCRIPTOR_UNAVAILABLE; 282 } 283 } 284 285 /* CPUID Leaf 4 constants: */ 286 287 /* EAX: */ 288 #define CACHE_TYPE_D 1 289 #define CACHE_TYPE_I 2 290 #define CACHE_TYPE_UNIFIED 3 291 292 #define CACHE_LEVEL(l) (l << 5) 293 294 #define CACHE_SELF_INIT_LEVEL (1 << 8) 295 296 /* EDX: */ 297 #define CACHE_NO_INVD_SHARING (1 << 0) 298 #define CACHE_INCLUSIVE (1 << 1) 299 #define CACHE_COMPLEX_IDX (1 << 2) 300 301 /* Encode CacheType for CPUID[4].EAX */ 302 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 303 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 304 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 305 0 /* Invalid value */) 306 307 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 308 enum CpuTopologyLevel share_level) 309 { 310 uint32_t num_ids = 0; 311 312 switch (share_level) { 313 case CPU_TOPOLOGY_LEVEL_CORE: 314 num_ids = 1 << apicid_core_offset(topo_info); 315 break; 316 case CPU_TOPOLOGY_LEVEL_MODULE: 317 num_ids = 1 << apicid_module_offset(topo_info); 318 break; 319 case CPU_TOPOLOGY_LEVEL_DIE: 320 num_ids = 1 << apicid_die_offset(topo_info); 321 break; 322 case CPU_TOPOLOGY_LEVEL_SOCKET: 323 num_ids = 1 << apicid_pkg_offset(topo_info); 324 break; 325 default: 326 /* 327 * Currently there is no use case for THREAD, so use 328 * assert directly to facilitate debugging. 329 */ 330 g_assert_not_reached(); 331 } 332 333 return num_ids - 1; 334 } 335 336 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 337 { 338 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 339 apicid_core_offset(topo_info)); 340 return num_cores - 1; 341 } 342 343 /* Encode cache info for CPUID[4] */ 344 static void encode_cache_cpuid4(CPUCacheInfo *cache, 345 X86CPUTopoInfo *topo_info, 346 uint32_t *eax, uint32_t *ebx, 347 uint32_t *ecx, uint32_t *edx) 348 { 349 assert(cache->size == cache->line_size * cache->associativity * 350 cache->partitions * cache->sets); 351 352 /* 353 * The following fields have bit-width limitations, so consider the 354 * maximum values to avoid overflow: 355 * Bits 25-14: maximum 4095. 356 * Bits 31-26: maximum 63. 357 */ 358 *eax = CACHE_TYPE(cache->type) | 359 CACHE_LEVEL(cache->level) | 360 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 361 (MIN(max_core_ids_in_package(topo_info), 63) << 26) | 362 (MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14); 363 364 assert(cache->line_size > 0); 365 assert(cache->partitions > 0); 366 assert(cache->associativity > 0); 367 /* We don't implement fully-associative caches */ 368 assert(cache->associativity < cache->sets); 369 *ebx = (cache->line_size - 1) | 370 ((cache->partitions - 1) << 12) | 371 ((cache->associativity - 1) << 22); 372 373 assert(cache->sets > 0); 374 *ecx = cache->sets - 1; 375 376 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 377 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 378 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 379 } 380 381 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 382 enum CpuTopologyLevel topo_level) 383 { 384 switch (topo_level) { 385 case CPU_TOPOLOGY_LEVEL_THREAD: 386 return 1; 387 case CPU_TOPOLOGY_LEVEL_CORE: 388 return topo_info->threads_per_core; 389 case CPU_TOPOLOGY_LEVEL_MODULE: 390 return x86_threads_per_module(topo_info); 391 case CPU_TOPOLOGY_LEVEL_DIE: 392 return x86_threads_per_die(topo_info); 393 case CPU_TOPOLOGY_LEVEL_SOCKET: 394 return x86_threads_per_pkg(topo_info); 395 default: 396 g_assert_not_reached(); 397 } 398 return 0; 399 } 400 401 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 402 enum CpuTopologyLevel topo_level) 403 { 404 switch (topo_level) { 405 case CPU_TOPOLOGY_LEVEL_THREAD: 406 return 0; 407 case CPU_TOPOLOGY_LEVEL_CORE: 408 return apicid_core_offset(topo_info); 409 case CPU_TOPOLOGY_LEVEL_MODULE: 410 return apicid_module_offset(topo_info); 411 case CPU_TOPOLOGY_LEVEL_DIE: 412 return apicid_die_offset(topo_info); 413 case CPU_TOPOLOGY_LEVEL_SOCKET: 414 return apicid_pkg_offset(topo_info); 415 default: 416 g_assert_not_reached(); 417 } 418 return 0; 419 } 420 421 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 422 { 423 switch (topo_level) { 424 case CPU_TOPOLOGY_LEVEL_INVALID: 425 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 426 case CPU_TOPOLOGY_LEVEL_THREAD: 427 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 428 case CPU_TOPOLOGY_LEVEL_CORE: 429 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 430 case CPU_TOPOLOGY_LEVEL_MODULE: 431 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 432 case CPU_TOPOLOGY_LEVEL_DIE: 433 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 434 default: 435 /* Other types are not supported in QEMU. */ 436 g_assert_not_reached(); 437 } 438 return 0; 439 } 440 441 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 442 X86CPUTopoInfo *topo_info, 443 uint32_t *eax, uint32_t *ebx, 444 uint32_t *ecx, uint32_t *edx) 445 { 446 X86CPU *cpu = env_archcpu(env); 447 unsigned long level, base_level, next_level; 448 uint32_t num_threads_next_level, offset_next_level; 449 450 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 451 452 /* 453 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 454 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 455 */ 456 level = CPU_TOPOLOGY_LEVEL_THREAD; 457 base_level = level; 458 for (int i = 0; i <= count; i++) { 459 level = find_next_bit(env->avail_cpu_topo, 460 CPU_TOPOLOGY_LEVEL_SOCKET, 461 base_level); 462 463 /* 464 * CPUID[0x1f] doesn't explicitly encode the package level, 465 * and it just encodes the invalid level (all fields are 0) 466 * into the last subleaf of 0x1f. 467 */ 468 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 469 level = CPU_TOPOLOGY_LEVEL_INVALID; 470 break; 471 } 472 /* Search the next level. */ 473 base_level = level + 1; 474 } 475 476 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 477 num_threads_next_level = 0; 478 offset_next_level = 0; 479 } else { 480 next_level = find_next_bit(env->avail_cpu_topo, 481 CPU_TOPOLOGY_LEVEL_SOCKET, 482 level + 1); 483 num_threads_next_level = num_threads_by_topo_level(topo_info, 484 next_level); 485 offset_next_level = apicid_offset_by_topo_level(topo_info, 486 next_level); 487 } 488 489 *eax = offset_next_level; 490 /* The count (bits 15-00) doesn't need to be reliable. */ 491 *ebx = num_threads_next_level & 0xffff; 492 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 493 *edx = cpu->apic_id; 494 495 assert(!(*eax & ~0x1f)); 496 } 497 498 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 499 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 500 { 501 assert(cache->size % 1024 == 0); 502 assert(cache->associativity > 0); 503 assert(cache->line_size > 0); 504 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 505 (cache->lines_per_tag << 8) | (cache->line_size); 506 } 507 508 #define ASSOC_FULL 0xFF 509 510 /* x86 associativity encoding used on CPUID Leaf 0x80000006: */ 511 #define X86_ENC_ASSOC(a) (a <= 1 ? a : \ 512 a == 2 ? 0x2 : \ 513 a == 4 ? 0x4 : \ 514 a == 8 ? 0x6 : \ 515 a == 16 ? 0x8 : \ 516 a == 32 ? 0xA : \ 517 a == 48 ? 0xB : \ 518 a == 64 ? 0xC : \ 519 a == 96 ? 0xD : \ 520 a == 128 ? 0xE : \ 521 a == ASSOC_FULL ? 0xF : \ 522 0 /* invalid value */) 523 524 /* 525 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 526 * @l3 can be NULL. 527 */ 528 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 529 CPUCacheInfo *l3, 530 uint32_t *ecx, uint32_t *edx) 531 { 532 assert(l2->size % 1024 == 0); 533 assert(l2->associativity > 0); 534 assert(l2->line_size > 0); 535 *ecx = ((l2->size / 1024) << 16) | 536 (X86_ENC_ASSOC(l2->associativity) << 12) | 537 (l2->lines_per_tag << 8) | (l2->line_size); 538 539 /* For Intel, EDX is reserved. */ 540 if (l3) { 541 assert(l3->size % (512 * 1024) == 0); 542 assert(l3->associativity > 0); 543 assert(l3->line_size > 0); 544 *edx = ((l3->size / (512 * 1024)) << 18) | 545 (X86_ENC_ASSOC(l3->associativity) << 12) | 546 (l3->lines_per_tag << 8) | (l3->line_size); 547 } else { 548 *edx = 0; 549 } 550 } 551 552 /* Encode cache info for CPUID[8000001D] */ 553 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 554 X86CPUTopoInfo *topo_info, 555 uint32_t *eax, uint32_t *ebx, 556 uint32_t *ecx, uint32_t *edx) 557 { 558 assert(cache->size == cache->line_size * cache->associativity * 559 cache->partitions * cache->sets); 560 561 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 562 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 563 /* Bits 25:14 - NumSharingCache: maximum 4095. */ 564 *eax |= MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14; 565 566 assert(cache->line_size > 0); 567 assert(cache->partitions > 0); 568 assert(cache->associativity > 0); 569 /* We don't implement fully-associative caches */ 570 assert(cache->associativity < cache->sets); 571 *ebx = (cache->line_size - 1) | 572 ((cache->partitions - 1) << 12) | 573 ((cache->associativity - 1) << 22); 574 575 assert(cache->sets > 0); 576 *ecx = cache->sets - 1; 577 578 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 579 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 580 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 581 } 582 583 /* Encode cache info for CPUID[8000001E] */ 584 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 585 uint32_t *eax, uint32_t *ebx, 586 uint32_t *ecx, uint32_t *edx) 587 { 588 X86CPUTopoIDs topo_ids; 589 590 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 591 592 *eax = cpu->apic_id; 593 594 /* 595 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 596 * Read-only. Reset: 0000_XXXXh. 597 * See Core::X86::Cpuid::ExtApicId. 598 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 599 * Bits Description 600 * 31:16 Reserved. 601 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 602 * The number of threads per core is ThreadsPerCore+1. 603 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 604 * 605 * NOTE: CoreId is already part of apic_id. Just use it. We can 606 * use all the 8 bits to represent the core_id here. 607 */ 608 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 609 610 /* 611 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 612 * Read-only. Reset: 0000_0XXXh. 613 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 614 * Bits Description 615 * 31:11 Reserved. 616 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 617 * ValidValues: 618 * Value Description 619 * 0h 1 node per processor. 620 * 7h-1h Reserved. 621 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 622 * 623 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 624 * But users can create more nodes than the actual hardware can 625 * support. To genaralize we can use all the upper 8 bits for nodes. 626 * NodeId is combination of node and socket_id which is already decoded 627 * in apic_id. Just use it by shifting. 628 */ 629 if (cpu->legacy_multi_node) { 630 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 631 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 632 } else { 633 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 634 } 635 636 *edx = 0; 637 } 638 639 /* 640 * Definitions of the hardcoded cache entries we expose: 641 * These are legacy cache values. If there is a need to change any 642 * of these values please use builtin_x86_defs 643 */ 644 static const CPUCaches legacy_amd_cache_info = { 645 .l1d_cache = &(CPUCacheInfo) { 646 .type = DATA_CACHE, 647 .level = 1, 648 .size = 64 * KiB, 649 .self_init = 1, 650 .line_size = 64, 651 .associativity = 2, 652 .sets = 512, 653 .partitions = 1, 654 .lines_per_tag = 1, 655 .no_invd_sharing = true, 656 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 657 }, 658 .l1i_cache = &(CPUCacheInfo) { 659 .type = INSTRUCTION_CACHE, 660 .level = 1, 661 .size = 64 * KiB, 662 .self_init = 1, 663 .line_size = 64, 664 .associativity = 2, 665 .sets = 512, 666 .partitions = 1, 667 .lines_per_tag = 1, 668 .no_invd_sharing = true, 669 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 670 }, 671 .l2_cache = &(CPUCacheInfo) { 672 .type = UNIFIED_CACHE, 673 .level = 2, 674 .size = 512 * KiB, 675 .line_size = 64, 676 .lines_per_tag = 1, 677 .associativity = 16, 678 .sets = 512, 679 .partitions = 1, 680 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 681 }, 682 .l3_cache = &(CPUCacheInfo) { 683 .type = UNIFIED_CACHE, 684 .level = 3, 685 .size = 16 * MiB, 686 .line_size = 64, 687 .associativity = 16, 688 .sets = 16384, 689 .partitions = 1, 690 .lines_per_tag = 1, 691 .self_init = true, 692 .inclusive = true, 693 .complex_indexing = true, 694 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 695 }, 696 }; 697 698 /* 699 * Only used for the CPU models with CPUID level < 4. 700 * These CPUs (CPUID level < 4) only use CPUID leaf 2 to present 701 * cache information. 702 * 703 * Note: This cache model is just a default one, and is not 704 * guaranteed to match real hardwares. 705 */ 706 static const CPUCaches legacy_intel_cpuid2_cache_info = { 707 .l1d_cache = &(CPUCacheInfo) { 708 .type = DATA_CACHE, 709 .level = 1, 710 .size = 32 * KiB, 711 .self_init = 1, 712 .line_size = 64, 713 .associativity = 8, 714 .sets = 64, 715 .partitions = 1, 716 .no_invd_sharing = true, 717 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 718 }, 719 .l1i_cache = &(CPUCacheInfo) { 720 .type = INSTRUCTION_CACHE, 721 .level = 1, 722 .size = 32 * KiB, 723 .self_init = 1, 724 .line_size = 64, 725 .associativity = 8, 726 .sets = 64, 727 .partitions = 1, 728 .no_invd_sharing = true, 729 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 730 }, 731 .l2_cache = &(CPUCacheInfo) { 732 .type = UNIFIED_CACHE, 733 .level = 2, 734 .size = 2 * MiB, 735 .self_init = 1, 736 .line_size = 64, 737 .associativity = 8, 738 .sets = 4096, 739 .partitions = 1, 740 .no_invd_sharing = true, 741 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 742 }, 743 .l3_cache = &(CPUCacheInfo) { 744 .type = UNIFIED_CACHE, 745 .level = 3, 746 .size = 16 * MiB, 747 .line_size = 64, 748 .associativity = 16, 749 .sets = 16384, 750 .partitions = 1, 751 .lines_per_tag = 1, 752 .self_init = true, 753 .inclusive = true, 754 .complex_indexing = true, 755 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 756 }, 757 }; 758 759 static const CPUCaches legacy_intel_cache_info = { 760 .l1d_cache = &(CPUCacheInfo) { 761 .type = DATA_CACHE, 762 .level = 1, 763 .size = 32 * KiB, 764 .self_init = 1, 765 .line_size = 64, 766 .associativity = 8, 767 .sets = 64, 768 .partitions = 1, 769 .no_invd_sharing = true, 770 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 771 }, 772 .l1i_cache = &(CPUCacheInfo) { 773 .type = INSTRUCTION_CACHE, 774 .level = 1, 775 .size = 32 * KiB, 776 .self_init = 1, 777 .line_size = 64, 778 .associativity = 8, 779 .sets = 64, 780 .partitions = 1, 781 .no_invd_sharing = true, 782 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 783 }, 784 .l2_cache = &(CPUCacheInfo) { 785 .type = UNIFIED_CACHE, 786 .level = 2, 787 .size = 4 * MiB, 788 .self_init = 1, 789 .line_size = 64, 790 .associativity = 16, 791 .sets = 4096, 792 .partitions = 1, 793 .no_invd_sharing = true, 794 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 795 }, 796 .l3_cache = &(CPUCacheInfo) { 797 .type = UNIFIED_CACHE, 798 .level = 3, 799 .size = 16 * MiB, 800 .line_size = 64, 801 .associativity = 16, 802 .sets = 16384, 803 .partitions = 1, 804 .lines_per_tag = 1, 805 .self_init = true, 806 .inclusive = true, 807 .complex_indexing = true, 808 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 809 }, 810 }; 811 812 /* TLB definitions: */ 813 814 #define L1_DTLB_2M_ASSOC 1 815 #define L1_DTLB_2M_ENTRIES 255 816 #define L1_DTLB_4K_ASSOC 1 817 #define L1_DTLB_4K_ENTRIES 255 818 819 #define L1_ITLB_2M_ASSOC 1 820 #define L1_ITLB_2M_ENTRIES 255 821 #define L1_ITLB_4K_ASSOC 1 822 #define L1_ITLB_4K_ENTRIES 255 823 824 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 825 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 826 #define L2_DTLB_4K_ASSOC 4 827 #define L2_DTLB_4K_ENTRIES 512 828 829 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 830 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 831 #define L2_ITLB_4K_ASSOC 4 832 #define L2_ITLB_4K_ENTRIES 512 833 834 /* CPUID Leaf 0x14 constants: */ 835 #define INTEL_PT_MAX_SUBLEAF 0x1 836 /* 837 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 838 * MSR can be accessed; 839 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 840 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 841 * of Intel PT MSRs across warm reset; 842 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 843 */ 844 #define INTEL_PT_MINIMAL_EBX 0xf 845 /* 846 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 847 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 848 * accessed; 849 * bit[01]: ToPA tables can hold any number of output entries, up to the 850 * maximum allowed by the MaskOrTableOffset field of 851 * IA32_RTIT_OUTPUT_MASK_PTRS; 852 * bit[02]: Support Single-Range Output scheme; 853 */ 854 #define INTEL_PT_MINIMAL_ECX 0x7 855 /* generated packets which contain IP payloads have LIP values */ 856 #define INTEL_PT_IP_LIP (1 << 31) 857 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 858 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 859 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 860 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 861 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 862 863 /* CPUID Leaf 0x1D constants: */ 864 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 865 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 866 #define INTEL_AMX_BYTES_PER_TILE 0x400 867 #define INTEL_AMX_BYTES_PER_ROW 0x40 868 #define INTEL_AMX_TILE_MAX_NAMES 0x8 869 #define INTEL_AMX_TILE_MAX_ROWS 0x10 870 871 /* CPUID Leaf 0x1E constants: */ 872 #define INTEL_AMX_TMUL_MAX_K 0x10 873 #define INTEL_AMX_TMUL_MAX_N 0x40 874 875 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 876 uint32_t vendor2, uint32_t vendor3) 877 { 878 int i; 879 for (i = 0; i < 4; i++) { 880 dst[i] = vendor1 >> (8 * i); 881 dst[i + 4] = vendor2 >> (8 * i); 882 dst[i + 8] = vendor3 >> (8 * i); 883 } 884 dst[CPUID_VENDOR_SZ] = '\0'; 885 } 886 887 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 888 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 889 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 890 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 891 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 892 CPUID_PSE36 | CPUID_FXSR) 893 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 894 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 895 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 896 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 897 CPUID_PAE | CPUID_SEP | CPUID_APIC) 898 899 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 900 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 901 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 902 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 903 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE | \ 904 CPUID_HT) 905 /* partly implemented: 906 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 907 /* missing: 908 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */ 909 910 /* 911 * Kernel-only features that can be shown to usermode programs even if 912 * they aren't actually supported by TCG, because qemu-user only runs 913 * in CPL=3; remove them if they are ever implemented for system emulation. 914 */ 915 #if defined CONFIG_USER_ONLY 916 #define CPUID_EXT_KERNEL_FEATURES \ 917 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 918 #else 919 #define CPUID_EXT_KERNEL_FEATURES 0 920 #endif 921 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 922 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 923 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 924 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 925 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 926 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 927 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 928 /* missing: 929 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 930 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 931 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 932 CPUID_EXT_TSC_DEADLINE_TIMER 933 */ 934 935 #ifdef TARGET_X86_64 936 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 937 #else 938 #define TCG_EXT2_X86_64_FEATURES 0 939 #endif 940 941 /* 942 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 943 * in usermode or by 32-bit programs. Those are added to supported 944 * TCG features unconditionally in user-mode emulation mode. This may 945 * indeed seem strange or incorrect, but it works because code running 946 * under usermode emulation cannot access them. 947 * 948 * Even for long mode, qemu-i386 is not running "a userspace program on a 949 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 950 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 951 * but again the difference is only visible in kernel mode. 952 */ 953 #if defined CONFIG_LINUX_USER 954 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 955 #elif defined CONFIG_USER_ONLY 956 /* FIXME: Long mode not yet supported for i386 bsd-user */ 957 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 958 #else 959 #define CPUID_EXT2_KERNEL_FEATURES 0 960 #endif 961 962 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 963 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 964 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 965 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 966 CPUID_EXT2_KERNEL_FEATURES) 967 968 #if defined CONFIG_USER_ONLY 969 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 970 #else 971 #define CPUID_EXT3_KERNEL_FEATURES 0 972 #endif 973 974 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 975 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 976 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES | \ 977 CPUID_EXT3_CMP_LEG) 978 979 #define TCG_EXT4_FEATURES 0 980 981 #if defined CONFIG_USER_ONLY 982 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 983 #else 984 #define CPUID_SVM_KERNEL_FEATURES 0 985 #endif 986 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 987 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 988 989 #define TCG_KVM_FEATURES 0 990 991 #if defined CONFIG_USER_ONLY 992 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 993 #else 994 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 995 #endif 996 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 997 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 998 CPUID_7_0_EBX_CLFLUSHOPT | \ 999 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 1000 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 1001 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 1002 /* missing: 1003 CPUID_7_0_EBX_HLE 1004 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 1005 1006 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 1007 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 1008 #else 1009 #define TCG_7_0_ECX_RDPID 0 1010 #endif 1011 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 1012 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 1013 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 1014 TCG_7_0_ECX_RDPID) 1015 1016 #if defined CONFIG_USER_ONLY 1017 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 1018 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 1019 #else 1020 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 1021 #endif 1022 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 1023 1024 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 1025 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 1026 #define TCG_7_1_ECX_FEATURES 0 1027 #define TCG_7_1_EDX_FEATURES 0 1028 #define TCG_7_2_EDX_FEATURES 0 1029 #define TCG_APM_FEATURES 0 1030 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 1031 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 1032 /* missing: 1033 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 1034 #define TCG_14_0_ECX_FEATURES 0 1035 #define TCG_SGX_12_0_EAX_FEATURES 0 1036 #define TCG_SGX_12_0_EBX_FEATURES 0 1037 #define TCG_SGX_12_1_EAX_FEATURES 0 1038 #define TCG_24_0_EBX_FEATURES 0 1039 1040 #if defined CONFIG_USER_ONLY 1041 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 1042 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 1043 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 1044 CPUID_8000_0008_EBX_AMD_PSFD) 1045 #else 1046 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 1047 #endif 1048 1049 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 1050 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 1051 1052 #if defined CONFIG_USER_ONLY 1053 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 1054 #else 1055 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 1056 #endif 1057 1058 #define TCG_8000_0021_EAX_FEATURES ( \ 1059 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 1060 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 1061 CPUID_8000_0021_EAX_KERNEL_FEATURES) 1062 1063 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 1064 [FEAT_1_EDX] = { 1065 .type = CPUID_FEATURE_WORD, 1066 .feat_names = { 1067 "fpu", "vme", "de", "pse", 1068 "tsc", "msr", "pae", "mce", 1069 "cx8", "apic", NULL, "sep", 1070 "mtrr", "pge", "mca", "cmov", 1071 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 1072 NULL, "ds" /* Intel dts */, "acpi", "mmx", 1073 "fxsr", "sse", "sse2", "ss", 1074 "ht" /* Intel htt */, "tm", "ia64", "pbe", 1075 }, 1076 .cpuid = {.eax = 1, .reg = R_EDX, }, 1077 .tcg_features = TCG_FEATURES, 1078 .no_autoenable_flags = CPUID_HT, 1079 }, 1080 [FEAT_1_ECX] = { 1081 .type = CPUID_FEATURE_WORD, 1082 .feat_names = { 1083 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 1084 "ds-cpl", "vmx", "smx", "est", 1085 "tm2", "ssse3", "cid", NULL, 1086 "fma", "cx16", "xtpr", "pdcm", 1087 NULL, "pcid", "dca", "sse4.1", 1088 "sse4.2", "x2apic", "movbe", "popcnt", 1089 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 1090 "avx", "f16c", "rdrand", "hypervisor", 1091 }, 1092 .cpuid = { .eax = 1, .reg = R_ECX, }, 1093 .tcg_features = TCG_EXT_FEATURES, 1094 }, 1095 /* Feature names that are already defined on feature_name[] but 1096 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 1097 * names on feat_names below. They are copied automatically 1098 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 1099 */ 1100 [FEAT_8000_0001_EDX] = { 1101 .type = CPUID_FEATURE_WORD, 1102 .feat_names = { 1103 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 1104 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 1105 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 1106 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 1107 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 1108 "nx", NULL, "mmxext", NULL /* mmx */, 1109 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 1110 NULL, "lm", "3dnowext", "3dnow", 1111 }, 1112 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 1113 .tcg_features = TCG_EXT2_FEATURES, 1114 }, 1115 [FEAT_8000_0001_ECX] = { 1116 .type = CPUID_FEATURE_WORD, 1117 .feat_names = { 1118 "lahf-lm", "cmp-legacy", "svm", "extapic", 1119 "cr8legacy", "abm", "sse4a", "misalignsse", 1120 "3dnowprefetch", "osvw", "ibs", "xop", 1121 "skinit", "wdt", NULL, "lwp", 1122 "fma4", "tce", NULL, "nodeid-msr", 1123 NULL, "tbm", "topoext", "perfctr-core", 1124 "perfctr-nb", NULL, NULL, NULL, 1125 NULL, NULL, NULL, NULL, 1126 }, 1127 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1128 .tcg_features = TCG_EXT3_FEATURES, 1129 /* 1130 * TOPOEXT is always allowed but can't be enabled blindly by 1131 * "-cpu host", as it requires consistent cache topology info 1132 * to be provided so it doesn't confuse guests. 1133 */ 1134 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1135 }, 1136 [FEAT_C000_0001_EDX] = { 1137 .type = CPUID_FEATURE_WORD, 1138 .feat_names = { 1139 NULL, NULL, "xstore", "xstore-en", 1140 NULL, NULL, "xcrypt", "xcrypt-en", 1141 "ace2", "ace2-en", "phe", "phe-en", 1142 "pmm", "pmm-en", NULL, NULL, 1143 NULL, NULL, NULL, NULL, 1144 NULL, NULL, NULL, NULL, 1145 NULL, NULL, NULL, NULL, 1146 NULL, NULL, NULL, NULL, 1147 }, 1148 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1149 .tcg_features = TCG_EXT4_FEATURES, 1150 }, 1151 [FEAT_KVM] = { 1152 .type = CPUID_FEATURE_WORD, 1153 .feat_names = { 1154 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1155 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1156 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1157 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1158 NULL, NULL, NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 "kvmclock-stable-bit", NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 }, 1163 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1164 .tcg_features = TCG_KVM_FEATURES, 1165 }, 1166 [FEAT_KVM_HINTS] = { 1167 .type = CPUID_FEATURE_WORD, 1168 .feat_names = { 1169 "kvm-hint-dedicated", NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 }, 1178 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1179 .tcg_features = TCG_KVM_FEATURES, 1180 /* 1181 * KVM hints aren't auto-enabled by -cpu host, they need to be 1182 * explicitly enabled in the command-line. 1183 */ 1184 .no_autoenable_flags = ~0U, 1185 }, 1186 [FEAT_SVM] = { 1187 .type = CPUID_FEATURE_WORD, 1188 .feat_names = { 1189 "npt", "lbrv", "svm-lock", "nrip-save", 1190 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1191 NULL, NULL, "pause-filter", NULL, 1192 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1193 "vgif", NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, "vnmi", NULL, NULL, 1196 "svme-addr-chk", NULL, NULL, NULL, 1197 }, 1198 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1199 .tcg_features = TCG_SVM_FEATURES, 1200 }, 1201 [FEAT_7_0_EBX] = { 1202 .type = CPUID_FEATURE_WORD, 1203 .feat_names = { 1204 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1205 "hle", "avx2", "fdp-excptn-only", "smep", 1206 "bmi2", "erms", "invpcid", "rtm", 1207 NULL, "zero-fcs-fds", "mpx", NULL, 1208 "avx512f", "avx512dq", "rdseed", "adx", 1209 "smap", "avx512ifma", "pcommit", "clflushopt", 1210 "clwb", "intel-pt", "avx512pf", "avx512er", 1211 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1212 }, 1213 .cpuid = { 1214 .eax = 7, 1215 .needs_ecx = true, .ecx = 0, 1216 .reg = R_EBX, 1217 }, 1218 .tcg_features = TCG_7_0_EBX_FEATURES, 1219 }, 1220 [FEAT_7_0_ECX] = { 1221 .type = CPUID_FEATURE_WORD, 1222 .feat_names = { 1223 NULL, "avx512vbmi", "umip", "pku", 1224 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1225 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1226 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1227 "la57", NULL, NULL, NULL, 1228 NULL, NULL, "rdpid", NULL, 1229 "bus-lock-detect", "cldemote", NULL, "movdiri", 1230 "movdir64b", NULL, "sgxlc", "pks", 1231 }, 1232 .cpuid = { 1233 .eax = 7, 1234 .needs_ecx = true, .ecx = 0, 1235 .reg = R_ECX, 1236 }, 1237 .tcg_features = TCG_7_0_ECX_FEATURES, 1238 }, 1239 [FEAT_7_0_EDX] = { 1240 .type = CPUID_FEATURE_WORD, 1241 .feat_names = { 1242 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1243 "fsrm", NULL, NULL, NULL, 1244 "avx512-vp2intersect", NULL, "md-clear", NULL, 1245 NULL, NULL, "serialize", NULL, 1246 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1247 NULL, NULL, "amx-bf16", "avx512-fp16", 1248 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1249 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1250 }, 1251 .cpuid = { 1252 .eax = 7, 1253 .needs_ecx = true, .ecx = 0, 1254 .reg = R_EDX, 1255 }, 1256 .tcg_features = TCG_7_0_EDX_FEATURES, 1257 }, 1258 [FEAT_7_1_EAX] = { 1259 .type = CPUID_FEATURE_WORD, 1260 .feat_names = { 1261 "sha512", "sm3", "sm4", NULL, 1262 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1263 NULL, NULL, "fzrm", "fsrs", 1264 "fsrc", NULL, NULL, NULL, 1265 NULL, "fred", "lkgs", "wrmsrns", 1266 NULL, "amx-fp16", NULL, "avx-ifma", 1267 NULL, NULL, "lam", NULL, 1268 NULL, NULL, NULL, NULL, 1269 }, 1270 .cpuid = { 1271 .eax = 7, 1272 .needs_ecx = true, .ecx = 1, 1273 .reg = R_EAX, 1274 }, 1275 .tcg_features = TCG_7_1_EAX_FEATURES, 1276 }, 1277 [FEAT_7_1_ECX] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .feat_names = { 1280 NULL, NULL, NULL, NULL, 1281 NULL, "msr-imm", NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 NULL, NULL, NULL, NULL, 1288 }, 1289 .cpuid = { 1290 .eax = 7, 1291 .needs_ecx = true, .ecx = 1, 1292 .reg = R_ECX, 1293 }, 1294 .tcg_features = TCG_7_1_ECX_FEATURES, 1295 }, 1296 [FEAT_7_1_EDX] = { 1297 .type = CPUID_FEATURE_WORD, 1298 .feat_names = { 1299 NULL, NULL, NULL, NULL, 1300 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1301 "amx-complex", NULL, "avx-vnni-int16", NULL, 1302 NULL, NULL, "prefetchiti", NULL, 1303 NULL, NULL, NULL, "avx10", 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 }, 1308 .cpuid = { 1309 .eax = 7, 1310 .needs_ecx = true, .ecx = 1, 1311 .reg = R_EDX, 1312 }, 1313 .tcg_features = TCG_7_1_EDX_FEATURES, 1314 }, 1315 [FEAT_7_2_EDX] = { 1316 .type = CPUID_FEATURE_WORD, 1317 .feat_names = { 1318 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1319 "bhi-ctrl", "mcdt-no", NULL, NULL, 1320 NULL, NULL, NULL, NULL, 1321 NULL, NULL, NULL, NULL, 1322 NULL, NULL, NULL, NULL, 1323 NULL, NULL, NULL, NULL, 1324 NULL, NULL, NULL, NULL, 1325 NULL, NULL, NULL, NULL, 1326 }, 1327 .cpuid = { 1328 .eax = 7, 1329 .needs_ecx = true, .ecx = 2, 1330 .reg = R_EDX, 1331 }, 1332 .tcg_features = TCG_7_2_EDX_FEATURES, 1333 }, 1334 [FEAT_24_0_EBX] = { 1335 .type = CPUID_FEATURE_WORD, 1336 .feat_names = { 1337 [16] = "avx10-128", 1338 [17] = "avx10-256", 1339 [18] = "avx10-512", 1340 }, 1341 .cpuid = { 1342 .eax = 0x24, 1343 .needs_ecx = true, .ecx = 0, 1344 .reg = R_EBX, 1345 }, 1346 .tcg_features = TCG_24_0_EBX_FEATURES, 1347 }, 1348 [FEAT_8000_0007_EDX] = { 1349 .type = CPUID_FEATURE_WORD, 1350 .feat_names = { 1351 NULL, NULL, NULL, NULL, 1352 NULL, NULL, NULL, NULL, 1353 "invtsc", NULL, NULL, NULL, 1354 NULL, NULL, NULL, NULL, 1355 NULL, NULL, NULL, NULL, 1356 NULL, NULL, NULL, NULL, 1357 NULL, NULL, NULL, NULL, 1358 NULL, NULL, NULL, NULL, 1359 }, 1360 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1361 .tcg_features = TCG_APM_FEATURES, 1362 .unmigratable_flags = CPUID_APM_INVTSC, 1363 }, 1364 [FEAT_8000_0007_EBX] = { 1365 .type = CPUID_FEATURE_WORD, 1366 .feat_names = { 1367 "overflow-recov", "succor", NULL, NULL, 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 NULL, NULL, NULL, NULL, 1371 NULL, NULL, NULL, NULL, 1372 NULL, NULL, NULL, NULL, 1373 NULL, NULL, NULL, NULL, 1374 NULL, NULL, NULL, NULL, 1375 }, 1376 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1377 .tcg_features = 0, 1378 .unmigratable_flags = 0, 1379 }, 1380 [FEAT_8000_0008_EBX] = { 1381 .type = CPUID_FEATURE_WORD, 1382 .feat_names = { 1383 "clzero", NULL, "xsaveerptr", NULL, 1384 NULL, NULL, NULL, NULL, 1385 NULL, "wbnoinvd", NULL, NULL, 1386 "ibpb", NULL, "ibrs", "amd-stibp", 1387 NULL, "stibp-always-on", NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1390 "amd-psfd", NULL, NULL, NULL, 1391 }, 1392 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1393 .tcg_features = TCG_8000_0008_EBX, 1394 .unmigratable_flags = 0, 1395 }, 1396 [FEAT_8000_0021_EAX] = { 1397 .type = CPUID_FEATURE_WORD, 1398 .feat_names = { 1399 "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL, 1400 NULL, "verw-clear", "null-sel-clr-base", NULL, 1401 "auto-ibrs", NULL, NULL, NULL, 1402 NULL, NULL, NULL, NULL, 1403 NULL, NULL, NULL, NULL, 1404 "prefetchi", NULL, NULL, NULL, 1405 "eraps", NULL, NULL, "sbpb", 1406 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1407 }, 1408 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1409 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1410 .unmigratable_flags = 0, 1411 }, 1412 [FEAT_8000_0021_EBX] = { 1413 .type = CPUID_FEATURE_WORD, 1414 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1415 .tcg_features = 0, 1416 .unmigratable_flags = 0, 1417 }, 1418 [FEAT_8000_0021_ECX] = { 1419 .type = CPUID_FEATURE_WORD, 1420 .feat_names = { 1421 NULL, "tsa-sq-no", "tsa-l1-no", NULL, 1422 NULL, NULL, NULL, NULL, 1423 NULL, NULL, NULL, NULL, 1424 NULL, NULL, NULL, NULL, 1425 NULL, NULL, NULL, NULL, 1426 NULL, NULL, NULL, NULL, 1427 NULL, NULL, NULL, NULL, 1428 NULL, NULL, NULL, NULL, 1429 }, 1430 .cpuid = { .eax = 0x80000021, .reg = R_ECX, }, 1431 .tcg_features = 0, 1432 .unmigratable_flags = 0, 1433 }, 1434 [FEAT_8000_0022_EAX] = { 1435 .type = CPUID_FEATURE_WORD, 1436 .feat_names = { 1437 "perfmon-v2", NULL, NULL, NULL, 1438 NULL, NULL, NULL, NULL, 1439 NULL, NULL, NULL, NULL, 1440 NULL, NULL, NULL, NULL, 1441 NULL, NULL, NULL, NULL, 1442 NULL, NULL, NULL, NULL, 1443 NULL, NULL, NULL, NULL, 1444 NULL, NULL, NULL, NULL, 1445 }, 1446 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1447 .tcg_features = 0, 1448 .unmigratable_flags = 0, 1449 }, 1450 [FEAT_XSAVE] = { 1451 .type = CPUID_FEATURE_WORD, 1452 .feat_names = { 1453 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1454 "xfd", NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 NULL, NULL, NULL, NULL, 1457 NULL, NULL, NULL, NULL, 1458 NULL, NULL, NULL, NULL, 1459 NULL, NULL, NULL, NULL, 1460 NULL, NULL, NULL, NULL, 1461 }, 1462 .cpuid = { 1463 .eax = 0xd, 1464 .needs_ecx = true, .ecx = 1, 1465 .reg = R_EAX, 1466 }, 1467 .tcg_features = TCG_XSAVE_FEATURES, 1468 }, 1469 [FEAT_XSAVE_XSS_LO] = { 1470 .type = CPUID_FEATURE_WORD, 1471 .feat_names = { 1472 NULL, NULL, NULL, NULL, 1473 NULL, NULL, NULL, NULL, 1474 NULL, NULL, NULL, NULL, 1475 NULL, NULL, NULL, NULL, 1476 NULL, NULL, NULL, NULL, 1477 NULL, NULL, NULL, NULL, 1478 NULL, NULL, NULL, NULL, 1479 NULL, NULL, NULL, NULL, 1480 }, 1481 .cpuid = { 1482 .eax = 0xD, 1483 .needs_ecx = true, 1484 .ecx = 1, 1485 .reg = R_ECX, 1486 }, 1487 }, 1488 [FEAT_XSAVE_XSS_HI] = { 1489 .type = CPUID_FEATURE_WORD, 1490 .cpuid = { 1491 .eax = 0xD, 1492 .needs_ecx = true, 1493 .ecx = 1, 1494 .reg = R_EDX 1495 }, 1496 }, 1497 [FEAT_6_EAX] = { 1498 .type = CPUID_FEATURE_WORD, 1499 .feat_names = { 1500 NULL, NULL, "arat", NULL, 1501 NULL, NULL, NULL, NULL, 1502 NULL, NULL, NULL, NULL, 1503 NULL, NULL, NULL, NULL, 1504 NULL, NULL, NULL, NULL, 1505 NULL, NULL, NULL, NULL, 1506 NULL, NULL, NULL, NULL, 1507 NULL, NULL, NULL, NULL, 1508 }, 1509 .cpuid = { .eax = 6, .reg = R_EAX, }, 1510 .tcg_features = TCG_6_EAX_FEATURES, 1511 }, 1512 [FEAT_XSAVE_XCR0_LO] = { 1513 .type = CPUID_FEATURE_WORD, 1514 .cpuid = { 1515 .eax = 0xD, 1516 .needs_ecx = true, .ecx = 0, 1517 .reg = R_EAX, 1518 }, 1519 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1520 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1521 XSTATE_PKRU_MASK, 1522 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1523 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1524 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1525 XSTATE_PKRU_MASK, 1526 }, 1527 [FEAT_XSAVE_XCR0_HI] = { 1528 .type = CPUID_FEATURE_WORD, 1529 .cpuid = { 1530 .eax = 0xD, 1531 .needs_ecx = true, .ecx = 0, 1532 .reg = R_EDX, 1533 }, 1534 .tcg_features = 0U, 1535 }, 1536 /*Below are MSR exposed features*/ 1537 [FEAT_ARCH_CAPABILITIES] = { 1538 .type = MSR_FEATURE_WORD, 1539 .feat_names = { 1540 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1541 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1542 "taa-no", NULL, NULL, NULL, 1543 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1544 NULL, "fb-clear", NULL, NULL, 1545 "bhi-no", NULL, NULL, NULL, 1546 "pbrsb-no", NULL, "gds-no", "rfds-no", 1547 "rfds-clear", NULL, NULL, NULL, 1548 NULL, NULL, NULL, NULL, 1549 NULL, NULL, NULL, NULL, 1550 NULL, NULL, NULL, NULL, 1551 NULL, NULL, NULL, NULL, 1552 NULL, NULL, NULL, NULL, 1553 NULL, NULL, NULL, NULL, 1554 NULL, NULL, NULL, NULL, 1555 NULL, NULL, "its-no", NULL, 1556 }, 1557 .msr = { 1558 .index = MSR_IA32_ARCH_CAPABILITIES, 1559 }, 1560 /* 1561 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1562 * cannot be read from user mode. Therefore, it has no impact 1563 > on any user-mode operation, and warnings about unsupported 1564 * features do not matter. 1565 */ 1566 .tcg_features = ~0U, 1567 }, 1568 [FEAT_CORE_CAPABILITY] = { 1569 .type = MSR_FEATURE_WORD, 1570 .feat_names = { 1571 NULL, NULL, NULL, NULL, 1572 NULL, "split-lock-detect", NULL, NULL, 1573 NULL, NULL, NULL, NULL, 1574 NULL, NULL, NULL, NULL, 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, NULL, 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 }, 1580 .msr = { 1581 .index = MSR_IA32_CORE_CAPABILITY, 1582 }, 1583 }, 1584 [FEAT_PERF_CAPABILITIES] = { 1585 .type = MSR_FEATURE_WORD, 1586 .feat_names = { 1587 NULL, NULL, NULL, NULL, 1588 NULL, NULL, NULL, NULL, 1589 NULL, NULL, NULL, NULL, 1590 NULL, "full-width-write", NULL, NULL, 1591 NULL, NULL, NULL, NULL, 1592 NULL, NULL, NULL, NULL, 1593 NULL, NULL, NULL, NULL, 1594 NULL, NULL, NULL, NULL, 1595 }, 1596 .msr = { 1597 .index = MSR_IA32_PERF_CAPABILITIES, 1598 }, 1599 }, 1600 1601 [FEAT_VMX_PROCBASED_CTLS] = { 1602 .type = MSR_FEATURE_WORD, 1603 .feat_names = { 1604 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1605 NULL, NULL, NULL, "vmx-hlt-exit", 1606 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1607 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1608 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1609 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1610 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1611 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1612 }, 1613 .msr = { 1614 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1615 } 1616 }, 1617 1618 [FEAT_VMX_SECONDARY_CTLS] = { 1619 .type = MSR_FEATURE_WORD, 1620 .feat_names = { 1621 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1622 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1623 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1624 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1625 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1626 "vmx-xsaves", NULL, NULL, NULL, 1627 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1628 NULL, NULL, NULL, NULL, 1629 }, 1630 .msr = { 1631 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1632 } 1633 }, 1634 1635 [FEAT_VMX_PINBASED_CTLS] = { 1636 .type = MSR_FEATURE_WORD, 1637 .feat_names = { 1638 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1639 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1640 NULL, NULL, NULL, NULL, 1641 NULL, NULL, NULL, NULL, 1642 NULL, NULL, NULL, NULL, 1643 NULL, NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 }, 1647 .msr = { 1648 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1649 } 1650 }, 1651 1652 [FEAT_VMX_EXIT_CTLS] = { 1653 .type = MSR_FEATURE_WORD, 1654 /* 1655 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1656 * the LM CPUID bit. 1657 */ 1658 .feat_names = { 1659 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1660 NULL, NULL, NULL, NULL, 1661 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1662 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1663 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1664 "vmx-exit-save-efer", "vmx-exit-load-efer", 1665 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1666 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1667 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1668 }, 1669 .msr = { 1670 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1671 } 1672 }, 1673 1674 [FEAT_VMX_ENTRY_CTLS] = { 1675 .type = MSR_FEATURE_WORD, 1676 .feat_names = { 1677 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1678 NULL, NULL, NULL, NULL, 1679 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1680 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1681 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1682 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1683 NULL, NULL, NULL, NULL, 1684 NULL, NULL, NULL, NULL, 1685 }, 1686 .msr = { 1687 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1688 } 1689 }, 1690 1691 [FEAT_VMX_MISC] = { 1692 .type = MSR_FEATURE_WORD, 1693 .feat_names = { 1694 NULL, NULL, NULL, NULL, 1695 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1696 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1697 NULL, NULL, NULL, NULL, 1698 NULL, NULL, NULL, NULL, 1699 NULL, NULL, NULL, NULL, 1700 NULL, NULL, NULL, NULL, 1701 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1702 }, 1703 .msr = { 1704 .index = MSR_IA32_VMX_MISC, 1705 } 1706 }, 1707 1708 [FEAT_VMX_EPT_VPID_CAPS] = { 1709 .type = MSR_FEATURE_WORD, 1710 .feat_names = { 1711 "vmx-ept-execonly", NULL, NULL, NULL, 1712 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1713 NULL, NULL, NULL, NULL, 1714 NULL, NULL, NULL, NULL, 1715 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1716 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1717 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1718 NULL, NULL, NULL, NULL, 1719 "vmx-invvpid", NULL, NULL, NULL, 1720 NULL, NULL, NULL, NULL, 1721 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1722 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1723 NULL, NULL, NULL, NULL, 1724 NULL, NULL, NULL, NULL, 1725 NULL, NULL, NULL, NULL, 1726 NULL, NULL, NULL, NULL, 1727 NULL, NULL, NULL, NULL, 1728 }, 1729 .msr = { 1730 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1731 } 1732 }, 1733 1734 [FEAT_VMX_BASIC] = { 1735 .type = MSR_FEATURE_WORD, 1736 .feat_names = { 1737 [54] = "vmx-ins-outs", 1738 [55] = "vmx-true-ctls", 1739 [56] = "vmx-any-errcode", 1740 [58] = "vmx-nested-exception", 1741 }, 1742 .msr = { 1743 .index = MSR_IA32_VMX_BASIC, 1744 }, 1745 /* Just to be safe - we don't support setting the MSEG version field. */ 1746 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1747 }, 1748 1749 [FEAT_VMX_VMFUNC] = { 1750 .type = MSR_FEATURE_WORD, 1751 .feat_names = { 1752 [0] = "vmx-eptp-switching", 1753 }, 1754 .msr = { 1755 .index = MSR_IA32_VMX_VMFUNC, 1756 } 1757 }, 1758 1759 [FEAT_14_0_ECX] = { 1760 .type = CPUID_FEATURE_WORD, 1761 .feat_names = { 1762 NULL, NULL, NULL, NULL, 1763 NULL, NULL, NULL, NULL, 1764 NULL, NULL, NULL, NULL, 1765 NULL, NULL, NULL, NULL, 1766 NULL, NULL, NULL, NULL, 1767 NULL, NULL, NULL, NULL, 1768 NULL, NULL, NULL, NULL, 1769 NULL, NULL, NULL, "intel-pt-lip", 1770 }, 1771 .cpuid = { 1772 .eax = 0x14, 1773 .needs_ecx = true, .ecx = 0, 1774 .reg = R_ECX, 1775 }, 1776 .tcg_features = TCG_14_0_ECX_FEATURES, 1777 }, 1778 1779 [FEAT_SGX_12_0_EAX] = { 1780 .type = CPUID_FEATURE_WORD, 1781 .feat_names = { 1782 "sgx1", "sgx2", NULL, NULL, 1783 NULL, NULL, NULL, NULL, 1784 NULL, NULL, NULL, "sgx-edeccssa", 1785 NULL, NULL, NULL, NULL, 1786 NULL, NULL, NULL, NULL, 1787 NULL, NULL, NULL, NULL, 1788 NULL, NULL, NULL, NULL, 1789 NULL, NULL, NULL, NULL, 1790 }, 1791 .cpuid = { 1792 .eax = 0x12, 1793 .needs_ecx = true, .ecx = 0, 1794 .reg = R_EAX, 1795 }, 1796 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1797 }, 1798 1799 [FEAT_SGX_12_0_EBX] = { 1800 .type = CPUID_FEATURE_WORD, 1801 .feat_names = { 1802 "sgx-exinfo" , NULL, NULL, NULL, 1803 NULL, NULL, NULL, NULL, 1804 NULL, NULL, NULL, NULL, 1805 NULL, NULL, NULL, NULL, 1806 NULL, NULL, NULL, NULL, 1807 NULL, NULL, NULL, NULL, 1808 NULL, NULL, NULL, NULL, 1809 NULL, NULL, NULL, NULL, 1810 }, 1811 .cpuid = { 1812 .eax = 0x12, 1813 .needs_ecx = true, .ecx = 0, 1814 .reg = R_EBX, 1815 }, 1816 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1817 }, 1818 1819 [FEAT_SGX_12_1_EAX] = { 1820 .type = CPUID_FEATURE_WORD, 1821 .feat_names = { 1822 NULL, "sgx-debug", "sgx-mode64", NULL, 1823 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1824 NULL, NULL, "sgx-aex-notify", NULL, 1825 NULL, NULL, NULL, NULL, 1826 NULL, NULL, NULL, NULL, 1827 NULL, NULL, NULL, NULL, 1828 NULL, NULL, NULL, NULL, 1829 NULL, NULL, NULL, NULL, 1830 }, 1831 .cpuid = { 1832 .eax = 0x12, 1833 .needs_ecx = true, .ecx = 1, 1834 .reg = R_EAX, 1835 }, 1836 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1837 }, 1838 }; 1839 1840 bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg) 1841 { 1842 FeatureWordInfo *wi; 1843 FeatureWord w; 1844 1845 for (w = 0; w < FEATURE_WORDS; w++) { 1846 wi = &feature_word_info[w]; 1847 if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature && 1848 (!wi->cpuid.needs_ecx || wi->cpuid.ecx == index) && 1849 wi->cpuid.reg == reg) { 1850 return true; 1851 } 1852 } 1853 return false; 1854 } 1855 1856 static FeatureDep feature_dependencies[] = { 1857 { 1858 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1859 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1860 }, 1861 { 1862 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1863 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1864 }, 1865 { 1866 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1867 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1868 }, 1869 { 1870 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1871 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1872 }, 1873 { 1874 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1875 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1876 }, 1877 { 1878 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1879 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1880 }, 1881 { 1882 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1883 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1884 }, 1885 { 1886 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1887 .to = { FEAT_VMX_MISC, ~0ull }, 1888 }, 1889 { 1890 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1891 .to = { FEAT_VMX_BASIC, ~0ull }, 1892 }, 1893 { 1894 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1895 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1896 }, 1897 { 1898 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1899 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1900 }, 1901 { 1902 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1903 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1904 }, 1905 { 1906 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1907 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1908 }, 1909 { 1910 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1911 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1912 }, 1913 { 1914 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1915 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1916 }, 1917 { 1918 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1919 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1920 }, 1921 { 1922 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1923 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1924 }, 1925 { 1926 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1927 .to = { FEAT_14_0_ECX, ~0ull }, 1928 }, 1929 { 1930 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1931 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1932 }, 1933 { 1934 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1935 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1936 }, 1937 { 1938 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1939 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1940 }, 1941 { 1942 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1943 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1944 }, 1945 { 1946 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1947 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1948 }, 1949 { 1950 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1951 .to = { FEAT_SVM, ~0ull }, 1952 }, 1953 { 1954 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1955 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1956 }, 1957 { 1958 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1959 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1960 }, 1961 { 1962 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1963 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1964 }, 1965 { 1966 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1967 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1968 }, 1969 { 1970 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1971 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1972 }, 1973 { 1974 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1975 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1976 }, 1977 { 1978 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1979 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1980 }, 1981 { 1982 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1983 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1984 }, 1985 { 1986 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1987 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1988 }, 1989 { 1990 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1991 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1992 }, 1993 { 1994 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1995 .to = { FEAT_24_0_EBX, ~0ull }, 1996 }, 1997 }; 1998 1999 typedef struct X86RegisterInfo32 { 2000 /* Name of register */ 2001 const char *name; 2002 /* QAPI enum value register */ 2003 X86CPURegister32 qapi_enum; 2004 } X86RegisterInfo32; 2005 2006 #define REGISTER(reg) \ 2007 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 2008 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 2009 REGISTER(EAX), 2010 REGISTER(ECX), 2011 REGISTER(EDX), 2012 REGISTER(EBX), 2013 REGISTER(ESP), 2014 REGISTER(EBP), 2015 REGISTER(ESI), 2016 REGISTER(EDI), 2017 }; 2018 #undef REGISTER 2019 2020 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 2021 [XSTATE_FP_BIT] = { 2022 /* x87 FP state component is always enabled if XSAVE is supported */ 2023 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 2024 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 2025 }, 2026 [XSTATE_SSE_BIT] = { 2027 /* SSE state component is always enabled if XSAVE is supported */ 2028 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 2029 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 2030 }, 2031 [XSTATE_YMM_BIT] = 2032 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 2033 .size = sizeof(XSaveAVX) }, 2034 [XSTATE_BNDREGS_BIT] = 2035 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 2036 .size = sizeof(XSaveBNDREG) }, 2037 [XSTATE_BNDCSR_BIT] = 2038 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 2039 .size = sizeof(XSaveBNDCSR) }, 2040 [XSTATE_OPMASK_BIT] = 2041 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 2042 .size = sizeof(XSaveOpmask) }, 2043 [XSTATE_ZMM_Hi256_BIT] = 2044 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 2045 .size = sizeof(XSaveZMM_Hi256) }, 2046 [XSTATE_Hi16_ZMM_BIT] = 2047 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 2048 .size = sizeof(XSaveHi16_ZMM) }, 2049 [XSTATE_PKRU_BIT] = 2050 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 2051 .size = sizeof(XSavePKRU) }, 2052 [XSTATE_ARCH_LBR_BIT] = { 2053 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 2054 .offset = 0 /*supervisor mode component, offset = 0 */, 2055 .size = sizeof(XSavesArchLBR) }, 2056 [XSTATE_XTILE_CFG_BIT] = { 2057 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 2058 .size = sizeof(XSaveXTILECFG), 2059 }, 2060 [XSTATE_XTILE_DATA_BIT] = { 2061 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 2062 .size = sizeof(XSaveXTILEDATA) 2063 }, 2064 }; 2065 2066 uint32_t xsave_area_size(uint64_t mask, bool compacted) 2067 { 2068 uint64_t ret = x86_ext_save_areas[0].size; 2069 const ExtSaveArea *esa; 2070 uint32_t offset = 0; 2071 int i; 2072 2073 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 2074 esa = &x86_ext_save_areas[i]; 2075 if ((mask >> i) & 1) { 2076 offset = compacted ? ret : esa->offset; 2077 ret = MAX(ret, offset + esa->size); 2078 } 2079 } 2080 return ret; 2081 } 2082 2083 static inline bool accel_uses_host_cpuid(void) 2084 { 2085 return !tcg_enabled() && !qtest_enabled(); 2086 } 2087 2088 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 2089 { 2090 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 2091 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 2092 } 2093 2094 /* Return name of 32-bit register, from a R_* constant */ 2095 static const char *get_register_name_32(unsigned int reg) 2096 { 2097 if (reg >= CPU_NB_REGS32) { 2098 return NULL; 2099 } 2100 return x86_reg_info_32[reg].name; 2101 } 2102 2103 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 2104 { 2105 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 2106 cpu->env.features[FEAT_XSAVE_XSS_LO]; 2107 } 2108 2109 /* 2110 * Returns the set of feature flags that are supported and migratable by 2111 * QEMU, for a given FeatureWord. 2112 */ 2113 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 2114 { 2115 FeatureWordInfo *wi = &feature_word_info[w]; 2116 CPUX86State *env = &cpu->env; 2117 uint64_t r = 0; 2118 int i; 2119 2120 for (i = 0; i < 64; i++) { 2121 uint64_t f = 1ULL << i; 2122 2123 /* If the feature name is known, it is implicitly considered migratable, 2124 * unless it is explicitly set in unmigratable_flags */ 2125 if ((wi->migratable_flags & f) || 2126 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 2127 r |= f; 2128 } 2129 } 2130 2131 /* when tsc-khz is set explicitly, invtsc is migratable */ 2132 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 2133 r |= CPUID_APM_INVTSC; 2134 } 2135 2136 return r; 2137 } 2138 2139 void host_cpuid(uint32_t function, uint32_t count, 2140 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 2141 { 2142 uint32_t vec[4]; 2143 2144 #ifdef __x86_64__ 2145 asm volatile("cpuid" 2146 : "=a"(vec[0]), "=b"(vec[1]), 2147 "=c"(vec[2]), "=d"(vec[3]) 2148 : "0"(function), "c"(count) : "cc"); 2149 #elif defined(__i386__) 2150 asm volatile("pusha \n\t" 2151 "cpuid \n\t" 2152 "mov %%eax, 0(%2) \n\t" 2153 "mov %%ebx, 4(%2) \n\t" 2154 "mov %%ecx, 8(%2) \n\t" 2155 "mov %%edx, 12(%2) \n\t" 2156 "popa" 2157 : : "a"(function), "c"(count), "S"(vec) 2158 : "memory", "cc"); 2159 #else 2160 abort(); 2161 #endif 2162 2163 if (eax) 2164 *eax = vec[0]; 2165 if (ebx) 2166 *ebx = vec[1]; 2167 if (ecx) 2168 *ecx = vec[2]; 2169 if (edx) 2170 *edx = vec[3]; 2171 } 2172 2173 /* CPU class name definitions: */ 2174 2175 /* Return type name for a given CPU model name 2176 * Caller is responsible for freeing the returned string. 2177 */ 2178 static char *x86_cpu_type_name(const char *model_name) 2179 { 2180 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2181 } 2182 2183 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2184 { 2185 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2186 return object_class_by_name(typename); 2187 } 2188 2189 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2190 { 2191 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2192 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2193 return cpu_model_from_type(class_name); 2194 } 2195 2196 typedef struct X86CPUVersionDefinition { 2197 X86CPUVersion version; 2198 const char *alias; 2199 const char *note; 2200 PropValue *props; 2201 const CPUCaches *const cache_info; 2202 } X86CPUVersionDefinition; 2203 2204 /* Base definition for a CPU model */ 2205 typedef struct X86CPUDefinition { 2206 const char *name; 2207 uint32_t level; 2208 uint32_t xlevel; 2209 /* vendor is zero-terminated, 12 character ASCII string */ 2210 char vendor[CPUID_VENDOR_SZ + 1]; 2211 int family; 2212 int model; 2213 int stepping; 2214 uint8_t avx10_version; 2215 FeatureWordArray features; 2216 const char *model_id; 2217 const CPUCaches *const cache_info; 2218 /* 2219 * Definitions for alternative versions of CPU model. 2220 * List is terminated by item with version == 0. 2221 * If NULL, version 1 will be registered automatically. 2222 */ 2223 const X86CPUVersionDefinition *versions; 2224 const char *deprecation_note; 2225 } X86CPUDefinition; 2226 2227 /* Reference to a specific CPU model version */ 2228 struct X86CPUModel { 2229 /* Base CPU definition */ 2230 const X86CPUDefinition *cpudef; 2231 /* CPU model version */ 2232 X86CPUVersion version; 2233 const char *note; 2234 /* 2235 * If true, this is an alias CPU model. 2236 * This matters only for "-cpu help" and query-cpu-definitions 2237 */ 2238 bool is_alias; 2239 }; 2240 2241 /* Get full model name for CPU version */ 2242 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2243 X86CPUVersion version) 2244 { 2245 assert(version > 0); 2246 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2247 } 2248 2249 static const X86CPUVersionDefinition * 2250 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2251 { 2252 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2253 static const X86CPUVersionDefinition default_version_list[] = { 2254 { 1 }, 2255 { /* end of list */ } 2256 }; 2257 2258 return def->versions ?: default_version_list; 2259 } 2260 2261 static const CPUCaches epyc_cache_info = { 2262 .l1d_cache = &(CPUCacheInfo) { 2263 .type = DATA_CACHE, 2264 .level = 1, 2265 .size = 32 * KiB, 2266 .line_size = 64, 2267 .associativity = 8, 2268 .partitions = 1, 2269 .sets = 64, 2270 .lines_per_tag = 1, 2271 .self_init = 1, 2272 .no_invd_sharing = true, 2273 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2274 }, 2275 .l1i_cache = &(CPUCacheInfo) { 2276 .type = INSTRUCTION_CACHE, 2277 .level = 1, 2278 .size = 64 * KiB, 2279 .line_size = 64, 2280 .associativity = 4, 2281 .partitions = 1, 2282 .sets = 256, 2283 .lines_per_tag = 1, 2284 .self_init = 1, 2285 .no_invd_sharing = true, 2286 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2287 }, 2288 .l2_cache = &(CPUCacheInfo) { 2289 .type = UNIFIED_CACHE, 2290 .level = 2, 2291 .size = 512 * KiB, 2292 .line_size = 64, 2293 .associativity = 8, 2294 .partitions = 1, 2295 .sets = 1024, 2296 .lines_per_tag = 1, 2297 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2298 }, 2299 .l3_cache = &(CPUCacheInfo) { 2300 .type = UNIFIED_CACHE, 2301 .level = 3, 2302 .size = 8 * MiB, 2303 .line_size = 64, 2304 .associativity = 16, 2305 .partitions = 1, 2306 .sets = 8192, 2307 .lines_per_tag = 1, 2308 .self_init = true, 2309 .inclusive = true, 2310 .complex_indexing = true, 2311 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2312 }, 2313 }; 2314 2315 static CPUCaches epyc_v4_cache_info = { 2316 .l1d_cache = &(CPUCacheInfo) { 2317 .type = DATA_CACHE, 2318 .level = 1, 2319 .size = 32 * KiB, 2320 .line_size = 64, 2321 .associativity = 8, 2322 .partitions = 1, 2323 .sets = 64, 2324 .lines_per_tag = 1, 2325 .self_init = 1, 2326 .no_invd_sharing = true, 2327 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2328 }, 2329 .l1i_cache = &(CPUCacheInfo) { 2330 .type = INSTRUCTION_CACHE, 2331 .level = 1, 2332 .size = 64 * KiB, 2333 .line_size = 64, 2334 .associativity = 4, 2335 .partitions = 1, 2336 .sets = 256, 2337 .lines_per_tag = 1, 2338 .self_init = 1, 2339 .no_invd_sharing = true, 2340 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2341 }, 2342 .l2_cache = &(CPUCacheInfo) { 2343 .type = UNIFIED_CACHE, 2344 .level = 2, 2345 .size = 512 * KiB, 2346 .line_size = 64, 2347 .associativity = 8, 2348 .partitions = 1, 2349 .sets = 1024, 2350 .lines_per_tag = 1, 2351 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2352 }, 2353 .l3_cache = &(CPUCacheInfo) { 2354 .type = UNIFIED_CACHE, 2355 .level = 3, 2356 .size = 8 * MiB, 2357 .line_size = 64, 2358 .associativity = 16, 2359 .partitions = 1, 2360 .sets = 8192, 2361 .lines_per_tag = 1, 2362 .self_init = true, 2363 .inclusive = true, 2364 .complex_indexing = false, 2365 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2366 }, 2367 }; 2368 2369 static CPUCaches epyc_v5_cache_info = { 2370 .l1d_cache = &(CPUCacheInfo) { 2371 .type = DATA_CACHE, 2372 .level = 1, 2373 .size = 32 * KiB, 2374 .line_size = 64, 2375 .associativity = 8, 2376 .partitions = 1, 2377 .sets = 64, 2378 .lines_per_tag = 1, 2379 .self_init = true, 2380 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2381 }, 2382 .l1i_cache = &(CPUCacheInfo) { 2383 .type = INSTRUCTION_CACHE, 2384 .level = 1, 2385 .size = 64 * KiB, 2386 .line_size = 64, 2387 .associativity = 4, 2388 .partitions = 1, 2389 .sets = 256, 2390 .lines_per_tag = 1, 2391 .self_init = true, 2392 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2393 }, 2394 .l2_cache = &(CPUCacheInfo) { 2395 .type = UNIFIED_CACHE, 2396 .level = 2, 2397 .size = 512 * KiB, 2398 .line_size = 64, 2399 .associativity = 8, 2400 .partitions = 1, 2401 .sets = 1024, 2402 .lines_per_tag = 1, 2403 .self_init = true, 2404 .inclusive = true, 2405 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2406 }, 2407 .l3_cache = &(CPUCacheInfo) { 2408 .type = UNIFIED_CACHE, 2409 .level = 3, 2410 .size = 8 * MiB, 2411 .line_size = 64, 2412 .associativity = 16, 2413 .partitions = 1, 2414 .sets = 8192, 2415 .lines_per_tag = 1, 2416 .self_init = true, 2417 .no_invd_sharing = true, 2418 .complex_indexing = false, 2419 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2420 }, 2421 }; 2422 2423 static const CPUCaches epyc_rome_cache_info = { 2424 .l1d_cache = &(CPUCacheInfo) { 2425 .type = DATA_CACHE, 2426 .level = 1, 2427 .size = 32 * KiB, 2428 .line_size = 64, 2429 .associativity = 8, 2430 .partitions = 1, 2431 .sets = 64, 2432 .lines_per_tag = 1, 2433 .self_init = 1, 2434 .no_invd_sharing = true, 2435 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2436 }, 2437 .l1i_cache = &(CPUCacheInfo) { 2438 .type = INSTRUCTION_CACHE, 2439 .level = 1, 2440 .size = 32 * KiB, 2441 .line_size = 64, 2442 .associativity = 8, 2443 .partitions = 1, 2444 .sets = 64, 2445 .lines_per_tag = 1, 2446 .self_init = 1, 2447 .no_invd_sharing = true, 2448 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2449 }, 2450 .l2_cache = &(CPUCacheInfo) { 2451 .type = UNIFIED_CACHE, 2452 .level = 2, 2453 .size = 512 * KiB, 2454 .line_size = 64, 2455 .associativity = 8, 2456 .partitions = 1, 2457 .sets = 1024, 2458 .lines_per_tag = 1, 2459 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2460 }, 2461 .l3_cache = &(CPUCacheInfo) { 2462 .type = UNIFIED_CACHE, 2463 .level = 3, 2464 .size = 16 * MiB, 2465 .line_size = 64, 2466 .associativity = 16, 2467 .partitions = 1, 2468 .sets = 16384, 2469 .lines_per_tag = 1, 2470 .self_init = true, 2471 .inclusive = true, 2472 .complex_indexing = true, 2473 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2474 }, 2475 }; 2476 2477 static const CPUCaches epyc_rome_v3_cache_info = { 2478 .l1d_cache = &(CPUCacheInfo) { 2479 .type = DATA_CACHE, 2480 .level = 1, 2481 .size = 32 * KiB, 2482 .line_size = 64, 2483 .associativity = 8, 2484 .partitions = 1, 2485 .sets = 64, 2486 .lines_per_tag = 1, 2487 .self_init = 1, 2488 .no_invd_sharing = true, 2489 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2490 }, 2491 .l1i_cache = &(CPUCacheInfo) { 2492 .type = INSTRUCTION_CACHE, 2493 .level = 1, 2494 .size = 32 * KiB, 2495 .line_size = 64, 2496 .associativity = 8, 2497 .partitions = 1, 2498 .sets = 64, 2499 .lines_per_tag = 1, 2500 .self_init = 1, 2501 .no_invd_sharing = true, 2502 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2503 }, 2504 .l2_cache = &(CPUCacheInfo) { 2505 .type = UNIFIED_CACHE, 2506 .level = 2, 2507 .size = 512 * KiB, 2508 .line_size = 64, 2509 .associativity = 8, 2510 .partitions = 1, 2511 .sets = 1024, 2512 .lines_per_tag = 1, 2513 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2514 }, 2515 .l3_cache = &(CPUCacheInfo) { 2516 .type = UNIFIED_CACHE, 2517 .level = 3, 2518 .size = 16 * MiB, 2519 .line_size = 64, 2520 .associativity = 16, 2521 .partitions = 1, 2522 .sets = 16384, 2523 .lines_per_tag = 1, 2524 .self_init = true, 2525 .inclusive = true, 2526 .complex_indexing = false, 2527 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2528 }, 2529 }; 2530 2531 static const CPUCaches epyc_rome_v5_cache_info = { 2532 .l1d_cache = &(CPUCacheInfo) { 2533 .type = DATA_CACHE, 2534 .level = 1, 2535 .size = 32 * KiB, 2536 .line_size = 64, 2537 .associativity = 8, 2538 .partitions = 1, 2539 .sets = 64, 2540 .lines_per_tag = 1, 2541 .self_init = true, 2542 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2543 }, 2544 .l1i_cache = &(CPUCacheInfo) { 2545 .type = INSTRUCTION_CACHE, 2546 .level = 1, 2547 .size = 32 * KiB, 2548 .line_size = 64, 2549 .associativity = 8, 2550 .partitions = 1, 2551 .sets = 64, 2552 .lines_per_tag = 1, 2553 .self_init = true, 2554 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2555 }, 2556 .l2_cache = &(CPUCacheInfo) { 2557 .type = UNIFIED_CACHE, 2558 .level = 2, 2559 .size = 512 * KiB, 2560 .line_size = 64, 2561 .associativity = 8, 2562 .partitions = 1, 2563 .sets = 1024, 2564 .lines_per_tag = 1, 2565 .self_init = true, 2566 .inclusive = true, 2567 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2568 }, 2569 .l3_cache = &(CPUCacheInfo) { 2570 .type = UNIFIED_CACHE, 2571 .level = 3, 2572 .size = 16 * MiB, 2573 .line_size = 64, 2574 .associativity = 16, 2575 .partitions = 1, 2576 .sets = 16384, 2577 .lines_per_tag = 1, 2578 .self_init = true, 2579 .no_invd_sharing = true, 2580 .complex_indexing = false, 2581 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2582 }, 2583 }; 2584 2585 static const CPUCaches epyc_milan_cache_info = { 2586 .l1d_cache = &(CPUCacheInfo) { 2587 .type = DATA_CACHE, 2588 .level = 1, 2589 .size = 32 * KiB, 2590 .line_size = 64, 2591 .associativity = 8, 2592 .partitions = 1, 2593 .sets = 64, 2594 .lines_per_tag = 1, 2595 .self_init = 1, 2596 .no_invd_sharing = true, 2597 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2598 }, 2599 .l1i_cache = &(CPUCacheInfo) { 2600 .type = INSTRUCTION_CACHE, 2601 .level = 1, 2602 .size = 32 * KiB, 2603 .line_size = 64, 2604 .associativity = 8, 2605 .partitions = 1, 2606 .sets = 64, 2607 .lines_per_tag = 1, 2608 .self_init = 1, 2609 .no_invd_sharing = true, 2610 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2611 }, 2612 .l2_cache = &(CPUCacheInfo) { 2613 .type = UNIFIED_CACHE, 2614 .level = 2, 2615 .size = 512 * KiB, 2616 .line_size = 64, 2617 .associativity = 8, 2618 .partitions = 1, 2619 .sets = 1024, 2620 .lines_per_tag = 1, 2621 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2622 }, 2623 .l3_cache = &(CPUCacheInfo) { 2624 .type = UNIFIED_CACHE, 2625 .level = 3, 2626 .size = 32 * MiB, 2627 .line_size = 64, 2628 .associativity = 16, 2629 .partitions = 1, 2630 .sets = 32768, 2631 .lines_per_tag = 1, 2632 .self_init = true, 2633 .inclusive = true, 2634 .complex_indexing = true, 2635 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2636 }, 2637 }; 2638 2639 static const CPUCaches epyc_milan_v2_cache_info = { 2640 .l1d_cache = &(CPUCacheInfo) { 2641 .type = DATA_CACHE, 2642 .level = 1, 2643 .size = 32 * KiB, 2644 .line_size = 64, 2645 .associativity = 8, 2646 .partitions = 1, 2647 .sets = 64, 2648 .lines_per_tag = 1, 2649 .self_init = 1, 2650 .no_invd_sharing = true, 2651 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2652 }, 2653 .l1i_cache = &(CPUCacheInfo) { 2654 .type = INSTRUCTION_CACHE, 2655 .level = 1, 2656 .size = 32 * KiB, 2657 .line_size = 64, 2658 .associativity = 8, 2659 .partitions = 1, 2660 .sets = 64, 2661 .lines_per_tag = 1, 2662 .self_init = 1, 2663 .no_invd_sharing = true, 2664 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2665 }, 2666 .l2_cache = &(CPUCacheInfo) { 2667 .type = UNIFIED_CACHE, 2668 .level = 2, 2669 .size = 512 * KiB, 2670 .line_size = 64, 2671 .associativity = 8, 2672 .partitions = 1, 2673 .sets = 1024, 2674 .lines_per_tag = 1, 2675 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2676 }, 2677 .l3_cache = &(CPUCacheInfo) { 2678 .type = UNIFIED_CACHE, 2679 .level = 3, 2680 .size = 32 * MiB, 2681 .line_size = 64, 2682 .associativity = 16, 2683 .partitions = 1, 2684 .sets = 32768, 2685 .lines_per_tag = 1, 2686 .self_init = true, 2687 .inclusive = true, 2688 .complex_indexing = false, 2689 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2690 }, 2691 }; 2692 2693 static const CPUCaches epyc_milan_v3_cache_info = { 2694 .l1d_cache = &(CPUCacheInfo) { 2695 .type = DATA_CACHE, 2696 .level = 1, 2697 .size = 32 * KiB, 2698 .line_size = 64, 2699 .associativity = 8, 2700 .partitions = 1, 2701 .sets = 64, 2702 .lines_per_tag = 1, 2703 .self_init = true, 2704 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2705 }, 2706 .l1i_cache = &(CPUCacheInfo) { 2707 .type = INSTRUCTION_CACHE, 2708 .level = 1, 2709 .size = 32 * KiB, 2710 .line_size = 64, 2711 .associativity = 8, 2712 .partitions = 1, 2713 .sets = 64, 2714 .lines_per_tag = 1, 2715 .self_init = true, 2716 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2717 }, 2718 .l2_cache = &(CPUCacheInfo) { 2719 .type = UNIFIED_CACHE, 2720 .level = 2, 2721 .size = 512 * KiB, 2722 .line_size = 64, 2723 .associativity = 8, 2724 .partitions = 1, 2725 .sets = 1024, 2726 .lines_per_tag = 1, 2727 .self_init = true, 2728 .inclusive = true, 2729 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2730 }, 2731 .l3_cache = &(CPUCacheInfo) { 2732 .type = UNIFIED_CACHE, 2733 .level = 3, 2734 .size = 32 * MiB, 2735 .line_size = 64, 2736 .associativity = 16, 2737 .partitions = 1, 2738 .sets = 32768, 2739 .lines_per_tag = 1, 2740 .self_init = true, 2741 .no_invd_sharing = true, 2742 .complex_indexing = false, 2743 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2744 }, 2745 }; 2746 2747 static const CPUCaches epyc_genoa_cache_info = { 2748 .l1d_cache = &(CPUCacheInfo) { 2749 .type = DATA_CACHE, 2750 .level = 1, 2751 .size = 32 * KiB, 2752 .line_size = 64, 2753 .associativity = 8, 2754 .partitions = 1, 2755 .sets = 64, 2756 .lines_per_tag = 1, 2757 .self_init = 1, 2758 .no_invd_sharing = true, 2759 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2760 }, 2761 .l1i_cache = &(CPUCacheInfo) { 2762 .type = INSTRUCTION_CACHE, 2763 .level = 1, 2764 .size = 32 * KiB, 2765 .line_size = 64, 2766 .associativity = 8, 2767 .partitions = 1, 2768 .sets = 64, 2769 .lines_per_tag = 1, 2770 .self_init = 1, 2771 .no_invd_sharing = true, 2772 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2773 }, 2774 .l2_cache = &(CPUCacheInfo) { 2775 .type = UNIFIED_CACHE, 2776 .level = 2, 2777 .size = 1 * MiB, 2778 .line_size = 64, 2779 .associativity = 8, 2780 .partitions = 1, 2781 .sets = 2048, 2782 .lines_per_tag = 1, 2783 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2784 }, 2785 .l3_cache = &(CPUCacheInfo) { 2786 .type = UNIFIED_CACHE, 2787 .level = 3, 2788 .size = 32 * MiB, 2789 .line_size = 64, 2790 .associativity = 16, 2791 .partitions = 1, 2792 .sets = 32768, 2793 .lines_per_tag = 1, 2794 .self_init = true, 2795 .inclusive = true, 2796 .complex_indexing = false, 2797 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2798 }, 2799 }; 2800 2801 static const CPUCaches epyc_genoa_v2_cache_info = { 2802 .l1d_cache = &(CPUCacheInfo) { 2803 .type = DATA_CACHE, 2804 .level = 1, 2805 .size = 32 * KiB, 2806 .line_size = 64, 2807 .associativity = 8, 2808 .partitions = 1, 2809 .sets = 64, 2810 .lines_per_tag = 1, 2811 .self_init = true, 2812 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2813 }, 2814 .l1i_cache = &(CPUCacheInfo) { 2815 .type = INSTRUCTION_CACHE, 2816 .level = 1, 2817 .size = 32 * KiB, 2818 .line_size = 64, 2819 .associativity = 8, 2820 .partitions = 1, 2821 .sets = 64, 2822 .lines_per_tag = 1, 2823 .self_init = true, 2824 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2825 }, 2826 .l2_cache = &(CPUCacheInfo) { 2827 .type = UNIFIED_CACHE, 2828 .level = 2, 2829 .size = 1 * MiB, 2830 .line_size = 64, 2831 .associativity = 8, 2832 .partitions = 1, 2833 .sets = 2048, 2834 .lines_per_tag = 1, 2835 .self_init = true, 2836 .inclusive = true, 2837 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2838 }, 2839 .l3_cache = &(CPUCacheInfo) { 2840 .type = UNIFIED_CACHE, 2841 .level = 3, 2842 .size = 32 * MiB, 2843 .line_size = 64, 2844 .associativity = 16, 2845 .partitions = 1, 2846 .sets = 32768, 2847 .lines_per_tag = 1, 2848 .self_init = true, 2849 .no_invd_sharing = true, 2850 .complex_indexing = false, 2851 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2852 }, 2853 }; 2854 2855 static const CPUCaches epyc_turin_cache_info = { 2856 .l1d_cache = &(CPUCacheInfo) { 2857 .type = DATA_CACHE, 2858 .level = 1, 2859 .size = 48 * KiB, 2860 .line_size = 64, 2861 .associativity = 12, 2862 .partitions = 1, 2863 .sets = 64, 2864 .lines_per_tag = 1, 2865 .self_init = true, 2866 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2867 }, 2868 .l1i_cache = &(CPUCacheInfo) { 2869 .type = INSTRUCTION_CACHE, 2870 .level = 1, 2871 .size = 32 * KiB, 2872 .line_size = 64, 2873 .associativity = 8, 2874 .partitions = 1, 2875 .sets = 64, 2876 .lines_per_tag = 1, 2877 .self_init = true, 2878 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2879 }, 2880 .l2_cache = &(CPUCacheInfo) { 2881 .type = UNIFIED_CACHE, 2882 .level = 2, 2883 .size = 1 * MiB, 2884 .line_size = 64, 2885 .associativity = 16, 2886 .partitions = 1, 2887 .sets = 1024, 2888 .lines_per_tag = 1, 2889 .self_init = true, 2890 .inclusive = true, 2891 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2892 }, 2893 .l3_cache = &(CPUCacheInfo) { 2894 .type = UNIFIED_CACHE, 2895 .level = 3, 2896 .size = 32 * MiB, 2897 .line_size = 64, 2898 .associativity = 16, 2899 .partitions = 1, 2900 .sets = 32768, 2901 .lines_per_tag = 1, 2902 .self_init = true, 2903 .no_invd_sharing = true, 2904 .complex_indexing = false, 2905 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2906 } 2907 }; 2908 2909 static const CPUCaches xeon_spr_cache_info = { 2910 .l1d_cache = &(CPUCacheInfo) { 2911 /* CPUID 0x4.0x0.EAX */ 2912 .type = DATA_CACHE, 2913 .level = 1, 2914 .self_init = true, 2915 2916 /* CPUID 0x4.0x0.EBX */ 2917 .line_size = 64, 2918 .partitions = 1, 2919 .associativity = 12, 2920 2921 /* CPUID 0x4.0x0.ECX */ 2922 .sets = 64, 2923 2924 /* CPUID 0x4.0x0.EDX */ 2925 .no_invd_sharing = false, 2926 .inclusive = false, 2927 .complex_indexing = false, 2928 2929 .size = 48 * KiB, 2930 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2931 }, 2932 .l1i_cache = &(CPUCacheInfo) { 2933 /* CPUID 0x4.0x1.EAX */ 2934 .type = INSTRUCTION_CACHE, 2935 .level = 1, 2936 .self_init = true, 2937 2938 /* CPUID 0x4.0x1.EBX */ 2939 .line_size = 64, 2940 .partitions = 1, 2941 .associativity = 8, 2942 2943 /* CPUID 0x4.0x1.ECX */ 2944 .sets = 64, 2945 2946 /* CPUID 0x4.0x1.EDX */ 2947 .no_invd_sharing = false, 2948 .inclusive = false, 2949 .complex_indexing = false, 2950 2951 .size = 32 * KiB, 2952 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2953 }, 2954 .l2_cache = &(CPUCacheInfo) { 2955 /* CPUID 0x4.0x2.EAX */ 2956 .type = UNIFIED_CACHE, 2957 .level = 2, 2958 .self_init = true, 2959 2960 /* CPUID 0x4.0x2.EBX */ 2961 .line_size = 64, 2962 .partitions = 1, 2963 .associativity = 16, 2964 2965 /* CPUID 0x4.0x2.ECX */ 2966 .sets = 2048, 2967 2968 /* CPUID 0x4.0x2.EDX */ 2969 .no_invd_sharing = false, 2970 .inclusive = false, 2971 .complex_indexing = false, 2972 2973 .size = 2 * MiB, 2974 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2975 }, 2976 .l3_cache = &(CPUCacheInfo) { 2977 /* CPUID 0x4.0x3.EAX */ 2978 .type = UNIFIED_CACHE, 2979 .level = 3, 2980 .self_init = true, 2981 2982 /* CPUID 0x4.0x3.EBX */ 2983 .line_size = 64, 2984 .partitions = 1, 2985 .associativity = 15, 2986 2987 /* CPUID 0x4.0x3.ECX */ 2988 .sets = 65536, 2989 2990 /* CPUID 0x4.0x3.EDX */ 2991 .no_invd_sharing = false, 2992 .inclusive = false, 2993 .complex_indexing = true, 2994 2995 .size = 60 * MiB, 2996 .share_level = CPU_TOPOLOGY_LEVEL_SOCKET, 2997 }, 2998 }; 2999 3000 static const CPUCaches xeon_gnr_cache_info = { 3001 .l1d_cache = &(CPUCacheInfo) { 3002 /* CPUID 0x4.0x0.EAX */ 3003 .type = DATA_CACHE, 3004 .level = 1, 3005 .self_init = true, 3006 3007 /* CPUID 0x4.0x0.EBX */ 3008 .line_size = 64, 3009 .partitions = 1, 3010 .associativity = 12, 3011 3012 /* CPUID 0x4.0x0.ECX */ 3013 .sets = 64, 3014 3015 /* CPUID 0x4.0x0.EDX */ 3016 .no_invd_sharing = false, 3017 .inclusive = false, 3018 .complex_indexing = false, 3019 3020 .size = 48 * KiB, 3021 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3022 }, 3023 .l1i_cache = &(CPUCacheInfo) { 3024 /* CPUID 0x4.0x1.EAX */ 3025 .type = INSTRUCTION_CACHE, 3026 .level = 1, 3027 .self_init = true, 3028 3029 /* CPUID 0x4.0x1.EBX */ 3030 .line_size = 64, 3031 .partitions = 1, 3032 .associativity = 16, 3033 3034 /* CPUID 0x4.0x1.ECX */ 3035 .sets = 64, 3036 3037 /* CPUID 0x4.0x1.EDX */ 3038 .no_invd_sharing = false, 3039 .inclusive = false, 3040 .complex_indexing = false, 3041 3042 .size = 64 * KiB, 3043 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3044 }, 3045 .l2_cache = &(CPUCacheInfo) { 3046 /* CPUID 0x4.0x2.EAX */ 3047 .type = UNIFIED_CACHE, 3048 .level = 2, 3049 .self_init = true, 3050 3051 /* CPUID 0x4.0x2.EBX */ 3052 .line_size = 64, 3053 .partitions = 1, 3054 .associativity = 16, 3055 3056 /* CPUID 0x4.0x2.ECX */ 3057 .sets = 2048, 3058 3059 /* CPUID 0x4.0x2.EDX */ 3060 .no_invd_sharing = false, 3061 .inclusive = false, 3062 .complex_indexing = false, 3063 3064 .size = 2 * MiB, 3065 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3066 }, 3067 .l3_cache = &(CPUCacheInfo) { 3068 /* CPUID 0x4.0x3.EAX */ 3069 .type = UNIFIED_CACHE, 3070 .level = 3, 3071 .self_init = true, 3072 3073 /* CPUID 0x4.0x3.EBX */ 3074 .line_size = 64, 3075 .partitions = 1, 3076 .associativity = 16, 3077 3078 /* CPUID 0x4.0x3.ECX */ 3079 .sets = 294912, 3080 3081 /* CPUID 0x4.0x3.EDX */ 3082 .no_invd_sharing = false, 3083 .inclusive = false, 3084 .complex_indexing = true, 3085 3086 .size = 288 * MiB, 3087 .share_level = CPU_TOPOLOGY_LEVEL_SOCKET, 3088 }, 3089 }; 3090 3091 static const CPUCaches xeon_srf_cache_info = { 3092 .l1d_cache = &(CPUCacheInfo) { 3093 /* CPUID 0x4.0x0.EAX */ 3094 .type = DATA_CACHE, 3095 .level = 1, 3096 .self_init = true, 3097 3098 /* CPUID 0x4.0x0.EBX */ 3099 .line_size = 64, 3100 .partitions = 1, 3101 .associativity = 8, 3102 3103 /* CPUID 0x4.0x0.ECX */ 3104 .sets = 64, 3105 3106 /* CPUID 0x4.0x0.EDX */ 3107 .no_invd_sharing = false, 3108 .inclusive = false, 3109 .complex_indexing = false, 3110 3111 .size = 32 * KiB, 3112 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3113 }, 3114 .l1i_cache = &(CPUCacheInfo) { 3115 /* CPUID 0x4.0x1.EAX */ 3116 .type = INSTRUCTION_CACHE, 3117 .level = 1, 3118 .self_init = true, 3119 3120 /* CPUID 0x4.0x1.EBX */ 3121 .line_size = 64, 3122 .partitions = 1, 3123 .associativity = 8, 3124 3125 /* CPUID 0x4.0x1.ECX */ 3126 .sets = 128, 3127 3128 /* CPUID 0x4.0x1.EDX */ 3129 .no_invd_sharing = false, 3130 .inclusive = false, 3131 .complex_indexing = false, 3132 3133 .size = 64 * KiB, 3134 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3135 }, 3136 .l2_cache = &(CPUCacheInfo) { 3137 /* CPUID 0x4.0x2.EAX */ 3138 .type = UNIFIED_CACHE, 3139 .level = 2, 3140 .self_init = true, 3141 3142 /* CPUID 0x4.0x2.EBX */ 3143 .line_size = 64, 3144 .partitions = 1, 3145 .associativity = 16, 3146 3147 /* CPUID 0x4.0x2.ECX */ 3148 .sets = 4096, 3149 3150 /* CPUID 0x4.0x2.EDX */ 3151 .no_invd_sharing = false, 3152 .inclusive = false, 3153 .complex_indexing = false, 3154 3155 .size = 4 * MiB, 3156 .share_level = CPU_TOPOLOGY_LEVEL_MODULE, 3157 }, 3158 .l3_cache = &(CPUCacheInfo) { 3159 /* CPUID 0x4.0x3.EAX */ 3160 .type = UNIFIED_CACHE, 3161 .level = 3, 3162 .self_init = true, 3163 3164 /* CPUID 0x4.0x3.EBX */ 3165 .line_size = 64, 3166 .partitions = 1, 3167 .associativity = 12, 3168 3169 /* CPUID 0x4.0x3.ECX */ 3170 .sets = 147456, 3171 3172 /* CPUID 0x4.0x3.EDX */ 3173 .no_invd_sharing = false, 3174 .inclusive = false, 3175 .complex_indexing = true, 3176 3177 .size = 108 * MiB, 3178 .share_level = CPU_TOPOLOGY_LEVEL_SOCKET, 3179 }, 3180 }; 3181 3182 static const CPUCaches yongfeng_cache_info = { 3183 .l1d_cache = &(CPUCacheInfo) { 3184 /* CPUID 0x4.0x0.EAX */ 3185 .type = DATA_CACHE, 3186 .level = 1, 3187 .self_init = true, 3188 3189 /* CPUID 0x4.0x0.EBX */ 3190 .line_size = 64, 3191 .partitions = 1, 3192 .associativity = 8, 3193 3194 /* CPUID 0x4.0x0.ECX */ 3195 .sets = 64, 3196 3197 /* CPUID 0x4.0x0.EDX */ 3198 .no_invd_sharing = false, 3199 .inclusive = false, 3200 .complex_indexing = false, 3201 3202 /* CPUID 0x80000005.ECX */ 3203 .lines_per_tag = 1, 3204 .size = 32 * KiB, 3205 3206 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3207 }, 3208 .l1i_cache = &(CPUCacheInfo) { 3209 /* CPUID 0x4.0x1.EAX */ 3210 .type = INSTRUCTION_CACHE, 3211 .level = 1, 3212 .self_init = true, 3213 3214 /* CPUID 0x4.0x1.EBX */ 3215 .line_size = 64, 3216 .partitions = 1, 3217 .associativity = 16, 3218 3219 /* CPUID 0x4.0x1.ECX */ 3220 .sets = 64, 3221 3222 /* CPUID 0x4.0x1.EDX */ 3223 .no_invd_sharing = false, 3224 .inclusive = false, 3225 .complex_indexing = false, 3226 3227 /* CPUID 0x80000005.EDX */ 3228 .lines_per_tag = 1, 3229 .size = 64 * KiB, 3230 3231 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3232 }, 3233 .l2_cache = &(CPUCacheInfo) { 3234 /* CPUID 0x4.0x2.EAX */ 3235 .type = UNIFIED_CACHE, 3236 .level = 2, 3237 .self_init = true, 3238 3239 /* CPUID 0x4.0x2.EBX */ 3240 .line_size = 64, 3241 .partitions = 1, 3242 .associativity = 8, 3243 3244 /* CPUID 0x4.0x2.ECX */ 3245 .sets = 512, 3246 3247 /* CPUID 0x4.0x2.EDX */ 3248 .no_invd_sharing = false, 3249 .inclusive = true, 3250 .complex_indexing = false, 3251 3252 /* CPUID 0x80000006.ECX */ 3253 .size = 256 * KiB, 3254 3255 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3256 }, 3257 .l3_cache = &(CPUCacheInfo) { 3258 /* CPUID 0x4.0x3.EAX */ 3259 .type = UNIFIED_CACHE, 3260 .level = 3, 3261 .self_init = true, 3262 3263 /* CPUID 0x4.0x3.EBX */ 3264 .line_size = 64, 3265 .partitions = 1, 3266 .associativity = 16, 3267 3268 /* CPUID 0x4.0x3.ECX */ 3269 .sets = 8192, 3270 3271 /* CPUID 0x4.0x3.EDX */ 3272 .no_invd_sharing = true, 3273 .inclusive = true, 3274 .complex_indexing = false, 3275 3276 .size = 8 * MiB, 3277 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 3278 }, 3279 }; 3280 3281 /* The following VMX features are not supported by KVM and are left out in the 3282 * CPU definitions: 3283 * 3284 * Dual-monitor support (all processors) 3285 * Entry to SMM 3286 * Deactivate dual-monitor treatment 3287 * Number of CR3-target values 3288 * Shutdown activity state 3289 * Wait-for-SIPI activity state 3290 * PAUSE-loop exiting (Westmere and newer) 3291 * EPT-violation #VE (Broadwell and newer) 3292 * Inject event with insn length=0 (Skylake and newer) 3293 * Conceal non-root operation from PT 3294 * Conceal VM exits from PT 3295 * Conceal VM entries from PT 3296 * Enable ENCLS exiting 3297 * Mode-based execute control (XS/XU) 3298 * TSC scaling (Skylake Server and newer) 3299 * GPA translation for PT (IceLake and newer) 3300 * User wait and pause 3301 * ENCLV exiting 3302 * Load IA32_RTIT_CTL 3303 * Clear IA32_RTIT_CTL 3304 * Advanced VM-exit information for EPT violations 3305 * Sub-page write permissions 3306 * PT in VMX operation 3307 */ 3308 3309 static const X86CPUDefinition builtin_x86_defs[] = { 3310 { 3311 .name = "qemu64", 3312 .level = 0xd, 3313 .vendor = CPUID_VENDOR_AMD, 3314 .family = 15, 3315 .model = 107, 3316 .stepping = 1, 3317 .features[FEAT_1_EDX] = 3318 PPRO_FEATURES | 3319 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3320 CPUID_PSE36, 3321 .features[FEAT_1_ECX] = 3322 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 3323 .features[FEAT_8000_0001_EDX] = 3324 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3325 .features[FEAT_8000_0001_ECX] = 3326 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 3327 .xlevel = 0x8000000A, 3328 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3329 }, 3330 { 3331 .name = "phenom", 3332 .level = 5, 3333 .vendor = CPUID_VENDOR_AMD, 3334 .family = 16, 3335 .model = 2, 3336 .stepping = 3, 3337 /* Missing: CPUID_HT */ 3338 .features[FEAT_1_EDX] = 3339 PPRO_FEATURES | 3340 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3341 CPUID_PSE36 | CPUID_VME, 3342 .features[FEAT_1_ECX] = 3343 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 3344 CPUID_EXT_POPCNT, 3345 .features[FEAT_8000_0001_EDX] = 3346 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 3347 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 3348 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 3349 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 3350 CPUID_EXT3_CR8LEG, 3351 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 3352 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 3353 .features[FEAT_8000_0001_ECX] = 3354 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 3355 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 3356 /* Missing: CPUID_SVM_LBRV */ 3357 .features[FEAT_SVM] = 3358 CPUID_SVM_NPT, 3359 .xlevel = 0x8000001A, 3360 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 3361 }, 3362 { 3363 .name = "core2duo", 3364 .level = 10, 3365 .vendor = CPUID_VENDOR_INTEL, 3366 .family = 6, 3367 .model = 15, 3368 .stepping = 11, 3369 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3370 .features[FEAT_1_EDX] = 3371 PPRO_FEATURES | 3372 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3373 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 3374 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 3375 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 3376 .features[FEAT_1_ECX] = 3377 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 3378 CPUID_EXT_CX16, 3379 .features[FEAT_8000_0001_EDX] = 3380 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3381 .features[FEAT_8000_0001_ECX] = 3382 CPUID_EXT3_LAHF_LM, 3383 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3384 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3385 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3386 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3387 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3388 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3389 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3390 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3391 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3392 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3393 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3394 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3395 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3396 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3397 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3398 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3399 .features[FEAT_VMX_SECONDARY_CTLS] = 3400 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 3401 .xlevel = 0x80000008, 3402 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 3403 }, 3404 { 3405 .name = "kvm64", 3406 .level = 0xd, 3407 .vendor = CPUID_VENDOR_INTEL, 3408 .family = 15, 3409 .model = 6, 3410 .stepping = 1, 3411 /* Missing: CPUID_HT */ 3412 .features[FEAT_1_EDX] = 3413 PPRO_FEATURES | CPUID_VME | 3414 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3415 CPUID_PSE36, 3416 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 3417 .features[FEAT_1_ECX] = 3418 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 3419 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 3420 .features[FEAT_8000_0001_EDX] = 3421 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3422 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 3423 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 3424 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 3425 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 3426 .features[FEAT_8000_0001_ECX] = 3427 0, 3428 /* VMX features from Cedar Mill/Prescott */ 3429 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3430 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3431 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3432 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3433 VMX_PIN_BASED_NMI_EXITING, 3434 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3435 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3436 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3437 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3438 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3439 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3440 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3441 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 3442 .xlevel = 0x80000008, 3443 .model_id = "Common KVM processor" 3444 }, 3445 { 3446 .name = "qemu32", 3447 .level = 4, 3448 .vendor = CPUID_VENDOR_INTEL, 3449 .family = 6, 3450 .model = 6, 3451 .stepping = 3, 3452 .features[FEAT_1_EDX] = 3453 PPRO_FEATURES, 3454 .features[FEAT_1_ECX] = 3455 CPUID_EXT_SSE3, 3456 .xlevel = 0x80000004, 3457 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3458 }, 3459 { 3460 .name = "kvm32", 3461 .level = 5, 3462 .vendor = CPUID_VENDOR_INTEL, 3463 .family = 15, 3464 .model = 6, 3465 .stepping = 1, 3466 .features[FEAT_1_EDX] = 3467 PPRO_FEATURES | CPUID_VME | 3468 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 3469 .features[FEAT_1_ECX] = 3470 CPUID_EXT_SSE3, 3471 .features[FEAT_8000_0001_ECX] = 3472 0, 3473 /* VMX features from Yonah */ 3474 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3475 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3476 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3477 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3478 VMX_PIN_BASED_NMI_EXITING, 3479 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3480 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3481 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3482 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3483 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3484 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3485 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 3486 .xlevel = 0x80000008, 3487 .model_id = "Common 32-bit KVM processor" 3488 }, 3489 { 3490 .name = "coreduo", 3491 .level = 10, 3492 .vendor = CPUID_VENDOR_INTEL, 3493 .family = 6, 3494 .model = 14, 3495 .stepping = 8, 3496 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3497 .features[FEAT_1_EDX] = 3498 PPRO_FEATURES | CPUID_VME | 3499 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 3500 CPUID_SS, 3501 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 3502 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 3503 .features[FEAT_1_ECX] = 3504 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 3505 .features[FEAT_8000_0001_EDX] = 3506 CPUID_EXT2_NX, 3507 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3508 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3509 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3510 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3511 VMX_PIN_BASED_NMI_EXITING, 3512 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3513 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3514 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3515 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3516 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3517 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3518 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 3519 .xlevel = 0x80000008, 3520 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 3521 }, 3522 { 3523 .name = "486", 3524 .level = 1, 3525 .vendor = CPUID_VENDOR_INTEL, 3526 .family = 4, 3527 .model = 8, 3528 .stepping = 0, 3529 .features[FEAT_1_EDX] = 3530 I486_FEATURES, 3531 .xlevel = 0, 3532 .model_id = "", 3533 .cache_info = &legacy_intel_cpuid2_cache_info, 3534 }, 3535 { 3536 .name = "pentium", 3537 .level = 1, 3538 .vendor = CPUID_VENDOR_INTEL, 3539 .family = 5, 3540 .model = 4, 3541 .stepping = 3, 3542 .features[FEAT_1_EDX] = 3543 PENTIUM_FEATURES, 3544 .xlevel = 0, 3545 .model_id = "", 3546 .cache_info = &legacy_intel_cpuid2_cache_info, 3547 }, 3548 { 3549 .name = "pentium2", 3550 .level = 2, 3551 .vendor = CPUID_VENDOR_INTEL, 3552 .family = 6, 3553 .model = 5, 3554 .stepping = 2, 3555 .features[FEAT_1_EDX] = 3556 PENTIUM2_FEATURES, 3557 .xlevel = 0, 3558 .model_id = "", 3559 .cache_info = &legacy_intel_cpuid2_cache_info, 3560 }, 3561 { 3562 .name = "pentium3", 3563 .level = 3, 3564 .vendor = CPUID_VENDOR_INTEL, 3565 .family = 6, 3566 .model = 7, 3567 .stepping = 3, 3568 .features[FEAT_1_EDX] = 3569 PENTIUM3_FEATURES, 3570 .xlevel = 0, 3571 .model_id = "", 3572 .cache_info = &legacy_intel_cpuid2_cache_info, 3573 }, 3574 { 3575 .name = "athlon", 3576 .level = 2, 3577 .vendor = CPUID_VENDOR_AMD, 3578 .family = 6, 3579 .model = 2, 3580 .stepping = 3, 3581 .features[FEAT_1_EDX] = 3582 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 3583 CPUID_MCA, 3584 .features[FEAT_8000_0001_EDX] = 3585 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 3586 .xlevel = 0x80000008, 3587 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3588 }, 3589 { 3590 .name = "n270", 3591 .level = 10, 3592 .vendor = CPUID_VENDOR_INTEL, 3593 .family = 6, 3594 .model = 28, 3595 .stepping = 2, 3596 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3597 .features[FEAT_1_EDX] = 3598 PPRO_FEATURES | 3599 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 3600 CPUID_ACPI | CPUID_SS, 3601 /* Some CPUs got no CPUID_SEP */ 3602 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 3603 * CPUID_EXT_XTPR */ 3604 .features[FEAT_1_ECX] = 3605 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 3606 CPUID_EXT_MOVBE, 3607 .features[FEAT_8000_0001_EDX] = 3608 CPUID_EXT2_NX, 3609 .features[FEAT_8000_0001_ECX] = 3610 CPUID_EXT3_LAHF_LM, 3611 .xlevel = 0x80000008, 3612 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 3613 }, 3614 { 3615 .name = "Conroe", 3616 .level = 10, 3617 .vendor = CPUID_VENDOR_INTEL, 3618 .family = 6, 3619 .model = 15, 3620 .stepping = 3, 3621 .features[FEAT_1_EDX] = 3622 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3623 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3624 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3625 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3626 CPUID_DE | CPUID_FP87, 3627 .features[FEAT_1_ECX] = 3628 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3629 .features[FEAT_8000_0001_EDX] = 3630 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3631 .features[FEAT_8000_0001_ECX] = 3632 CPUID_EXT3_LAHF_LM, 3633 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3634 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3635 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3636 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3637 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3638 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3639 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3640 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3641 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3642 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3643 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3644 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3645 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3646 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3647 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3648 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3649 .features[FEAT_VMX_SECONDARY_CTLS] = 3650 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 3651 .xlevel = 0x80000008, 3652 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 3653 }, 3654 { 3655 .name = "Penryn", 3656 .level = 10, 3657 .vendor = CPUID_VENDOR_INTEL, 3658 .family = 6, 3659 .model = 23, 3660 .stepping = 3, 3661 .features[FEAT_1_EDX] = 3662 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3663 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3664 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3665 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3666 CPUID_DE | CPUID_FP87, 3667 .features[FEAT_1_ECX] = 3668 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3669 CPUID_EXT_SSE3, 3670 .features[FEAT_8000_0001_EDX] = 3671 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3672 .features[FEAT_8000_0001_ECX] = 3673 CPUID_EXT3_LAHF_LM, 3674 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3675 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3676 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 3677 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 3678 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 3679 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3680 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3681 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3682 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3683 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3684 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3685 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3686 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3687 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3688 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3689 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3690 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3691 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3692 .features[FEAT_VMX_SECONDARY_CTLS] = 3693 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3694 VMX_SECONDARY_EXEC_WBINVD_EXITING, 3695 .xlevel = 0x80000008, 3696 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 3697 }, 3698 { 3699 .name = "Nehalem", 3700 .level = 11, 3701 .vendor = CPUID_VENDOR_INTEL, 3702 .family = 6, 3703 .model = 26, 3704 .stepping = 3, 3705 .features[FEAT_1_EDX] = 3706 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3707 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3708 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3709 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3710 CPUID_DE | CPUID_FP87, 3711 .features[FEAT_1_ECX] = 3712 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3713 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3714 .features[FEAT_8000_0001_EDX] = 3715 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3716 .features[FEAT_8000_0001_ECX] = 3717 CPUID_EXT3_LAHF_LM, 3718 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3719 MSR_VMX_BASIC_TRUE_CTLS, 3720 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3721 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3722 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3723 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3724 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3725 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3726 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3727 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3728 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3729 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3730 .features[FEAT_VMX_EXIT_CTLS] = 3731 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3732 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3733 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3734 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3735 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3736 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3737 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3738 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3739 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3740 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3741 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3742 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3743 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3744 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3745 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3746 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3747 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3748 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3749 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3750 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3751 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3752 .features[FEAT_VMX_SECONDARY_CTLS] = 3753 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3754 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3755 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3756 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3757 VMX_SECONDARY_EXEC_ENABLE_VPID, 3758 .xlevel = 0x80000008, 3759 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 3760 .versions = (X86CPUVersionDefinition[]) { 3761 { .version = 1 }, 3762 { 3763 .version = 2, 3764 .alias = "Nehalem-IBRS", 3765 .props = (PropValue[]) { 3766 { "spec-ctrl", "on" }, 3767 { "model-id", 3768 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 3769 { /* end of list */ } 3770 } 3771 }, 3772 { /* end of list */ } 3773 } 3774 }, 3775 { 3776 .name = "Westmere", 3777 .level = 11, 3778 .vendor = CPUID_VENDOR_INTEL, 3779 .family = 6, 3780 .model = 44, 3781 .stepping = 1, 3782 .features[FEAT_1_EDX] = 3783 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3784 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3785 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3786 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3787 CPUID_DE | CPUID_FP87, 3788 .features[FEAT_1_ECX] = 3789 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3790 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3791 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3792 .features[FEAT_8000_0001_EDX] = 3793 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3794 .features[FEAT_8000_0001_ECX] = 3795 CPUID_EXT3_LAHF_LM, 3796 .features[FEAT_6_EAX] = 3797 CPUID_6_EAX_ARAT, 3798 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3799 MSR_VMX_BASIC_TRUE_CTLS, 3800 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3801 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3802 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3803 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3804 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3805 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3806 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3807 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3808 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3809 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3810 .features[FEAT_VMX_EXIT_CTLS] = 3811 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3812 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3813 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3814 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3815 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3816 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3817 MSR_VMX_MISC_STORE_LMA, 3818 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3819 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3820 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3821 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3822 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3823 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3824 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3825 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3826 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3827 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3828 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3829 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3830 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3831 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3832 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3833 .features[FEAT_VMX_SECONDARY_CTLS] = 3834 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3835 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3836 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3837 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3838 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3839 .xlevel = 0x80000008, 3840 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3841 .versions = (X86CPUVersionDefinition[]) { 3842 { .version = 1 }, 3843 { 3844 .version = 2, 3845 .alias = "Westmere-IBRS", 3846 .props = (PropValue[]) { 3847 { "spec-ctrl", "on" }, 3848 { "model-id", 3849 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3850 { /* end of list */ } 3851 } 3852 }, 3853 { /* end of list */ } 3854 } 3855 }, 3856 { 3857 .name = "SandyBridge", 3858 .level = 0xd, 3859 .vendor = CPUID_VENDOR_INTEL, 3860 .family = 6, 3861 .model = 42, 3862 .stepping = 1, 3863 .features[FEAT_1_EDX] = 3864 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3865 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3866 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3867 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3868 CPUID_DE | CPUID_FP87, 3869 .features[FEAT_1_ECX] = 3870 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3871 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3872 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3873 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3874 CPUID_EXT_SSE3, 3875 .features[FEAT_8000_0001_EDX] = 3876 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3877 CPUID_EXT2_SYSCALL, 3878 .features[FEAT_8000_0001_ECX] = 3879 CPUID_EXT3_LAHF_LM, 3880 .features[FEAT_XSAVE] = 3881 CPUID_XSAVE_XSAVEOPT, 3882 .features[FEAT_6_EAX] = 3883 CPUID_6_EAX_ARAT, 3884 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3885 MSR_VMX_BASIC_TRUE_CTLS, 3886 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3887 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3888 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3889 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3890 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3891 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3892 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3893 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3894 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3895 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3896 .features[FEAT_VMX_EXIT_CTLS] = 3897 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3898 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3899 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3900 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3901 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3902 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3903 MSR_VMX_MISC_STORE_LMA, 3904 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3905 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3906 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3907 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3908 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3909 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3910 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3911 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3912 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3913 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3914 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3915 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3916 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3917 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3918 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3919 .features[FEAT_VMX_SECONDARY_CTLS] = 3920 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3921 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3922 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3923 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3924 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3925 .xlevel = 0x80000008, 3926 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3927 .versions = (X86CPUVersionDefinition[]) { 3928 { .version = 1 }, 3929 { 3930 .version = 2, 3931 .alias = "SandyBridge-IBRS", 3932 .props = (PropValue[]) { 3933 { "spec-ctrl", "on" }, 3934 { "model-id", 3935 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3936 { /* end of list */ } 3937 } 3938 }, 3939 { /* end of list */ } 3940 } 3941 }, 3942 { 3943 .name = "IvyBridge", 3944 .level = 0xd, 3945 .vendor = CPUID_VENDOR_INTEL, 3946 .family = 6, 3947 .model = 58, 3948 .stepping = 9, 3949 .features[FEAT_1_EDX] = 3950 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3954 CPUID_DE | CPUID_FP87, 3955 .features[FEAT_1_ECX] = 3956 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3957 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3958 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3959 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3960 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3961 .features[FEAT_7_0_EBX] = 3962 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3963 CPUID_7_0_EBX_ERMS, 3964 .features[FEAT_8000_0001_EDX] = 3965 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3966 CPUID_EXT2_SYSCALL, 3967 .features[FEAT_8000_0001_ECX] = 3968 CPUID_EXT3_LAHF_LM, 3969 .features[FEAT_XSAVE] = 3970 CPUID_XSAVE_XSAVEOPT, 3971 .features[FEAT_6_EAX] = 3972 CPUID_6_EAX_ARAT, 3973 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3974 MSR_VMX_BASIC_TRUE_CTLS, 3975 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3976 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3977 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3978 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3979 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3980 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3981 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3982 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3983 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3984 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3985 .features[FEAT_VMX_EXIT_CTLS] = 3986 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3987 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3988 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3989 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3990 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3991 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3992 MSR_VMX_MISC_STORE_LMA, 3993 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3994 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3995 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3996 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3997 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3998 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3999 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4000 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4001 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4002 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4003 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4004 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4005 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4006 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4007 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4008 .features[FEAT_VMX_SECONDARY_CTLS] = 4009 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4010 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4011 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4012 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4013 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4014 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4015 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4016 VMX_SECONDARY_EXEC_RDRAND_EXITING, 4017 .xlevel = 0x80000008, 4018 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 4019 .versions = (X86CPUVersionDefinition[]) { 4020 { .version = 1 }, 4021 { 4022 .version = 2, 4023 .alias = "IvyBridge-IBRS", 4024 .props = (PropValue[]) { 4025 { "spec-ctrl", "on" }, 4026 { "model-id", 4027 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 4028 { /* end of list */ } 4029 } 4030 }, 4031 { /* end of list */ } 4032 } 4033 }, 4034 { 4035 .name = "Haswell", 4036 .level = 0xd, 4037 .vendor = CPUID_VENDOR_INTEL, 4038 .family = 6, 4039 .model = 60, 4040 .stepping = 4, 4041 .features[FEAT_1_EDX] = 4042 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4043 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4044 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4045 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4046 CPUID_DE | CPUID_FP87, 4047 .features[FEAT_1_ECX] = 4048 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4049 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4050 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4051 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4052 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4053 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4054 .features[FEAT_8000_0001_EDX] = 4055 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 4056 CPUID_EXT2_SYSCALL, 4057 .features[FEAT_8000_0001_ECX] = 4058 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 4059 .features[FEAT_7_0_EBX] = 4060 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4061 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4062 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4063 CPUID_7_0_EBX_RTM, 4064 .features[FEAT_XSAVE] = 4065 CPUID_XSAVE_XSAVEOPT, 4066 .features[FEAT_6_EAX] = 4067 CPUID_6_EAX_ARAT, 4068 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4069 MSR_VMX_BASIC_TRUE_CTLS, 4070 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4071 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4072 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4073 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4074 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4075 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4076 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4077 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4078 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4079 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4080 .features[FEAT_VMX_EXIT_CTLS] = 4081 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4082 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4083 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4084 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4085 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4086 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4087 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4088 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4089 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4090 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4091 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4092 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4093 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4094 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4095 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4096 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4097 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4098 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4099 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4100 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4101 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4102 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4103 .features[FEAT_VMX_SECONDARY_CTLS] = 4104 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4105 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4106 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4107 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4108 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4109 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4110 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4111 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4112 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4113 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4114 .xlevel = 0x80000008, 4115 .model_id = "Intel Core Processor (Haswell)", 4116 .versions = (X86CPUVersionDefinition[]) { 4117 { .version = 1 }, 4118 { 4119 .version = 2, 4120 .alias = "Haswell-noTSX", 4121 .props = (PropValue[]) { 4122 { "hle", "off" }, 4123 { "rtm", "off" }, 4124 { "stepping", "1" }, 4125 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 4126 { /* end of list */ } 4127 }, 4128 }, 4129 { 4130 .version = 3, 4131 .alias = "Haswell-IBRS", 4132 .props = (PropValue[]) { 4133 /* Restore TSX features removed by -v2 above */ 4134 { "hle", "on" }, 4135 { "rtm", "on" }, 4136 /* 4137 * Haswell and Haswell-IBRS had stepping=4 in 4138 * QEMU 4.0 and older 4139 */ 4140 { "stepping", "4" }, 4141 { "spec-ctrl", "on" }, 4142 { "model-id", 4143 "Intel Core Processor (Haswell, IBRS)" }, 4144 { /* end of list */ } 4145 } 4146 }, 4147 { 4148 .version = 4, 4149 .alias = "Haswell-noTSX-IBRS", 4150 .props = (PropValue[]) { 4151 { "hle", "off" }, 4152 { "rtm", "off" }, 4153 /* spec-ctrl was already enabled by -v3 above */ 4154 { "stepping", "1" }, 4155 { "model-id", 4156 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 4157 { /* end of list */ } 4158 } 4159 }, 4160 { /* end of list */ } 4161 } 4162 }, 4163 { 4164 .name = "Broadwell", 4165 .level = 0xd, 4166 .vendor = CPUID_VENDOR_INTEL, 4167 .family = 6, 4168 .model = 61, 4169 .stepping = 2, 4170 .features[FEAT_1_EDX] = 4171 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4172 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4173 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4174 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4175 CPUID_DE | CPUID_FP87, 4176 .features[FEAT_1_ECX] = 4177 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4178 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4179 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4180 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4181 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4182 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4183 .features[FEAT_8000_0001_EDX] = 4184 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 4185 CPUID_EXT2_SYSCALL, 4186 .features[FEAT_8000_0001_ECX] = 4187 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4188 .features[FEAT_7_0_EBX] = 4189 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4190 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4191 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4192 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4193 CPUID_7_0_EBX_SMAP, 4194 .features[FEAT_XSAVE] = 4195 CPUID_XSAVE_XSAVEOPT, 4196 .features[FEAT_6_EAX] = 4197 CPUID_6_EAX_ARAT, 4198 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4199 MSR_VMX_BASIC_TRUE_CTLS, 4200 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4201 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4202 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4203 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4204 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4205 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4206 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4207 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4208 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4209 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4210 .features[FEAT_VMX_EXIT_CTLS] = 4211 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4212 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4213 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4214 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4215 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4216 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4217 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4218 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4219 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4220 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4221 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4222 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4223 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4224 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4225 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4226 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4227 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4228 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4229 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4230 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4231 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4232 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4233 .features[FEAT_VMX_SECONDARY_CTLS] = 4234 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4235 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4236 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4237 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4238 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4239 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4240 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4241 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4242 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4243 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4244 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4245 .xlevel = 0x80000008, 4246 .model_id = "Intel Core Processor (Broadwell)", 4247 .versions = (X86CPUVersionDefinition[]) { 4248 { .version = 1 }, 4249 { 4250 .version = 2, 4251 .alias = "Broadwell-noTSX", 4252 .props = (PropValue[]) { 4253 { "hle", "off" }, 4254 { "rtm", "off" }, 4255 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 4256 { /* end of list */ } 4257 }, 4258 }, 4259 { 4260 .version = 3, 4261 .alias = "Broadwell-IBRS", 4262 .props = (PropValue[]) { 4263 /* Restore TSX features removed by -v2 above */ 4264 { "hle", "on" }, 4265 { "rtm", "on" }, 4266 { "spec-ctrl", "on" }, 4267 { "model-id", 4268 "Intel Core Processor (Broadwell, IBRS)" }, 4269 { /* end of list */ } 4270 } 4271 }, 4272 { 4273 .version = 4, 4274 .alias = "Broadwell-noTSX-IBRS", 4275 .props = (PropValue[]) { 4276 { "hle", "off" }, 4277 { "rtm", "off" }, 4278 /* spec-ctrl was already enabled by -v3 above */ 4279 { "model-id", 4280 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 4281 { /* end of list */ } 4282 } 4283 }, 4284 { /* end of list */ } 4285 } 4286 }, 4287 { 4288 .name = "Skylake-Client", 4289 .level = 0xd, 4290 .vendor = CPUID_VENDOR_INTEL, 4291 .family = 6, 4292 .model = 94, 4293 .stepping = 3, 4294 .features[FEAT_1_EDX] = 4295 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4296 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4297 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4298 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4299 CPUID_DE | CPUID_FP87, 4300 .features[FEAT_1_ECX] = 4301 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4302 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4303 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4304 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4305 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4306 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4307 .features[FEAT_8000_0001_EDX] = 4308 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 4309 CPUID_EXT2_SYSCALL, 4310 .features[FEAT_8000_0001_ECX] = 4311 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4312 .features[FEAT_7_0_EBX] = 4313 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4314 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4315 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4316 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4317 CPUID_7_0_EBX_SMAP, 4318 /* XSAVES is added in version 4 */ 4319 .features[FEAT_XSAVE] = 4320 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4321 CPUID_XSAVE_XGETBV1, 4322 .features[FEAT_6_EAX] = 4323 CPUID_6_EAX_ARAT, 4324 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4325 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4326 MSR_VMX_BASIC_TRUE_CTLS, 4327 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4328 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4329 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4330 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4331 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4332 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4333 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4334 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4335 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4336 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4337 .features[FEAT_VMX_EXIT_CTLS] = 4338 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4339 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4340 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4341 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4342 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4343 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4344 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4345 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4346 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4347 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 4348 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4349 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4350 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4351 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4352 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4353 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4354 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4355 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4356 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4357 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4358 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4359 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4360 .features[FEAT_VMX_SECONDARY_CTLS] = 4361 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4362 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4363 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4364 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4365 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4366 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4367 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4368 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4369 .xlevel = 0x80000008, 4370 .model_id = "Intel Core Processor (Skylake)", 4371 .versions = (X86CPUVersionDefinition[]) { 4372 { .version = 1 }, 4373 { 4374 .version = 2, 4375 .alias = "Skylake-Client-IBRS", 4376 .props = (PropValue[]) { 4377 { "spec-ctrl", "on" }, 4378 { "model-id", 4379 "Intel Core Processor (Skylake, IBRS)" }, 4380 { /* end of list */ } 4381 } 4382 }, 4383 { 4384 .version = 3, 4385 .alias = "Skylake-Client-noTSX-IBRS", 4386 .props = (PropValue[]) { 4387 { "hle", "off" }, 4388 { "rtm", "off" }, 4389 { "model-id", 4390 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 4391 { /* end of list */ } 4392 } 4393 }, 4394 { 4395 .version = 4, 4396 .note = "IBRS, XSAVES, no TSX", 4397 .props = (PropValue[]) { 4398 { "xsaves", "on" }, 4399 { "vmx-xsaves", "on" }, 4400 { /* end of list */ } 4401 } 4402 }, 4403 { /* end of list */ } 4404 } 4405 }, 4406 { 4407 .name = "Skylake-Server", 4408 .level = 0xd, 4409 .vendor = CPUID_VENDOR_INTEL, 4410 .family = 6, 4411 .model = 85, 4412 .stepping = 4, 4413 .features[FEAT_1_EDX] = 4414 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4415 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4416 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4417 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4418 CPUID_DE | CPUID_FP87, 4419 .features[FEAT_1_ECX] = 4420 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4421 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4422 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4423 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4424 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4425 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4426 .features[FEAT_8000_0001_EDX] = 4427 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4428 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4429 .features[FEAT_8000_0001_ECX] = 4430 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4431 .features[FEAT_7_0_EBX] = 4432 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4433 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4434 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4435 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4436 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4437 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4438 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4439 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4440 .features[FEAT_7_0_ECX] = 4441 CPUID_7_0_ECX_PKU, 4442 /* XSAVES is added in version 5 */ 4443 .features[FEAT_XSAVE] = 4444 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4445 CPUID_XSAVE_XGETBV1, 4446 .features[FEAT_6_EAX] = 4447 CPUID_6_EAX_ARAT, 4448 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4449 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4450 MSR_VMX_BASIC_TRUE_CTLS, 4451 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4452 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4453 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4454 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4455 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4456 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4457 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4458 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4459 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4460 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4461 .features[FEAT_VMX_EXIT_CTLS] = 4462 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4463 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4464 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4465 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4466 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4467 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4468 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4469 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4470 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4471 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4472 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4473 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4474 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4475 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4476 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4477 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4478 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4479 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4480 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4481 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4482 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4483 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4484 .features[FEAT_VMX_SECONDARY_CTLS] = 4485 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4486 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4487 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4488 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4489 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4490 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4491 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4492 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4493 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4494 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4495 .xlevel = 0x80000008, 4496 .model_id = "Intel Xeon Processor (Skylake)", 4497 .versions = (X86CPUVersionDefinition[]) { 4498 { .version = 1 }, 4499 { 4500 .version = 2, 4501 .alias = "Skylake-Server-IBRS", 4502 .props = (PropValue[]) { 4503 /* clflushopt was not added to Skylake-Server-IBRS */ 4504 /* TODO: add -v3 including clflushopt */ 4505 { "clflushopt", "off" }, 4506 { "spec-ctrl", "on" }, 4507 { "model-id", 4508 "Intel Xeon Processor (Skylake, IBRS)" }, 4509 { /* end of list */ } 4510 } 4511 }, 4512 { 4513 .version = 3, 4514 .alias = "Skylake-Server-noTSX-IBRS", 4515 .props = (PropValue[]) { 4516 { "hle", "off" }, 4517 { "rtm", "off" }, 4518 { "model-id", 4519 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 4520 { /* end of list */ } 4521 } 4522 }, 4523 { 4524 .version = 4, 4525 .note = "IBRS, EPT switching, no TSX", 4526 .props = (PropValue[]) { 4527 { "vmx-eptp-switching", "on" }, 4528 { /* end of list */ } 4529 } 4530 }, 4531 { 4532 .version = 5, 4533 .note = "IBRS, XSAVES, EPT switching, no TSX", 4534 .props = (PropValue[]) { 4535 { "xsaves", "on" }, 4536 { "vmx-xsaves", "on" }, 4537 { /* end of list */ } 4538 } 4539 }, 4540 { /* end of list */ } 4541 } 4542 }, 4543 { 4544 .name = "Cascadelake-Server", 4545 .level = 0xd, 4546 .vendor = CPUID_VENDOR_INTEL, 4547 .family = 6, 4548 .model = 85, 4549 .stepping = 6, 4550 .features[FEAT_1_EDX] = 4551 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4552 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4553 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4554 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4555 CPUID_DE | CPUID_FP87, 4556 .features[FEAT_1_ECX] = 4557 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4558 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4559 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4560 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4561 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4562 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4563 .features[FEAT_8000_0001_EDX] = 4564 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4565 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4566 .features[FEAT_8000_0001_ECX] = 4567 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4568 .features[FEAT_7_0_EBX] = 4569 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4570 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4571 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4572 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4573 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4574 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4575 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4576 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4577 .features[FEAT_7_0_ECX] = 4578 CPUID_7_0_ECX_PKU | 4579 CPUID_7_0_ECX_AVX512VNNI, 4580 .features[FEAT_7_0_EDX] = 4581 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4582 /* XSAVES is added in version 5 */ 4583 .features[FEAT_XSAVE] = 4584 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4585 CPUID_XSAVE_XGETBV1, 4586 .features[FEAT_6_EAX] = 4587 CPUID_6_EAX_ARAT, 4588 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4589 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4590 MSR_VMX_BASIC_TRUE_CTLS, 4591 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4592 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4593 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4594 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4595 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4596 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4597 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4598 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4599 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4600 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4601 .features[FEAT_VMX_EXIT_CTLS] = 4602 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4603 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4604 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4605 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4606 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4607 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4608 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4609 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4610 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4611 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4612 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4613 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4614 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4615 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4616 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4617 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4618 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4619 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4620 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4621 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4622 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4623 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4624 .features[FEAT_VMX_SECONDARY_CTLS] = 4625 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4626 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4627 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4628 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4629 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4630 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4631 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4632 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4633 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4634 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4635 .xlevel = 0x80000008, 4636 .model_id = "Intel Xeon Processor (Cascadelake)", 4637 .versions = (X86CPUVersionDefinition[]) { 4638 { .version = 1 }, 4639 { .version = 2, 4640 .note = "ARCH_CAPABILITIES", 4641 .props = (PropValue[]) { 4642 { "arch-capabilities", "on" }, 4643 { "rdctl-no", "on" }, 4644 { "ibrs-all", "on" }, 4645 { "skip-l1dfl-vmentry", "on" }, 4646 { "mds-no", "on" }, 4647 { /* end of list */ } 4648 }, 4649 }, 4650 { .version = 3, 4651 .alias = "Cascadelake-Server-noTSX", 4652 .note = "ARCH_CAPABILITIES, no TSX", 4653 .props = (PropValue[]) { 4654 { "hle", "off" }, 4655 { "rtm", "off" }, 4656 { /* end of list */ } 4657 }, 4658 }, 4659 { .version = 4, 4660 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 4661 .props = (PropValue[]) { 4662 { "vmx-eptp-switching", "on" }, 4663 { /* end of list */ } 4664 }, 4665 }, 4666 { .version = 5, 4667 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 4668 .props = (PropValue[]) { 4669 { "xsaves", "on" }, 4670 { "vmx-xsaves", "on" }, 4671 { /* end of list */ } 4672 }, 4673 }, 4674 { /* end of list */ } 4675 } 4676 }, 4677 { 4678 .name = "Cooperlake", 4679 .level = 0xd, 4680 .vendor = CPUID_VENDOR_INTEL, 4681 .family = 6, 4682 .model = 85, 4683 .stepping = 10, 4684 .features[FEAT_1_EDX] = 4685 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4686 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4687 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4688 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4689 CPUID_DE | CPUID_FP87, 4690 .features[FEAT_1_ECX] = 4691 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4692 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4693 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4694 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4695 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4696 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4697 .features[FEAT_8000_0001_EDX] = 4698 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4699 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4700 .features[FEAT_8000_0001_ECX] = 4701 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4702 .features[FEAT_7_0_EBX] = 4703 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4704 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4705 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4706 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4707 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4708 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4709 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4710 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4711 .features[FEAT_7_0_ECX] = 4712 CPUID_7_0_ECX_PKU | 4713 CPUID_7_0_ECX_AVX512VNNI, 4714 .features[FEAT_7_0_EDX] = 4715 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 4716 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 4717 .features[FEAT_ARCH_CAPABILITIES] = 4718 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4719 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4720 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4721 .features[FEAT_7_1_EAX] = 4722 CPUID_7_1_EAX_AVX512_BF16, 4723 /* XSAVES is added in version 2 */ 4724 .features[FEAT_XSAVE] = 4725 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4726 CPUID_XSAVE_XGETBV1, 4727 .features[FEAT_6_EAX] = 4728 CPUID_6_EAX_ARAT, 4729 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4730 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4731 MSR_VMX_BASIC_TRUE_CTLS, 4732 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4733 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4734 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4735 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4736 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4737 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4738 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4739 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4740 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4741 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4742 .features[FEAT_VMX_EXIT_CTLS] = 4743 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4744 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4745 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4746 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4747 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4748 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4749 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4750 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4751 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4752 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4753 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4754 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4755 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4756 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4757 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4758 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4759 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4760 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4761 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4762 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4763 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4764 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4765 .features[FEAT_VMX_SECONDARY_CTLS] = 4766 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4767 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4768 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4769 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4770 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4771 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4772 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4773 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4774 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4775 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4776 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4777 .xlevel = 0x80000008, 4778 .model_id = "Intel Xeon Processor (Cooperlake)", 4779 .versions = (X86CPUVersionDefinition[]) { 4780 { .version = 1 }, 4781 { .version = 2, 4782 .note = "XSAVES", 4783 .props = (PropValue[]) { 4784 { "xsaves", "on" }, 4785 { "vmx-xsaves", "on" }, 4786 { /* end of list */ } 4787 }, 4788 }, 4789 { /* end of list */ } 4790 } 4791 }, 4792 { 4793 .name = "Icelake-Server", 4794 .level = 0xd, 4795 .vendor = CPUID_VENDOR_INTEL, 4796 .family = 6, 4797 .model = 134, 4798 .stepping = 0, 4799 .features[FEAT_1_EDX] = 4800 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4801 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4802 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4803 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4804 CPUID_DE | CPUID_FP87, 4805 .features[FEAT_1_ECX] = 4806 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4807 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4808 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4809 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4810 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4811 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4812 .features[FEAT_8000_0001_EDX] = 4813 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4814 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4815 .features[FEAT_8000_0001_ECX] = 4816 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4817 .features[FEAT_8000_0008_EBX] = 4818 CPUID_8000_0008_EBX_WBNOINVD, 4819 .features[FEAT_7_0_EBX] = 4820 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4821 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4822 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4823 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4824 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4825 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4826 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4827 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4828 .features[FEAT_7_0_ECX] = 4829 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4830 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4831 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4832 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4833 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4834 .features[FEAT_7_0_EDX] = 4835 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4836 /* XSAVES is added in version 5 */ 4837 .features[FEAT_XSAVE] = 4838 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4839 CPUID_XSAVE_XGETBV1, 4840 .features[FEAT_6_EAX] = 4841 CPUID_6_EAX_ARAT, 4842 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4843 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4844 MSR_VMX_BASIC_TRUE_CTLS, 4845 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4846 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4847 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4848 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4849 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4850 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4851 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4852 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4853 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4854 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4855 .features[FEAT_VMX_EXIT_CTLS] = 4856 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4857 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4858 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4859 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4860 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4861 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4862 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4863 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4864 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4865 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4866 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4867 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4868 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4869 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4870 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4871 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4872 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4873 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4874 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4875 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4876 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4877 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4878 .features[FEAT_VMX_SECONDARY_CTLS] = 4879 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4880 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4881 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4882 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4883 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4884 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4885 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4886 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4887 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4888 .xlevel = 0x80000008, 4889 .model_id = "Intel Xeon Processor (Icelake)", 4890 .versions = (X86CPUVersionDefinition[]) { 4891 { .version = 1 }, 4892 { 4893 .version = 2, 4894 .note = "no TSX", 4895 .alias = "Icelake-Server-noTSX", 4896 .props = (PropValue[]) { 4897 { "hle", "off" }, 4898 { "rtm", "off" }, 4899 { /* end of list */ } 4900 }, 4901 }, 4902 { 4903 .version = 3, 4904 .props = (PropValue[]) { 4905 { "arch-capabilities", "on" }, 4906 { "rdctl-no", "on" }, 4907 { "ibrs-all", "on" }, 4908 { "skip-l1dfl-vmentry", "on" }, 4909 { "mds-no", "on" }, 4910 { "pschange-mc-no", "on" }, 4911 { "taa-no", "on" }, 4912 { /* end of list */ } 4913 }, 4914 }, 4915 { 4916 .version = 4, 4917 .props = (PropValue[]) { 4918 { "sha-ni", "on" }, 4919 { "avx512ifma", "on" }, 4920 { "rdpid", "on" }, 4921 { "fsrm", "on" }, 4922 { "vmx-rdseed-exit", "on" }, 4923 { "vmx-pml", "on" }, 4924 { "vmx-eptp-switching", "on" }, 4925 { "model", "106" }, 4926 { /* end of list */ } 4927 }, 4928 }, 4929 { 4930 .version = 5, 4931 .note = "XSAVES", 4932 .props = (PropValue[]) { 4933 { "xsaves", "on" }, 4934 { "vmx-xsaves", "on" }, 4935 { /* end of list */ } 4936 }, 4937 }, 4938 { 4939 .version = 6, 4940 .note = "5-level EPT", 4941 .props = (PropValue[]) { 4942 { "vmx-page-walk-5", "on" }, 4943 { /* end of list */ } 4944 }, 4945 }, 4946 { 4947 .version = 7, 4948 .note = "TSX, taa-no", 4949 .props = (PropValue[]) { 4950 /* Restore TSX features removed by -v2 above */ 4951 { "hle", "on" }, 4952 { "rtm", "on" }, 4953 { /* end of list */ } 4954 }, 4955 }, 4956 { /* end of list */ } 4957 } 4958 }, 4959 { 4960 .name = "SapphireRapids", 4961 .level = 0x20, 4962 .vendor = CPUID_VENDOR_INTEL, 4963 .family = 6, 4964 .model = 143, 4965 .stepping = 4, 4966 /* 4967 * please keep the ascending order so that we can have a clear view of 4968 * bit position of each feature. 4969 */ 4970 .features[FEAT_1_EDX] = 4971 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4972 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4973 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4974 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4975 CPUID_SSE | CPUID_SSE2, 4976 .features[FEAT_1_ECX] = 4977 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4978 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4979 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4980 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4981 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4982 .features[FEAT_8000_0001_EDX] = 4983 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4984 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4985 .features[FEAT_8000_0001_ECX] = 4986 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4987 .features[FEAT_8000_0008_EBX] = 4988 CPUID_8000_0008_EBX_WBNOINVD, 4989 .features[FEAT_7_0_EBX] = 4990 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4991 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4992 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4993 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4994 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4995 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4996 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4997 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4998 .features[FEAT_7_0_ECX] = 4999 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5000 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5001 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5002 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5003 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5004 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 5005 .features[FEAT_7_0_EDX] = 5006 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 5007 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 5008 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 5009 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 5010 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5011 .features[FEAT_ARCH_CAPABILITIES] = 5012 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 5013 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 5014 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 5015 .features[FEAT_XSAVE] = 5016 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5017 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 5018 .features[FEAT_6_EAX] = 5019 CPUID_6_EAX_ARAT, 5020 .features[FEAT_7_1_EAX] = 5021 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 5022 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 5023 .features[FEAT_VMX_BASIC] = 5024 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5025 .features[FEAT_VMX_ENTRY_CTLS] = 5026 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5027 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5028 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5029 .features[FEAT_VMX_EPT_VPID_CAPS] = 5030 MSR_VMX_EPT_EXECONLY | 5031 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 5032 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5033 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5034 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5035 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5036 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5037 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5038 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5039 .features[FEAT_VMX_EXIT_CTLS] = 5040 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5041 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5042 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5043 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5044 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5045 .features[FEAT_VMX_MISC] = 5046 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5047 MSR_VMX_MISC_VMWRITE_VMEXIT, 5048 .features[FEAT_VMX_PINBASED_CTLS] = 5049 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5050 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5051 VMX_PIN_BASED_POSTED_INTR, 5052 .features[FEAT_VMX_PROCBASED_CTLS] = 5053 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5054 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5055 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5056 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5057 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5058 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5059 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5060 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5061 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5062 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5063 VMX_CPU_BASED_PAUSE_EXITING | 5064 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5065 .features[FEAT_VMX_SECONDARY_CTLS] = 5066 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5067 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5068 VMX_SECONDARY_EXEC_RDTSCP | 5069 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5070 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5071 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5072 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5073 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5074 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5075 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5076 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5077 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5078 VMX_SECONDARY_EXEC_XSAVES, 5079 .features[FEAT_VMX_VMFUNC] = 5080 MSR_VMX_VMFUNC_EPT_SWITCHING, 5081 .xlevel = 0x80000008, 5082 .model_id = "Intel Xeon Processor (SapphireRapids)", 5083 .versions = (X86CPUVersionDefinition[]) { 5084 { .version = 1 }, 5085 { 5086 .version = 2, 5087 .props = (PropValue[]) { 5088 { "sbdr-ssdp-no", "on" }, 5089 { "fbsdp-no", "on" }, 5090 { "psdp-no", "on" }, 5091 { /* end of list */ } 5092 } 5093 }, 5094 { 5095 .version = 3, 5096 .props = (PropValue[]) { 5097 { "ss", "on" }, 5098 { "tsc-adjust", "on" }, 5099 { "cldemote", "on" }, 5100 { "movdiri", "on" }, 5101 { "movdir64b", "on" }, 5102 { /* end of list */ } 5103 } 5104 }, 5105 { 5106 .version = 4, 5107 .note = "with spr-sp cache model and 0x1f leaf", 5108 .cache_info = &xeon_spr_cache_info, 5109 .props = (PropValue[]) { 5110 { "x-force-cpuid-0x1f", "on" }, 5111 { /* end of list */ }, 5112 } 5113 }, 5114 { /* end of list */ } 5115 } 5116 }, 5117 { 5118 .name = "GraniteRapids", 5119 .level = 0x20, 5120 .vendor = CPUID_VENDOR_INTEL, 5121 .family = 6, 5122 .model = 173, 5123 .stepping = 0, 5124 /* 5125 * please keep the ascending order so that we can have a clear view of 5126 * bit position of each feature. 5127 */ 5128 .features[FEAT_1_EDX] = 5129 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5130 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5131 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5132 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5133 CPUID_SSE | CPUID_SSE2, 5134 .features[FEAT_1_ECX] = 5135 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 5136 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 5137 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5138 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 5139 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5140 .features[FEAT_8000_0001_EDX] = 5141 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5142 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5143 .features[FEAT_8000_0001_ECX] = 5144 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 5145 .features[FEAT_8000_0008_EBX] = 5146 CPUID_8000_0008_EBX_WBNOINVD, 5147 .features[FEAT_7_0_EBX] = 5148 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 5149 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 5150 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 5151 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 5152 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 5153 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 5154 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5155 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5156 .features[FEAT_7_0_ECX] = 5157 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5158 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5159 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5160 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5161 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5162 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 5163 .features[FEAT_7_0_EDX] = 5164 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 5165 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 5166 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 5167 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 5168 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5169 .features[FEAT_ARCH_CAPABILITIES] = 5170 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 5171 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 5172 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 5173 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 5174 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 5175 .features[FEAT_XSAVE] = 5176 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5177 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 5178 .features[FEAT_6_EAX] = 5179 CPUID_6_EAX_ARAT, 5180 .features[FEAT_7_1_EAX] = 5181 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 5182 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 5183 CPUID_7_1_EAX_AMX_FP16, 5184 .features[FEAT_7_1_EDX] = 5185 CPUID_7_1_EDX_PREFETCHITI, 5186 .features[FEAT_7_2_EDX] = 5187 CPUID_7_2_EDX_MCDT_NO, 5188 .features[FEAT_VMX_BASIC] = 5189 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5190 .features[FEAT_VMX_ENTRY_CTLS] = 5191 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5192 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5193 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5194 .features[FEAT_VMX_EPT_VPID_CAPS] = 5195 MSR_VMX_EPT_EXECONLY | 5196 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 5197 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5198 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5199 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5200 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5201 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5202 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5203 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5204 .features[FEAT_VMX_EXIT_CTLS] = 5205 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5206 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5207 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5208 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5209 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5210 .features[FEAT_VMX_MISC] = 5211 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5212 MSR_VMX_MISC_VMWRITE_VMEXIT, 5213 .features[FEAT_VMX_PINBASED_CTLS] = 5214 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5215 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5216 VMX_PIN_BASED_POSTED_INTR, 5217 .features[FEAT_VMX_PROCBASED_CTLS] = 5218 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5219 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5220 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5221 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5222 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5223 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5224 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5225 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5226 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5227 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5228 VMX_CPU_BASED_PAUSE_EXITING | 5229 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5230 .features[FEAT_VMX_SECONDARY_CTLS] = 5231 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5232 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5233 VMX_SECONDARY_EXEC_RDTSCP | 5234 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5235 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5236 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5237 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5238 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5239 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5240 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5241 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5242 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5243 VMX_SECONDARY_EXEC_XSAVES, 5244 .features[FEAT_VMX_VMFUNC] = 5245 MSR_VMX_VMFUNC_EPT_SWITCHING, 5246 .xlevel = 0x80000008, 5247 .model_id = "Intel Xeon Processor (GraniteRapids)", 5248 .versions = (X86CPUVersionDefinition[]) { 5249 { .version = 1 }, 5250 { 5251 .version = 2, 5252 .props = (PropValue[]) { 5253 { "ss", "on" }, 5254 { "tsc-adjust", "on" }, 5255 { "cldemote", "on" }, 5256 { "movdiri", "on" }, 5257 { "movdir64b", "on" }, 5258 { "avx10", "on" }, 5259 { "avx10-128", "on" }, 5260 { "avx10-256", "on" }, 5261 { "avx10-512", "on" }, 5262 { "avx10-version", "1" }, 5263 { "stepping", "1" }, 5264 { /* end of list */ } 5265 } 5266 }, 5267 { 5268 .version = 3, 5269 .note = "with gnr-sp cache model and 0x1f leaf", 5270 .cache_info = &xeon_gnr_cache_info, 5271 .props = (PropValue[]) { 5272 { "x-force-cpuid-0x1f", "on" }, 5273 { /* end of list */ }, 5274 } 5275 }, 5276 { /* end of list */ }, 5277 }, 5278 }, 5279 { 5280 .name = "SierraForest", 5281 .level = 0x23, 5282 .vendor = CPUID_VENDOR_INTEL, 5283 .family = 6, 5284 .model = 175, 5285 .stepping = 0, 5286 /* 5287 * please keep the ascending order so that we can have a clear view of 5288 * bit position of each feature. 5289 */ 5290 .features[FEAT_1_EDX] = 5291 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5292 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5293 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5294 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5295 CPUID_SSE | CPUID_SSE2, 5296 .features[FEAT_1_ECX] = 5297 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 5298 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 5299 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5300 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 5301 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5302 .features[FEAT_8000_0001_EDX] = 5303 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5304 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5305 .features[FEAT_8000_0001_ECX] = 5306 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 5307 .features[FEAT_8000_0008_EBX] = 5308 CPUID_8000_0008_EBX_WBNOINVD, 5309 .features[FEAT_7_0_EBX] = 5310 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5311 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5312 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5313 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5314 CPUID_7_0_EBX_SHA_NI, 5315 .features[FEAT_7_0_ECX] = 5316 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 5317 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5318 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 5319 .features[FEAT_7_0_EDX] = 5320 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 5321 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5322 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5323 .features[FEAT_ARCH_CAPABILITIES] = 5324 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 5325 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 5326 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 5327 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 5328 MSR_ARCH_CAP_PBRSB_NO, 5329 .features[FEAT_XSAVE] = 5330 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5331 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5332 .features[FEAT_6_EAX] = 5333 CPUID_6_EAX_ARAT, 5334 .features[FEAT_7_1_EAX] = 5335 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 5336 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 5337 .features[FEAT_7_1_EDX] = 5338 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 5339 .features[FEAT_7_2_EDX] = 5340 CPUID_7_2_EDX_MCDT_NO, 5341 .features[FEAT_VMX_BASIC] = 5342 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5343 .features[FEAT_VMX_ENTRY_CTLS] = 5344 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5345 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5346 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5347 .features[FEAT_VMX_EPT_VPID_CAPS] = 5348 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5349 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5350 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5351 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5352 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5353 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5354 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5355 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5356 .features[FEAT_VMX_EXIT_CTLS] = 5357 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5358 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5359 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5360 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5361 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5362 .features[FEAT_VMX_MISC] = 5363 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5364 MSR_VMX_MISC_VMWRITE_VMEXIT, 5365 .features[FEAT_VMX_PINBASED_CTLS] = 5366 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5367 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5368 VMX_PIN_BASED_POSTED_INTR, 5369 .features[FEAT_VMX_PROCBASED_CTLS] = 5370 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5371 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5372 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5373 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5374 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5375 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5376 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5377 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5378 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5379 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5380 VMX_CPU_BASED_PAUSE_EXITING | 5381 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5382 .features[FEAT_VMX_SECONDARY_CTLS] = 5383 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5384 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5385 VMX_SECONDARY_EXEC_RDTSCP | 5386 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5387 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5388 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5389 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5390 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5391 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5392 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5393 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5394 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5395 VMX_SECONDARY_EXEC_XSAVES, 5396 .features[FEAT_VMX_VMFUNC] = 5397 MSR_VMX_VMFUNC_EPT_SWITCHING, 5398 .xlevel = 0x80000008, 5399 .model_id = "Intel Xeon Processor (SierraForest)", 5400 .versions = (X86CPUVersionDefinition[]) { 5401 { .version = 1 }, 5402 { 5403 .version = 2, 5404 .props = (PropValue[]) { 5405 { "ss", "on" }, 5406 { "tsc-adjust", "on" }, 5407 { "cldemote", "on" }, 5408 { "movdiri", "on" }, 5409 { "movdir64b", "on" }, 5410 { "gds-no", "on" }, 5411 { "rfds-no", "on" }, 5412 { "lam", "on" }, 5413 { "intel-psfd", "on"}, 5414 { "ipred-ctrl", "on"}, 5415 { "rrsba-ctrl", "on"}, 5416 { "bhi-ctrl", "on"}, 5417 { "stepping", "3" }, 5418 { /* end of list */ } 5419 } 5420 }, 5421 { 5422 .version = 3, 5423 .note = "with srf-sp cache model and 0x1f leaf", 5424 .cache_info = &xeon_srf_cache_info, 5425 .props = (PropValue[]) { 5426 { "x-force-cpuid-0x1f", "on" }, 5427 { /* end of list */ }, 5428 } 5429 }, 5430 { /* end of list */ }, 5431 }, 5432 }, 5433 { 5434 .name = "ClearwaterForest", 5435 .level = 0x23, 5436 .xlevel = 0x80000008, 5437 .vendor = CPUID_VENDOR_INTEL, 5438 .family = 6, 5439 .model = 221, 5440 .stepping = 0, 5441 /* 5442 * please keep the ascending order so that we can have a clear view of 5443 * bit position of each feature. 5444 */ 5445 .features[FEAT_1_EDX] = 5446 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5447 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5448 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5449 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5450 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 5451 .features[FEAT_1_ECX] = 5452 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 5453 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 5454 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5455 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 5456 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5457 .features[FEAT_8000_0001_EDX] = 5458 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5459 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5460 .features[FEAT_8000_0001_ECX] = 5461 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 5462 .features[FEAT_8000_0008_EBX] = 5463 CPUID_8000_0008_EBX_WBNOINVD, 5464 .features[FEAT_7_0_EBX] = 5465 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 5466 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 5467 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 5468 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 5469 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5470 CPUID_7_0_EBX_SHA_NI, 5471 .features[FEAT_7_0_ECX] = 5472 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 5473 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5474 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 5475 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 5476 CPUID_7_0_ECX_MOVDIR64B, 5477 .features[FEAT_7_0_EDX] = 5478 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 5479 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5480 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5481 .features[FEAT_ARCH_CAPABILITIES] = 5482 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 5483 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 5484 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 5485 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 5486 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 5487 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 5488 .features[FEAT_XSAVE] = 5489 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5490 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5491 .features[FEAT_6_EAX] = 5492 CPUID_6_EAX_ARAT, 5493 .features[FEAT_7_1_EAX] = 5494 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 5495 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 5496 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 5497 CPUID_7_1_EAX_LAM, 5498 .features[FEAT_7_1_EDX] = 5499 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 5500 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 5501 .features[FEAT_7_2_EDX] = 5502 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 5503 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 5504 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 5505 .features[FEAT_VMX_BASIC] = 5506 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5507 .features[FEAT_VMX_ENTRY_CTLS] = 5508 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5509 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5510 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5511 .features[FEAT_VMX_EPT_VPID_CAPS] = 5512 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5513 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5514 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5515 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5516 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5517 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5518 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5519 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5520 .features[FEAT_VMX_EXIT_CTLS] = 5521 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5522 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5523 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5524 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5525 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5526 .features[FEAT_VMX_MISC] = 5527 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5528 MSR_VMX_MISC_VMWRITE_VMEXIT, 5529 .features[FEAT_VMX_PINBASED_CTLS] = 5530 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5531 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5532 VMX_PIN_BASED_POSTED_INTR, 5533 .features[FEAT_VMX_PROCBASED_CTLS] = 5534 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5535 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5536 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5537 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5538 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5539 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5540 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5541 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5542 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5543 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5544 VMX_CPU_BASED_PAUSE_EXITING | 5545 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5546 .features[FEAT_VMX_SECONDARY_CTLS] = 5547 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5548 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5549 VMX_SECONDARY_EXEC_RDTSCP | 5550 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5551 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5552 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5553 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5554 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5555 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5556 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5557 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5558 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5559 VMX_SECONDARY_EXEC_XSAVES, 5560 .features[FEAT_VMX_VMFUNC] = 5561 MSR_VMX_VMFUNC_EPT_SWITCHING, 5562 .model_id = "Intel Xeon Processor (ClearwaterForest)", 5563 .versions = (X86CPUVersionDefinition[]) { 5564 { .version = 1 }, 5565 { /* end of list */ }, 5566 }, 5567 }, 5568 { 5569 .name = "Denverton", 5570 .level = 21, 5571 .vendor = CPUID_VENDOR_INTEL, 5572 .family = 6, 5573 .model = 95, 5574 .stepping = 1, 5575 .features[FEAT_1_EDX] = 5576 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5577 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5578 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5579 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5580 CPUID_SSE | CPUID_SSE2, 5581 .features[FEAT_1_ECX] = 5582 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5583 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 5584 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5585 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 5586 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 5587 .features[FEAT_8000_0001_EDX] = 5588 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5589 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5590 .features[FEAT_8000_0001_ECX] = 5591 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5592 .features[FEAT_7_0_EBX] = 5593 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 5594 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 5595 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 5596 .features[FEAT_7_0_EDX] = 5597 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5598 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5599 /* XSAVES is added in version 3 */ 5600 .features[FEAT_XSAVE] = 5601 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 5602 .features[FEAT_6_EAX] = 5603 CPUID_6_EAX_ARAT, 5604 .features[FEAT_ARCH_CAPABILITIES] = 5605 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 5606 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5607 MSR_VMX_BASIC_TRUE_CTLS, 5608 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5609 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5610 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5611 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5612 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5613 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5614 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5615 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5616 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5617 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5618 .features[FEAT_VMX_EXIT_CTLS] = 5619 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5620 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5621 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5622 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5623 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5624 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5625 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5626 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5627 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5628 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5629 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5630 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5631 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5632 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5633 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5634 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5635 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5636 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5637 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5638 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5639 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5640 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5641 .features[FEAT_VMX_SECONDARY_CTLS] = 5642 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5643 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5644 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5645 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5646 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5647 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5648 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5649 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5650 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5651 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5652 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5653 .xlevel = 0x80000008, 5654 .model_id = "Intel Atom Processor (Denverton)", 5655 .versions = (X86CPUVersionDefinition[]) { 5656 { .version = 1 }, 5657 { 5658 .version = 2, 5659 .note = "no MPX, no MONITOR", 5660 .props = (PropValue[]) { 5661 { "monitor", "off" }, 5662 { "mpx", "off" }, 5663 { /* end of list */ }, 5664 }, 5665 }, 5666 { 5667 .version = 3, 5668 .note = "XSAVES, no MPX, no MONITOR", 5669 .props = (PropValue[]) { 5670 { "xsaves", "on" }, 5671 { "vmx-xsaves", "on" }, 5672 { /* end of list */ }, 5673 }, 5674 }, 5675 { /* end of list */ }, 5676 }, 5677 }, 5678 { 5679 .name = "Snowridge", 5680 .level = 27, 5681 .vendor = CPUID_VENDOR_INTEL, 5682 .family = 6, 5683 .model = 134, 5684 .stepping = 1, 5685 .features[FEAT_1_EDX] = 5686 /* missing: CPUID_PN CPUID_IA64 */ 5687 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 5688 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 5689 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 5690 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 5691 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5692 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 5693 CPUID_MMX | 5694 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 5695 .features[FEAT_1_ECX] = 5696 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5697 CPUID_EXT_SSSE3 | 5698 CPUID_EXT_CX16 | 5699 CPUID_EXT_SSE41 | 5700 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5701 CPUID_EXT_POPCNT | 5702 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 5703 CPUID_EXT_RDRAND, 5704 .features[FEAT_8000_0001_EDX] = 5705 CPUID_EXT2_SYSCALL | 5706 CPUID_EXT2_NX | 5707 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5708 CPUID_EXT2_LM, 5709 .features[FEAT_8000_0001_ECX] = 5710 CPUID_EXT3_LAHF_LM | 5711 CPUID_EXT3_3DNOWPREFETCH, 5712 .features[FEAT_7_0_EBX] = 5713 CPUID_7_0_EBX_FSGSBASE | 5714 CPUID_7_0_EBX_SMEP | 5715 CPUID_7_0_EBX_ERMS | 5716 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 5717 CPUID_7_0_EBX_RDSEED | 5718 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5719 CPUID_7_0_EBX_CLWB | 5720 CPUID_7_0_EBX_SHA_NI, 5721 .features[FEAT_7_0_ECX] = 5722 CPUID_7_0_ECX_UMIP | 5723 /* missing bit 5 */ 5724 CPUID_7_0_ECX_GFNI | 5725 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 5726 CPUID_7_0_ECX_MOVDIR64B, 5727 .features[FEAT_7_0_EDX] = 5728 CPUID_7_0_EDX_SPEC_CTRL | 5729 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 5730 CPUID_7_0_EDX_CORE_CAPABILITY, 5731 .features[FEAT_CORE_CAPABILITY] = 5732 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 5733 /* XSAVES is added in version 3 */ 5734 .features[FEAT_XSAVE] = 5735 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5736 CPUID_XSAVE_XGETBV1, 5737 .features[FEAT_6_EAX] = 5738 CPUID_6_EAX_ARAT, 5739 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5740 MSR_VMX_BASIC_TRUE_CTLS, 5741 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5742 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5743 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5744 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5745 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5746 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5747 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5748 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5749 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5750 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5751 .features[FEAT_VMX_EXIT_CTLS] = 5752 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5753 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5754 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5755 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5756 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5757 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5758 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5759 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5760 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5761 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5762 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5763 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5764 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5765 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5766 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5767 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5768 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5769 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5770 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5771 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5772 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5773 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5774 .features[FEAT_VMX_SECONDARY_CTLS] = 5775 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5776 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5777 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5778 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5779 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5780 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5781 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5782 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5783 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5784 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5785 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5786 .xlevel = 0x80000008, 5787 .model_id = "Intel Atom Processor (SnowRidge)", 5788 .versions = (X86CPUVersionDefinition[]) { 5789 { .version = 1 }, 5790 { 5791 .version = 2, 5792 .props = (PropValue[]) { 5793 { "mpx", "off" }, 5794 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 5795 { /* end of list */ }, 5796 }, 5797 }, 5798 { 5799 .version = 3, 5800 .note = "XSAVES, no MPX", 5801 .props = (PropValue[]) { 5802 { "xsaves", "on" }, 5803 { "vmx-xsaves", "on" }, 5804 { /* end of list */ }, 5805 }, 5806 }, 5807 { 5808 .version = 4, 5809 .note = "no split lock detect, no core-capability", 5810 .props = (PropValue[]) { 5811 { "split-lock-detect", "off" }, 5812 { "core-capability", "off" }, 5813 { /* end of list */ }, 5814 }, 5815 }, 5816 { /* end of list */ }, 5817 }, 5818 }, 5819 { 5820 .name = "KnightsMill", 5821 .level = 0xd, 5822 .vendor = CPUID_VENDOR_INTEL, 5823 .family = 6, 5824 .model = 133, 5825 .stepping = 0, 5826 .features[FEAT_1_EDX] = 5827 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 5828 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5829 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5830 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5831 CPUID_PSE | CPUID_DE | CPUID_FP87, 5832 .features[FEAT_1_ECX] = 5833 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5834 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 5835 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 5836 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5837 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 5838 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5839 .features[FEAT_8000_0001_EDX] = 5840 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5841 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5842 .features[FEAT_8000_0001_ECX] = 5843 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5844 .features[FEAT_7_0_EBX] = 5845 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5846 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5847 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5848 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5849 CPUID_7_0_EBX_AVX512ER, 5850 .features[FEAT_7_0_ECX] = 5851 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5852 .features[FEAT_7_0_EDX] = 5853 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5854 .features[FEAT_XSAVE] = 5855 CPUID_XSAVE_XSAVEOPT, 5856 .features[FEAT_6_EAX] = 5857 CPUID_6_EAX_ARAT, 5858 .xlevel = 0x80000008, 5859 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5860 }, 5861 { 5862 .name = "Opteron_G1", 5863 .level = 5, 5864 .vendor = CPUID_VENDOR_AMD, 5865 .family = 15, 5866 .model = 6, 5867 .stepping = 1, 5868 .features[FEAT_1_EDX] = 5869 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5870 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5871 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5872 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5873 CPUID_DE | CPUID_FP87, 5874 .features[FEAT_1_ECX] = 5875 CPUID_EXT_SSE3, 5876 .features[FEAT_8000_0001_EDX] = 5877 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5878 .xlevel = 0x80000008, 5879 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5880 }, 5881 { 5882 .name = "Opteron_G2", 5883 .level = 5, 5884 .vendor = CPUID_VENDOR_AMD, 5885 .family = 15, 5886 .model = 6, 5887 .stepping = 1, 5888 .features[FEAT_1_EDX] = 5889 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5890 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5891 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5892 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5893 CPUID_DE | CPUID_FP87, 5894 .features[FEAT_1_ECX] = 5895 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5896 .features[FEAT_8000_0001_EDX] = 5897 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5898 .features[FEAT_8000_0001_ECX] = 5899 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5900 .xlevel = 0x80000008, 5901 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5902 }, 5903 { 5904 .name = "Opteron_G3", 5905 .level = 5, 5906 .vendor = CPUID_VENDOR_AMD, 5907 .family = 16, 5908 .model = 2, 5909 .stepping = 3, 5910 .features[FEAT_1_EDX] = 5911 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5912 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5913 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5914 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5915 CPUID_DE | CPUID_FP87, 5916 .features[FEAT_1_ECX] = 5917 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5918 CPUID_EXT_SSE3, 5919 .features[FEAT_8000_0001_EDX] = 5920 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5921 CPUID_EXT2_RDTSCP, 5922 .features[FEAT_8000_0001_ECX] = 5923 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5924 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5925 .xlevel = 0x80000008, 5926 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5927 }, 5928 { 5929 .name = "Opteron_G4", 5930 .level = 0xd, 5931 .vendor = CPUID_VENDOR_AMD, 5932 .family = 21, 5933 .model = 1, 5934 .stepping = 2, 5935 .features[FEAT_1_EDX] = 5936 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5937 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5938 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5939 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5940 CPUID_DE | CPUID_FP87, 5941 .features[FEAT_1_ECX] = 5942 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5943 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5944 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5945 CPUID_EXT_SSE3, 5946 .features[FEAT_8000_0001_EDX] = 5947 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5948 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5949 .features[FEAT_8000_0001_ECX] = 5950 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5951 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5952 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5953 CPUID_EXT3_LAHF_LM, 5954 .features[FEAT_SVM] = 5955 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5956 /* no xsaveopt! */ 5957 .xlevel = 0x8000001A, 5958 .model_id = "AMD Opteron 62xx class CPU", 5959 }, 5960 { 5961 .name = "Opteron_G5", 5962 .level = 0xd, 5963 .vendor = CPUID_VENDOR_AMD, 5964 .family = 21, 5965 .model = 2, 5966 .stepping = 0, 5967 .features[FEAT_1_EDX] = 5968 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5969 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5970 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5971 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5972 CPUID_DE | CPUID_FP87, 5973 .features[FEAT_1_ECX] = 5974 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5975 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5976 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5977 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5978 .features[FEAT_8000_0001_EDX] = 5979 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5980 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5981 .features[FEAT_8000_0001_ECX] = 5982 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5983 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5984 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5985 CPUID_EXT3_LAHF_LM, 5986 .features[FEAT_SVM] = 5987 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5988 /* no xsaveopt! */ 5989 .xlevel = 0x8000001A, 5990 .model_id = "AMD Opteron 63xx class CPU", 5991 }, 5992 { 5993 .name = "EPYC", 5994 .level = 0xd, 5995 .vendor = CPUID_VENDOR_AMD, 5996 .family = 23, 5997 .model = 1, 5998 .stepping = 2, 5999 .features[FEAT_1_EDX] = 6000 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6001 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6002 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6003 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6004 CPUID_VME | CPUID_FP87, 6005 .features[FEAT_1_ECX] = 6006 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6007 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6008 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6009 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6010 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 6011 .features[FEAT_8000_0001_EDX] = 6012 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6013 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6014 CPUID_EXT2_SYSCALL, 6015 .features[FEAT_8000_0001_ECX] = 6016 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6017 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6018 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6019 CPUID_EXT3_TOPOEXT, 6020 .features[FEAT_7_0_EBX] = 6021 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6022 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6023 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 6024 CPUID_7_0_EBX_SHA_NI, 6025 .features[FEAT_XSAVE] = 6026 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6027 CPUID_XSAVE_XGETBV1, 6028 .features[FEAT_6_EAX] = 6029 CPUID_6_EAX_ARAT, 6030 .features[FEAT_SVM] = 6031 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 6032 .xlevel = 0x8000001E, 6033 .model_id = "AMD EPYC Processor", 6034 .cache_info = &epyc_cache_info, 6035 .versions = (X86CPUVersionDefinition[]) { 6036 { .version = 1 }, 6037 { 6038 .version = 2, 6039 .alias = "EPYC-IBPB", 6040 .props = (PropValue[]) { 6041 { "ibpb", "on" }, 6042 { "model-id", 6043 "AMD EPYC Processor (with IBPB)" }, 6044 { /* end of list */ } 6045 } 6046 }, 6047 { 6048 .version = 3, 6049 .props = (PropValue[]) { 6050 { "ibpb", "on" }, 6051 { "perfctr-core", "on" }, 6052 { "clzero", "on" }, 6053 { "xsaveerptr", "on" }, 6054 { "xsaves", "on" }, 6055 { "model-id", 6056 "AMD EPYC Processor" }, 6057 { /* end of list */ } 6058 } 6059 }, 6060 { 6061 .version = 4, 6062 .props = (PropValue[]) { 6063 { "model-id", 6064 "AMD EPYC-v4 Processor" }, 6065 { /* end of list */ } 6066 }, 6067 .cache_info = &epyc_v4_cache_info 6068 }, 6069 { 6070 .version = 5, 6071 .props = (PropValue[]) { 6072 { "overflow-recov", "on" }, 6073 { "succor", "on" }, 6074 { "lbrv", "on" }, 6075 { "tsc-scale", "on" }, 6076 { "vmcb-clean", "on" }, 6077 { "flushbyasid", "on" }, 6078 { "pause-filter", "on" }, 6079 { "pfthreshold", "on" }, 6080 { "v-vmsave-vmload", "on" }, 6081 { "vgif", "on" }, 6082 { "model-id", 6083 "AMD EPYC-v5 Processor" }, 6084 { /* end of list */ } 6085 }, 6086 .cache_info = &epyc_v5_cache_info 6087 }, 6088 { /* end of list */ } 6089 } 6090 }, 6091 { 6092 .name = "Dhyana", 6093 .level = 0xd, 6094 .vendor = CPUID_VENDOR_HYGON, 6095 .family = 24, 6096 .model = 0, 6097 .stepping = 1, 6098 .features[FEAT_1_EDX] = 6099 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6100 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6101 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6102 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6103 CPUID_VME | CPUID_FP87, 6104 .features[FEAT_1_ECX] = 6105 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6106 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 6107 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6108 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6109 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 6110 .features[FEAT_8000_0001_EDX] = 6111 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6112 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6113 CPUID_EXT2_SYSCALL, 6114 .features[FEAT_8000_0001_ECX] = 6115 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6116 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6117 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6118 CPUID_EXT3_TOPOEXT, 6119 .features[FEAT_8000_0008_EBX] = 6120 CPUID_8000_0008_EBX_IBPB, 6121 .features[FEAT_7_0_EBX] = 6122 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6123 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6124 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 6125 /* XSAVES is added in version 2 */ 6126 .features[FEAT_XSAVE] = 6127 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6128 CPUID_XSAVE_XGETBV1, 6129 .features[FEAT_6_EAX] = 6130 CPUID_6_EAX_ARAT, 6131 .features[FEAT_SVM] = 6132 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 6133 .xlevel = 0x8000001E, 6134 .model_id = "Hygon Dhyana Processor", 6135 .cache_info = &epyc_cache_info, 6136 .versions = (X86CPUVersionDefinition[]) { 6137 { .version = 1 }, 6138 { .version = 2, 6139 .note = "XSAVES", 6140 .props = (PropValue[]) { 6141 { "xsaves", "on" }, 6142 { /* end of list */ } 6143 }, 6144 }, 6145 { /* end of list */ } 6146 } 6147 }, 6148 { 6149 .name = "EPYC-Rome", 6150 .level = 0xd, 6151 .vendor = CPUID_VENDOR_AMD, 6152 .family = 23, 6153 .model = 49, 6154 .stepping = 0, 6155 .features[FEAT_1_EDX] = 6156 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6157 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6158 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6159 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6160 CPUID_VME | CPUID_FP87, 6161 .features[FEAT_1_ECX] = 6162 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6163 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6164 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6165 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6166 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 6167 .features[FEAT_8000_0001_EDX] = 6168 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6169 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6170 CPUID_EXT2_SYSCALL, 6171 .features[FEAT_8000_0001_ECX] = 6172 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6173 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6174 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6175 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6176 .features[FEAT_8000_0008_EBX] = 6177 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6178 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6179 CPUID_8000_0008_EBX_STIBP, 6180 .features[FEAT_7_0_EBX] = 6181 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6182 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6183 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 6184 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 6185 .features[FEAT_7_0_ECX] = 6186 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 6187 .features[FEAT_XSAVE] = 6188 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6189 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6190 .features[FEAT_6_EAX] = 6191 CPUID_6_EAX_ARAT, 6192 .features[FEAT_SVM] = 6193 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 6194 .xlevel = 0x8000001E, 6195 .model_id = "AMD EPYC-Rome Processor", 6196 .cache_info = &epyc_rome_cache_info, 6197 .versions = (X86CPUVersionDefinition[]) { 6198 { .version = 1 }, 6199 { 6200 .version = 2, 6201 .props = (PropValue[]) { 6202 { "ibrs", "on" }, 6203 { "amd-ssbd", "on" }, 6204 { /* end of list */ } 6205 } 6206 }, 6207 { 6208 .version = 3, 6209 .props = (PropValue[]) { 6210 { "model-id", 6211 "AMD EPYC-Rome-v3 Processor" }, 6212 { /* end of list */ } 6213 }, 6214 .cache_info = &epyc_rome_v3_cache_info 6215 }, 6216 { 6217 .version = 4, 6218 .props = (PropValue[]) { 6219 /* Erratum 1386 */ 6220 { "model-id", 6221 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 6222 { "xsaves", "off" }, 6223 { /* end of list */ } 6224 }, 6225 }, 6226 { 6227 .version = 5, 6228 .props = (PropValue[]) { 6229 { "overflow-recov", "on" }, 6230 { "succor", "on" }, 6231 { "lbrv", "on" }, 6232 { "tsc-scale", "on" }, 6233 { "vmcb-clean", "on" }, 6234 { "flushbyasid", "on" }, 6235 { "pause-filter", "on" }, 6236 { "pfthreshold", "on" }, 6237 { "v-vmsave-vmload", "on" }, 6238 { "vgif", "on" }, 6239 { "model-id", 6240 "AMD EPYC-Rome-v5 Processor" }, 6241 { /* end of list */ } 6242 }, 6243 .cache_info = &epyc_rome_v5_cache_info 6244 }, 6245 { /* end of list */ } 6246 } 6247 }, 6248 { 6249 .name = "EPYC-Milan", 6250 .level = 0xd, 6251 .vendor = CPUID_VENDOR_AMD, 6252 .family = 25, 6253 .model = 1, 6254 .stepping = 1, 6255 .features[FEAT_1_EDX] = 6256 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6257 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6258 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6259 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6260 CPUID_VME | CPUID_FP87, 6261 .features[FEAT_1_ECX] = 6262 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6263 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6264 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6265 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6266 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 6267 CPUID_EXT_PCID, 6268 .features[FEAT_8000_0001_EDX] = 6269 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6270 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6271 CPUID_EXT2_SYSCALL, 6272 .features[FEAT_8000_0001_ECX] = 6273 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6274 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6275 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6276 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6277 .features[FEAT_8000_0008_EBX] = 6278 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6279 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6280 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6281 CPUID_8000_0008_EBX_AMD_SSBD, 6282 .features[FEAT_7_0_EBX] = 6283 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6284 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6285 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 6286 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 6287 CPUID_7_0_EBX_INVPCID, 6288 .features[FEAT_7_0_ECX] = 6289 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 6290 .features[FEAT_7_0_EDX] = 6291 CPUID_7_0_EDX_FSRM, 6292 .features[FEAT_XSAVE] = 6293 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6294 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6295 .features[FEAT_6_EAX] = 6296 CPUID_6_EAX_ARAT, 6297 .features[FEAT_SVM] = 6298 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 6299 .xlevel = 0x8000001E, 6300 .model_id = "AMD EPYC-Milan Processor", 6301 .cache_info = &epyc_milan_cache_info, 6302 .versions = (X86CPUVersionDefinition[]) { 6303 { .version = 1 }, 6304 { 6305 .version = 2, 6306 .props = (PropValue[]) { 6307 { "model-id", 6308 "AMD EPYC-Milan-v2 Processor" }, 6309 { "vaes", "on" }, 6310 { "vpclmulqdq", "on" }, 6311 { "stibp-always-on", "on" }, 6312 { "amd-psfd", "on" }, 6313 { "no-nested-data-bp", "on" }, 6314 { "lfence-always-serializing", "on" }, 6315 { "null-sel-clr-base", "on" }, 6316 { /* end of list */ } 6317 }, 6318 .cache_info = &epyc_milan_v2_cache_info 6319 }, 6320 { 6321 .version = 3, 6322 .props = (PropValue[]) { 6323 { "overflow-recov", "on" }, 6324 { "succor", "on" }, 6325 { "lbrv", "on" }, 6326 { "tsc-scale", "on" }, 6327 { "vmcb-clean", "on" }, 6328 { "flushbyasid", "on" }, 6329 { "pause-filter", "on" }, 6330 { "pfthreshold", "on" }, 6331 { "v-vmsave-vmload", "on" }, 6332 { "vgif", "on" }, 6333 { "model-id", 6334 "AMD EPYC-Milan-v3 Processor" }, 6335 { /* end of list */ } 6336 }, 6337 .cache_info = &epyc_milan_v3_cache_info 6338 }, 6339 { /* end of list */ } 6340 } 6341 }, 6342 { 6343 .name = "EPYC-Genoa", 6344 .level = 0xd, 6345 .vendor = CPUID_VENDOR_AMD, 6346 .family = 25, 6347 .model = 17, 6348 .stepping = 0, 6349 .features[FEAT_1_EDX] = 6350 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6351 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6352 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6353 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6354 CPUID_VME | CPUID_FP87, 6355 .features[FEAT_1_ECX] = 6356 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6357 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6358 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6359 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 6360 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 6361 CPUID_EXT_SSE3, 6362 .features[FEAT_8000_0001_EDX] = 6363 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6364 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6365 CPUID_EXT2_SYSCALL, 6366 .features[FEAT_8000_0001_ECX] = 6367 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6368 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6369 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6370 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6371 .features[FEAT_8000_0008_EBX] = 6372 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6373 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6374 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6375 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 6376 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 6377 .features[FEAT_8000_0021_EAX] = 6378 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 6379 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 6380 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 6381 CPUID_8000_0021_EAX_AUTO_IBRS, 6382 .features[FEAT_7_0_EBX] = 6383 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6384 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 6385 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 6386 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 6387 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 6388 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 6389 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 6390 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 6391 .features[FEAT_7_0_ECX] = 6392 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 6393 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 6394 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 6395 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 6396 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 6397 CPUID_7_0_ECX_RDPID, 6398 .features[FEAT_7_0_EDX] = 6399 CPUID_7_0_EDX_FSRM, 6400 .features[FEAT_7_1_EAX] = 6401 CPUID_7_1_EAX_AVX512_BF16, 6402 .features[FEAT_XSAVE] = 6403 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6404 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6405 .features[FEAT_6_EAX] = 6406 CPUID_6_EAX_ARAT, 6407 .features[FEAT_SVM] = 6408 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 6409 CPUID_SVM_SVME_ADDR_CHK, 6410 .xlevel = 0x80000022, 6411 .model_id = "AMD EPYC-Genoa Processor", 6412 .cache_info = &epyc_genoa_cache_info, 6413 .versions = (X86CPUVersionDefinition[]) { 6414 { .version = 1 }, 6415 { 6416 .version = 2, 6417 .props = (PropValue[]) { 6418 { "overflow-recov", "on" }, 6419 { "succor", "on" }, 6420 { "lbrv", "on" }, 6421 { "tsc-scale", "on" }, 6422 { "vmcb-clean", "on" }, 6423 { "flushbyasid", "on" }, 6424 { "pause-filter", "on" }, 6425 { "pfthreshold", "on" }, 6426 { "v-vmsave-vmload", "on" }, 6427 { "vgif", "on" }, 6428 { "fs-gs-base-ns", "on" }, 6429 { "perfmon-v2", "on" }, 6430 { "model-id", 6431 "AMD EPYC-Genoa-v2 Processor" }, 6432 { /* end of list */ } 6433 }, 6434 .cache_info = &epyc_genoa_v2_cache_info 6435 }, 6436 { /* end of list */ } 6437 } 6438 }, 6439 { 6440 .name = "YongFeng", 6441 .level = 0x1F, 6442 .vendor = CPUID_VENDOR_ZHAOXIN1, 6443 .family = 7, 6444 .model = 11, 6445 .stepping = 3, 6446 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 6447 .features[FEAT_1_EDX] = 6448 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 6449 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 6450 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 6451 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 6452 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 6453 /* 6454 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 6455 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 6456 */ 6457 .features[FEAT_1_ECX] = 6458 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6459 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 6460 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 6461 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 6462 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6463 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 6464 .features[FEAT_7_0_EBX] = 6465 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 6466 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 6467 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 6468 CPUID_7_0_EBX_FSGSBASE, 6469 /* missing: CPUID_7_0_ECX_OSPKE */ 6470 .features[FEAT_7_0_ECX] = 6471 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 6472 .features[FEAT_7_0_EDX] = 6473 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 6474 .features[FEAT_8000_0001_EDX] = 6475 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6476 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 6477 .features[FEAT_8000_0001_ECX] = 6478 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 6479 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 6480 /* 6481 * TODO: When the Linux kernel introduces other existing definitions 6482 * for this leaf, remember to update the definitions here. 6483 */ 6484 .features[FEAT_C000_0001_EDX] = 6485 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 6486 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 6487 CPUID_C000_0001_EDX_ACE2 | 6488 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 6489 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 6490 .features[FEAT_XSAVE] = 6491 CPUID_XSAVE_XSAVEOPT, 6492 .features[FEAT_ARCH_CAPABILITIES] = 6493 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 6494 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 6495 MSR_ARCH_CAP_SSB_NO, 6496 .features[FEAT_VMX_PROCBASED_CTLS] = 6497 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 6498 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 6499 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 6500 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 6501 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 6502 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 6503 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 6504 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 6505 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 6506 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 6507 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 6508 /* 6509 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 6510 * VMX_SECONDARY_EXEC_TSC_SCALING 6511 */ 6512 .features[FEAT_VMX_SECONDARY_CTLS] = 6513 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6514 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 6515 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 6516 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6517 VMX_SECONDARY_EXEC_WBINVD_EXITING | 6518 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 6519 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 6520 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 6521 VMX_SECONDARY_EXEC_RDRAND_EXITING | 6522 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 6523 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 6524 VMX_SECONDARY_EXEC_SHADOW_VMCS | 6525 VMX_SECONDARY_EXEC_ENABLE_PML, 6526 .features[FEAT_VMX_PINBASED_CTLS] = 6527 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 6528 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 6529 VMX_PIN_BASED_POSTED_INTR, 6530 .features[FEAT_VMX_EXIT_CTLS] = 6531 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 6532 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 6533 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 6534 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 6535 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 6536 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 6537 .features[FEAT_VMX_ENTRY_CTLS] = 6538 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 6539 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 6540 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 6541 /* 6542 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 6543 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 6544 */ 6545 .features[FEAT_VMX_MISC] = 6546 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 6547 MSR_VMX_MISC_VMWRITE_VMEXIT, 6548 /* missing: MSR_VMX_EPT_UC */ 6549 .features[FEAT_VMX_EPT_VPID_CAPS] = 6550 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 6551 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 6552 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 6553 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 6554 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 6555 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 6556 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 6557 .features[FEAT_VMX_BASIC] = 6558 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 6559 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 6560 .xlevel = 0x80000008, 6561 .model_id = "Zhaoxin YongFeng Processor", 6562 .versions = (X86CPUVersionDefinition[]) { 6563 { .version = 1 }, 6564 { 6565 .version = 2, 6566 .note = "with the correct model number", 6567 .props = (PropValue[]) { 6568 { "model", "0x5b" }, 6569 { /* end of list */ } 6570 } 6571 }, 6572 { 6573 .version = 3, 6574 .note = "with the cache model and 0x1f leaf", 6575 .cache_info = &yongfeng_cache_info, 6576 .props = (PropValue[]) { 6577 { "x-force-cpuid-0x1f", "on" }, 6578 { /* end of list */ }, 6579 } 6580 }, 6581 { /* end of list */ } 6582 } 6583 }, 6584 { 6585 .name = "EPYC-Turin", 6586 .level = 0xd, 6587 .vendor = CPUID_VENDOR_AMD, 6588 .family = 26, 6589 .model = 0, 6590 .stepping = 0, 6591 .features[FEAT_1_ECX] = 6592 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6593 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6594 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6595 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 6596 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 6597 CPUID_EXT_SSE3, 6598 .features[FEAT_1_EDX] = 6599 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6600 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6601 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6602 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6603 CPUID_VME | CPUID_FP87, 6604 .features[FEAT_6_EAX] = 6605 CPUID_6_EAX_ARAT, 6606 .features[FEAT_7_0_EBX] = 6607 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6608 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 6609 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 6610 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 6611 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 6612 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 6613 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 6614 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 6615 .features[FEAT_7_0_ECX] = 6616 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 6617 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 6618 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 6619 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 6620 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 6621 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_MOVDIRI | 6622 CPUID_7_0_ECX_MOVDIR64B, 6623 .features[FEAT_7_0_EDX] = 6624 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_AVX512_VP2INTERSECT, 6625 .features[FEAT_7_1_EAX] = 6626 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16, 6627 .features[FEAT_8000_0001_ECX] = 6628 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6629 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6630 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6631 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6632 .features[FEAT_8000_0001_EDX] = 6633 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6634 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6635 CPUID_EXT2_SYSCALL, 6636 .features[FEAT_8000_0007_EBX] = 6637 CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR, 6638 .features[FEAT_8000_0008_EBX] = 6639 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6640 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6641 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6642 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 6643 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 6644 .features[FEAT_8000_0021_EAX] = 6645 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 6646 CPUID_8000_0021_EAX_FS_GS_BASE_NS | 6647 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 6648 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 6649 CPUID_8000_0021_EAX_AUTO_IBRS | CPUID_8000_0021_EAX_PREFETCHI | 6650 CPUID_8000_0021_EAX_SBPB | CPUID_8000_0021_EAX_IBPB_BRTYPE | 6651 CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO, 6652 .features[FEAT_8000_0022_EAX] = 6653 CPUID_8000_0022_EAX_PERFMON_V2, 6654 .features[FEAT_XSAVE] = 6655 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6656 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6657 .features[FEAT_SVM] = 6658 CPUID_SVM_NPT | CPUID_SVM_LBRV | CPUID_SVM_NRIPSAVE | 6659 CPUID_SVM_TSCSCALE | CPUID_SVM_VMCBCLEAN | CPUID_SVM_FLUSHASID | 6660 CPUID_SVM_PAUSEFILTER | CPUID_SVM_PFTHRESHOLD | 6661 CPUID_SVM_V_VMSAVE_VMLOAD | CPUID_SVM_VGIF | 6662 CPUID_SVM_VNMI | CPUID_SVM_SVME_ADDR_CHK, 6663 .xlevel = 0x80000022, 6664 .model_id = "AMD EPYC-Turin Processor", 6665 .cache_info = &epyc_turin_cache_info, 6666 }, 6667 }; 6668 6669 /* 6670 * We resolve CPU model aliases using -v1 when using "-machine 6671 * none", but this is just for compatibility while libvirt isn't 6672 * adapted to resolve CPU model versions before creating VMs. 6673 * See "Runnability guarantee of CPU models" at 6674 * docs/about/deprecated.rst. 6675 */ 6676 X86CPUVersion default_cpu_version = 1; 6677 6678 void x86_cpu_set_default_version(X86CPUVersion version) 6679 { 6680 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 6681 assert(version != CPU_VERSION_AUTO); 6682 default_cpu_version = version; 6683 } 6684 6685 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 6686 { 6687 int v = 0; 6688 const X86CPUVersionDefinition *vdef = 6689 x86_cpu_def_get_versions(model->cpudef); 6690 while (vdef->version) { 6691 v = vdef->version; 6692 vdef++; 6693 } 6694 return v; 6695 } 6696 6697 /* Return the actual version being used for a specific CPU model */ 6698 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 6699 { 6700 X86CPUVersion v = model->version; 6701 if (v == CPU_VERSION_AUTO) { 6702 v = default_cpu_version; 6703 } 6704 if (v == CPU_VERSION_LATEST) { 6705 return x86_cpu_model_last_version(model); 6706 } 6707 return v; 6708 } 6709 6710 static const Property max_x86_cpu_properties[] = { 6711 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 6712 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 6713 }; 6714 6715 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 6716 { 6717 Object *obj = OBJECT(dev); 6718 6719 if (!object_property_get_int(obj, "family", &error_abort)) { 6720 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6721 object_property_set_int(obj, "family", 15, &error_abort); 6722 object_property_set_int(obj, "model", 107, &error_abort); 6723 object_property_set_int(obj, "stepping", 1, &error_abort); 6724 } else { 6725 object_property_set_int(obj, "family", 6, &error_abort); 6726 object_property_set_int(obj, "model", 6, &error_abort); 6727 object_property_set_int(obj, "stepping", 3, &error_abort); 6728 } 6729 } 6730 6731 x86_cpu_realizefn(dev, errp); 6732 } 6733 6734 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 6735 { 6736 DeviceClass *dc = DEVICE_CLASS(oc); 6737 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6738 6739 xcc->ordering = 9; 6740 6741 xcc->max_features = true; 6742 xcc->model_description = 6743 "Enables all features supported by the accelerator in the current host"; 6744 6745 device_class_set_props(dc, max_x86_cpu_properties); 6746 dc->realize = max_x86_cpu_realize; 6747 } 6748 6749 static void max_x86_cpu_initfn(Object *obj) 6750 { 6751 X86CPU *cpu = X86_CPU(obj); 6752 CPUX86State *env = &cpu->env; 6753 6754 /* 6755 * these defaults are used for TCG, other accelerators have overwritten 6756 * these values 6757 */ 6758 if (!env->cpuid_vendor1) { 6759 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 6760 &error_abort); 6761 } 6762 if (!env->cpuid_model[0]) { 6763 object_property_set_str(OBJECT(cpu), "model-id", 6764 "QEMU TCG CPU version " QEMU_HW_VERSION, 6765 &error_abort); 6766 } 6767 } 6768 6769 static const TypeInfo max_x86_cpu_type_info = { 6770 .name = X86_CPU_TYPE_NAME("max"), 6771 .parent = TYPE_X86_CPU, 6772 .instance_init = max_x86_cpu_initfn, 6773 .class_init = max_x86_cpu_class_init, 6774 }; 6775 6776 static char *feature_word_description(FeatureWordInfo *f) 6777 { 6778 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 6779 6780 switch (f->type) { 6781 case CPUID_FEATURE_WORD: 6782 { 6783 const char *reg = get_register_name_32(f->cpuid.reg); 6784 assert(reg); 6785 if (!f->cpuid.needs_ecx) { 6786 return g_strdup_printf("CPUID[eax=%02Xh].%s", f->cpuid.eax, reg); 6787 } else { 6788 return g_strdup_printf("CPUID[eax=%02Xh,ecx=%02Xh].%s", 6789 f->cpuid.eax, f->cpuid.ecx, reg); 6790 } 6791 } 6792 case MSR_FEATURE_WORD: 6793 return g_strdup_printf("MSR(%02Xh)", 6794 f->msr.index); 6795 } 6796 6797 return NULL; 6798 } 6799 6800 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 6801 { 6802 FeatureWord w; 6803 6804 for (w = 0; w < FEATURE_WORDS; w++) { 6805 if (cpu->filtered_features[w]) { 6806 return true; 6807 } 6808 } 6809 6810 return false; 6811 } 6812 6813 void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6814 const char *verbose_prefix) 6815 { 6816 CPUX86State *env = &cpu->env; 6817 FeatureWordInfo *f = &feature_word_info[w]; 6818 int i; 6819 g_autofree char *feat_word_str = feature_word_description(f); 6820 6821 if (!cpu->force_features) { 6822 env->features[w] &= ~mask; 6823 } 6824 cpu->filtered_features[w] |= mask; 6825 6826 if (!verbose_prefix) { 6827 return; 6828 } 6829 6830 for (i = 0; i < 64; ++i) { 6831 if ((1ULL << i) & mask) { 6832 warn_report("%s: %s%s%s [bit %d]", 6833 verbose_prefix, 6834 feat_word_str, 6835 f->feat_names[i] ? "." : "", 6836 f->feat_names[i] ? f->feat_names[i] : "", i); 6837 } 6838 } 6839 } 6840 6841 void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6842 const char *verbose_prefix) 6843 { 6844 CPUX86State *env = &cpu->env; 6845 FeatureWordInfo *f = &feature_word_info[w]; 6846 int i; 6847 6848 if (!cpu->force_features) { 6849 env->features[w] |= mask; 6850 } 6851 6852 cpu->forced_on_features[w] |= mask; 6853 6854 if (!verbose_prefix) { 6855 return; 6856 } 6857 6858 for (i = 0; i < 64; ++i) { 6859 if ((1ULL << i) & mask) { 6860 g_autofree char *feat_word_str = feature_word_description(f); 6861 warn_report("%s: %s%s%s [bit %d]", 6862 verbose_prefix, 6863 feat_word_str, 6864 f->feat_names[i] ? "." : "", 6865 f->feat_names[i] ? f->feat_names[i] : "", i); 6866 } 6867 } 6868 } 6869 6870 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 6871 const char *name, void *opaque, 6872 Error **errp) 6873 { 6874 X86CPU *cpu = X86_CPU(obj); 6875 CPUX86State *env = &cpu->env; 6876 uint64_t value; 6877 6878 value = x86_cpu_family(env->cpuid_version); 6879 visit_type_uint64(v, name, &value, errp); 6880 } 6881 6882 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 6883 const char *name, void *opaque, 6884 Error **errp) 6885 { 6886 X86CPU *cpu = X86_CPU(obj); 6887 CPUX86State *env = &cpu->env; 6888 const uint64_t max = 0xff + 0xf; 6889 uint64_t value; 6890 6891 if (!visit_type_uint64(v, name, &value, errp)) { 6892 return; 6893 } 6894 if (value > max) { 6895 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6896 name ? name : "null", max); 6897 return; 6898 } 6899 6900 env->cpuid_version &= ~0xff00f00; 6901 if (value > 0x0f) { 6902 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 6903 } else { 6904 env->cpuid_version |= value << 8; 6905 } 6906 } 6907 6908 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 6909 const char *name, void *opaque, 6910 Error **errp) 6911 { 6912 X86CPU *cpu = X86_CPU(obj); 6913 CPUX86State *env = &cpu->env; 6914 uint64_t value; 6915 6916 value = x86_cpu_model(env->cpuid_version); 6917 visit_type_uint64(v, name, &value, errp); 6918 } 6919 6920 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 6921 const char *name, void *opaque, 6922 Error **errp) 6923 { 6924 X86CPU *cpu = X86_CPU(obj); 6925 CPUX86State *env = &cpu->env; 6926 const uint64_t max = 0xff; 6927 uint64_t value; 6928 6929 if (!visit_type_uint64(v, name, &value, errp)) { 6930 return; 6931 } 6932 if (value > max) { 6933 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6934 name ? name : "null", max); 6935 return; 6936 } 6937 6938 env->cpuid_version &= ~0xf00f0; 6939 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 6940 } 6941 6942 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 6943 const char *name, void *opaque, 6944 Error **errp) 6945 { 6946 X86CPU *cpu = X86_CPU(obj); 6947 CPUX86State *env = &cpu->env; 6948 uint64_t value; 6949 6950 value = x86_cpu_stepping(env->cpuid_version); 6951 visit_type_uint64(v, name, &value, errp); 6952 } 6953 6954 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 6955 const char *name, void *opaque, 6956 Error **errp) 6957 { 6958 X86CPU *cpu = X86_CPU(obj); 6959 CPUX86State *env = &cpu->env; 6960 const uint64_t max = 0xf; 6961 uint64_t value; 6962 6963 if (!visit_type_uint64(v, name, &value, errp)) { 6964 return; 6965 } 6966 if (value > max) { 6967 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6968 name ? name : "null", max); 6969 return; 6970 } 6971 6972 env->cpuid_version &= ~0xf; 6973 env->cpuid_version |= value & 0xf; 6974 } 6975 6976 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 6977 { 6978 X86CPU *cpu = X86_CPU(obj); 6979 CPUX86State *env = &cpu->env; 6980 char *value; 6981 6982 value = g_malloc(CPUID_VENDOR_SZ + 1); 6983 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 6984 env->cpuid_vendor3); 6985 return value; 6986 } 6987 6988 static void x86_cpuid_set_vendor(Object *obj, const char *value, 6989 Error **errp) 6990 { 6991 X86CPU *cpu = X86_CPU(obj); 6992 CPUX86State *env = &cpu->env; 6993 int i; 6994 6995 if (strlen(value) != CPUID_VENDOR_SZ) { 6996 error_setg(errp, "value of property 'vendor' must consist of" 6997 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 6998 return; 6999 } 7000 7001 env->cpuid_vendor1 = 0; 7002 env->cpuid_vendor2 = 0; 7003 env->cpuid_vendor3 = 0; 7004 for (i = 0; i < 4; i++) { 7005 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 7006 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 7007 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 7008 } 7009 } 7010 7011 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 7012 { 7013 X86CPU *cpu = X86_CPU(obj); 7014 CPUX86State *env = &cpu->env; 7015 char *value; 7016 int i; 7017 7018 value = g_malloc(CPUID_MODEL_ID_SZ + 1); 7019 for (i = 0; i < CPUID_MODEL_ID_SZ; i++) { 7020 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 7021 } 7022 value[CPUID_MODEL_ID_SZ] = '\0'; 7023 return value; 7024 } 7025 7026 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 7027 Error **errp) 7028 { 7029 X86CPU *cpu = X86_CPU(obj); 7030 CPUX86State *env = &cpu->env; 7031 int c, len, i; 7032 7033 if (model_id == NULL) { 7034 model_id = ""; 7035 } 7036 len = strlen(model_id); 7037 memset(env->cpuid_model, 0, CPUID_MODEL_ID_SZ); 7038 for (i = 0; i < 48; i++) { 7039 if (i >= len) { 7040 c = '\0'; 7041 } else { 7042 c = (uint8_t)model_id[i]; 7043 } 7044 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 7045 } 7046 } 7047 7048 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 7049 void *opaque, Error **errp) 7050 { 7051 X86CPU *cpu = X86_CPU(obj); 7052 int64_t value; 7053 7054 value = cpu->env.tsc_khz * 1000; 7055 visit_type_int(v, name, &value, errp); 7056 } 7057 7058 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 7059 void *opaque, Error **errp) 7060 { 7061 X86CPU *cpu = X86_CPU(obj); 7062 const int64_t max = INT64_MAX; 7063 int64_t value; 7064 7065 if (!visit_type_int(v, name, &value, errp)) { 7066 return; 7067 } 7068 if (value < 0 || value > max) { 7069 error_setg(errp, "parameter '%s' can be at most %" PRId64, 7070 name ? name : "null", max); 7071 return; 7072 } 7073 7074 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 7075 } 7076 7077 /* Generic getter for "feature-words" and "filtered-features" properties */ 7078 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 7079 const char *name, void *opaque, 7080 Error **errp) 7081 { 7082 uint64_t *array = (uint64_t *)opaque; 7083 FeatureWord w; 7084 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 7085 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 7086 X86CPUFeatureWordInfoList *list = NULL; 7087 7088 for (w = 0; w < FEATURE_WORDS; w++) { 7089 FeatureWordInfo *wi = &feature_word_info[w]; 7090 /* 7091 * We didn't have MSR features when "feature-words" was 7092 * introduced. Therefore skipped other type entries. 7093 */ 7094 if (wi->type != CPUID_FEATURE_WORD) { 7095 continue; 7096 } 7097 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 7098 qwi->cpuid_input_eax = wi->cpuid.eax; 7099 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 7100 qwi->cpuid_input_ecx = wi->cpuid.ecx; 7101 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 7102 qwi->features = array[w]; 7103 7104 /* List will be in reverse order, but order shouldn't matter */ 7105 list_entries[w].next = list; 7106 list_entries[w].value = &word_infos[w]; 7107 list = &list_entries[w]; 7108 } 7109 7110 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 7111 } 7112 7113 /* Convert all '_' in a feature string option name to '-', to make feature 7114 * name conform to QOM property naming rule, which uses '-' instead of '_'. 7115 */ 7116 static inline void feat2prop(char *s) 7117 { 7118 while ((s = strchr(s, '_'))) { 7119 *s = '-'; 7120 } 7121 } 7122 7123 /* Return the feature property name for a feature flag bit */ 7124 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 7125 { 7126 const char *name; 7127 /* XSAVE components are automatically enabled by other features, 7128 * so return the original feature name instead 7129 */ 7130 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 7131 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 7132 7133 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 7134 x86_ext_save_areas[comp].bits) { 7135 w = x86_ext_save_areas[comp].feature; 7136 bitnr = ctz32(x86_ext_save_areas[comp].bits); 7137 } 7138 } 7139 7140 assert(bitnr < 64); 7141 assert(w < FEATURE_WORDS); 7142 name = feature_word_info[w].feat_names[bitnr]; 7143 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 7144 return name; 7145 } 7146 7147 /* Compatibility hack to maintain legacy +-feat semantic, 7148 * where +-feat overwrites any feature set by 7149 * feat=on|feat even if the later is parsed after +-feat 7150 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 7151 */ 7152 static GList *plus_features, *minus_features; 7153 7154 static gint compare_string(gconstpointer a, gconstpointer b) 7155 { 7156 return g_strcmp0(a, b); 7157 } 7158 7159 /* Parse "+feature,-feature,feature=foo" CPU feature string 7160 */ 7161 static void x86_cpu_parse_featurestr(const char *typename, char *features, 7162 Error **errp) 7163 { 7164 char *featurestr; /* Single 'key=value" string being parsed */ 7165 static bool cpu_globals_initialized; 7166 bool ambiguous = false; 7167 7168 if (cpu_globals_initialized) { 7169 return; 7170 } 7171 cpu_globals_initialized = true; 7172 7173 if (!features) { 7174 return; 7175 } 7176 7177 for (featurestr = strtok(features, ","); 7178 featurestr; 7179 featurestr = strtok(NULL, ",")) { 7180 const char *name; 7181 const char *val = NULL; 7182 char *eq = NULL; 7183 char num[32]; 7184 GlobalProperty *prop; 7185 7186 /* Compatibility syntax: */ 7187 if (featurestr[0] == '+') { 7188 plus_features = g_list_append(plus_features, 7189 g_strdup(featurestr + 1)); 7190 continue; 7191 } else if (featurestr[0] == '-') { 7192 minus_features = g_list_append(minus_features, 7193 g_strdup(featurestr + 1)); 7194 continue; 7195 } 7196 7197 eq = strchr(featurestr, '='); 7198 if (eq) { 7199 *eq++ = 0; 7200 val = eq; 7201 } else { 7202 val = "on"; 7203 } 7204 7205 feat2prop(featurestr); 7206 name = featurestr; 7207 7208 if (g_list_find_custom(plus_features, name, compare_string)) { 7209 warn_report("Ambiguous CPU model string. " 7210 "Don't mix both \"+%s\" and \"%s=%s\"", 7211 name, name, val); 7212 ambiguous = true; 7213 } 7214 if (g_list_find_custom(minus_features, name, compare_string)) { 7215 warn_report("Ambiguous CPU model string. " 7216 "Don't mix both \"-%s\" and \"%s=%s\"", 7217 name, name, val); 7218 ambiguous = true; 7219 } 7220 7221 /* Special case: */ 7222 if (!strcmp(name, "tsc-freq")) { 7223 int ret; 7224 uint64_t tsc_freq; 7225 7226 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 7227 if (ret < 0 || tsc_freq > INT64_MAX) { 7228 error_setg(errp, "bad numerical value %s", val); 7229 return; 7230 } 7231 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 7232 val = num; 7233 name = "tsc-frequency"; 7234 } 7235 7236 prop = g_new0(typeof(*prop), 1); 7237 prop->driver = typename; 7238 prop->property = g_strdup(name); 7239 prop->value = g_strdup(val); 7240 qdev_prop_register_global(prop); 7241 } 7242 7243 if (ambiguous) { 7244 warn_report("Compatibility of ambiguous CPU model " 7245 "strings won't be kept on future QEMU versions"); 7246 } 7247 } 7248 7249 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 7250 7251 /* Build a list with the name of all features on a feature word array */ 7252 static void x86_cpu_list_feature_names(FeatureWordArray features, 7253 strList **list) 7254 { 7255 strList **tail = list; 7256 FeatureWord w; 7257 7258 for (w = 0; w < FEATURE_WORDS; w++) { 7259 uint64_t filtered = features[w]; 7260 int i; 7261 for (i = 0; i < 64; i++) { 7262 if (filtered & (1ULL << i)) { 7263 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 7264 } 7265 } 7266 } 7267 } 7268 7269 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 7270 const char *name, void *opaque, 7271 Error **errp) 7272 { 7273 X86CPU *xc = X86_CPU(obj); 7274 strList *result = NULL; 7275 7276 x86_cpu_list_feature_names(xc->filtered_features, &result); 7277 visit_type_strList(v, "unavailable-features", &result, errp); 7278 } 7279 7280 /* Print all cpuid feature names in featureset 7281 */ 7282 static void listflags(GList *features) 7283 { 7284 size_t len = 0; 7285 GList *tmp; 7286 7287 for (tmp = features; tmp; tmp = tmp->next) { 7288 const char *name = tmp->data; 7289 if ((len + strlen(name) + 1) >= 75) { 7290 qemu_printf("\n"); 7291 len = 0; 7292 } 7293 qemu_printf("%s%s", len == 0 ? " " : " ", name); 7294 len += strlen(name) + 1; 7295 } 7296 qemu_printf("\n"); 7297 } 7298 7299 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 7300 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 7301 { 7302 ObjectClass *class_a = (ObjectClass *)a; 7303 ObjectClass *class_b = (ObjectClass *)b; 7304 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 7305 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 7306 int ret; 7307 7308 if (cc_a->ordering != cc_b->ordering) { 7309 ret = cc_a->ordering - cc_b->ordering; 7310 } else { 7311 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 7312 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 7313 ret = strcmp(name_a, name_b); 7314 } 7315 return ret; 7316 } 7317 7318 static GSList *get_sorted_cpu_model_list(void) 7319 { 7320 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 7321 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 7322 return list; 7323 } 7324 7325 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 7326 { 7327 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 7328 char *r = object_property_get_str(obj, "model-id", &error_abort); 7329 object_unref(obj); 7330 return r; 7331 } 7332 7333 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 7334 { 7335 X86CPUVersion version; 7336 7337 if (!cc->model || !cc->model->is_alias) { 7338 return NULL; 7339 } 7340 version = x86_cpu_model_resolve_version(cc->model); 7341 if (version <= 0) { 7342 return NULL; 7343 } 7344 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 7345 } 7346 7347 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 7348 { 7349 ObjectClass *oc = data; 7350 X86CPUClass *cc = X86_CPU_CLASS(oc); 7351 g_autofree char *name = x86_cpu_class_get_model_name(cc); 7352 g_autofree char *desc = g_strdup(cc->model_description); 7353 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 7354 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 7355 7356 if (!desc && alias_of) { 7357 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 7358 desc = g_strdup("(alias configured by machine type)"); 7359 } else { 7360 desc = g_strdup_printf("(alias of %s)", alias_of); 7361 } 7362 } 7363 if (!desc && cc->model && cc->model->note) { 7364 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 7365 } 7366 if (!desc) { 7367 desc = g_strdup(model_id); 7368 } 7369 7370 if (cc->model && cc->model->cpudef->deprecation_note) { 7371 g_autofree char *olddesc = desc; 7372 desc = g_strdup_printf("%s (deprecated)", olddesc); 7373 } 7374 7375 qemu_printf(" %-20s %s\n", name, desc); 7376 } 7377 7378 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 7379 { 7380 return strcmp(a, b); 7381 } 7382 7383 /* list available CPU models and flags */ 7384 static void x86_cpu_list(void) 7385 { 7386 int i, j; 7387 GSList *list; 7388 GList *names = NULL; 7389 7390 qemu_printf("Available CPUs:\n"); 7391 list = get_sorted_cpu_model_list(); 7392 g_slist_foreach(list, x86_cpu_list_entry, NULL); 7393 g_slist_free(list); 7394 7395 names = NULL; 7396 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 7397 FeatureWordInfo *fw = &feature_word_info[i]; 7398 for (j = 0; j < 64; j++) { 7399 if (fw->feat_names[j]) { 7400 names = g_list_append(names, (gpointer)fw->feat_names[j]); 7401 } 7402 } 7403 } 7404 7405 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 7406 7407 qemu_printf("\nRecognized CPUID flags:\n"); 7408 listflags(names); 7409 qemu_printf("\n"); 7410 g_list_free(names); 7411 } 7412 7413 #ifndef CONFIG_USER_ONLY 7414 7415 /* Check for missing features that may prevent the CPU class from 7416 * running using the current machine and accelerator. 7417 */ 7418 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 7419 strList **list) 7420 { 7421 strList **tail = list; 7422 X86CPU *xc; 7423 Error *err = NULL; 7424 7425 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7426 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 7427 return; 7428 } 7429 7430 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 7431 7432 x86_cpu_expand_features(xc, &err); 7433 if (err) { 7434 /* Errors at x86_cpu_expand_features should never happen, 7435 * but in case it does, just report the model as not 7436 * runnable at all using the "type" property. 7437 */ 7438 QAPI_LIST_APPEND(tail, g_strdup("type")); 7439 error_free(err); 7440 } 7441 7442 x86_cpu_filter_features(xc, false); 7443 7444 x86_cpu_list_feature_names(xc->filtered_features, tail); 7445 7446 object_unref(OBJECT(xc)); 7447 } 7448 7449 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 7450 { 7451 ObjectClass *oc = data; 7452 X86CPUClass *cc = X86_CPU_CLASS(oc); 7453 CpuDefinitionInfoList **cpu_list = user_data; 7454 CpuDefinitionInfo *info; 7455 7456 info = g_malloc0(sizeof(*info)); 7457 info->name = x86_cpu_class_get_model_name(cc); 7458 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 7459 info->has_unavailable_features = true; 7460 info->q_typename = g_strdup(object_class_get_name(oc)); 7461 info->migration_safe = cc->migration_safe; 7462 info->has_migration_safe = true; 7463 info->q_static = cc->static_model; 7464 if (cc->model && cc->model->cpudef->deprecation_note) { 7465 info->deprecated = true; 7466 } else { 7467 info->deprecated = false; 7468 } 7469 /* 7470 * Old machine types won't report aliases, so that alias translation 7471 * doesn't break compatibility with previous QEMU versions. 7472 */ 7473 if (default_cpu_version != CPU_VERSION_LEGACY) { 7474 info->alias_of = x86_cpu_class_get_alias_of(cc); 7475 } 7476 7477 QAPI_LIST_PREPEND(*cpu_list, info); 7478 } 7479 7480 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7481 { 7482 CpuDefinitionInfoList *cpu_list = NULL; 7483 GSList *list = get_sorted_cpu_model_list(); 7484 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 7485 g_slist_free(list); 7486 return cpu_list; 7487 } 7488 7489 #endif /* !CONFIG_USER_ONLY */ 7490 7491 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 7492 { 7493 FeatureWordInfo *wi = &feature_word_info[w]; 7494 uint64_t r = 0; 7495 uint64_t unavail = 0; 7496 7497 if (kvm_enabled()) { 7498 switch (wi->type) { 7499 case CPUID_FEATURE_WORD: 7500 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 7501 wi->cpuid.ecx, 7502 wi->cpuid.reg); 7503 break; 7504 case MSR_FEATURE_WORD: 7505 r = kvm_arch_get_supported_msr_feature(kvm_state, 7506 wi->msr.index); 7507 break; 7508 } 7509 } else if (hvf_enabled()) { 7510 if (wi->type != CPUID_FEATURE_WORD) { 7511 return 0; 7512 } 7513 r = hvf_get_supported_cpuid(wi->cpuid.eax, 7514 wi->cpuid.ecx, 7515 wi->cpuid.reg); 7516 } else if (tcg_enabled()) { 7517 r = wi->tcg_features; 7518 } else { 7519 return ~0; 7520 } 7521 7522 switch (w) { 7523 #ifndef TARGET_X86_64 7524 case FEAT_8000_0001_EDX: 7525 /* 7526 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 7527 * way for userspace to get out of its 32-bit jail, we can leave 7528 * the LM bit set. 7529 */ 7530 unavail = tcg_enabled() 7531 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 7532 : CPUID_EXT2_LM; 7533 break; 7534 #endif 7535 7536 case FEAT_8000_0007_EBX: 7537 if (cpu && !IS_AMD_CPU(&cpu->env)) { 7538 /* Disable AMD machine check architecture for Intel CPU. */ 7539 unavail = ~0; 7540 } 7541 break; 7542 7543 case FEAT_7_0_EBX: 7544 #ifndef CONFIG_USER_ONLY 7545 if (!check_sgx_support()) { 7546 unavail = CPUID_7_0_EBX_SGX; 7547 } 7548 #endif 7549 break; 7550 case FEAT_7_0_ECX: 7551 #ifndef CONFIG_USER_ONLY 7552 if (!check_sgx_support()) { 7553 unavail = CPUID_7_0_ECX_SGX_LC; 7554 } 7555 #endif 7556 break; 7557 7558 case FEAT_7_0_EDX: 7559 /* 7560 * Windows does not like ARCH_CAPABILITIES on AMD machines at all. 7561 * Do not show the fake ARCH_CAPABILITIES MSR that KVM sets up, 7562 * except if needed for migration. 7563 * 7564 * When arch_cap_always_on is removed, this tweak can move to 7565 * kvm_arch_get_supported_cpuid. 7566 */ 7567 if (cpu && IS_AMD_CPU(&cpu->env) && !cpu->arch_cap_always_on) { 7568 unavail = CPUID_7_0_EDX_ARCH_CAPABILITIES; 7569 } 7570 break; 7571 7572 default: 7573 break; 7574 } 7575 7576 r &= ~unavail; 7577 if (cpu && cpu->migratable) { 7578 r &= x86_cpu_get_migratable_flags(cpu, w); 7579 } 7580 return r; 7581 } 7582 7583 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 7584 uint32_t *eax, uint32_t *ebx, 7585 uint32_t *ecx, uint32_t *edx) 7586 { 7587 if (kvm_enabled()) { 7588 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 7589 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 7590 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 7591 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 7592 } else if (hvf_enabled()) { 7593 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 7594 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 7595 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 7596 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 7597 } else { 7598 *eax = 0; 7599 *ebx = 0; 7600 *ecx = 0; 7601 *edx = 0; 7602 } 7603 } 7604 7605 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 7606 uint32_t *eax, uint32_t *ebx, 7607 uint32_t *ecx, uint32_t *edx) 7608 { 7609 uint32_t level, unused; 7610 7611 /* Only return valid host leaves. */ 7612 switch (func) { 7613 case 2: 7614 case 4: 7615 host_cpuid(0, 0, &level, &unused, &unused, &unused); 7616 break; 7617 case 0x80000005: 7618 case 0x80000006: 7619 case 0x8000001d: 7620 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 7621 break; 7622 default: 7623 return; 7624 } 7625 7626 if (func > level) { 7627 *eax = 0; 7628 *ebx = 0; 7629 *ecx = 0; 7630 *edx = 0; 7631 } else { 7632 host_cpuid(func, index, eax, ebx, ecx, edx); 7633 } 7634 } 7635 7636 /* 7637 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7638 */ 7639 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 7640 { 7641 PropValue *pv; 7642 for (pv = props; pv->prop; pv++) { 7643 if (!pv->value) { 7644 continue; 7645 } 7646 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 7647 &error_abort); 7648 } 7649 } 7650 7651 /* 7652 * Apply properties for the CPU model version specified in model. 7653 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7654 */ 7655 7656 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 7657 { 7658 const X86CPUVersionDefinition *vdef; 7659 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7660 7661 if (version == CPU_VERSION_LEGACY) { 7662 return; 7663 } 7664 7665 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7666 PropValue *p; 7667 7668 for (p = vdef->props; p && p->prop; p++) { 7669 object_property_parse(OBJECT(cpu), p->prop, p->value, 7670 &error_abort); 7671 } 7672 7673 if (vdef->version == version) { 7674 break; 7675 } 7676 } 7677 7678 /* 7679 * If we reached the end of the list, version number was invalid 7680 */ 7681 assert(vdef->version == version); 7682 } 7683 7684 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 7685 const X86CPUModel *model) 7686 { 7687 const X86CPUVersionDefinition *vdef; 7688 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7689 const CPUCaches *cache_info = model->cpudef->cache_info; 7690 7691 if (version == CPU_VERSION_LEGACY) { 7692 return cache_info; 7693 } 7694 7695 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7696 if (vdef->cache_info) { 7697 cache_info = vdef->cache_info; 7698 } 7699 7700 if (vdef->version == version) { 7701 break; 7702 } 7703 } 7704 7705 assert(vdef->version == version); 7706 return cache_info; 7707 } 7708 7709 /* 7710 * Load data from X86CPUDefinition into a X86CPU object. 7711 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7712 */ 7713 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 7714 { 7715 const X86CPUDefinition *def = model->cpudef; 7716 CPUX86State *env = &cpu->env; 7717 FeatureWord w; 7718 7719 /*NOTE: any property set by this function should be returned by 7720 * x86_cpu_static_props(), so static expansion of 7721 * query-cpu-model-expansion is always complete. 7722 */ 7723 7724 /* CPU models only set _minimum_ values for level/xlevel: */ 7725 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 7726 &error_abort); 7727 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 7728 &error_abort); 7729 7730 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 7731 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 7732 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 7733 &error_abort); 7734 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 7735 &error_abort); 7736 for (w = 0; w < FEATURE_WORDS; w++) { 7737 env->features[w] = def->features[w]; 7738 } 7739 7740 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 7741 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 7742 7743 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 7744 7745 /* sysenter isn't supported in compatibility mode on AMD, 7746 * syscall isn't supported in compatibility mode on Intel. 7747 * Normally we advertise the actual CPU vendor, but you can 7748 * override this using the 'vendor' property if you want to use 7749 * KVM's sysenter/syscall emulation in compatibility mode and 7750 * when doing cross vendor migration 7751 */ 7752 7753 /* 7754 * vendor property is set here but then overloaded with the 7755 * host cpu vendor for KVM and HVF. 7756 */ 7757 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 7758 7759 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 7760 &error_abort); 7761 7762 x86_cpu_apply_version_props(cpu, model); 7763 7764 /* 7765 * Properties in versioned CPU model are not user specified features. 7766 * We can simply clear env->user_features here since it will be filled later 7767 * in x86_cpu_expand_features() based on plus_features and minus_features. 7768 */ 7769 memset(&env->user_features, 0, sizeof(env->user_features)); 7770 } 7771 7772 static const gchar *x86_gdb_arch_name(CPUState *cs) 7773 { 7774 #ifdef TARGET_X86_64 7775 return "i386:x86-64"; 7776 #else 7777 return "i386"; 7778 #endif 7779 } 7780 7781 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 7782 { 7783 const X86CPUModel *model = data; 7784 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7785 CPUClass *cc = CPU_CLASS(oc); 7786 7787 xcc->model = model; 7788 xcc->migration_safe = true; 7789 cc->deprecation_note = model->cpudef->deprecation_note; 7790 } 7791 7792 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 7793 { 7794 g_autofree char *typename = x86_cpu_type_name(name); 7795 TypeInfo ti = { 7796 .name = typename, 7797 .parent = TYPE_X86_CPU, 7798 .class_init = x86_cpu_cpudef_class_init, 7799 .class_data = model, 7800 }; 7801 7802 type_register_static(&ti); 7803 } 7804 7805 7806 /* 7807 * register builtin_x86_defs; 7808 * "max", "base" and subclasses ("host") are not registered here. 7809 * See x86_cpu_register_types for all model registrations. 7810 */ 7811 static void x86_register_cpudef_types(const X86CPUDefinition *def) 7812 { 7813 X86CPUModel *m; 7814 const X86CPUVersionDefinition *vdef; 7815 7816 /* AMD aliases are handled at runtime based on CPUID vendor, so 7817 * they shouldn't be set on the CPU model table. 7818 */ 7819 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 7820 /* catch mistakes instead of silently truncating model_id when too long */ 7821 assert(def->model_id && strlen(def->model_id) <= 48); 7822 7823 /* Unversioned model: */ 7824 m = g_new0(X86CPUModel, 1); 7825 m->cpudef = def; 7826 m->version = CPU_VERSION_AUTO; 7827 m->is_alias = true; 7828 x86_register_cpu_model_type(def->name, m); 7829 7830 /* Versioned models: */ 7831 7832 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 7833 g_autofree char *name = 7834 x86_cpu_versioned_model_name(def, vdef->version); 7835 7836 m = g_new0(X86CPUModel, 1); 7837 m->cpudef = def; 7838 m->version = vdef->version; 7839 m->note = vdef->note; 7840 x86_register_cpu_model_type(name, m); 7841 7842 if (vdef->alias) { 7843 X86CPUModel *am = g_new0(X86CPUModel, 1); 7844 am->cpudef = def; 7845 am->version = vdef->version; 7846 am->is_alias = true; 7847 x86_register_cpu_model_type(vdef->alias, am); 7848 } 7849 } 7850 7851 } 7852 7853 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 7854 { 7855 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 7856 return 57; /* 57 bits virtual */ 7857 } else { 7858 return 48; /* 48 bits virtual */ 7859 } 7860 } 7861 7862 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 7863 uint32_t *eax, uint32_t *ebx, 7864 uint32_t *ecx, uint32_t *edx) 7865 { 7866 X86CPU *cpu = env_archcpu(env); 7867 CPUState *cs = env_cpu(env); 7868 uint32_t limit; 7869 uint32_t signature[3]; 7870 X86CPUTopoInfo *topo_info = &env->topo_info; 7871 uint32_t threads_per_pkg; 7872 7873 threads_per_pkg = x86_threads_per_pkg(topo_info); 7874 7875 /* Calculate & apply limits for different index ranges */ 7876 if (index >= 0xC0000000) { 7877 limit = env->cpuid_xlevel2; 7878 } else if (index >= 0x80000000) { 7879 limit = env->cpuid_xlevel; 7880 } else if (index >= 0x40000000) { 7881 limit = 0x40000001; 7882 } else { 7883 limit = env->cpuid_level; 7884 } 7885 7886 if (index > limit) { 7887 /* Intel documentation states that invalid EAX input will 7888 * return the same information as EAX=cpuid_level 7889 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 7890 */ 7891 index = env->cpuid_level; 7892 } 7893 7894 switch(index) { 7895 case 0: 7896 *eax = env->cpuid_level; 7897 *ebx = env->cpuid_vendor1; 7898 *edx = env->cpuid_vendor2; 7899 *ecx = env->cpuid_vendor3; 7900 break; 7901 case 1: 7902 *eax = env->cpuid_version; 7903 *ebx = (cpu->apic_id << 24) | 7904 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 7905 *ecx = env->features[FEAT_1_ECX]; 7906 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 7907 *ecx |= CPUID_EXT_OSXSAVE; 7908 } 7909 *edx = env->features[FEAT_1_EDX]; 7910 if (threads_per_pkg > 1) { 7911 uint32_t num; 7912 7913 /* 7914 * For CPUID.01H.EBX[Bits 23-16], AMD requires logical processor 7915 * count, but Intel needs maximum number of addressable IDs for 7916 * logical processors per package. 7917 */ 7918 if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 7919 num = 1 << apicid_pkg_offset(topo_info); 7920 } else { 7921 num = threads_per_pkg; 7922 } 7923 7924 /* Fixup overflow: max value for bits 23-16 is 255. */ 7925 *ebx |= MIN(num, 255) << 16; 7926 } 7927 if (cpu->pdcm_on_even_without_pmu) { 7928 if (!cpu->enable_pmu) { 7929 *ecx &= ~CPUID_EXT_PDCM; 7930 } 7931 } 7932 break; 7933 case 2: { /* cache info: needed for Pentium Pro compatibility */ 7934 const CPUCaches *caches; 7935 7936 if (env->enable_legacy_cpuid2_cache) { 7937 caches = &legacy_intel_cpuid2_cache_info; 7938 } else if (env->enable_legacy_vendor_cache) { 7939 caches = &legacy_intel_cache_info; 7940 } else { 7941 caches = &env->cache_info; 7942 } 7943 7944 if (cpu->cache_info_passthrough) { 7945 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7946 break; 7947 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7948 *eax = *ebx = *ecx = *edx = 0; 7949 break; 7950 } 7951 encode_cache_cpuid2(cpu, caches, eax, ebx, ecx, edx); 7952 break; 7953 } 7954 case 4: { 7955 const CPUCaches *caches; 7956 7957 if (env->enable_legacy_vendor_cache) { 7958 caches = &legacy_intel_cache_info; 7959 } else { 7960 caches = &env->cache_info; 7961 } 7962 7963 /* cache info: needed for Core compatibility */ 7964 if (cpu->cache_info_passthrough) { 7965 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7966 /* 7967 * QEMU has its own number of cores/logical cpus, 7968 * set 24..14, 31..26 bit to configured values 7969 */ 7970 if (*eax & 31) { 7971 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 7972 7973 *eax &= ~0xFC000000; 7974 *eax |= MIN(max_core_ids_in_package(topo_info), 63) << 26; 7975 if (host_vcpus_per_cache > threads_per_pkg) { 7976 *eax &= ~0x3FFC000; 7977 7978 /* Share the cache at package level. */ 7979 *eax |= MIN(max_thread_ids_for_cache(topo_info, 7980 CPU_TOPOLOGY_LEVEL_SOCKET), 4095) << 14; 7981 } 7982 } 7983 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7984 *eax = *ebx = *ecx = *edx = 0; 7985 } else { 7986 *eax = 0; 7987 7988 switch (count) { 7989 case 0: /* L1 dcache info */ 7990 encode_cache_cpuid4(caches->l1d_cache, topo_info, 7991 eax, ebx, ecx, edx); 7992 if (!cpu->l1_cache_per_core) { 7993 *eax &= ~MAKE_64BIT_MASK(14, 12); 7994 } 7995 break; 7996 case 1: /* L1 icache info */ 7997 encode_cache_cpuid4(caches->l1i_cache, topo_info, 7998 eax, ebx, ecx, edx); 7999 if (!cpu->l1_cache_per_core) { 8000 *eax &= ~MAKE_64BIT_MASK(14, 12); 8001 } 8002 break; 8003 case 2: /* L2 cache info */ 8004 encode_cache_cpuid4(caches->l2_cache, topo_info, 8005 eax, ebx, ecx, edx); 8006 break; 8007 case 3: /* L3 cache info */ 8008 if (cpu->enable_l3_cache) { 8009 encode_cache_cpuid4(caches->l3_cache, topo_info, 8010 eax, ebx, ecx, edx); 8011 break; 8012 } 8013 /* fall through */ 8014 default: /* end of info */ 8015 *eax = *ebx = *ecx = *edx = 0; 8016 break; 8017 } 8018 } 8019 break; 8020 } 8021 case 5: 8022 /* MONITOR/MWAIT Leaf */ 8023 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 8024 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 8025 *ecx = cpu->mwait.ecx; /* flags */ 8026 *edx = cpu->mwait.edx; /* mwait substates */ 8027 break; 8028 case 6: 8029 /* Thermal and Power Leaf */ 8030 *eax = env->features[FEAT_6_EAX]; 8031 *ebx = 0; 8032 *ecx = 0; 8033 *edx = 0; 8034 break; 8035 case 7: 8036 /* Structured Extended Feature Flags Enumeration Leaf */ 8037 if (count == 0) { 8038 /* Maximum ECX value for sub-leaves */ 8039 *eax = env->cpuid_level_func7; 8040 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 8041 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 8042 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 8043 *ecx |= CPUID_7_0_ECX_OSPKE; 8044 } 8045 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 8046 } else if (count == 1) { 8047 *eax = env->features[FEAT_7_1_EAX]; 8048 *ecx = env->features[FEAT_7_1_ECX]; 8049 *edx = env->features[FEAT_7_1_EDX]; 8050 *ebx = 0; 8051 } else if (count == 2) { 8052 *edx = env->features[FEAT_7_2_EDX]; 8053 *eax = 0; 8054 *ebx = 0; 8055 *ecx = 0; 8056 } else { 8057 *eax = 0; 8058 *ebx = 0; 8059 *ecx = 0; 8060 *edx = 0; 8061 } 8062 break; 8063 case 9: 8064 /* Direct Cache Access Information Leaf */ 8065 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 8066 *ebx = 0; 8067 *ecx = 0; 8068 *edx = 0; 8069 break; 8070 case 0xA: 8071 /* Architectural Performance Monitoring Leaf */ 8072 if (cpu->enable_pmu) { 8073 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 8074 } else { 8075 *eax = 0; 8076 *ebx = 0; 8077 *ecx = 0; 8078 *edx = 0; 8079 } 8080 break; 8081 case 0xB: 8082 /* Extended Topology Enumeration Leaf */ 8083 if (!cpu->enable_cpuid_0xb) { 8084 *eax = *ebx = *ecx = *edx = 0; 8085 break; 8086 } 8087 8088 *ecx = count & 0xff; 8089 *edx = cpu->apic_id; 8090 8091 switch (count) { 8092 case 0: 8093 *eax = apicid_core_offset(topo_info); 8094 *ebx = topo_info->threads_per_core; 8095 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 8096 break; 8097 case 1: 8098 *eax = apicid_pkg_offset(topo_info); 8099 *ebx = threads_per_pkg; 8100 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 8101 break; 8102 default: 8103 *eax = 0; 8104 *ebx = 0; 8105 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 8106 } 8107 8108 assert(!(*eax & ~0x1f)); 8109 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 8110 break; 8111 case 0xD: { 8112 /* Processor Extended State */ 8113 *eax = 0; 8114 *ebx = 0; 8115 *ecx = 0; 8116 *edx = 0; 8117 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 8118 break; 8119 } 8120 8121 if (count == 0) { 8122 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 8123 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 8124 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 8125 /* 8126 * The initial value of xcr0 and ebx == 0, On host without kvm 8127 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 8128 * even through guest update xcr0, this will crash some legacy guest 8129 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 8130 */ 8131 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 8132 } else if (count == 1) { 8133 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 8134 x86_cpu_xsave_xss_components(cpu); 8135 8136 *eax = env->features[FEAT_XSAVE]; 8137 *ebx = xsave_area_size(xstate, true); 8138 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 8139 *edx = env->features[FEAT_XSAVE_XSS_HI]; 8140 if (kvm_enabled() && cpu->enable_pmu && 8141 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 8142 (*eax & CPUID_XSAVE_XSAVES)) { 8143 *ecx |= XSTATE_ARCH_LBR_MASK; 8144 } else { 8145 *ecx &= ~XSTATE_ARCH_LBR_MASK; 8146 } 8147 } else if (count == 0xf && cpu->enable_pmu 8148 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 8149 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 8150 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 8151 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 8152 8153 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 8154 *eax = esa->size; 8155 *ebx = esa->offset; 8156 *ecx = esa->ecx & 8157 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 8158 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 8159 *eax = esa->size; 8160 *ebx = 0; 8161 *ecx = 1; 8162 } 8163 } 8164 break; 8165 } 8166 case 0x12: 8167 #ifndef CONFIG_USER_ONLY 8168 if (!kvm_enabled() || 8169 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 8170 *eax = *ebx = *ecx = *edx = 0; 8171 break; 8172 } 8173 8174 /* 8175 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 8176 * the EPC properties, e.g. confidentiality and integrity, from the 8177 * host's first EPC section, i.e. assume there is one EPC section or 8178 * that all EPC sections have the same security properties. 8179 */ 8180 if (count > 1) { 8181 uint64_t epc_addr, epc_size; 8182 8183 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 8184 *eax = *ebx = *ecx = *edx = 0; 8185 break; 8186 } 8187 host_cpuid(index, 2, eax, ebx, ecx, edx); 8188 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 8189 *ebx = (uint32_t)(epc_addr >> 32); 8190 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 8191 *edx = (uint32_t)(epc_size >> 32); 8192 break; 8193 } 8194 8195 /* 8196 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 8197 * and KVM, i.e. QEMU cannot emulate features to override what KVM 8198 * supports. Features can be further restricted by userspace, but not 8199 * made more permissive. 8200 */ 8201 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 8202 8203 if (count == 0) { 8204 *eax &= env->features[FEAT_SGX_12_0_EAX]; 8205 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 8206 } else { 8207 *eax &= env->features[FEAT_SGX_12_1_EAX]; 8208 *ebx &= 0; /* ebx reserve */ 8209 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 8210 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 8211 8212 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 8213 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 8214 8215 /* Access to PROVISIONKEY requires additional credentials. */ 8216 if ((*eax & (1U << 4)) && 8217 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 8218 *eax &= ~(1U << 4); 8219 } 8220 } 8221 #endif 8222 break; 8223 case 0x14: { 8224 /* Intel Processor Trace Enumeration */ 8225 *eax = 0; 8226 *ebx = 0; 8227 *ecx = 0; 8228 *edx = 0; 8229 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 8230 !kvm_enabled()) { 8231 break; 8232 } 8233 8234 /* 8235 * If these are changed, they should stay in sync with 8236 * x86_cpu_filter_features(). 8237 */ 8238 if (count == 0) { 8239 *eax = INTEL_PT_MAX_SUBLEAF; 8240 *ebx = INTEL_PT_MINIMAL_EBX; 8241 *ecx = INTEL_PT_MINIMAL_ECX; 8242 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 8243 *ecx |= CPUID_14_0_ECX_LIP; 8244 } 8245 } else if (count == 1) { 8246 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 8247 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 8248 } 8249 break; 8250 } 8251 case 0x1C: 8252 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 8253 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 8254 *edx = 0; 8255 } 8256 break; 8257 case 0x1D: { 8258 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 8259 *eax = 0; 8260 *ebx = 0; 8261 *ecx = 0; 8262 *edx = 0; 8263 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 8264 break; 8265 } 8266 8267 if (count == 0) { 8268 /* Highest numbered palette subleaf */ 8269 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 8270 } else if (count == 1) { 8271 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 8272 (INTEL_AMX_BYTES_PER_TILE << 16); 8273 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 8274 *ecx = INTEL_AMX_TILE_MAX_ROWS; 8275 } 8276 break; 8277 } 8278 case 0x1E: { 8279 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 8280 *eax = 0; 8281 *ebx = 0; 8282 *ecx = 0; 8283 *edx = 0; 8284 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 8285 break; 8286 } 8287 8288 if (count == 0) { 8289 /* Highest numbered palette subleaf */ 8290 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 8291 } 8292 break; 8293 } 8294 case 0x1F: 8295 /* V2 Extended Topology Enumeration Leaf */ 8296 if (!x86_has_cpuid_0x1f(cpu)) { 8297 *eax = *ebx = *ecx = *edx = 0; 8298 break; 8299 } 8300 8301 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 8302 break; 8303 case 0x24: { 8304 *eax = 0; 8305 *ebx = 0; 8306 *ecx = 0; 8307 *edx = 0; 8308 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 8309 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 8310 } 8311 break; 8312 } 8313 case 0x40000000: 8314 /* 8315 * CPUID code in kvm_arch_init_vcpu() ignores stuff 8316 * set here, but we restrict to TCG none the less. 8317 */ 8318 if (tcg_enabled() && cpu->expose_tcg) { 8319 memcpy(signature, "TCGTCGTCGTCG", 12); 8320 *eax = 0x40000001; 8321 *ebx = signature[0]; 8322 *ecx = signature[1]; 8323 *edx = signature[2]; 8324 } else { 8325 *eax = 0; 8326 *ebx = 0; 8327 *ecx = 0; 8328 *edx = 0; 8329 } 8330 break; 8331 case 0x40000001: 8332 *eax = 0; 8333 *ebx = 0; 8334 *ecx = 0; 8335 *edx = 0; 8336 break; 8337 case 0x80000000: 8338 *eax = env->cpuid_xlevel; 8339 8340 if (cpu->vendor_cpuid_only_v2 && 8341 (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 8342 *ebx = *ecx = *edx = 0; 8343 } else { 8344 *ebx = env->cpuid_vendor1; 8345 *edx = env->cpuid_vendor2; 8346 *ecx = env->cpuid_vendor3; 8347 } 8348 break; 8349 case 0x80000001: 8350 *eax = env->cpuid_version; 8351 *ebx = 0; 8352 *ecx = env->features[FEAT_8000_0001_ECX]; 8353 *edx = env->features[FEAT_8000_0001_EDX]; 8354 8355 if (tcg_enabled() && IS_INTEL_CPU(env) && 8356 !(env->hflags & HF_LMA_MASK)) { 8357 *edx &= ~CPUID_EXT2_SYSCALL; 8358 } 8359 break; 8360 case 0x80000002: 8361 case 0x80000003: 8362 case 0x80000004: 8363 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 8364 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 8365 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 8366 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 8367 break; 8368 case 0x80000005: { 8369 /* cache info (L1 cache/TLB Associativity Field) */ 8370 const CPUCaches *caches; 8371 8372 if (env->enable_legacy_vendor_cache) { 8373 caches = &legacy_amd_cache_info; 8374 } else { 8375 caches = &env->cache_info; 8376 } 8377 8378 if (cpu->cache_info_passthrough) { 8379 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 8380 break; 8381 } 8382 8383 if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { 8384 *eax = *ebx = *ecx = *edx = 0; 8385 break; 8386 } 8387 8388 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 8389 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 8390 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 8391 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 8392 *ecx = encode_cache_cpuid80000005(caches->l1d_cache); 8393 *edx = encode_cache_cpuid80000005(caches->l1i_cache); 8394 break; 8395 } 8396 case 0x80000006: { /* cache info (L2 cache/TLB/L3 cache) */ 8397 const CPUCaches *caches; 8398 8399 if (env->enable_legacy_vendor_cache) { 8400 caches = &legacy_amd_cache_info; 8401 } else { 8402 caches = &env->cache_info; 8403 } 8404 8405 if (cpu->cache_info_passthrough) { 8406 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 8407 break; 8408 } 8409 8410 if (cpu->vendor_cpuid_only_v2 && 8411 (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 8412 *eax = *ebx = 0; 8413 encode_cache_cpuid80000006(caches->l2_cache, 8414 NULL, ecx, edx); 8415 break; 8416 } 8417 8418 *eax = (X86_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 8419 (L2_DTLB_2M_ENTRIES << 16) | 8420 (X86_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 8421 (L2_ITLB_2M_ENTRIES); 8422 *ebx = (X86_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 8423 (L2_DTLB_4K_ENTRIES << 16) | 8424 (X86_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 8425 (L2_ITLB_4K_ENTRIES); 8426 8427 encode_cache_cpuid80000006(caches->l2_cache, 8428 cpu->enable_l3_cache ? 8429 caches->l3_cache : NULL, 8430 ecx, edx); 8431 break; 8432 } 8433 case 0x80000007: 8434 *eax = 0; 8435 if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { 8436 *ebx = 0; 8437 } else { 8438 *ebx = env->features[FEAT_8000_0007_EBX]; 8439 } 8440 *ecx = 0; 8441 *edx = env->features[FEAT_8000_0007_EDX]; 8442 break; 8443 case 0x80000008: 8444 /* virtual & phys address size in low 2 bytes. */ 8445 *eax = cpu->phys_bits; 8446 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8447 /* 64 bit processor */ 8448 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 8449 *eax |= (cpu->guest_phys_bits << 16); 8450 } 8451 *ebx = env->features[FEAT_8000_0008_EBX]; 8452 8453 /* 8454 * Don't emulate Bits [7:0] & Bits [15:12] for Intel/Zhaoxin, since 8455 * they're using 0x1f leaf. 8456 */ 8457 if (cpu->vendor_cpuid_only_v2 && 8458 (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 8459 *ecx = *edx = 0; 8460 break; 8461 } 8462 8463 if (threads_per_pkg > 1) { 8464 /* 8465 * Bits 15:12 is "The number of bits in the initial 8466 * Core::X86::Apic::ApicId[ApicId] value that indicate 8467 * thread ID within a package". 8468 * Bits 7:0 is "The number of threads in the package is NC+1" 8469 */ 8470 *ecx = (apicid_pkg_offset(topo_info) << 12) | 8471 (threads_per_pkg - 1); 8472 } else { 8473 *ecx = 0; 8474 } 8475 *edx = 0; 8476 break; 8477 case 0x8000000A: 8478 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 8479 *eax = 0x00000001; /* SVM Revision */ 8480 *ebx = 0x00000010; /* nr of ASIDs */ 8481 *ecx = 0; 8482 *edx = env->features[FEAT_SVM]; /* optional features */ 8483 } else { 8484 *eax = 0; 8485 *ebx = 0; 8486 *ecx = 0; 8487 *edx = 0; 8488 } 8489 break; 8490 case 0x8000001D: 8491 *eax = 0; 8492 if (cpu->cache_info_passthrough) { 8493 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 8494 break; 8495 } 8496 switch (count) { 8497 case 0: /* L1 dcache info */ 8498 encode_cache_cpuid8000001d(env->cache_info.l1d_cache, 8499 topo_info, eax, ebx, ecx, edx); 8500 break; 8501 case 1: /* L1 icache info */ 8502 encode_cache_cpuid8000001d(env->cache_info.l1i_cache, 8503 topo_info, eax, ebx, ecx, edx); 8504 break; 8505 case 2: /* L2 cache info */ 8506 encode_cache_cpuid8000001d(env->cache_info.l2_cache, 8507 topo_info, eax, ebx, ecx, edx); 8508 break; 8509 case 3: /* L3 cache info */ 8510 encode_cache_cpuid8000001d(env->cache_info.l3_cache, 8511 topo_info, eax, ebx, ecx, edx); 8512 break; 8513 default: /* end of info */ 8514 *eax = *ebx = *ecx = *edx = 0; 8515 break; 8516 } 8517 if (cpu->amd_topoext_features_only) { 8518 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 8519 } 8520 break; 8521 case 0x8000001E: 8522 if (cpu->core_id <= 255) { 8523 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 8524 } else { 8525 *eax = 0; 8526 *ebx = 0; 8527 *ecx = 0; 8528 *edx = 0; 8529 } 8530 break; 8531 case 0x8000001F: 8532 *eax = *ebx = *ecx = *edx = 0; 8533 if (sev_enabled()) { 8534 *eax = 0x2; 8535 *eax |= sev_es_enabled() ? 0x8 : 0; 8536 *eax |= sev_snp_enabled() ? 0x10 : 0; 8537 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 8538 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 8539 } 8540 break; 8541 case 0x80000021: 8542 *eax = *ebx = *ecx = *edx = 0; 8543 *eax = env->features[FEAT_8000_0021_EAX]; 8544 *ebx = env->features[FEAT_8000_0021_EBX]; 8545 *ecx = env->features[FEAT_8000_0021_ECX]; 8546 break; 8547 case 0x80000022: 8548 *eax = *ebx = *ecx = *edx = 0; 8549 /* AMD Extended Performance Monitoring and Debug */ 8550 if (kvm_enabled() && cpu->enable_pmu && 8551 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 8552 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 8553 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 8554 R_EBX) & 0xf; 8555 } 8556 break; 8557 case 0xC0000000: 8558 *eax = env->cpuid_xlevel2; 8559 *ebx = 0; 8560 *ecx = 0; 8561 *edx = 0; 8562 break; 8563 case 0xC0000001: 8564 /* Support for VIA CPU's CPUID instruction */ 8565 *eax = env->cpuid_version; 8566 *ebx = 0; 8567 *ecx = 0; 8568 *edx = env->features[FEAT_C000_0001_EDX]; 8569 break; 8570 case 0xC0000002: 8571 case 0xC0000003: 8572 case 0xC0000004: 8573 /* Reserved for the future, and now filled with zero */ 8574 *eax = 0; 8575 *ebx = 0; 8576 *ecx = 0; 8577 *edx = 0; 8578 break; 8579 default: 8580 /* reserved values: zero */ 8581 *eax = 0; 8582 *ebx = 0; 8583 *ecx = 0; 8584 *edx = 0; 8585 break; 8586 } 8587 } 8588 8589 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 8590 { 8591 #ifndef CONFIG_USER_ONLY 8592 /* Those default values are defined in Skylake HW */ 8593 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 8594 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 8595 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 8596 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 8597 #endif 8598 } 8599 8600 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 8601 { 8602 if (!esa->size) { 8603 return false; 8604 } 8605 8606 if (env->features[esa->feature] & esa->bits) { 8607 return true; 8608 } 8609 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 8610 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 8611 return true; 8612 } 8613 8614 return false; 8615 } 8616 8617 static void x86_cpu_reset_hold(Object *obj, ResetType type) 8618 { 8619 CPUState *cs = CPU(obj); 8620 X86CPU *cpu = X86_CPU(cs); 8621 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8622 CPUX86State *env = &cpu->env; 8623 target_ulong cr4; 8624 uint64_t xcr0; 8625 int i; 8626 8627 if (xcc->parent_phases.hold) { 8628 xcc->parent_phases.hold(obj, type); 8629 } 8630 8631 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 8632 8633 if (tcg_enabled()) { 8634 cpu_init_fp_statuses(env); 8635 } 8636 8637 env->old_exception = -1; 8638 8639 /* init to reset state */ 8640 env->int_ctl = 0; 8641 env->hflags2 |= HF2_GIF_MASK; 8642 env->hflags2 |= HF2_VGIF_MASK; 8643 env->hflags &= ~HF_GUEST_MASK; 8644 8645 cpu_x86_update_cr0(env, 0x60000010); 8646 env->a20_mask = ~0x0; 8647 env->smbase = 0x30000; 8648 env->msr_smi_count = 0; 8649 8650 env->idt.limit = 0xffff; 8651 env->gdt.limit = 0xffff; 8652 #if defined(CONFIG_USER_ONLY) 8653 env->ldt.limit = 0; 8654 #else 8655 env->ldt.limit = 0xffff; 8656 #endif 8657 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 8658 env->tr.limit = 0xffff; 8659 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 8660 8661 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 8662 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 8663 DESC_R_MASK | DESC_A_MASK); 8664 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 8665 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8666 DESC_A_MASK); 8667 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 8668 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8669 DESC_A_MASK); 8670 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 8671 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8672 DESC_A_MASK); 8673 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 8674 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8675 DESC_A_MASK); 8676 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 8677 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8678 DESC_A_MASK); 8679 8680 env->eip = 0xfff0; 8681 env->regs[R_EDX] = env->cpuid_version; 8682 8683 env->eflags = 0x2; 8684 8685 /* FPU init */ 8686 for (i = 0; i < 8; i++) { 8687 env->fptags[i] = 1; 8688 } 8689 cpu_set_fpuc(env, 0x37f); 8690 8691 env->mxcsr = 0x1f80; 8692 /* All units are in INIT state. */ 8693 env->xstate_bv = 0; 8694 8695 env->pat = 0x0007040600070406ULL; 8696 8697 if (kvm_enabled()) { 8698 /* 8699 * KVM handles TSC = 0 specially and thinks we are hot-plugging 8700 * a new CPU, use 1 instead to force a reset. 8701 */ 8702 if (env->tsc != 0) { 8703 env->tsc = 1; 8704 } 8705 } else { 8706 env->tsc = 0; 8707 } 8708 8709 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 8710 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 8711 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 8712 } 8713 8714 memset(env->dr, 0, sizeof(env->dr)); 8715 env->dr[6] = DR6_FIXED_1; 8716 env->dr[7] = DR7_FIXED_1; 8717 cpu_breakpoint_remove_all(cs, BP_CPU); 8718 cpu_watchpoint_remove_all(cs, BP_CPU); 8719 8720 cr4 = 0; 8721 xcr0 = XSTATE_FP_MASK; 8722 8723 #ifdef CONFIG_USER_ONLY 8724 /* Enable all the features for user-mode. */ 8725 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 8726 xcr0 |= XSTATE_SSE_MASK; 8727 } 8728 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8729 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8730 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 8731 continue; 8732 } 8733 if (cpuid_has_xsave_feature(env, esa)) { 8734 xcr0 |= 1ull << i; 8735 } 8736 } 8737 8738 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 8739 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 8740 } 8741 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 8742 cr4 |= CR4_FSGSBASE_MASK; 8743 } 8744 #endif 8745 8746 env->xcr0 = xcr0; 8747 cpu_x86_update_cr4(env, cr4); 8748 8749 /* 8750 * SDM 11.11.5 requires: 8751 * - IA32_MTRR_DEF_TYPE MSR.E = 0 8752 * - IA32_MTRR_PHYSMASKn.V = 0 8753 * All other bits are undefined. For simplification, zero it all. 8754 */ 8755 env->mtrr_deftype = 0; 8756 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 8757 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 8758 8759 env->interrupt_injected = -1; 8760 env->exception_nr = -1; 8761 env->exception_pending = 0; 8762 env->exception_injected = 0; 8763 env->exception_has_payload = false; 8764 env->exception_payload = 0; 8765 env->nmi_injected = false; 8766 env->triple_fault_pending = false; 8767 #if !defined(CONFIG_USER_ONLY) 8768 /* We hard-wire the BSP to the first CPU. */ 8769 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 8770 8771 cs->halted = !cpu_is_bsp(cpu); 8772 8773 #if defined(CONFIG_IGVM) 8774 if (cpu_is_bsp(cpu)) { 8775 qigvm_x86_bsp_reset(env); 8776 } 8777 #endif 8778 8779 if (kvm_enabled()) { 8780 kvm_arch_reset_vcpu(cpu); 8781 } 8782 8783 x86_cpu_set_sgxlepubkeyhash(env); 8784 8785 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 8786 8787 #endif 8788 } 8789 8790 void x86_cpu_after_reset(X86CPU *cpu) 8791 { 8792 #ifndef CONFIG_USER_ONLY 8793 if (kvm_enabled()) { 8794 kvm_arch_after_reset_vcpu(cpu); 8795 } 8796 8797 if (cpu->apic_state) { 8798 device_cold_reset(DEVICE(cpu->apic_state)); 8799 } 8800 #endif 8801 } 8802 8803 static void mce_init(X86CPU *cpu) 8804 { 8805 CPUX86State *cenv = &cpu->env; 8806 unsigned int bank; 8807 8808 if (x86_cpu_family(cenv->cpuid_version) >= 6 8809 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 8810 (CPUID_MCE | CPUID_MCA)) { 8811 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 8812 (cpu->enable_lmce ? MCG_LMCE_P : 0); 8813 cenv->mcg_ctl = ~(uint64_t)0; 8814 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 8815 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 8816 } 8817 } 8818 } 8819 8820 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 8821 { 8822 if (*min < value) { 8823 *min = value; 8824 } 8825 } 8826 8827 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 8828 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 8829 { 8830 CPUX86State *env = &cpu->env; 8831 FeatureWordInfo *fi = &feature_word_info[w]; 8832 uint32_t eax = fi->cpuid.eax; 8833 uint32_t region = eax & 0xF0000000; 8834 8835 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 8836 if (!env->features[w]) { 8837 return; 8838 } 8839 8840 switch (region) { 8841 case 0x00000000: 8842 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 8843 break; 8844 case 0x80000000: 8845 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 8846 break; 8847 case 0xC0000000: 8848 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 8849 break; 8850 } 8851 8852 if (eax == 7) { 8853 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 8854 fi->cpuid.ecx); 8855 } 8856 } 8857 8858 /* Calculate XSAVE components based on the configured CPU feature flags */ 8859 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 8860 { 8861 CPUX86State *env = &cpu->env; 8862 int i; 8863 uint64_t mask; 8864 static bool request_perm; 8865 8866 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 8867 env->features[FEAT_XSAVE_XCR0_LO] = 0; 8868 env->features[FEAT_XSAVE_XCR0_HI] = 0; 8869 env->features[FEAT_XSAVE_XSS_LO] = 0; 8870 env->features[FEAT_XSAVE_XSS_HI] = 0; 8871 return; 8872 } 8873 8874 mask = 0; 8875 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8876 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8877 if (cpuid_has_xsave_feature(env, esa)) { 8878 mask |= (1ULL << i); 8879 } 8880 } 8881 8882 /* Only request permission for first vcpu */ 8883 if (kvm_enabled() && !request_perm) { 8884 kvm_request_xsave_components(cpu, mask); 8885 request_perm = true; 8886 } 8887 8888 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 8889 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 8890 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 8891 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 8892 } 8893 8894 /***** Steps involved on loading and filtering CPUID data 8895 * 8896 * When initializing and realizing a CPU object, the steps 8897 * involved in setting up CPUID data are: 8898 * 8899 * 1) Loading CPU model definition (X86CPUDefinition). This is 8900 * implemented by x86_cpu_load_model() and should be completely 8901 * transparent, as it is done automatically by instance_init. 8902 * No code should need to look at X86CPUDefinition structs 8903 * outside instance_init. 8904 * 8905 * 2) CPU expansion. This is done by realize before CPUID 8906 * filtering, and will make sure host/accelerator data is 8907 * loaded for CPU models that depend on host capabilities 8908 * (e.g. "host"). Done by x86_cpu_expand_features(). 8909 * 8910 * 3) CPUID filtering. This initializes extra data related to 8911 * CPUID, and checks if the host supports all capabilities 8912 * required by the CPU. Runnability of a CPU model is 8913 * determined at this step. Done by x86_cpu_filter_features(). 8914 * 8915 * Some operations don't require all steps to be performed. 8916 * More precisely: 8917 * 8918 * - CPU instance creation (instance_init) will run only CPU 8919 * model loading. CPU expansion can't run at instance_init-time 8920 * because host/accelerator data may be not available yet. 8921 * - CPU realization will perform both CPU model expansion and CPUID 8922 * filtering, and return an error in case one of them fails. 8923 * - query-cpu-definitions needs to run all 3 steps. It needs 8924 * to run CPUID filtering, as the 'unavailable-features' 8925 * field is set based on the filtering results. 8926 * - The query-cpu-model-expansion QMP command only needs to run 8927 * CPU model loading and CPU expansion. It should not filter 8928 * any CPUID data based on host capabilities. 8929 */ 8930 8931 /* Expand CPU configuration data, based on configured features 8932 * and host/accelerator capabilities when appropriate. 8933 */ 8934 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 8935 { 8936 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 8937 CPUX86State *env = &cpu->env; 8938 FeatureWord w; 8939 int i; 8940 GList *l; 8941 8942 for (l = plus_features; l; l = l->next) { 8943 const char *prop = l->data; 8944 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 8945 return; 8946 } 8947 } 8948 8949 for (l = minus_features; l; l = l->next) { 8950 const char *prop = l->data; 8951 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 8952 return; 8953 } 8954 } 8955 8956 /* TODO: Now xcc->max_features doesn't overwrite features 8957 * set using QOM properties, and we can convert 8958 * plus_features & minus_features to global properties 8959 * inside x86_cpu_parse_featurestr() too. 8960 */ 8961 if (xcc->max_features) { 8962 for (w = 0; w < FEATURE_WORDS; w++) { 8963 /* Override only features that weren't set explicitly 8964 * by the user. 8965 */ 8966 env->features[w] |= 8967 x86_cpu_get_supported_feature_word(cpu, w) & 8968 ~env->user_features[w] & 8969 ~feature_word_info[w].no_autoenable_flags; 8970 } 8971 8972 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 8973 uint32_t eax, ebx, ecx, edx; 8974 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 8975 env->avx10_version = ebx & 0xff; 8976 } 8977 } 8978 8979 if (x86_threads_per_pkg(&env->topo_info) > 1) { 8980 env->features[FEAT_1_EDX] |= CPUID_HT; 8981 8982 /* 8983 * The Linux kernel checks for the CMPLegacy bit and 8984 * discards multiple thread information if it is set. 8985 * So don't set it here for Intel (and other processors 8986 * following Intel's behavior) to make Linux guests happy. 8987 */ 8988 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 8989 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 8990 } 8991 } 8992 8993 if (!cpu->pdcm_on_even_without_pmu) { 8994 /* PDCM is fixed1 bit for TDX */ 8995 if (!cpu->enable_pmu && !is_tdx_vm()) { 8996 env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; 8997 } 8998 } 8999 9000 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 9001 FeatureDep *d = &feature_dependencies[i]; 9002 if (!(env->features[d->from.index] & d->from.mask)) { 9003 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 9004 9005 /* Not an error unless the dependent feature was added explicitly. */ 9006 mark_unavailable_features(cpu, d->to.index, 9007 unavailable_features & env->user_features[d->to.index], 9008 "This feature depends on other features that were not requested"); 9009 9010 env->features[d->to.index] &= ~unavailable_features; 9011 } 9012 } 9013 9014 if (!kvm_enabled() || !cpu->expose_kvm) { 9015 env->features[FEAT_KVM] = 0; 9016 } 9017 9018 x86_cpu_enable_xsave_components(cpu); 9019 9020 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 9021 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 9022 if (cpu->full_cpuid_auto_level) { 9023 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 9024 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 9025 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 9026 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 9027 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 9028 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); 9029 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 9030 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 9031 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 9032 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 9033 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 9034 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 9035 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 9036 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 9037 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 9038 9039 /* Intel Processor Trace requires CPUID[0x14] */ 9040 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 9041 if (cpu->intel_pt_auto_level) { 9042 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 9043 } else if (cpu->env.cpuid_min_level < 0x14) { 9044 mark_unavailable_features(cpu, FEAT_7_0_EBX, 9045 CPUID_7_0_EBX_INTEL_PT, 9046 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 9047 } 9048 } 9049 9050 /* 9051 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 9052 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 9053 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 9054 * cpu->vendor_cpuid_only has been unset for compatibility with older 9055 * machine types. 9056 */ 9057 if (x86_has_cpuid_0x1f(cpu) && 9058 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 9059 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 9060 } 9061 9062 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 9063 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 9064 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 9065 } 9066 9067 /* SVM requires CPUID[0x8000000A] */ 9068 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 9069 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 9070 } 9071 9072 /* SEV requires CPUID[0x8000001F] */ 9073 if (sev_enabled()) { 9074 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 9075 } 9076 9077 if (env->features[FEAT_8000_0021_EAX]) { 9078 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 9079 } 9080 9081 /* SGX requires CPUID[0x12] for EPC enumeration */ 9082 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 9083 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 9084 } 9085 } 9086 9087 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 9088 if (env->cpuid_level_func7 == UINT32_MAX) { 9089 env->cpuid_level_func7 = env->cpuid_min_level_func7; 9090 } 9091 if (env->cpuid_level == UINT32_MAX) { 9092 env->cpuid_level = env->cpuid_min_level; 9093 } 9094 if (env->cpuid_xlevel == UINT32_MAX) { 9095 env->cpuid_xlevel = env->cpuid_min_xlevel; 9096 } 9097 if (env->cpuid_xlevel2 == UINT32_MAX) { 9098 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 9099 } 9100 9101 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 9102 return; 9103 } 9104 } 9105 9106 /* 9107 * Finishes initialization of CPUID data, filters CPU feature 9108 * words based on host availability of each feature. 9109 * 9110 * Returns: true if any flag is not supported by the host, false otherwise. 9111 */ 9112 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 9113 { 9114 CPUX86State *env = &cpu->env; 9115 FeatureWord w; 9116 const char *prefix = NULL; 9117 bool have_filtered_features; 9118 9119 uint32_t eax_0, ebx_0, ecx_0, edx_0; 9120 uint32_t eax_1, ebx_1, ecx_1, edx_1; 9121 9122 if (verbose) { 9123 prefix = accel_uses_host_cpuid() 9124 ? "host doesn't support requested feature" 9125 : "TCG doesn't support requested feature"; 9126 } 9127 9128 for (w = 0; w < FEATURE_WORDS; w++) { 9129 uint64_t host_feat = 9130 x86_cpu_get_supported_feature_word(NULL, w); 9131 uint64_t requested_features = env->features[w]; 9132 uint64_t unavailable_features = requested_features & ~host_feat; 9133 mark_unavailable_features(cpu, w, unavailable_features, prefix); 9134 } 9135 9136 /* 9137 * Check that KVM actually allows the processor tracing features that 9138 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 9139 */ 9140 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 9141 kvm_enabled()) { 9142 x86_cpu_get_supported_cpuid(0x14, 0, 9143 &eax_0, &ebx_0, &ecx_0, &edx_0); 9144 x86_cpu_get_supported_cpuid(0x14, 1, 9145 &eax_1, &ebx_1, &ecx_1, &edx_1); 9146 9147 if (!eax_0 || 9148 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 9149 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 9150 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 9151 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 9152 INTEL_PT_ADDR_RANGES_NUM) || 9153 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 9154 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 9155 ((ecx_0 & CPUID_14_0_ECX_LIP) != 9156 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 9157 /* 9158 * Processor Trace capabilities aren't configurable, so if the 9159 * host can't emulate the capabilities we report on 9160 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 9161 */ 9162 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 9163 } 9164 } 9165 9166 have_filtered_features = x86_cpu_have_filtered_features(cpu); 9167 9168 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 9169 x86_cpu_get_supported_cpuid(0x24, 0, 9170 &eax_0, &ebx_0, &ecx_0, &edx_0); 9171 uint8_t version = ebx_0 & 0xff; 9172 9173 if (version < env->avx10_version) { 9174 if (prefix) { 9175 warn_report("%s: avx10.%d. Adjust to avx10.%d", 9176 prefix, env->avx10_version, version); 9177 } 9178 env->avx10_version = version; 9179 have_filtered_features = true; 9180 } 9181 } else if (env->avx10_version) { 9182 if (prefix) { 9183 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 9184 } 9185 have_filtered_features = true; 9186 } 9187 9188 return have_filtered_features; 9189 } 9190 9191 static void x86_cpu_hyperv_realize(X86CPU *cpu) 9192 { 9193 size_t len; 9194 9195 /* Hyper-V vendor id */ 9196 if (!cpu->hyperv_vendor) { 9197 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 9198 &error_abort); 9199 } 9200 len = strlen(cpu->hyperv_vendor); 9201 if (len > 12) { 9202 warn_report("hv-vendor-id truncated to 12 characters"); 9203 len = 12; 9204 } 9205 memset(cpu->hyperv_vendor_id, 0, 12); 9206 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 9207 9208 /* 'Hv#1' interface identification*/ 9209 cpu->hyperv_interface_id[0] = 0x31237648; 9210 cpu->hyperv_interface_id[1] = 0; 9211 cpu->hyperv_interface_id[2] = 0; 9212 cpu->hyperv_interface_id[3] = 0; 9213 9214 /* Hypervisor implementation limits */ 9215 cpu->hyperv_limits[0] = 64; 9216 cpu->hyperv_limits[1] = 0; 9217 cpu->hyperv_limits[2] = 0; 9218 } 9219 9220 #ifndef CONFIG_USER_ONLY 9221 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 9222 Error **errp) 9223 { 9224 CPUX86State *env = &cpu->env; 9225 CpuTopologyLevel level; 9226 9227 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 9228 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9229 env->cache_info.l1d_cache->share_level = level; 9230 } else { 9231 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 9232 env->cache_info.l1d_cache->share_level); 9233 } 9234 9235 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 9236 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9237 env->cache_info.l1i_cache->share_level = level; 9238 } else { 9239 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 9240 env->cache_info.l1i_cache->share_level); 9241 } 9242 9243 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 9244 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9245 env->cache_info.l2_cache->share_level = level; 9246 } else { 9247 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 9248 env->cache_info.l2_cache->share_level); 9249 } 9250 9251 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 9252 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9253 env->cache_info.l3_cache->share_level = level; 9254 } else { 9255 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 9256 env->cache_info.l3_cache->share_level); 9257 } 9258 9259 if (!machine_check_smp_cache(ms, errp)) { 9260 return false; 9261 } 9262 return true; 9263 } 9264 #endif 9265 9266 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 9267 { 9268 CPUState *cs = CPU(dev); 9269 X86CPU *cpu = X86_CPU(dev); 9270 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 9271 CPUX86State *env = &cpu->env; 9272 Error *local_err = NULL; 9273 unsigned requested_lbr_fmt; 9274 9275 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 9276 /* Use pc-relative instructions in system-mode */ 9277 tcg_cflags_set(cs, CF_PCREL); 9278 #endif 9279 9280 /* 9281 * x-vendor-cpuid-only and v2 should be initernal only. But 9282 * QEMU doesn't support "internal" property. 9283 */ 9284 if (!cpu->vendor_cpuid_only && cpu->vendor_cpuid_only_v2) { 9285 error_setg(errp, "x-vendor-cpuid-only-v2 property " 9286 "depends on x-vendor-cpuid-only"); 9287 return; 9288 } 9289 9290 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 9291 error_setg(errp, "apic-id property was not initialized properly"); 9292 return; 9293 } 9294 9295 /* 9296 * Process Hyper-V enlightenments. 9297 * Note: this currently has to happen before the expansion of CPU features. 9298 */ 9299 x86_cpu_hyperv_realize(cpu); 9300 9301 x86_cpu_expand_features(cpu, &local_err); 9302 if (local_err) { 9303 goto out; 9304 } 9305 9306 /* 9307 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 9308 * with user-provided setting. 9309 */ 9310 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 9311 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 9312 error_setg(errp, "invalid lbr-fmt"); 9313 return; 9314 } 9315 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 9316 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 9317 } 9318 9319 /* 9320 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 9321 * 3)vPMU LBR format matches that of host setting. 9322 */ 9323 requested_lbr_fmt = 9324 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 9325 if (requested_lbr_fmt && kvm_enabled()) { 9326 uint64_t host_perf_cap = 9327 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 9328 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 9329 9330 if (!cpu->enable_pmu) { 9331 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 9332 return; 9333 } 9334 if (requested_lbr_fmt != host_lbr_fmt) { 9335 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 9336 "the host value (0x%x).", 9337 requested_lbr_fmt, host_lbr_fmt); 9338 return; 9339 } 9340 } 9341 9342 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 9343 if (cpu->enforce_cpuid) { 9344 error_setg(&local_err, 9345 accel_uses_host_cpuid() ? 9346 "Host doesn't support requested features" : 9347 "TCG doesn't support requested features"); 9348 goto out; 9349 } 9350 } 9351 9352 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 9353 * CPUID[1].EDX. 9354 */ 9355 if (IS_AMD_CPU(env)) { 9356 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 9357 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 9358 & CPUID_EXT2_AMD_ALIASES); 9359 } 9360 9361 x86_cpu_set_sgxlepubkeyhash(env); 9362 9363 /* 9364 * note: the call to the framework needs to happen after feature expansion, 9365 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 9366 * These may be set by the accel-specific code, 9367 * and the results are subsequently checked / assumed in this function. 9368 */ 9369 cpu_exec_realizefn(cs, &local_err); 9370 if (local_err != NULL) { 9371 error_propagate(errp, local_err); 9372 return; 9373 } 9374 9375 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 9376 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 9377 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 9378 goto out; 9379 } 9380 9381 if (cpu->guest_phys_bits == -1) { 9382 /* 9383 * If it was not set by the user, or by the accelerator via 9384 * cpu_exec_realizefn, clear. 9385 */ 9386 cpu->guest_phys_bits = 0; 9387 } 9388 9389 if (cpu->ucode_rev == 0) { 9390 /* 9391 * The default is the same as KVM's. Note that this check 9392 * needs to happen after the evenual setting of ucode_rev in 9393 * accel-specific code in cpu_exec_realizefn. 9394 */ 9395 if (IS_AMD_CPU(env)) { 9396 cpu->ucode_rev = 0x01000065; 9397 } else { 9398 cpu->ucode_rev = 0x100000000ULL; 9399 } 9400 } 9401 9402 /* 9403 * mwait extended info: needed for Core compatibility 9404 * We always wake on interrupt even if host does not have the capability. 9405 * 9406 * requires the accel-specific code in cpu_exec_realizefn to 9407 * have already acquired the CPUID data into cpu->mwait. 9408 */ 9409 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 9410 9411 /* 9412 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 9413 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 9414 * based on inputs (sockets,cores,threads), it is still better to give 9415 * users a warning. 9416 */ 9417 if (IS_AMD_CPU(env) && 9418 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 9419 env->topo_info.threads_per_core > 1) { 9420 warn_report_once("This family of AMD CPU doesn't support " 9421 "hyperthreading(%d). Please configure -smp " 9422 "options properly or try enabling topoext " 9423 "feature.", env->topo_info.threads_per_core); 9424 } 9425 9426 /* For 64bit systems think about the number of physical bits to present. 9427 * ideally this should be the same as the host; anything other than matching 9428 * the host can cause incorrect guest behaviour. 9429 * QEMU used to pick the magic value of 40 bits that corresponds to 9430 * consumer AMD devices but nothing else. 9431 * 9432 * Note that this code assumes features expansion has already been done 9433 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 9434 * phys_bits adjustments to match the host have been already done in 9435 * accel-specific code in cpu_exec_realizefn. 9436 */ 9437 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 9438 if (cpu->phys_bits && 9439 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 9440 cpu->phys_bits < 32)) { 9441 error_setg(errp, "phys-bits should be between 32 and %u " 9442 " (but is %u)", 9443 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 9444 return; 9445 } 9446 /* 9447 * 0 means it was not explicitly set by the user (or by machine 9448 * compat_props or by the host code in host-cpu.c). 9449 * In this case, the default is the value used by TCG (40). 9450 */ 9451 if (cpu->phys_bits == 0) { 9452 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 9453 } 9454 if (cpu->guest_phys_bits && 9455 (cpu->guest_phys_bits > cpu->phys_bits || 9456 cpu->guest_phys_bits < 32)) { 9457 error_setg(errp, "guest-phys-bits should be between 32 and %u " 9458 " (but is %u)", 9459 cpu->phys_bits, cpu->guest_phys_bits); 9460 return; 9461 } 9462 } else { 9463 /* For 32 bit systems don't use the user set value, but keep 9464 * phys_bits consistent with what we tell the guest. 9465 */ 9466 if (cpu->phys_bits != 0) { 9467 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 9468 return; 9469 } 9470 if (cpu->guest_phys_bits != 0) { 9471 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 9472 return; 9473 } 9474 9475 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 9476 cpu->phys_bits = 36; 9477 } else { 9478 cpu->phys_bits = 32; 9479 } 9480 } 9481 9482 /* Cache information initialization */ 9483 if (!cpu->legacy_cache) { 9484 const CPUCaches *cache_info = 9485 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 9486 9487 if (!xcc->model || !cache_info) { 9488 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 9489 error_setg(errp, 9490 "CPU model '%s' doesn't support legacy-cache=off", name); 9491 return; 9492 } 9493 env->cache_info = *cache_info; 9494 } else { 9495 /* Build legacy cache information */ 9496 if (!cpu->consistent_cache) { 9497 env->enable_legacy_cpuid2_cache = true; 9498 } 9499 9500 if (!cpu->vendor_cpuid_only_v2) { 9501 env->enable_legacy_vendor_cache = true; 9502 } 9503 9504 if (IS_AMD_CPU(env)) { 9505 env->cache_info = legacy_amd_cache_info; 9506 } else { 9507 env->cache_info = legacy_intel_cache_info; 9508 } 9509 } 9510 9511 #ifndef CONFIG_USER_ONLY 9512 MachineState *ms = MACHINE(qdev_get_machine()); 9513 MachineClass *mc = MACHINE_GET_CLASS(ms); 9514 9515 if (mc->smp_props.has_caches) { 9516 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 9517 return; 9518 } 9519 } 9520 9521 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 9522 9523 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 9524 x86_cpu_apic_create(cpu, &local_err); 9525 if (local_err != NULL) { 9526 goto out; 9527 } 9528 } 9529 #endif 9530 9531 mce_init(cpu); 9532 9533 x86_cpu_gdb_init(cs); 9534 qemu_init_vcpu(cs); 9535 9536 #ifndef CONFIG_USER_ONLY 9537 x86_cpu_apic_realize(cpu, &local_err); 9538 if (local_err != NULL) { 9539 goto out; 9540 } 9541 #endif /* !CONFIG_USER_ONLY */ 9542 cpu_reset(cs); 9543 9544 xcc->parent_realize(dev, &local_err); 9545 9546 out: 9547 if (local_err != NULL) { 9548 error_propagate(errp, local_err); 9549 return; 9550 } 9551 } 9552 9553 static void x86_cpu_unrealizefn(DeviceState *dev) 9554 { 9555 X86CPU *cpu = X86_CPU(dev); 9556 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 9557 9558 #ifndef CONFIG_USER_ONLY 9559 cpu_remove_sync(CPU(dev)); 9560 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 9561 #endif 9562 9563 if (cpu->apic_state) { 9564 object_unparent(OBJECT(cpu->apic_state)); 9565 cpu->apic_state = NULL; 9566 } 9567 9568 xcc->parent_unrealize(dev); 9569 } 9570 9571 typedef struct BitProperty { 9572 FeatureWord w; 9573 uint64_t mask; 9574 } BitProperty; 9575 9576 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 9577 void *opaque, Error **errp) 9578 { 9579 X86CPU *cpu = X86_CPU(obj); 9580 BitProperty *fp = opaque; 9581 uint64_t f = cpu->env.features[fp->w]; 9582 bool value = (f & fp->mask) == fp->mask; 9583 visit_type_bool(v, name, &value, errp); 9584 } 9585 9586 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 9587 void *opaque, Error **errp) 9588 { 9589 DeviceState *dev = DEVICE(obj); 9590 X86CPU *cpu = X86_CPU(obj); 9591 BitProperty *fp = opaque; 9592 bool value; 9593 9594 if (dev->realized) { 9595 qdev_prop_set_after_realize(dev, name, errp); 9596 return; 9597 } 9598 9599 if (!visit_type_bool(v, name, &value, errp)) { 9600 return; 9601 } 9602 9603 if (value) { 9604 cpu->env.features[fp->w] |= fp->mask; 9605 } else { 9606 cpu->env.features[fp->w] &= ~fp->mask; 9607 } 9608 cpu->env.user_features[fp->w] |= fp->mask; 9609 } 9610 9611 /* Register a boolean property to get/set a single bit in a uint32_t field. 9612 * 9613 * The same property name can be registered multiple times to make it affect 9614 * multiple bits in the same FeatureWord. In that case, the getter will return 9615 * true only if all bits are set. 9616 */ 9617 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 9618 const char *prop_name, 9619 FeatureWord w, 9620 int bitnr) 9621 { 9622 ObjectClass *oc = OBJECT_CLASS(xcc); 9623 BitProperty *fp; 9624 ObjectProperty *op; 9625 uint64_t mask = (1ULL << bitnr); 9626 9627 op = object_class_property_find(oc, prop_name); 9628 if (op) { 9629 fp = op->opaque; 9630 assert(fp->w == w); 9631 fp->mask |= mask; 9632 } else { 9633 fp = g_new0(BitProperty, 1); 9634 fp->w = w; 9635 fp->mask = mask; 9636 object_class_property_add(oc, prop_name, "bool", 9637 x86_cpu_get_bit_prop, 9638 x86_cpu_set_bit_prop, 9639 NULL, fp); 9640 } 9641 } 9642 9643 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 9644 FeatureWord w, 9645 int bitnr) 9646 { 9647 FeatureWordInfo *fi = &feature_word_info[w]; 9648 const char *name = fi->feat_names[bitnr]; 9649 9650 if (!name) { 9651 return; 9652 } 9653 9654 /* Property names should use "-" instead of "_". 9655 * Old names containing underscores are registered as aliases 9656 * using object_property_add_alias() 9657 */ 9658 assert(!strchr(name, '_')); 9659 /* aliases don't use "|" delimiters anymore, they are registered 9660 * manually using object_property_add_alias() */ 9661 assert(!strchr(name, '|')); 9662 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 9663 } 9664 9665 static void x86_cpu_post_initfn(Object *obj) 9666 { 9667 #ifndef CONFIG_USER_ONLY 9668 if (current_machine && current_machine->cgs) { 9669 x86_confidential_guest_cpu_instance_init( 9670 X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj))); 9671 } 9672 #endif 9673 } 9674 9675 static void x86_cpu_init_xsave(void) 9676 { 9677 static bool first = true; 9678 uint64_t supported_xcr0; 9679 int i; 9680 9681 if (first) { 9682 first = false; 9683 9684 supported_xcr0 = 9685 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 9686 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 9687 9688 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 9689 ExtSaveArea *esa = &x86_ext_save_areas[i]; 9690 9691 if (!(supported_xcr0 & (1 << i))) { 9692 esa->size = 0; 9693 } 9694 } 9695 } 9696 } 9697 9698 static void x86_cpu_init_default_topo(X86CPU *cpu) 9699 { 9700 CPUX86State *env = &cpu->env; 9701 9702 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 9703 9704 /* thread, core and socket levels are set by default. */ 9705 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 9706 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 9707 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 9708 } 9709 9710 static void x86_cpu_initfn(Object *obj) 9711 { 9712 X86CPU *cpu = X86_CPU(obj); 9713 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 9714 CPUX86State *env = &cpu->env; 9715 9716 x86_cpu_init_default_topo(cpu); 9717 9718 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 9719 x86_cpu_get_feature_words, 9720 NULL, NULL, (void *)env->features); 9721 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 9722 x86_cpu_get_feature_words, 9723 NULL, NULL, (void *)cpu->filtered_features); 9724 9725 object_property_add_alias(obj, "sse3", obj, "pni"); 9726 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 9727 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 9728 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 9729 object_property_add_alias(obj, "xd", obj, "nx"); 9730 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 9731 object_property_add_alias(obj, "i64", obj, "lm"); 9732 9733 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 9734 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 9735 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 9736 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 9737 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 9738 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 9739 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 9740 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 9741 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 9742 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 9743 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 9744 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 9745 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 9746 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 9747 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 9748 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 9749 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 9750 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 9751 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 9752 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 9753 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 9754 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 9755 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 9756 9757 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 9758 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 9759 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 9760 9761 if (xcc->model) { 9762 x86_cpu_load_model(cpu, xcc->model); 9763 } 9764 9765 /* 9766 * accel's cpu_instance_init may have the xsave check, 9767 * so x86_ext_save_areas[] must be initialized before this. 9768 */ 9769 x86_cpu_init_xsave(); 9770 accel_cpu_instance_init(CPU(obj)); 9771 } 9772 9773 static int64_t x86_cpu_get_arch_id(CPUState *cs) 9774 { 9775 X86CPU *cpu = X86_CPU(cs); 9776 9777 return cpu->apic_id; 9778 } 9779 9780 #if !defined(CONFIG_USER_ONLY) 9781 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 9782 { 9783 X86CPU *cpu = X86_CPU(cs); 9784 9785 return cpu->env.cr[0] & CR0_PG_MASK; 9786 } 9787 #endif /* !CONFIG_USER_ONLY */ 9788 9789 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 9790 { 9791 X86CPU *cpu = X86_CPU(cs); 9792 9793 cpu->env.eip = value; 9794 } 9795 9796 static vaddr x86_cpu_get_pc(CPUState *cs) 9797 { 9798 X86CPU *cpu = X86_CPU(cs); 9799 9800 /* Match cpu_get_tb_cpu_state. */ 9801 return cpu->env.eip + cpu->env.segs[R_CS].base; 9802 } 9803 9804 #if !defined(CONFIG_USER_ONLY) 9805 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 9806 { 9807 X86CPU *cpu = X86_CPU(cs); 9808 CPUX86State *env = &cpu->env; 9809 9810 if (interrupt_request & CPU_INTERRUPT_POLL) { 9811 return CPU_INTERRUPT_POLL; 9812 } 9813 if (interrupt_request & CPU_INTERRUPT_SIPI) { 9814 return CPU_INTERRUPT_SIPI; 9815 } 9816 9817 if (env->hflags2 & HF2_GIF_MASK) { 9818 if ((interrupt_request & CPU_INTERRUPT_SMI) && 9819 !(env->hflags & HF_SMM_MASK)) { 9820 return CPU_INTERRUPT_SMI; 9821 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 9822 !(env->hflags2 & HF2_NMI_MASK)) { 9823 return CPU_INTERRUPT_NMI; 9824 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 9825 return CPU_INTERRUPT_MCE; 9826 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 9827 (((env->hflags2 & HF2_VINTR_MASK) && 9828 (env->hflags2 & HF2_HIF_MASK)) || 9829 (!(env->hflags2 & HF2_VINTR_MASK) && 9830 (env->eflags & IF_MASK && 9831 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 9832 return CPU_INTERRUPT_HARD; 9833 } else if (env->hflags2 & HF2_VGIF_MASK) { 9834 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 9835 (env->eflags & IF_MASK) && 9836 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 9837 return CPU_INTERRUPT_VIRQ; 9838 } 9839 } 9840 } 9841 9842 return 0; 9843 } 9844 9845 static bool x86_cpu_has_work(CPUState *cs) 9846 { 9847 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 9848 } 9849 #endif /* !CONFIG_USER_ONLY */ 9850 9851 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 9852 { 9853 X86CPU *cpu = X86_CPU(cs); 9854 CPUX86State *env = &cpu->env; 9855 9856 info->endian = BFD_ENDIAN_LITTLE; 9857 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 9858 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 9859 : bfd_mach_i386_i8086); 9860 9861 info->cap_arch = CS_ARCH_X86; 9862 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 9863 : env->hflags & HF_CS32_MASK ? CS_MODE_32 9864 : CS_MODE_16); 9865 info->cap_insn_unit = 1; 9866 info->cap_insn_split = 8; 9867 } 9868 9869 void x86_update_hflags(CPUX86State *env) 9870 { 9871 uint32_t hflags; 9872 #define HFLAG_COPY_MASK \ 9873 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 9874 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 9875 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 9876 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 9877 9878 hflags = env->hflags & HFLAG_COPY_MASK; 9879 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 9880 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 9881 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 9882 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 9883 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 9884 9885 if (env->cr[4] & CR4_OSFXSR_MASK) { 9886 hflags |= HF_OSFXSR_MASK; 9887 } 9888 9889 if (env->efer & MSR_EFER_LMA) { 9890 hflags |= HF_LMA_MASK; 9891 } 9892 9893 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 9894 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 9895 } else { 9896 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 9897 (DESC_B_SHIFT - HF_CS32_SHIFT); 9898 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 9899 (DESC_B_SHIFT - HF_SS32_SHIFT); 9900 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 9901 !(hflags & HF_CS32_MASK)) { 9902 hflags |= HF_ADDSEG_MASK; 9903 } else { 9904 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 9905 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 9906 } 9907 } 9908 env->hflags = hflags; 9909 } 9910 9911 static const Property x86_cpu_properties[] = { 9912 #ifdef CONFIG_USER_ONLY 9913 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 9914 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 9915 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 9916 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 9917 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 9918 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 9919 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 9920 #else 9921 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 9922 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 9923 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 9924 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 9925 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 9926 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 9927 #endif 9928 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 9929 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 9930 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 9931 9932 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 9933 HYPERV_SPINLOCK_NEVER_NOTIFY), 9934 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 9935 HYPERV_FEAT_RELAXED, 0), 9936 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 9937 HYPERV_FEAT_VAPIC, 0), 9938 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 9939 HYPERV_FEAT_TIME, 0), 9940 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 9941 HYPERV_FEAT_CRASH, 0), 9942 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 9943 HYPERV_FEAT_RESET, 0), 9944 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 9945 HYPERV_FEAT_VPINDEX, 0), 9946 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 9947 HYPERV_FEAT_RUNTIME, 0), 9948 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 9949 HYPERV_FEAT_SYNIC, 0), 9950 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 9951 HYPERV_FEAT_STIMER, 0), 9952 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 9953 HYPERV_FEAT_FREQUENCIES, 0), 9954 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 9955 HYPERV_FEAT_REENLIGHTENMENT, 0), 9956 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 9957 HYPERV_FEAT_TLBFLUSH, 0), 9958 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 9959 HYPERV_FEAT_EVMCS, 0), 9960 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 9961 HYPERV_FEAT_IPI, 0), 9962 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 9963 HYPERV_FEAT_STIMER_DIRECT, 0), 9964 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 9965 HYPERV_FEAT_AVIC, 0), 9966 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 9967 HYPERV_FEAT_MSR_BITMAP, 0), 9968 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 9969 HYPERV_FEAT_XMM_INPUT, 0), 9970 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 9971 HYPERV_FEAT_TLBFLUSH_EXT, 0), 9972 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 9973 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 9974 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 9975 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 9976 #ifdef CONFIG_SYNDBG 9977 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 9978 HYPERV_FEAT_SYNDBG, 0), 9979 #endif 9980 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 9981 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 9982 9983 /* WS2008R2 identify by default */ 9984 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 9985 0x3839), 9986 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 9987 0x000A), 9988 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 9989 0x0000), 9990 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 9991 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 9992 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 9993 9994 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 9995 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 9996 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 9997 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 9998 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 9999 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 10000 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 10001 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 10002 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 10003 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 10004 UINT32_MAX), 10005 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 10006 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 10007 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 10008 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 10009 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 10010 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 10011 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 10012 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 10013 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 10014 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 10015 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 10016 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 10017 DEFINE_PROP_BOOL("x-vendor-cpuid-only-v2", X86CPU, vendor_cpuid_only_v2, true), 10018 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 10019 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 10020 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 10021 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 10022 false), 10023 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 10024 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 10025 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 10026 true), 10027 /* 10028 * lecacy_cache defaults to true unless the CPU model provides its 10029 * own cache information (see x86_cpu_load_def()). 10030 */ 10031 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 10032 DEFINE_PROP_BOOL("x-consistent-cache", X86CPU, consistent_cache, true), 10033 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 10034 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 10035 10036 /* 10037 * From "Requirements for Implementing the Microsoft 10038 * Hypervisor Interface": 10039 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 10040 * 10041 * "Starting with Windows Server 2012 and Windows 8, if 10042 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 10043 * the hypervisor imposes no specific limit to the number of VPs. 10044 * In this case, Windows Server 2012 guest VMs may use more than 10045 * 64 VPs, up to the maximum supported number of processors applicable 10046 * to the specific Windows version being used." 10047 */ 10048 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 10049 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 10050 false), 10051 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 10052 true), 10053 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 10054 DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false), 10055 10056 DEFINE_PROP_BOOL("x-arch-cap-always-on", X86CPU, 10057 arch_cap_always_on, false), 10058 DEFINE_PROP_BOOL("x-pdcm-on-even-without-pmu", X86CPU, 10059 pdcm_on_even_without_pmu, false), 10060 }; 10061 10062 #ifndef CONFIG_USER_ONLY 10063 #include "hw/core/sysemu-cpu-ops.h" 10064 10065 static const struct SysemuCPUOps i386_sysemu_ops = { 10066 .has_work = x86_cpu_has_work, 10067 .get_memory_mapping = x86_cpu_get_memory_mapping, 10068 .get_paging_enabled = x86_cpu_get_paging_enabled, 10069 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 10070 .asidx_from_attrs = x86_asidx_from_attrs, 10071 .get_crash_info = x86_cpu_get_crash_info, 10072 .write_elf32_note = x86_cpu_write_elf32_note, 10073 .write_elf64_note = x86_cpu_write_elf64_note, 10074 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 10075 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 10076 .legacy_vmsd = &vmstate_x86_cpu, 10077 }; 10078 #endif 10079 10080 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 10081 { 10082 X86CPUClass *xcc = X86_CPU_CLASS(oc); 10083 CPUClass *cc = CPU_CLASS(oc); 10084 DeviceClass *dc = DEVICE_CLASS(oc); 10085 ResettableClass *rc = RESETTABLE_CLASS(oc); 10086 FeatureWord w; 10087 10088 device_class_set_parent_realize(dc, x86_cpu_realizefn, 10089 &xcc->parent_realize); 10090 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 10091 &xcc->parent_unrealize); 10092 device_class_set_props(dc, x86_cpu_properties); 10093 10094 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 10095 &xcc->parent_phases); 10096 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 10097 10098 cc->class_by_name = x86_cpu_class_by_name; 10099 cc->list_cpus = x86_cpu_list; 10100 cc->parse_features = x86_cpu_parse_featurestr; 10101 cc->dump_state = x86_cpu_dump_state; 10102 cc->set_pc = x86_cpu_set_pc; 10103 cc->get_pc = x86_cpu_get_pc; 10104 cc->gdb_read_register = x86_cpu_gdb_read_register; 10105 cc->gdb_write_register = x86_cpu_gdb_write_register; 10106 cc->get_arch_id = x86_cpu_get_arch_id; 10107 10108 #ifndef CONFIG_USER_ONLY 10109 cc->sysemu_ops = &i386_sysemu_ops; 10110 #endif /* !CONFIG_USER_ONLY */ 10111 #ifdef CONFIG_TCG 10112 cc->tcg_ops = &x86_tcg_ops; 10113 #endif /* CONFIG_TCG */ 10114 10115 cc->gdb_arch_name = x86_gdb_arch_name; 10116 #ifdef TARGET_X86_64 10117 cc->gdb_core_xml_file = "i386-64bit.xml"; 10118 #else 10119 cc->gdb_core_xml_file = "i386-32bit.xml"; 10120 #endif 10121 cc->disas_set_info = x86_disas_set_info; 10122 10123 dc->user_creatable = true; 10124 10125 object_class_property_add(oc, "family", "int", 10126 x86_cpuid_version_get_family, 10127 x86_cpuid_version_set_family, NULL, NULL); 10128 object_class_property_add(oc, "model", "int", 10129 x86_cpuid_version_get_model, 10130 x86_cpuid_version_set_model, NULL, NULL); 10131 object_class_property_add(oc, "stepping", "int", 10132 x86_cpuid_version_get_stepping, 10133 x86_cpuid_version_set_stepping, NULL, NULL); 10134 object_class_property_add_str(oc, "vendor", 10135 x86_cpuid_get_vendor, 10136 x86_cpuid_set_vendor); 10137 object_class_property_add_str(oc, "model-id", 10138 x86_cpuid_get_model_id, 10139 x86_cpuid_set_model_id); 10140 object_class_property_add(oc, "tsc-frequency", "int", 10141 x86_cpuid_get_tsc_freq, 10142 x86_cpuid_set_tsc_freq, NULL, NULL); 10143 /* 10144 * The "unavailable-features" property has the same semantics as 10145 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 10146 * QMP command: they list the features that would have prevented the 10147 * CPU from running if the "enforce" flag was set. 10148 */ 10149 object_class_property_add(oc, "unavailable-features", "strList", 10150 x86_cpu_get_unavailable_features, 10151 NULL, NULL, NULL); 10152 10153 #if !defined(CONFIG_USER_ONLY) 10154 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 10155 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 10156 #endif 10157 10158 for (w = 0; w < FEATURE_WORDS; w++) { 10159 int bitnr; 10160 for (bitnr = 0; bitnr < 64; bitnr++) { 10161 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 10162 } 10163 } 10164 } 10165 10166 static const TypeInfo x86_cpu_type_info = { 10167 .name = TYPE_X86_CPU, 10168 .parent = TYPE_CPU, 10169 .instance_size = sizeof(X86CPU), 10170 .instance_align = __alignof(X86CPU), 10171 .instance_init = x86_cpu_initfn, 10172 .instance_post_init = x86_cpu_post_initfn, 10173 10174 .abstract = true, 10175 .class_size = sizeof(X86CPUClass), 10176 .class_init = x86_cpu_common_class_init, 10177 }; 10178 10179 /* "base" CPU model, used by query-cpu-model-expansion */ 10180 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 10181 { 10182 X86CPUClass *xcc = X86_CPU_CLASS(oc); 10183 10184 xcc->static_model = true; 10185 xcc->migration_safe = true; 10186 xcc->model_description = "base CPU model type with no features enabled"; 10187 xcc->ordering = 8; 10188 } 10189 10190 static const TypeInfo x86_base_cpu_type_info = { 10191 .name = X86_CPU_TYPE_NAME("base"), 10192 .parent = TYPE_X86_CPU, 10193 .class_init = x86_cpu_base_class_init, 10194 }; 10195 10196 static void x86_cpu_register_types(void) 10197 { 10198 int i; 10199 10200 type_register_static(&x86_cpu_type_info); 10201 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 10202 x86_register_cpudef_types(&builtin_x86_defs[i]); 10203 } 10204 type_register_static(&max_x86_cpu_type_info); 10205 type_register_static(&x86_base_cpu_type_info); 10206 } 10207 10208 type_init(x86_cpu_register_types) 10209