1 /*
2 * Intel XScale PXA255/270 GPIO controller emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "cpu.h"
12 #include "hw/irq.h"
13 #include "hw/qdev-properties.h"
14 #include "hw/sysbus.h"
15 #include "migration/vmstate.h"
16 #include "hw/arm/pxa.h"
17 #include "qapi/error.h"
18 #include "qemu/log.h"
19 #include "qemu/module.h"
20 #include "qom/object.h"
21
22 #define PXA2XX_GPIO_BANKS 4
23
24 #define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
25 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxGPIOInfo, PXA2XX_GPIO)
26
27 struct PXA2xxGPIOInfo {
28 /*< private >*/
29 SysBusDevice parent_obj;
30 /*< public >*/
31
32 MemoryRegion iomem;
33 qemu_irq irq0, irq1, irqX;
34 int lines;
35 ARMCPU *cpu;
36
37 /* XXX: GNU C vectors are more suitable */
38 uint32_t ilevel[PXA2XX_GPIO_BANKS];
39 uint32_t olevel[PXA2XX_GPIO_BANKS];
40 uint32_t dir[PXA2XX_GPIO_BANKS];
41 uint32_t rising[PXA2XX_GPIO_BANKS];
42 uint32_t falling[PXA2XX_GPIO_BANKS];
43 uint32_t status[PXA2XX_GPIO_BANKS];
44 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
45
46 uint32_t prev_level[PXA2XX_GPIO_BANKS];
47 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
48 qemu_irq read_notify;
49 };
50
51 static struct {
52 enum {
53 GPIO_NONE,
54 GPLR,
55 GPSR,
56 GPCR,
57 GPDR,
58 GRER,
59 GFER,
60 GEDR,
61 GAFR_L,
62 GAFR_U,
63 } reg;
64 int bank;
65 } pxa2xx_gpio_regs[0x200] = {
66 [0 ... 0x1ff] = { GPIO_NONE, 0 },
67 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
68 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
69
70 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
71 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
72 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
73 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
74 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
75 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
76 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
77 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
78 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
79 };
80
pxa2xx_gpio_irq_update(PXA2xxGPIOInfo * s)81 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
82 {
83 if (s->status[0] & (1 << 0))
84 qemu_irq_raise(s->irq0);
85 else
86 qemu_irq_lower(s->irq0);
87
88 if (s->status[0] & (1 << 1))
89 qemu_irq_raise(s->irq1);
90 else
91 qemu_irq_lower(s->irq1);
92
93 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
94 qemu_irq_raise(s->irqX);
95 else
96 qemu_irq_lower(s->irqX);
97 }
98
99 /* Bitmap of pins used as standby and sleep wake-up sources. */
100 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
101 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
102 };
103
pxa2xx_gpio_set(void * opaque,int line,int level)104 static void pxa2xx_gpio_set(void *opaque, int line, int level)
105 {
106 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
107 CPUState *cpu = CPU(s->cpu);
108 int bank;
109 uint32_t mask;
110
111 if (line >= s->lines) {
112 printf("%s: No GPIO pin %i\n", __func__, line);
113 return;
114 }
115
116 bank = line >> 5;
117 mask = 1U << (line & 31);
118
119 if (level) {
120 s->status[bank] |= s->rising[bank] & mask &
121 ~s->ilevel[bank] & ~s->dir[bank];
122 s->ilevel[bank] |= mask;
123 } else {
124 s->status[bank] |= s->falling[bank] & mask &
125 s->ilevel[bank] & ~s->dir[bank];
126 s->ilevel[bank] &= ~mask;
127 }
128
129 if (s->status[bank] & mask)
130 pxa2xx_gpio_irq_update(s);
131
132 /* Wake-up GPIOs */
133 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
134 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
135 }
136 }
137
pxa2xx_gpio_handler_update(PXA2xxGPIOInfo * s)138 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
139 uint32_t level, diff;
140 int i, bit, line;
141 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
142 level = s->olevel[i] & s->dir[i];
143
144 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
145 bit = ctz32(diff);
146 line = bit + 32 * i;
147 qemu_set_irq(s->handler[line], (level >> bit) & 1);
148 }
149
150 s->prev_level[i] = level;
151 }
152 }
153
pxa2xx_gpio_read(void * opaque,hwaddr offset,unsigned size)154 static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
155 unsigned size)
156 {
157 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
158 uint32_t ret;
159 int bank;
160 if (offset >= 0x200)
161 return 0;
162
163 bank = pxa2xx_gpio_regs[offset].bank;
164 switch (pxa2xx_gpio_regs[offset].reg) {
165 case GPDR: /* GPIO Pin-Direction registers */
166 return s->dir[bank];
167
168 case GPSR: /* GPIO Pin-Output Set registers */
169 qemu_log_mask(LOG_GUEST_ERROR,
170 "pxa2xx GPIO: read from write only register GPSR\n");
171 return 0;
172
173 case GPCR: /* GPIO Pin-Output Clear registers */
174 qemu_log_mask(LOG_GUEST_ERROR,
175 "pxa2xx GPIO: read from write only register GPCR\n");
176 return 0;
177
178 case GRER: /* GPIO Rising-Edge Detect Enable registers */
179 return s->rising[bank];
180
181 case GFER: /* GPIO Falling-Edge Detect Enable registers */
182 return s->falling[bank];
183
184 case GAFR_L: /* GPIO Alternate Function registers */
185 return s->gafr[bank * 2];
186
187 case GAFR_U: /* GPIO Alternate Function registers */
188 return s->gafr[bank * 2 + 1];
189
190 case GPLR: /* GPIO Pin-Level registers */
191 ret = (s->olevel[bank] & s->dir[bank]) |
192 (s->ilevel[bank] & ~s->dir[bank]);
193 qemu_irq_raise(s->read_notify);
194 return ret;
195
196 case GEDR: /* GPIO Edge Detect Status registers */
197 return s->status[bank];
198
199 default:
200 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
201 __func__, offset);
202 }
203
204 return 0;
205 }
206
pxa2xx_gpio_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)207 static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
208 uint64_t value, unsigned size)
209 {
210 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
211 int bank;
212 if (offset >= 0x200)
213 return;
214
215 bank = pxa2xx_gpio_regs[offset].bank;
216 switch (pxa2xx_gpio_regs[offset].reg) {
217 case GPDR: /* GPIO Pin-Direction registers */
218 s->dir[bank] = value;
219 pxa2xx_gpio_handler_update(s);
220 break;
221
222 case GPSR: /* GPIO Pin-Output Set registers */
223 s->olevel[bank] |= value;
224 pxa2xx_gpio_handler_update(s);
225 break;
226
227 case GPCR: /* GPIO Pin-Output Clear registers */
228 s->olevel[bank] &= ~value;
229 pxa2xx_gpio_handler_update(s);
230 break;
231
232 case GRER: /* GPIO Rising-Edge Detect Enable registers */
233 s->rising[bank] = value;
234 break;
235
236 case GFER: /* GPIO Falling-Edge Detect Enable registers */
237 s->falling[bank] = value;
238 break;
239
240 case GAFR_L: /* GPIO Alternate Function registers */
241 s->gafr[bank * 2] = value;
242 break;
243
244 case GAFR_U: /* GPIO Alternate Function registers */
245 s->gafr[bank * 2 + 1] = value;
246 break;
247
248 case GEDR: /* GPIO Edge Detect Status registers */
249 s->status[bank] &= ~value;
250 pxa2xx_gpio_irq_update(s);
251 break;
252
253 default:
254 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
255 __func__, offset);
256 }
257 }
258
259 static const MemoryRegionOps pxa_gpio_ops = {
260 .read = pxa2xx_gpio_read,
261 .write = pxa2xx_gpio_write,
262 .endianness = DEVICE_NATIVE_ENDIAN,
263 };
264
pxa2xx_gpio_init(hwaddr base,ARMCPU * cpu,DeviceState * pic,int lines)265 DeviceState *pxa2xx_gpio_init(hwaddr base,
266 ARMCPU *cpu, DeviceState *pic, int lines)
267 {
268 DeviceState *dev;
269
270 dev = qdev_new(TYPE_PXA2XX_GPIO);
271 qdev_prop_set_int32(dev, "lines", lines);
272 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
273 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
274
275 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
276 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
277 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
278 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
279 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
280 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
281 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
282
283 return dev;
284 }
285
pxa2xx_gpio_initfn(Object * obj)286 static void pxa2xx_gpio_initfn(Object *obj)
287 {
288 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
289 DeviceState *dev = DEVICE(sbd);
290 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
291
292 memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
293 s, "pxa2xx-gpio", 0x1000);
294 sysbus_init_mmio(sbd, &s->iomem);
295 sysbus_init_irq(sbd, &s->irq0);
296 sysbus_init_irq(sbd, &s->irq1);
297 sysbus_init_irq(sbd, &s->irqX);
298 }
299
pxa2xx_gpio_realize(DeviceState * dev,Error ** errp)300 static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
301 {
302 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
303
304 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
305 qdev_init_gpio_out(dev, s->handler, s->lines);
306 }
307
308 /*
309 * Registers a callback to notify on GPLR reads. This normally
310 * shouldn't be needed but it is used for the hack on Spitz machines.
311 */
pxa2xx_gpio_read_notifier(DeviceState * dev,qemu_irq handler)312 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
313 {
314 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
315
316 s->read_notify = handler;
317 }
318
319 static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
320 .name = "pxa2xx-gpio",
321 .version_id = 1,
322 .minimum_version_id = 1,
323 .fields = (const VMStateField[]) {
324 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
325 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
326 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
327 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
328 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
329 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
330 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
331 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
332 VMSTATE_END_OF_LIST(),
333 },
334 };
335
336 static Property pxa2xx_gpio_properties[] = {
337 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
338 DEFINE_PROP_LINK("cpu", PXA2xxGPIOInfo, cpu, TYPE_ARM_CPU, ARMCPU *),
339 DEFINE_PROP_END_OF_LIST(),
340 };
341
pxa2xx_gpio_class_init(ObjectClass * klass,void * data)342 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
343 {
344 DeviceClass *dc = DEVICE_CLASS(klass);
345
346 dc->desc = "PXA2xx GPIO controller";
347 device_class_set_props(dc, pxa2xx_gpio_properties);
348 dc->vmsd = &vmstate_pxa2xx_gpio_regs;
349 dc->realize = pxa2xx_gpio_realize;
350 }
351
352 static const TypeInfo pxa2xx_gpio_info = {
353 .name = TYPE_PXA2XX_GPIO,
354 .parent = TYPE_SYS_BUS_DEVICE,
355 .instance_size = sizeof(PXA2xxGPIOInfo),
356 .instance_init = pxa2xx_gpio_initfn,
357 .class_init = pxa2xx_gpio_class_init,
358 };
359
pxa2xx_gpio_register_types(void)360 static void pxa2xx_gpio_register_types(void)
361 {
362 type_register_static(&pxa2xx_gpio_info);
363 }
364
365 type_init(pxa2xx_gpio_register_types)
366