1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * Please try to maintain the following order within this file unless it makes 6 * sense to do otherwise. From top to bottom: 7 * 1. typedefs 8 * 2. #defines, and macros 9 * 3. structure definitions 10 * 4. function prototypes 11 * 12 * Within each section, please try to order by generation in ascending order, 13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 14 */ 15 16 #ifndef __INTEL_GTT_H__ 17 #define __INTEL_GTT_H__ 18 19 #include <linux/io-mapping.h> 20 #include <linux/kref.h> 21 #include <linux/mm.h> 22 #include <linux/pagevec.h> 23 #include <linux/scatterlist.h> 24 #include <linux/workqueue.h> 25 26 #include <drm/drm_mm.h> 27 28 #include "gt/intel_reset.h" 29 #include "i915_selftest.h" 30 #include "i915_vma_resource.h" 31 #include "i915_vma_types.h" 32 #include "i915_params.h" 33 #include "intel_memory_region.h" 34 35 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 36 37 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 38 #define DBG(...) trace_printk(__VA_ARGS__) 39 #else 40 #define DBG(...) 41 #endif 42 43 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 44 45 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 46 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 47 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 48 49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 51 52 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 53 54 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 55 56 #define I915_FENCE_REG_NONE -1 57 #define I915_MAX_NUM_FENCES 32 58 /* 32 fences + sign bit for FENCE_REG_NONE */ 59 #define I915_MAX_NUM_FENCE_BITS 6 60 61 typedef u32 gen6_pte_t; 62 typedef u64 gen8_pte_t; 63 64 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 65 66 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 67 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 68 #define I915_PDES 512 69 #define I915_PDE_MASK (I915_PDES - 1) 70 71 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 72 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 73 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 74 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 75 #define GEN6_PTE_CACHE_LLC (2 << 1) 76 #define GEN6_PTE_UNCACHED (1 << 1) 77 #define GEN6_PTE_VALID REG_BIT(0) 78 79 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 80 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 81 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 82 #define GEN6_PDE_SHIFT 22 83 #define GEN6_PDE_VALID REG_BIT(0) 84 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 85 86 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 87 88 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 89 #define BYT_PTE_WRITEABLE REG_BIT(1) 90 91 #define MTL_PPGTT_PTE_PAT3 BIT_ULL(62) 92 #define GEN12_PPGTT_PTE_LM BIT_ULL(11) 93 #define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7) 94 #define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4) 95 #define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3) 96 97 #define GEN12_GGTT_PTE_LM BIT_ULL(1) 98 #define MTL_GGTT_PTE_PAT0 BIT_ULL(52) 99 #define MTL_GGTT_PTE_PAT1 BIT_ULL(53) 100 #define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12) 101 #define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52) 102 103 #define GEN12_PDE_64K BIT(6) 104 #define GEN12_PTE_PS64 BIT(8) 105 106 /* 107 * Cacheability Control is a 4-bit value. The low three bits are stored in bits 108 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 109 */ 110 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 111 (((bits) & 0x8) << (11 - 3))) 112 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 113 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 114 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 115 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 116 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 117 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 118 #define HSW_PTE_UNCACHED (0) 119 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 120 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 121 122 /* 123 * GEN8 32b style address is defined as a 3 level page table: 124 * 31:30 | 29:21 | 20:12 | 11:0 125 * PDPE | PDE | PTE | offset 126 * The difference as compared to normal x86 3 level page table is the PDPEs are 127 * programmed via register. 128 * 129 * GEN8 48b style address is defined as a 4 level page table: 130 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 131 * PML4E | PDPE | PDE | PTE | offset 132 */ 133 #define GEN8_3LVL_PDPES 4 134 135 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 136 #define PPAT_CACHED_PDE 0 /* WB LLC */ 137 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 138 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 139 140 #define CHV_PPAT_SNOOP REG_BIT(6) 141 #define GEN8_PPAT_AGE(x) ((x)<<4) 142 #define GEN8_PPAT_LLCeLLC (3<<2) 143 #define GEN8_PPAT_LLCELLC (2<<2) 144 #define GEN8_PPAT_LLC (1<<2) 145 #define GEN8_PPAT_WB (3<<0) 146 #define GEN8_PPAT_WT (2<<0) 147 #define GEN8_PPAT_WC (1<<0) 148 #define GEN8_PPAT_UC (0<<0) 149 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 150 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 151 152 #define GEN8_PAGE_PRESENT BIT_ULL(0) 153 #define GEN8_PAGE_RW BIT_ULL(1) 154 155 #define GEN8_PDE_IPS_64K BIT(11) 156 #define GEN8_PDE_PS_2M BIT(7) 157 158 #define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2) 159 #define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) 160 #define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3) 161 #define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1) 162 #define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0) 163 #define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3) 164 #define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2) 165 166 struct drm_i915_gem_object; 167 struct i915_fence_reg; 168 struct i915_vma; 169 struct intel_gt; 170 171 #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 172 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 173 174 struct i915_page_table { 175 struct drm_i915_gem_object *base; 176 union { 177 atomic_t used; 178 struct i915_page_table *stash; 179 }; 180 bool is_compact; 181 }; 182 183 struct i915_page_directory { 184 struct i915_page_table pt; 185 spinlock_t lock; 186 void **entry; 187 }; 188 189 #define __px_choose_expr(x, type, expr, other) \ 190 __builtin_choose_expr( \ 191 __builtin_types_compatible_p(typeof(x), type) || \ 192 __builtin_types_compatible_p(typeof(x), const type), \ 193 ({ type __x = (type)(x); expr; }), \ 194 other) 195 196 #define px_base(px) \ 197 __px_choose_expr(px, struct drm_i915_gem_object *, __x, \ 198 __px_choose_expr(px, struct i915_page_table *, __x->base, \ 199 __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \ 200 (void)0))) 201 202 struct page *__px_page(struct drm_i915_gem_object *p); 203 dma_addr_t __px_dma(struct drm_i915_gem_object *p); 204 #define px_dma(px) (__px_dma(px_base(px))) 205 206 void *__px_vaddr(struct drm_i915_gem_object *p); 207 #define px_vaddr(px) (__px_vaddr(px_base(px))) 208 209 #define px_pt(px) \ 210 __px_choose_expr(px, struct i915_page_table *, __x, \ 211 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 212 (void)0)) 213 #define px_used(px) (&px_pt(px)->used) 214 215 struct i915_vm_pt_stash { 216 /* preallocated chains of page tables/directories */ 217 struct i915_page_table *pt[2]; 218 /* 219 * Optionally override the alignment/size of the physical page that 220 * contains each PT. If not set defaults back to the usual 221 * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging 222 * structures. MUST be a power-of-two. ONLY applicable on discrete 223 * platforms. 224 */ 225 int pt_sz; 226 }; 227 228 struct i915_vma_ops { 229 /* Map an object into an address space with the given cache flags. */ 230 void (*bind_vma)(struct i915_address_space *vm, 231 struct i915_vm_pt_stash *stash, 232 struct i915_vma_resource *vma_res, 233 unsigned int pat_index, 234 u32 flags); 235 /* 236 * Unmap an object from an address space. This usually consists of 237 * setting the valid PTE entries to a reserved scratch page. 238 */ 239 void (*unbind_vma)(struct i915_address_space *vm, 240 struct i915_vma_resource *vma_res); 241 242 }; 243 244 struct i915_address_space { 245 struct kref ref; 246 struct work_struct release_work; 247 248 struct drm_mm mm; 249 struct intel_gt *gt; 250 struct drm_i915_private *i915; 251 struct device *dma; 252 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 253 u64 reserved; /* size addr space reserved */ 254 u64 min_alignment[INTEL_MEMORY_STOLEN_LOCAL + 1]; 255 256 unsigned int bind_async_flags; 257 258 struct mutex mutex; /* protects vma and our lists */ 259 260 struct kref resv_ref; /* kref to keep the reservation lock alive. */ 261 struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */ 262 #define VM_CLASS_GGTT 0 263 #define VM_CLASS_PPGTT 1 264 #define VM_CLASS_DPT 2 265 266 struct drm_i915_gem_object *scratch[4]; 267 /** 268 * List of vma currently bound. 269 */ 270 struct list_head bound_list; 271 272 /** 273 * List of vmas not yet bound or evicted. 274 */ 275 struct list_head unbound_list; 276 277 /* Global GTT */ 278 bool is_ggtt:1; 279 280 /* Display page table */ 281 bool is_dpt:1; 282 283 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 284 bool has_read_only:1; 285 286 /* Skip pte rewrite on unbind for suspend. Protected by @mutex */ 287 bool skip_pte_rewrite:1; 288 289 u8 top; 290 u8 pd_shift; 291 u8 scratch_order; 292 293 /* Flags used when creating page-table objects for this vm */ 294 unsigned long lmem_pt_obj_flags; 295 296 /* Interval tree for pending unbind vma resources */ 297 struct rb_root_cached pending_unbind; 298 299 struct drm_i915_gem_object * 300 (*alloc_pt_dma)(struct i915_address_space *vm, int sz); 301 struct drm_i915_gem_object * 302 (*alloc_scratch_dma)(struct i915_address_space *vm, int sz); 303 304 u64 (*pte_encode)(dma_addr_t addr, 305 unsigned int pat_index, 306 u32 flags); /* Create a valid PTE */ 307 #define PTE_READ_ONLY BIT(0) 308 #define PTE_LM BIT(1) 309 310 void (*allocate_va_range)(struct i915_address_space *vm, 311 struct i915_vm_pt_stash *stash, 312 u64 start, u64 length); 313 void (*clear_range)(struct i915_address_space *vm, 314 u64 start, u64 length); 315 void (*scratch_range)(struct i915_address_space *vm, 316 u64 start, u64 length); 317 void (*insert_page)(struct i915_address_space *vm, 318 dma_addr_t addr, 319 u64 offset, 320 unsigned int pat_index, 321 u32 flags); 322 void (*insert_entries)(struct i915_address_space *vm, 323 struct i915_vma_resource *vma_res, 324 unsigned int pat_index, 325 u32 flags); 326 void (*raw_insert_page)(struct i915_address_space *vm, 327 dma_addr_t addr, 328 u64 offset, 329 unsigned int pat_index, 330 u32 flags); 331 void (*raw_insert_entries)(struct i915_address_space *vm, 332 struct i915_vma_resource *vma_res, 333 unsigned int pat_index, 334 u32 flags); 335 void (*cleanup)(struct i915_address_space *vm); 336 337 void (*foreach)(struct i915_address_space *vm, 338 u64 start, u64 length, 339 void (*fn)(struct i915_address_space *vm, 340 struct i915_page_table *pt, 341 void *data), 342 void *data); 343 344 struct i915_vma_ops vma_ops; 345 346 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 347 I915_SELFTEST_DECLARE(bool scrub_64K); 348 }; 349 350 /* 351 * The Graphics Translation Table is the way in which GEN hardware translates a 352 * Graphics Virtual Address into a Physical Address. In addition to the normal 353 * collateral associated with any va->pa translations GEN hardware also has a 354 * portion of the GTT which can be mapped by the CPU and remain both coherent 355 * and correct (in cases like swizzling). That region is referred to as GMADR in 356 * the spec. 357 */ 358 struct i915_ggtt { 359 struct i915_address_space vm; 360 361 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 362 struct resource gmadr; /* GMADR resource */ 363 resource_size_t mappable_end; /* End offset that we can CPU map */ 364 365 /** "Graphics Stolen Memory" holds the global PTEs */ 366 void __iomem *gsm; 367 void (*invalidate)(struct i915_ggtt *ggtt); 368 369 /** PPGTT used for aliasing the PPGTT with the GTT */ 370 struct i915_ppgtt *alias; 371 372 bool do_idle_maps; 373 374 int mtrr; 375 376 /** Bit 6 swizzling required for X tiling */ 377 u32 bit_6_swizzle_x; 378 /** Bit 6 swizzling required for Y tiling */ 379 u32 bit_6_swizzle_y; 380 381 u32 pin_bias; 382 383 unsigned int num_fences; 384 struct i915_fence_reg *fence_regs; 385 struct list_head fence_list; 386 387 /** 388 * List of all objects in gtt_space, currently mmaped by userspace. 389 * All objects within this list must also be on bound_list. 390 */ 391 struct list_head userfault_list; 392 393 struct mutex error_mutex; 394 struct drm_mm_node error_capture; 395 struct drm_mm_node uc_fw; 396 397 /** List of GTs mapping this GGTT */ 398 struct list_head gt_list; 399 }; 400 401 struct i915_ppgtt { 402 struct i915_address_space vm; 403 404 struct i915_page_directory *pd; 405 }; 406 407 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 408 #define i915_is_dpt(vm) ((vm)->is_dpt) 409 #define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm)) 410 411 bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915); 412 413 int __must_check 414 i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww); 415 416 static inline bool i915_vm_is_4lvl(const struct i915_address_space * vm)417 i915_vm_is_4lvl(const struct i915_address_space *vm) 418 { 419 return (vm->total - 1) >> 32; 420 } 421 422 static inline bool i915_vm_has_scratch_64K(struct i915_address_space * vm)423 i915_vm_has_scratch_64K(struct i915_address_space *vm) 424 { 425 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 426 } 427 i915_vm_min_alignment(struct i915_address_space * vm,enum intel_memory_type type)428 static inline u64 i915_vm_min_alignment(struct i915_address_space *vm, 429 enum intel_memory_type type) 430 { 431 /* avoid INTEL_MEMORY_MOCK overflow */ 432 if ((int)type >= ARRAY_SIZE(vm->min_alignment)) 433 type = INTEL_MEMORY_SYSTEM; 434 435 return vm->min_alignment[type]; 436 } 437 i915_vm_obj_min_alignment(struct i915_address_space * vm,struct drm_i915_gem_object * obj)438 static inline u64 i915_vm_obj_min_alignment(struct i915_address_space *vm, 439 struct drm_i915_gem_object *obj) 440 { 441 struct intel_memory_region *mr = READ_ONCE(obj->mm.region); 442 enum intel_memory_type type = mr ? mr->type : INTEL_MEMORY_SYSTEM; 443 444 return i915_vm_min_alignment(vm, type); 445 } 446 447 static inline bool i915_vm_has_cache_coloring(struct i915_address_space * vm)448 i915_vm_has_cache_coloring(struct i915_address_space *vm) 449 { 450 return i915_is_ggtt(vm) && vm->mm.color_adjust; 451 } 452 453 static inline struct i915_ggtt * i915_vm_to_ggtt(struct i915_address_space * vm)454 i915_vm_to_ggtt(struct i915_address_space *vm) 455 { 456 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 457 GEM_BUG_ON(!i915_is_ggtt(vm)); 458 return container_of(vm, struct i915_ggtt, vm); 459 } 460 461 static inline struct i915_ppgtt * i915_vm_to_ppgtt(struct i915_address_space * vm)462 i915_vm_to_ppgtt(struct i915_address_space *vm) 463 { 464 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 465 GEM_BUG_ON(i915_is_ggtt_or_dpt(vm)); 466 return container_of(vm, struct i915_ppgtt, vm); 467 } 468 469 static inline struct i915_address_space * i915_vm_get(struct i915_address_space * vm)470 i915_vm_get(struct i915_address_space *vm) 471 { 472 kref_get(&vm->ref); 473 return vm; 474 } 475 476 static inline struct i915_address_space * i915_vm_tryget(struct i915_address_space * vm)477 i915_vm_tryget(struct i915_address_space *vm) 478 { 479 return kref_get_unless_zero(&vm->ref) ? vm : NULL; 480 } 481 assert_vm_alive(struct i915_address_space * vm)482 static inline void assert_vm_alive(struct i915_address_space *vm) 483 { 484 GEM_BUG_ON(!kref_read(&vm->ref)); 485 } 486 487 /** 488 * i915_vm_resv_get - Obtain a reference on the vm's reservation lock 489 * @vm: The vm whose reservation lock we want to share. 490 * 491 * Return: A pointer to the vm's reservation lock. 492 */ i915_vm_resv_get(struct i915_address_space * vm)493 static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm) 494 { 495 kref_get(&vm->resv_ref); 496 return &vm->_resv; 497 } 498 499 void i915_vm_release(struct kref *kref); 500 501 void i915_vm_resv_release(struct kref *kref); 502 i915_vm_put(struct i915_address_space * vm)503 static inline void i915_vm_put(struct i915_address_space *vm) 504 { 505 kref_put(&vm->ref, i915_vm_release); 506 } 507 508 /** 509 * i915_vm_resv_put - Release a reference on the vm's reservation lock 510 * @vm: The vm whose reservation lock reference we want to release 511 */ i915_vm_resv_put(struct i915_address_space * vm)512 static inline void i915_vm_resv_put(struct i915_address_space *vm) 513 { 514 kref_put(&vm->resv_ref, i915_vm_resv_release); 515 } 516 517 void i915_address_space_init(struct i915_address_space *vm, int subclass); 518 void i915_address_space_fini(struct i915_address_space *vm); 519 i915_pte_index(u64 address,unsigned int pde_shift)520 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 521 { 522 const u32 mask = NUM_PTE(pde_shift) - 1; 523 524 return (address >> PAGE_SHIFT) & mask; 525 } 526 527 /* 528 * Helper to counts the number of PTEs within the given length. This count 529 * does not cross a page table boundary, so the max value would be 530 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 531 */ i915_pte_count(u64 addr,u64 length,unsigned int pde_shift)532 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 533 { 534 const u64 mask = ~((1ULL << pde_shift) - 1); 535 u64 end; 536 537 GEM_BUG_ON(length == 0); 538 GEM_BUG_ON(offset_in_page(addr | length)); 539 540 end = addr + length; 541 542 if ((addr & mask) != (end & mask)) 543 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 544 545 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 546 } 547 i915_pde_index(u64 addr,u32 shift)548 static inline u32 i915_pde_index(u64 addr, u32 shift) 549 { 550 return (addr >> shift) & I915_PDE_MASK; 551 } 552 553 static inline struct i915_page_table * i915_pt_entry(const struct i915_page_directory * const pd,const unsigned short n)554 i915_pt_entry(const struct i915_page_directory * const pd, 555 const unsigned short n) 556 { 557 return pd->entry[n]; 558 } 559 560 static inline struct i915_page_directory * i915_pd_entry(const struct i915_page_directory * const pdp,const unsigned short n)561 i915_pd_entry(const struct i915_page_directory * const pdp, 562 const unsigned short n) 563 { 564 return pdp->entry[n]; 565 } 566 567 static inline dma_addr_t i915_page_dir_dma_addr(const struct i915_ppgtt * ppgtt,const unsigned int n)568 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 569 { 570 struct i915_page_table *pt = ppgtt->pd->entry[n]; 571 572 return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]); 573 } 574 575 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt, 576 unsigned long lmem_pt_obj_flags); 577 void intel_ggtt_bind_vma(struct i915_address_space *vm, 578 struct i915_vm_pt_stash *stash, 579 struct i915_vma_resource *vma_res, 580 unsigned int pat_index, 581 u32 flags); 582 void intel_ggtt_unbind_vma(struct i915_address_space *vm, 583 struct i915_vma_resource *vma_res); 584 585 int i915_ggtt_probe_hw(struct drm_i915_private *i915); 586 int i915_ggtt_init_hw(struct drm_i915_private *i915); 587 int i915_ggtt_enable_hw(struct drm_i915_private *i915); 588 int i915_init_ggtt(struct drm_i915_private *i915); 589 void i915_ggtt_driver_release(struct drm_i915_private *i915); 590 void i915_ggtt_driver_late_release(struct drm_i915_private *i915); 591 struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915); 592 i915_ggtt_has_aperture(const struct i915_ggtt * ggtt)593 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 594 { 595 return ggtt->mappable_end > 0; 596 } 597 598 int i915_ppgtt_init_hw(struct intel_gt *gt); 599 600 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt, 601 unsigned long lmem_pt_obj_flags); 602 603 void i915_ggtt_suspend_vm(struct i915_address_space *vm); 604 bool i915_ggtt_resume_vm(struct i915_address_space *vm); 605 void i915_ggtt_suspend(struct i915_ggtt *gtt); 606 void i915_ggtt_resume(struct i915_ggtt *ggtt); 607 608 void 609 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); 610 611 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 612 #define fill32_px(px, v) do { \ 613 u64 v__ = lower_32_bits(v); \ 614 fill_px((px), v__ << 32 | v__); \ 615 } while (0) 616 617 int setup_scratch_page(struct i915_address_space *vm); 618 void free_scratch(struct i915_address_space *vm); 619 620 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); 621 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); 622 struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz); 623 struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 624 struct i915_page_directory *__alloc_pd(int npde); 625 626 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 627 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 628 629 void free_px(struct i915_address_space *vm, 630 struct i915_page_table *pt, int lvl); 631 #define free_pt(vm, px) free_px(vm, px, 0) 632 #define free_pd(vm, px) free_px(vm, px_pt(px), 1) 633 634 void 635 __set_pd_entry(struct i915_page_directory * const pd, 636 const unsigned short idx, 637 struct i915_page_table *pt, 638 u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 639 640 #define set_pd_entry(pd, idx, to) \ 641 __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode) 642 643 void 644 clear_pd_entry(struct i915_page_directory * const pd, 645 const unsigned short idx, 646 const struct drm_i915_gem_object * const scratch); 647 648 bool 649 release_pd_entry(struct i915_page_directory * const pd, 650 const unsigned short idx, 651 struct i915_page_table * const pt, 652 const struct drm_i915_gem_object * const scratch); 653 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 654 655 void ppgtt_bind_vma(struct i915_address_space *vm, 656 struct i915_vm_pt_stash *stash, 657 struct i915_vma_resource *vma_res, 658 unsigned int pat_index, 659 u32 flags); 660 void ppgtt_unbind_vma(struct i915_address_space *vm, 661 struct i915_vma_resource *vma_res); 662 663 void gtt_write_workarounds(struct intel_gt *gt); 664 665 void setup_private_pat(struct intel_gt *gt); 666 667 int i915_vm_alloc_pt_stash(struct i915_address_space *vm, 668 struct i915_vm_pt_stash *stash, 669 u64 size); 670 int i915_vm_map_pt_stash(struct i915_address_space *vm, 671 struct i915_vm_pt_stash *stash); 672 void i915_vm_free_pt_stash(struct i915_address_space *vm, 673 struct i915_vm_pt_stash *stash); 674 675 struct i915_vma * 676 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size); 677 678 struct i915_vma * 679 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size); 680 681 static inline struct sgt_dma { 682 struct scatterlist *sg; 683 dma_addr_t dma, max; sgt_dma(struct i915_vma_resource * vma_res)684 } sgt_dma(struct i915_vma_resource *vma_res) { 685 struct scatterlist *sg = vma_res->bi.pages->sgl; 686 dma_addr_t addr = sg_dma_address(sg); 687 688 return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; 689 } 690 691 #endif 692