1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
3
4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/spinlock.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
22
23 #include "rockchip_i2s_tdm.h"
24
25 #define DRV_NAME "rockchip-i2s-tdm"
26
27 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */
28 #define MULTIPLEX_CH_MAX 10
29
30 #define TRCM_TXRX 0
31 #define TRCM_TX 1
32 #define TRCM_RX 2
33
34 struct txrx_config {
35 u32 addr;
36 u32 reg;
37 u32 txonly;
38 u32 rxonly;
39 };
40
41 struct rk_i2s_soc_data {
42 u32 softrst_offset;
43 u32 grf_reg_offset;
44 u32 grf_shift;
45 int config_count;
46 const struct txrx_config *configs;
47 int (*init)(struct device *dev, u32 addr);
48 };
49
50 struct rk_i2s_tdm_dev {
51 struct device *dev;
52 struct clk *hclk;
53 struct clk *mclk_tx;
54 struct clk *mclk_rx;
55 struct regmap *regmap;
56 struct regmap *grf;
57 struct snd_dmaengine_dai_dma_data capture_dma_data;
58 struct snd_dmaengine_dai_dma_data playback_dma_data;
59 struct reset_control *tx_reset;
60 struct reset_control *rx_reset;
61 struct rk_i2s_soc_data *soc_data;
62 bool is_master_mode;
63 bool io_multiplex;
64 bool tdm_mode;
65 unsigned int frame_width;
66 unsigned int clk_trcm;
67 unsigned int i2s_sdis[CH_GRP_MAX];
68 unsigned int i2s_sdos[CH_GRP_MAX];
69 int refcount;
70 spinlock_t lock; /* xfer lock */
71 bool has_playback;
72 bool has_capture;
73 struct snd_soc_dai_driver *dai;
74 unsigned int mclk_rx_freq;
75 unsigned int mclk_tx_freq;
76 };
77
to_ch_num(unsigned int val)78 static int to_ch_num(unsigned int val)
79 {
80 switch (val) {
81 case I2S_CHN_4:
82 return 4;
83 case I2S_CHN_6:
84 return 6;
85 case I2S_CHN_8:
86 return 8;
87 default:
88 return 2;
89 }
90 }
91
i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev * i2s_tdm)92 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
93 {
94 clk_disable_unprepare(i2s_tdm->mclk_tx);
95 clk_disable_unprepare(i2s_tdm->mclk_rx);
96 }
97
98 /**
99 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
100 * failure.
101 * @i2s_tdm: rk_i2s_tdm_dev struct
102 *
103 * This function attempts to enable all mclk clocks, but cleans up after
104 * itself on failure. Guarantees to balance its calls.
105 *
106 * Returns success (0) or negative errno.
107 */
i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev * i2s_tdm)108 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
109 {
110 int ret = 0;
111
112 ret = clk_prepare_enable(i2s_tdm->mclk_tx);
113 if (ret)
114 goto err_mclk_tx;
115 ret = clk_prepare_enable(i2s_tdm->mclk_rx);
116 if (ret)
117 goto err_mclk_rx;
118
119 return 0;
120
121 err_mclk_rx:
122 clk_disable_unprepare(i2s_tdm->mclk_tx);
123 err_mclk_tx:
124 return ret;
125 }
126
i2s_tdm_runtime_suspend(struct device * dev)127 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
128 {
129 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
130
131 regcache_cache_only(i2s_tdm->regmap, true);
132 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
133
134 clk_disable_unprepare(i2s_tdm->hclk);
135
136 return 0;
137 }
138
i2s_tdm_runtime_resume(struct device * dev)139 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
140 {
141 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
142 int ret;
143
144 ret = clk_prepare_enable(i2s_tdm->hclk);
145 if (ret)
146 goto err_hclk;
147
148 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
149 if (ret)
150 goto err_mclk;
151
152 regcache_cache_only(i2s_tdm->regmap, false);
153 regcache_mark_dirty(i2s_tdm->regmap);
154
155 ret = regcache_sync(i2s_tdm->regmap);
156 if (ret)
157 goto err_regcache;
158
159 return 0;
160
161 err_regcache:
162 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
163 err_mclk:
164 clk_disable_unprepare(i2s_tdm->hclk);
165 err_hclk:
166 return ret;
167 }
168
to_info(struct snd_soc_dai * dai)169 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
170 {
171 return snd_soc_dai_get_drvdata(dai);
172 }
173
174 /*
175 * Makes sure that both tx and rx are reset at the same time to sync lrck
176 * when clk_trcm > 0.
177 */
rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev * i2s_tdm)178 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
179 {
180 /* This is technically race-y.
181 *
182 * In an ideal world, we could atomically assert both resets at the
183 * same time, through an atomic bulk reset API. This API however does
184 * not exist, so what the downstream vendor code used to do was
185 * implement half a reset controller here and require the CRU to be
186 * passed to the driver as a device tree node. Violating abstractions
187 * like that is bad, especially when it influences something like the
188 * bindings which are supposed to describe the hardware, not whatever
189 * workarounds the driver needs, so it was dropped.
190 *
191 * In practice, asserting the resets one by one appears to work just
192 * fine for playback. During duplex (playback + capture) operation,
193 * this might become an issue, but that should be solved by the
194 * implementation of the aforementioned API, not by shoving a reset
195 * controller into an audio driver.
196 */
197
198 reset_control_assert(i2s_tdm->tx_reset);
199 reset_control_assert(i2s_tdm->rx_reset);
200 udelay(10);
201 reset_control_deassert(i2s_tdm->tx_reset);
202 reset_control_deassert(i2s_tdm->rx_reset);
203 udelay(10);
204 }
205
rockchip_snd_reset(struct reset_control * rc)206 static void rockchip_snd_reset(struct reset_control *rc)
207 {
208 reset_control_assert(rc);
209 udelay(10);
210 reset_control_deassert(rc);
211 udelay(10);
212 }
213
rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev * i2s_tdm,unsigned int clr)214 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
215 unsigned int clr)
216 {
217 unsigned int xfer_mask = 0;
218 unsigned int xfer_val = 0;
219 unsigned int val;
220 int retry = 10;
221 bool tx = clr & I2S_CLR_TXC;
222 bool rx = clr & I2S_CLR_RXC;
223
224 if (!(rx || tx))
225 return;
226
227 if (tx) {
228 xfer_mask = I2S_XFER_TXS_START;
229 xfer_val = I2S_XFER_TXS_STOP;
230 }
231 if (rx) {
232 xfer_mask |= I2S_XFER_RXS_START;
233 xfer_val |= I2S_XFER_RXS_STOP;
234 }
235
236 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
237 udelay(150);
238 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
239
240 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
241 /* Wait on the clear operation to finish */
242 while (val) {
243 udelay(15);
244 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
245 retry--;
246 if (!retry) {
247 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
248 tx ? "tx" : "", rx ? "rx" : "");
249 if (rx && tx)
250 rockchip_snd_xfer_sync_reset(i2s_tdm);
251 else if (tx)
252 rockchip_snd_reset(i2s_tdm->tx_reset);
253 else if (rx)
254 rockchip_snd_reset(i2s_tdm->rx_reset);
255 break;
256 }
257 }
258 }
259
rockchip_enable_tde(struct regmap * regmap)260 static inline void rockchip_enable_tde(struct regmap *regmap)
261 {
262 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
263 I2S_DMACR_TDE_ENABLE);
264 }
265
rockchip_disable_tde(struct regmap * regmap)266 static inline void rockchip_disable_tde(struct regmap *regmap)
267 {
268 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
269 I2S_DMACR_TDE_DISABLE);
270 }
271
rockchip_enable_rde(struct regmap * regmap)272 static inline void rockchip_enable_rde(struct regmap *regmap)
273 {
274 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
275 I2S_DMACR_RDE_ENABLE);
276 }
277
rockchip_disable_rde(struct regmap * regmap)278 static inline void rockchip_disable_rde(struct regmap *regmap)
279 {
280 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
281 I2S_DMACR_RDE_DISABLE);
282 }
283
284 /* only used when clk_trcm > 0 */
rockchip_snd_txrxctrl(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,int on)285 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
286 struct snd_soc_dai *dai, int on)
287 {
288 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
289 unsigned long flags;
290
291 spin_lock_irqsave(&i2s_tdm->lock, flags);
292 if (on) {
293 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
294 rockchip_enable_tde(i2s_tdm->regmap);
295 else
296 rockchip_enable_rde(i2s_tdm->regmap);
297
298 if (++i2s_tdm->refcount == 1) {
299 rockchip_snd_xfer_sync_reset(i2s_tdm);
300 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
301 I2S_XFER_TXS_START |
302 I2S_XFER_RXS_START,
303 I2S_XFER_TXS_START |
304 I2S_XFER_RXS_START);
305 }
306 } else {
307 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
308 rockchip_disable_tde(i2s_tdm->regmap);
309 else
310 rockchip_disable_rde(i2s_tdm->regmap);
311
312 if (--i2s_tdm->refcount == 0) {
313 rockchip_snd_xfer_clear(i2s_tdm,
314 I2S_CLR_TXC | I2S_CLR_RXC);
315 }
316 }
317 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
318 }
319
rockchip_snd_txctrl(struct rk_i2s_tdm_dev * i2s_tdm,int on)320 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
321 {
322 if (on) {
323 rockchip_enable_tde(i2s_tdm->regmap);
324
325 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
326 I2S_XFER_TXS_START,
327 I2S_XFER_TXS_START);
328 } else {
329 rockchip_disable_tde(i2s_tdm->regmap);
330
331 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
332 }
333 }
334
rockchip_snd_rxctrl(struct rk_i2s_tdm_dev * i2s_tdm,int on)335 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
336 {
337 if (on) {
338 rockchip_enable_rde(i2s_tdm->regmap);
339
340 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
341 I2S_XFER_RXS_START,
342 I2S_XFER_RXS_START);
343 } else {
344 rockchip_disable_rde(i2s_tdm->regmap);
345
346 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
347 }
348 }
349
rockchip_i2s_tdm_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)350 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
351 unsigned int fmt)
352 {
353 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
354 unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
355 int ret;
356 bool is_tdm = i2s_tdm->tdm_mode;
357
358 ret = pm_runtime_resume_and_get(cpu_dai->dev);
359 if (ret < 0 && ret != -EACCES)
360 return ret;
361
362 mask = I2S_CKR_MSS_MASK;
363 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
364 case SND_SOC_DAIFMT_BP_FP:
365 val = I2S_CKR_MSS_MASTER;
366 i2s_tdm->is_master_mode = true;
367 break;
368 case SND_SOC_DAIFMT_BC_FC:
369 val = I2S_CKR_MSS_SLAVE;
370 i2s_tdm->is_master_mode = false;
371 break;
372 default:
373 ret = -EINVAL;
374 goto err_pm_put;
375 }
376
377 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
378
379 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
380 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
381 case SND_SOC_DAIFMT_NB_NF:
382 val = I2S_CKR_CKP_NORMAL |
383 I2S_CKR_TLP_NORMAL |
384 I2S_CKR_RLP_NORMAL;
385 break;
386 case SND_SOC_DAIFMT_NB_IF:
387 val = I2S_CKR_CKP_NORMAL |
388 I2S_CKR_TLP_INVERTED |
389 I2S_CKR_RLP_INVERTED;
390 break;
391 case SND_SOC_DAIFMT_IB_NF:
392 val = I2S_CKR_CKP_INVERTED |
393 I2S_CKR_TLP_NORMAL |
394 I2S_CKR_RLP_NORMAL;
395 break;
396 case SND_SOC_DAIFMT_IB_IF:
397 val = I2S_CKR_CKP_INVERTED |
398 I2S_CKR_TLP_INVERTED |
399 I2S_CKR_RLP_INVERTED;
400 break;
401 default:
402 ret = -EINVAL;
403 goto err_pm_put;
404 }
405
406 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
407
408 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
409 case SND_SOC_DAIFMT_RIGHT_J:
410 txcr_val = I2S_TXCR_IBM_RSJM;
411 rxcr_val = I2S_RXCR_IBM_RSJM;
412 break;
413 case SND_SOC_DAIFMT_LEFT_J:
414 txcr_val = I2S_TXCR_IBM_LSJM;
415 rxcr_val = I2S_RXCR_IBM_LSJM;
416 break;
417 case SND_SOC_DAIFMT_I2S:
418 txcr_val = I2S_TXCR_IBM_NORMAL;
419 rxcr_val = I2S_RXCR_IBM_NORMAL;
420 break;
421 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
422 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
423 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
424 break;
425 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
426 txcr_val = I2S_TXCR_TFS_PCM;
427 rxcr_val = I2S_RXCR_TFS_PCM;
428 break;
429 default:
430 ret = -EINVAL;
431 goto err_pm_put;
432 }
433
434 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
435 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
436
437 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
438 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
439
440 if (is_tdm) {
441 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
442 case SND_SOC_DAIFMT_RIGHT_J:
443 val = I2S_TXCR_TFS_TDM_I2S;
444 tdm_val = TDM_SHIFT_CTRL(2);
445 break;
446 case SND_SOC_DAIFMT_LEFT_J:
447 val = I2S_TXCR_TFS_TDM_I2S;
448 tdm_val = TDM_SHIFT_CTRL(1);
449 break;
450 case SND_SOC_DAIFMT_I2S:
451 val = I2S_TXCR_TFS_TDM_I2S;
452 tdm_val = TDM_SHIFT_CTRL(0);
453 break;
454 case SND_SOC_DAIFMT_DSP_A:
455 val = I2S_TXCR_TFS_TDM_PCM;
456 tdm_val = TDM_SHIFT_CTRL(0);
457 break;
458 case SND_SOC_DAIFMT_DSP_B:
459 val = I2S_TXCR_TFS_TDM_PCM;
460 tdm_val = TDM_SHIFT_CTRL(2);
461 break;
462 default:
463 ret = -EINVAL;
464 goto err_pm_put;
465 }
466
467 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
468 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
469
470 mask = I2S_TXCR_TFS_MASK;
471 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
472 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
473
474 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
475 TDM_SHIFT_CTRL_MSK;
476 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
477 mask, tdm_val);
478 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
479 mask, tdm_val);
480 }
481
482 err_pm_put:
483 pm_runtime_put(cpu_dai->dev);
484
485 return ret;
486 }
487
rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)488 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
489 struct rk_i2s_tdm_dev *i2s_tdm)
490 {
491 int stream;
492
493 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
494 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
495 rockchip_disable_tde(i2s_tdm->regmap);
496 else
497 rockchip_disable_rde(i2s_tdm->regmap);
498
499 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
500 }
501
rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)502 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
503 struct rk_i2s_tdm_dev *i2s_tdm)
504 {
505 int stream;
506
507 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
508 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
509 rockchip_enable_tde(i2s_tdm->regmap);
510 else
511 rockchip_enable_rde(i2s_tdm->regmap);
512
513 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
514 I2S_XFER_TXS_START |
515 I2S_XFER_RXS_START,
516 I2S_XFER_TXS_START |
517 I2S_XFER_RXS_START);
518 }
519
rockchip_i2s_ch_to_io(unsigned int ch,bool substream_capture)520 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
521 {
522 if (substream_capture) {
523 switch (ch) {
524 case I2S_CHN_4:
525 return I2S_IO_6CH_OUT_4CH_IN;
526 case I2S_CHN_6:
527 return I2S_IO_4CH_OUT_6CH_IN;
528 case I2S_CHN_8:
529 return I2S_IO_2CH_OUT_8CH_IN;
530 default:
531 return I2S_IO_8CH_OUT_2CH_IN;
532 }
533 } else {
534 switch (ch) {
535 case I2S_CHN_4:
536 return I2S_IO_4CH_OUT_6CH_IN;
537 case I2S_CHN_6:
538 return I2S_IO_6CH_OUT_4CH_IN;
539 case I2S_CHN_8:
540 return I2S_IO_8CH_OUT_2CH_IN;
541 default:
542 return I2S_IO_2CH_OUT_8CH_IN;
543 }
544 }
545 }
546
rockchip_i2s_io_multiplex(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)547 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
548 struct snd_soc_dai *dai)
549 {
550 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
551 int usable_chs = MULTIPLEX_CH_MAX;
552 unsigned int val = 0;
553
554 if (!i2s_tdm->io_multiplex)
555 return 0;
556
557 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
558 dev_err(i2s_tdm->dev,
559 "io multiplex not supported for this device\n");
560 return -EINVAL;
561 }
562
563 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
564 struct snd_pcm_str *playback_str =
565 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
566
567 if (playback_str->substream_opened) {
568 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
569 val &= I2S_TXCR_CSR_MASK;
570 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
571 }
572
573 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
574 val &= I2S_RXCR_CSR_MASK;
575
576 if (to_ch_num(val) > usable_chs) {
577 dev_err(i2s_tdm->dev,
578 "Capture channels (%d) > usable channels (%d)\n",
579 to_ch_num(val), usable_chs);
580 return -EINVAL;
581 }
582
583 rockchip_i2s_ch_to_io(val, true);
584 } else {
585 struct snd_pcm_str *capture_str =
586 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
587
588 if (capture_str->substream_opened) {
589 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
590 val &= I2S_RXCR_CSR_MASK;
591 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
592 }
593
594 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
595 val &= I2S_TXCR_CSR_MASK;
596
597 if (to_ch_num(val) > usable_chs) {
598 dev_err(i2s_tdm->dev,
599 "Playback channels (%d) > usable channels (%d)\n",
600 to_ch_num(val), usable_chs);
601 return -EINVAL;
602 }
603 }
604
605 val <<= i2s_tdm->soc_data->grf_shift;
606 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
607 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
608
609 return 0;
610 }
611
rockchip_i2s_trcm_mode(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,unsigned int div_bclk,unsigned int div_lrck,unsigned int fmt)612 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
613 struct snd_soc_dai *dai,
614 unsigned int div_bclk,
615 unsigned int div_lrck,
616 unsigned int fmt)
617 {
618 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
619 unsigned long flags;
620
621 if (!i2s_tdm->clk_trcm)
622 return 0;
623
624 spin_lock_irqsave(&i2s_tdm->lock, flags);
625 if (i2s_tdm->refcount)
626 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
627
628 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
629 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
630 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
631 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
632 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
633 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
634
635 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
636 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
637 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
638 fmt);
639 else
640 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
641 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
642 fmt);
643
644 if (i2s_tdm->refcount)
645 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
646 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
647
648 return 0;
649 }
650
rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai * cpu_dai,int stream,unsigned int freq,int dir)651 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
652 unsigned int freq, int dir)
653 {
654 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
655
656 if (i2s_tdm->clk_trcm) {
657 i2s_tdm->mclk_tx_freq = freq;
658 i2s_tdm->mclk_rx_freq = freq;
659 } else {
660 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
661 i2s_tdm->mclk_tx_freq = freq;
662 else
663 i2s_tdm->mclk_rx_freq = freq;
664 }
665
666 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
667 stream ? "rx" : "tx", freq);
668
669 return 0;
670 }
671
rockchip_i2s_tdm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)672 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
673 struct snd_pcm_hw_params *params,
674 struct snd_soc_dai *dai)
675 {
676 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
677 unsigned int val = 0;
678 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
679 int err;
680
681 if (i2s_tdm->is_master_mode) {
682 struct clk *mclk;
683
684 if (i2s_tdm->clk_trcm == TRCM_TX) {
685 mclk = i2s_tdm->mclk_tx;
686 mclk_rate = i2s_tdm->mclk_tx_freq;
687 } else if (i2s_tdm->clk_trcm == TRCM_RX) {
688 mclk = i2s_tdm->mclk_rx;
689 mclk_rate = i2s_tdm->mclk_rx_freq;
690 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
691 mclk = i2s_tdm->mclk_tx;
692 mclk_rate = i2s_tdm->mclk_tx_freq;
693 } else {
694 mclk = i2s_tdm->mclk_rx;
695 mclk_rate = i2s_tdm->mclk_rx_freq;
696 }
697
698 err = clk_set_rate(mclk, mclk_rate);
699 if (err)
700 return err;
701
702 mclk_rate = clk_get_rate(mclk);
703 bclk_rate = i2s_tdm->frame_width * params_rate(params);
704 if (!bclk_rate)
705 return -EINVAL;
706
707 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
708 div_lrck = bclk_rate / params_rate(params);
709 }
710
711 switch (params_format(params)) {
712 case SNDRV_PCM_FORMAT_S8:
713 val |= I2S_TXCR_VDW(8);
714 break;
715 case SNDRV_PCM_FORMAT_S16_LE:
716 val |= I2S_TXCR_VDW(16);
717 break;
718 case SNDRV_PCM_FORMAT_S20_3LE:
719 val |= I2S_TXCR_VDW(20);
720 break;
721 case SNDRV_PCM_FORMAT_S24_LE:
722 val |= I2S_TXCR_VDW(24);
723 break;
724 case SNDRV_PCM_FORMAT_S32_LE:
725 val |= I2S_TXCR_VDW(32);
726 break;
727 default:
728 return -EINVAL;
729 }
730
731 switch (params_channels(params)) {
732 case 8:
733 val |= I2S_CHN_8;
734 break;
735 case 6:
736 val |= I2S_CHN_6;
737 break;
738 case 4:
739 val |= I2S_CHN_4;
740 break;
741 case 2:
742 val |= I2S_CHN_2;
743 break;
744 default:
745 return -EINVAL;
746 }
747
748 if (i2s_tdm->clk_trcm) {
749 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
750 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
751 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
752 I2S_CLKDIV_TXM_MASK,
753 I2S_CLKDIV_TXM(div_bclk));
754 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
755 I2S_CKR_TSD_MASK,
756 I2S_CKR_TSD(div_lrck));
757 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
758 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
759 val);
760 } else {
761 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
762 I2S_CLKDIV_RXM_MASK,
763 I2S_CLKDIV_RXM(div_bclk));
764 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
765 I2S_CKR_RSD_MASK,
766 I2S_CKR_RSD(div_lrck));
767 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
768 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
769 val);
770 }
771
772 return rockchip_i2s_io_multiplex(substream, dai);
773 }
774
rockchip_i2s_tdm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)775 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
776 int cmd, struct snd_soc_dai *dai)
777 {
778 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
779
780 switch (cmd) {
781 case SNDRV_PCM_TRIGGER_START:
782 case SNDRV_PCM_TRIGGER_RESUME:
783 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
784 if (i2s_tdm->clk_trcm)
785 rockchip_snd_txrxctrl(substream, dai, 1);
786 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
787 rockchip_snd_rxctrl(i2s_tdm, 1);
788 else
789 rockchip_snd_txctrl(i2s_tdm, 1);
790 break;
791 case SNDRV_PCM_TRIGGER_SUSPEND:
792 case SNDRV_PCM_TRIGGER_STOP:
793 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
794 if (i2s_tdm->clk_trcm)
795 rockchip_snd_txrxctrl(substream, dai, 0);
796 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
797 rockchip_snd_rxctrl(i2s_tdm, 0);
798 else
799 rockchip_snd_txctrl(i2s_tdm, 0);
800 break;
801 default:
802 return -EINVAL;
803 }
804
805 return 0;
806 }
807
rockchip_i2s_tdm_dai_probe(struct snd_soc_dai * dai)808 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
809 {
810 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
811
812 if (i2s_tdm->has_capture)
813 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data);
814 if (i2s_tdm->has_playback)
815 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data);
816
817 return 0;
818 }
819
rockchip_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)820 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
821 unsigned int tx_mask, unsigned int rx_mask,
822 int slots, int slot_width)
823 {
824 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
825 unsigned int mask, val;
826
827 i2s_tdm->tdm_mode = true;
828 i2s_tdm->frame_width = slots * slot_width;
829 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
830 val = TDM_SLOT_BIT_WIDTH(slot_width) |
831 TDM_FRAME_WIDTH(slots * slot_width);
832 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
833 mask, val);
834 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
835 mask, val);
836
837 return 0;
838 }
839
rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)840 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
841 unsigned int ratio)
842 {
843 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
844
845 if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
846 return -EINVAL;
847
848 i2s_tdm->frame_width = ratio;
849
850 return 0;
851 }
852
853 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
854 .probe = rockchip_i2s_tdm_dai_probe,
855 .hw_params = rockchip_i2s_tdm_hw_params,
856 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
857 .set_fmt = rockchip_i2s_tdm_set_fmt,
858 .set_sysclk = rockchip_i2s_tdm_set_sysclk,
859 .set_tdm_slot = rockchip_dai_tdm_slot,
860 .trigger = rockchip_i2s_tdm_trigger,
861 };
862
863 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
864 .name = DRV_NAME,
865 .legacy_dai_naming = 1,
866 };
867
rockchip_i2s_tdm_wr_reg(struct device * dev,unsigned int reg)868 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
869 {
870 switch (reg) {
871 case I2S_TXCR:
872 case I2S_RXCR:
873 case I2S_CKR:
874 case I2S_DMACR:
875 case I2S_INTCR:
876 case I2S_XFER:
877 case I2S_CLR:
878 case I2S_TXDR:
879 case I2S_TDM_TXCR:
880 case I2S_TDM_RXCR:
881 case I2S_CLKDIV:
882 return true;
883 default:
884 return false;
885 }
886 }
887
rockchip_i2s_tdm_rd_reg(struct device * dev,unsigned int reg)888 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
889 {
890 switch (reg) {
891 case I2S_TXCR:
892 case I2S_RXCR:
893 case I2S_CKR:
894 case I2S_DMACR:
895 case I2S_INTCR:
896 case I2S_XFER:
897 case I2S_CLR:
898 case I2S_TXDR:
899 case I2S_RXDR:
900 case I2S_TXFIFOLR:
901 case I2S_INTSR:
902 case I2S_RXFIFOLR:
903 case I2S_TDM_TXCR:
904 case I2S_TDM_RXCR:
905 case I2S_CLKDIV:
906 return true;
907 default:
908 return false;
909 }
910 }
911
rockchip_i2s_tdm_volatile_reg(struct device * dev,unsigned int reg)912 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
913 {
914 switch (reg) {
915 case I2S_TXFIFOLR:
916 case I2S_INTSR:
917 case I2S_CLR:
918 case I2S_TXDR:
919 case I2S_RXDR:
920 case I2S_RXFIFOLR:
921 return true;
922 default:
923 return false;
924 }
925 }
926
rockchip_i2s_tdm_precious_reg(struct device * dev,unsigned int reg)927 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
928 {
929 if (reg == I2S_RXDR)
930 return true;
931 return false;
932 }
933
934 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
935 {0x00, 0x7200000f},
936 {0x04, 0x01c8000f},
937 {0x08, 0x00001f1f},
938 {0x10, 0x001f0000},
939 {0x14, 0x01f00000},
940 {0x30, 0x00003eff},
941 {0x34, 0x00003eff},
942 {0x38, 0x00000707},
943 };
944
945 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
946 .reg_bits = 32,
947 .reg_stride = 4,
948 .val_bits = 32,
949 .max_register = I2S_CLKDIV,
950 .reg_defaults = rockchip_i2s_tdm_reg_defaults,
951 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
952 .writeable_reg = rockchip_i2s_tdm_wr_reg,
953 .readable_reg = rockchip_i2s_tdm_rd_reg,
954 .volatile_reg = rockchip_i2s_tdm_volatile_reg,
955 .precious_reg = rockchip_i2s_tdm_precious_reg,
956 .cache_type = REGCACHE_FLAT,
957 };
958
common_soc_init(struct device * dev,u32 addr)959 static int common_soc_init(struct device *dev, u32 addr)
960 {
961 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
962 const struct txrx_config *configs = i2s_tdm->soc_data->configs;
963 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
964 int i;
965
966 if (trcm == TRCM_TXRX)
967 return 0;
968
969 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
970 dev_err(i2s_tdm->dev,
971 "no grf present but non-txrx TRCM specified\n");
972 return -EINVAL;
973 }
974
975 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
976 if (addr != configs[i].addr)
977 continue;
978 reg = configs[i].reg;
979 if (trcm == TRCM_TX)
980 val = configs[i].txonly;
981 else
982 val = configs[i].rxonly;
983
984 if (reg)
985 regmap_write(i2s_tdm->grf, reg, val);
986 }
987
988 return 0;
989 }
990
991 static const struct txrx_config px30_txrx_config[] = {
992 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
993 };
994
995 static const struct txrx_config rk1808_txrx_config[] = {
996 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
997 };
998
999 static const struct txrx_config rk3308_txrx_config[] = {
1000 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
1001 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1002 };
1003
1004 static const struct txrx_config rk3568_txrx_config[] = {
1005 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1006 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1007 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1008 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1009 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1010 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1011 };
1012
1013 static const struct txrx_config rv1126_txrx_config[] = {
1014 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1015 };
1016
1017 static struct rk_i2s_soc_data px30_i2s_soc_data = {
1018 .softrst_offset = 0x0300,
1019 .configs = px30_txrx_config,
1020 .config_count = ARRAY_SIZE(px30_txrx_config),
1021 .init = common_soc_init,
1022 };
1023
1024 static struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1025 .softrst_offset = 0x0300,
1026 .configs = rk1808_txrx_config,
1027 .config_count = ARRAY_SIZE(rk1808_txrx_config),
1028 .init = common_soc_init,
1029 };
1030
1031 static struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1032 .softrst_offset = 0x0400,
1033 .grf_reg_offset = 0x0308,
1034 .grf_shift = 5,
1035 .configs = rk3308_txrx_config,
1036 .config_count = ARRAY_SIZE(rk3308_txrx_config),
1037 .init = common_soc_init,
1038 };
1039
1040 static struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1041 .softrst_offset = 0x0400,
1042 .configs = rk3568_txrx_config,
1043 .config_count = ARRAY_SIZE(rk3568_txrx_config),
1044 .init = common_soc_init,
1045 };
1046
1047 static struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1048 .softrst_offset = 0x0300,
1049 .configs = rv1126_txrx_config,
1050 .config_count = ARRAY_SIZE(rv1126_txrx_config),
1051 .init = common_soc_init,
1052 };
1053
1054 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1055 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1056 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1057 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1058 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1059 { .compatible = "rockchip,rk3588-i2s-tdm" },
1060 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1061 {},
1062 };
1063
1064 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1065 .ops = &rockchip_i2s_tdm_dai_ops,
1066 };
1067
rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev * i2s_tdm)1068 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1069 {
1070 struct snd_soc_dai_driver *dai;
1071 struct property *dma_names;
1072 const char *dma_name;
1073 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1074 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1075 SNDRV_PCM_FMTBIT_S32_LE);
1076 struct device_node *node = i2s_tdm->dev->of_node;
1077
1078 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1079 if (!strcmp(dma_name, "tx"))
1080 i2s_tdm->has_playback = true;
1081 if (!strcmp(dma_name, "rx"))
1082 i2s_tdm->has_capture = true;
1083 }
1084
1085 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1086 sizeof(*dai), GFP_KERNEL);
1087 if (!dai)
1088 return -ENOMEM;
1089
1090 if (i2s_tdm->has_playback) {
1091 dai->playback.stream_name = "Playback";
1092 dai->playback.channels_min = 2;
1093 dai->playback.channels_max = 8;
1094 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1095 dai->playback.formats = formats;
1096 }
1097
1098 if (i2s_tdm->has_capture) {
1099 dai->capture.stream_name = "Capture";
1100 dai->capture.channels_min = 2;
1101 dai->capture.channels_max = 8;
1102 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1103 dai->capture.formats = formats;
1104 }
1105
1106 if (i2s_tdm->clk_trcm != TRCM_TXRX)
1107 dai->symmetric_rate = 1;
1108
1109 i2s_tdm->dai = dai;
1110
1111 return 0;
1112 }
1113
rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)1114 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1115 int num,
1116 bool is_rx_path)
1117 {
1118 unsigned int *i2s_data;
1119 int i, j;
1120
1121 if (is_rx_path)
1122 i2s_data = i2s_tdm->i2s_sdis;
1123 else
1124 i2s_data = i2s_tdm->i2s_sdos;
1125
1126 for (i = 0; i < num; i++) {
1127 if (i2s_data[i] > CH_GRP_MAX - 1) {
1128 dev_err(i2s_tdm->dev,
1129 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1130 is_rx_path ? "RX" : "TX",
1131 i, i2s_data[i], CH_GRP_MAX);
1132 return -EINVAL;
1133 }
1134
1135 for (j = 0; j < num; j++) {
1136 if (i == j)
1137 continue;
1138
1139 if (i2s_data[i] == i2s_data[j]) {
1140 dev_err(i2s_tdm->dev,
1141 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1142 is_rx_path ? "RX" : "TX",
1143 i, i2s_data[i],
1144 j, i2s_data[j]);
1145 return -EINVAL;
1146 }
1147 }
1148 }
1149
1150 return 0;
1151 }
1152
rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)1153 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1154 int num)
1155 {
1156 int idx;
1157
1158 for (idx = 0; idx < num; idx++) {
1159 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1160 I2S_TXCR_PATH_MASK(idx),
1161 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1162 }
1163 }
1164
rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)1165 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1166 int num)
1167 {
1168 int idx;
1169
1170 for (idx = 0; idx < num; idx++) {
1171 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1172 I2S_RXCR_PATH_MASK(idx),
1173 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1174 }
1175 }
1176
rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)1177 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1178 int num, bool is_rx_path)
1179 {
1180 if (is_rx_path)
1181 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1182 else
1183 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1184 }
1185
rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np,bool is_rx_path)1186 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1187 struct device_node *np,
1188 bool is_rx_path)
1189 {
1190 char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1191 char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1192 char *i2s_path_prop;
1193 unsigned int *i2s_data;
1194 int num, ret = 0;
1195
1196 if (is_rx_path) {
1197 i2s_path_prop = i2s_rx_path_prop;
1198 i2s_data = i2s_tdm->i2s_sdis;
1199 } else {
1200 i2s_path_prop = i2s_tx_path_prop;
1201 i2s_data = i2s_tdm->i2s_sdos;
1202 }
1203
1204 num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1205 if (num < 0) {
1206 if (num != -ENOENT) {
1207 dev_err(i2s_tdm->dev,
1208 "Failed to read '%s' num: %d\n",
1209 i2s_path_prop, num);
1210 ret = num;
1211 }
1212 return ret;
1213 } else if (num != CH_GRP_MAX) {
1214 dev_err(i2s_tdm->dev,
1215 "The num: %d should be: %d\n", num, CH_GRP_MAX);
1216 return -EINVAL;
1217 }
1218
1219 ret = of_property_read_u32_array(np, i2s_path_prop,
1220 i2s_data, num);
1221 if (ret < 0) {
1222 dev_err(i2s_tdm->dev,
1223 "Failed to read '%s': %d\n",
1224 i2s_path_prop, ret);
1225 return ret;
1226 }
1227
1228 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1229 if (ret < 0) {
1230 dev_err(i2s_tdm->dev,
1231 "Failed to check i2s data bus: %d\n", ret);
1232 return ret;
1233 }
1234
1235 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1236
1237 return 0;
1238 }
1239
rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)1240 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1241 struct device_node *np)
1242 {
1243 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1244 }
1245
rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)1246 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1247 struct device_node *np)
1248 {
1249 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1250 }
1251
rockchip_i2s_tdm_probe(struct platform_device * pdev)1252 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1253 {
1254 struct device_node *node = pdev->dev.of_node;
1255 const struct of_device_id *of_id;
1256 struct rk_i2s_tdm_dev *i2s_tdm;
1257 struct resource *res;
1258 void __iomem *regs;
1259 int ret;
1260
1261 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1262 if (!i2s_tdm)
1263 return -ENOMEM;
1264
1265 i2s_tdm->dev = &pdev->dev;
1266
1267 of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1268 if (!of_id)
1269 return -EINVAL;
1270
1271 spin_lock_init(&i2s_tdm->lock);
1272 i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data;
1273
1274 i2s_tdm->frame_width = 64;
1275
1276 i2s_tdm->clk_trcm = TRCM_TXRX;
1277 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1278 i2s_tdm->clk_trcm = TRCM_TX;
1279 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1280 if (i2s_tdm->clk_trcm) {
1281 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1282 return -EINVAL;
1283 }
1284 i2s_tdm->clk_trcm = TRCM_RX;
1285 }
1286
1287 ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1288 if (ret)
1289 return ret;
1290
1291 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1292 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1293 "tx-m");
1294 if (IS_ERR(i2s_tdm->tx_reset)) {
1295 ret = PTR_ERR(i2s_tdm->tx_reset);
1296 return dev_err_probe(i2s_tdm->dev, ret,
1297 "Error in tx-m reset control\n");
1298 }
1299
1300 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1301 "rx-m");
1302 if (IS_ERR(i2s_tdm->rx_reset)) {
1303 ret = PTR_ERR(i2s_tdm->rx_reset);
1304 return dev_err_probe(i2s_tdm->dev, ret,
1305 "Error in rx-m reset control\n");
1306 }
1307
1308 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1309 if (IS_ERR(i2s_tdm->hclk)) {
1310 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1311 "Failed to get clock hclk\n");
1312 }
1313
1314 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1315 if (IS_ERR(i2s_tdm->mclk_tx)) {
1316 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1317 "Failed to get clock mclk_tx\n");
1318 }
1319
1320 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1321 if (IS_ERR(i2s_tdm->mclk_rx)) {
1322 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1323 "Failed to get clock mclk_rx\n");
1324 }
1325
1326 i2s_tdm->io_multiplex =
1327 of_property_read_bool(node, "rockchip,io-multiplex");
1328
1329 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1330 if (IS_ERR(regs)) {
1331 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1332 "Failed to get resource IORESOURCE_MEM\n");
1333 }
1334
1335 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1336 &rockchip_i2s_tdm_regmap_config);
1337 if (IS_ERR(i2s_tdm->regmap)) {
1338 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1339 "Failed to initialise regmap\n");
1340 }
1341
1342 if (i2s_tdm->has_playback) {
1343 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1344 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1345 i2s_tdm->playback_dma_data.maxburst = 8;
1346 }
1347
1348 if (i2s_tdm->has_capture) {
1349 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1350 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1351 i2s_tdm->capture_dma_data.maxburst = 8;
1352 }
1353
1354 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1355 if (ret < 0) {
1356 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1357 return ret;
1358 }
1359
1360 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1361 if (ret < 0) {
1362 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1363 return ret;
1364 }
1365
1366 dev_set_drvdata(&pdev->dev, i2s_tdm);
1367
1368 ret = clk_prepare_enable(i2s_tdm->hclk);
1369 if (ret) {
1370 return dev_err_probe(i2s_tdm->dev, ret,
1371 "Failed to enable clock hclk\n");
1372 }
1373
1374 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1375 if (ret) {
1376 ret = dev_err_probe(i2s_tdm->dev, ret,
1377 "Failed to enable one or more mclks\n");
1378 goto err_disable_hclk;
1379 }
1380
1381 pm_runtime_enable(&pdev->dev);
1382
1383 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1384 I2S_DMACR_TDL(16));
1385 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1386 I2S_DMACR_RDL(16));
1387 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1388 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1389
1390 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1391 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1392
1393 ret = devm_snd_soc_register_component(&pdev->dev,
1394 &rockchip_i2s_tdm_component,
1395 i2s_tdm->dai, 1);
1396
1397 if (ret) {
1398 dev_err(&pdev->dev, "Could not register DAI\n");
1399 goto err_suspend;
1400 }
1401
1402 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1403 if (ret) {
1404 dev_err(&pdev->dev, "Could not register PCM\n");
1405 goto err_suspend;
1406 }
1407
1408 return 0;
1409
1410 err_suspend:
1411 if (!pm_runtime_status_suspended(&pdev->dev))
1412 i2s_tdm_runtime_suspend(&pdev->dev);
1413 pm_runtime_disable(&pdev->dev);
1414
1415 err_disable_hclk:
1416 clk_disable_unprepare(i2s_tdm->hclk);
1417
1418 return ret;
1419 }
1420
rockchip_i2s_tdm_remove(struct platform_device * pdev)1421 static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
1422 {
1423 if (!pm_runtime_status_suspended(&pdev->dev))
1424 i2s_tdm_runtime_suspend(&pdev->dev);
1425
1426 pm_runtime_disable(&pdev->dev);
1427
1428 return 0;
1429 }
1430
rockchip_i2s_tdm_suspend(struct device * dev)1431 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1432 {
1433 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1434
1435 regcache_mark_dirty(i2s_tdm->regmap);
1436
1437 return 0;
1438 }
1439
rockchip_i2s_tdm_resume(struct device * dev)1440 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1441 {
1442 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1443 int ret;
1444
1445 ret = pm_runtime_resume_and_get(dev);
1446 if (ret < 0)
1447 return ret;
1448 ret = regcache_sync(i2s_tdm->regmap);
1449 pm_runtime_put(dev);
1450
1451 return ret;
1452 }
1453
1454 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1455 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1456 NULL)
1457 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1458 rockchip_i2s_tdm_resume)
1459 };
1460
1461 static struct platform_driver rockchip_i2s_tdm_driver = {
1462 .probe = rockchip_i2s_tdm_probe,
1463 .remove = rockchip_i2s_tdm_remove,
1464 .driver = {
1465 .name = DRV_NAME,
1466 .of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
1467 .pm = &rockchip_i2s_tdm_pm_ops,
1468 },
1469 };
1470 module_platform_driver(rockchip_i2s_tdm_driver);
1471
1472 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1473 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1474 MODULE_LICENSE("GPL v2");
1475 MODULE_ALIAS("platform:" DRV_NAME);
1476 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
1477